1[ 2 { 3 "BriefDescription": "Number of occurrences where a microcode assist is invoked by hardware.", 4 "CollectPEBSRecord": "2", 5 "Counter": "0,1,2,3,4,5,6,7", 6 "EventCode": "0xc1", 7 "EventName": "ASSISTS.ANY", 8 "PEBScounters": "0,1,2,3,4,5,6,7", 9 "PublicDescription": "Counts the number of occurrences where a microcode assist is invoked by hardware Examples include AD (page Access Dirty), FP and AVX related assists.", 10 "SampleAfterValue": "100003", 11 "Speculative": "1", 12 "UMask": "0x7" 13 }, 14 { 15 "BriefDescription": "Core cycles where the core was running in a manner where Turbo may be clipped to the Non-AVX turbo schedule.", 16 "CollectPEBSRecord": "2", 17 "Counter": "0,1,2,3", 18 "EventCode": "0x28", 19 "EventName": "CORE_POWER.LVL0_TURBO_LICENSE", 20 "PEBScounters": "0,1,2,3", 21 "PublicDescription": "Counts Core cycles where the core was running with power-delivery for baseline license level 0. This includes non-AVX codes, SSE, AVX 128-bit, and low-current AVX 256-bit codes.", 22 "SampleAfterValue": "200003", 23 "Speculative": "1", 24 "UMask": "0x7" 25 }, 26 { 27 "BriefDescription": "Core cycles where the core was running in a manner where Turbo may be clipped to the AVX2 turbo schedule.", 28 "CollectPEBSRecord": "2", 29 "Counter": "0,1,2,3", 30 "EventCode": "0x28", 31 "EventName": "CORE_POWER.LVL1_TURBO_LICENSE", 32 "PEBScounters": "0,1,2,3", 33 "PublicDescription": "Counts Core cycles where the core was running with power-delivery for license level 1. This includes high current AVX 256-bit instructions as well as low current AVX 512-bit instructions.", 34 "SampleAfterValue": "200003", 35 "Speculative": "1", 36 "UMask": "0x18" 37 }, 38 { 39 "BriefDescription": "Core cycles where the core was running in a manner where Turbo may be clipped to the AVX512 turbo schedule.", 40 "CollectPEBSRecord": "2", 41 "Counter": "0,1,2,3", 42 "EventCode": "0x28", 43 "EventName": "CORE_POWER.LVL2_TURBO_LICENSE", 44 "PEBScounters": "0,1,2,3", 45 "PublicDescription": "Core cycles where the core was running with power-delivery for license level 2 (introduced in Skylake Server microarchtecture). This includes high current AVX 512-bit instructions.", 46 "SampleAfterValue": "200003", 47 "Speculative": "1", 48 "UMask": "0x20" 49 }, 50 { 51 "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that have any type of response.", 52 "CollectPEBSRecord": "2", 53 "Counter": "0,1,2,3", 54 "EventCode": "0xB7, 0xBB", 55 "EventName": "OCR.DEMAND_CODE_RD.ANY_RESPONSE", 56 "MSRIndex": "0x1a6,0x1a7", 57 "MSRValue": "0x10004", 58 "Offcore": "1", 59 "PEBScounters": "0,1,2,3", 60 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 61 "SampleAfterValue": "100003", 62 "Speculative": "1", 63 "UMask": "0x1" 64 }, 65 { 66 "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that DRAM supplied the request.", 67 "CollectPEBSRecord": "2", 68 "Counter": "0,1,2,3", 69 "EventCode": "0xB7, 0xBB", 70 "EventName": "OCR.DEMAND_CODE_RD.DRAM", 71 "MSRIndex": "0x1a6,0x1a7", 72 "MSRValue": "0x184000004", 73 "Offcore": "1", 74 "PEBScounters": "0,1,2,3", 75 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 76 "SampleAfterValue": "100003", 77 "Speculative": "1", 78 "UMask": "0x1" 79 }, 80 { 81 "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that DRAM supplied the request.", 82 "CollectPEBSRecord": "2", 83 "Counter": "0,1,2,3", 84 "EventCode": "0xB7, 0xBB", 85 "EventName": "OCR.DEMAND_CODE_RD.LOCAL_DRAM", 86 "MSRIndex": "0x1a6,0x1a7", 87 "MSRValue": "0x184000004", 88 "Offcore": "1", 89 "PEBScounters": "0,1,2,3", 90 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 91 "SampleAfterValue": "100003", 92 "Speculative": "1", 93 "UMask": "0x1" 94 }, 95 { 96 "BriefDescription": "Counts demand data reads that have any type of response.", 97 "CollectPEBSRecord": "2", 98 "Counter": "0,1,2,3", 99 "EventCode": "0xB7, 0xBB", 100 "EventName": "OCR.DEMAND_DATA_RD.ANY_RESPONSE", 101 "MSRIndex": "0x1a6,0x1a7", 102 "MSRValue": "0x10001", 103 "Offcore": "1", 104 "PEBScounters": "0,1,2,3", 105 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 106 "SampleAfterValue": "100003", 107 "Speculative": "1", 108 "UMask": "0x1" 109 }, 110 { 111 "BriefDescription": "Counts demand data reads that DRAM supplied the request.", 112 "CollectPEBSRecord": "2", 113 "Counter": "0,1,2,3", 114 "EventCode": "0xB7, 0xBB", 115 "EventName": "OCR.DEMAND_DATA_RD.DRAM", 116 "MSRIndex": "0x1a6,0x1a7", 117 "MSRValue": "0x184000001", 118 "Offcore": "1", 119 "PEBScounters": "0,1,2,3", 120 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 121 "SampleAfterValue": "100003", 122 "Speculative": "1", 123 "UMask": "0x1" 124 }, 125 { 126 "BriefDescription": "Counts demand data reads that DRAM supplied the request.", 127 "CollectPEBSRecord": "2", 128 "Counter": "0,1,2,3", 129 "EventCode": "0xB7, 0xBB", 130 "EventName": "OCR.DEMAND_DATA_RD.LOCAL_DRAM", 131 "MSRIndex": "0x1a6,0x1a7", 132 "MSRValue": "0x184000001", 133 "Offcore": "1", 134 "PEBScounters": "0,1,2,3", 135 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 136 "SampleAfterValue": "100003", 137 "Speculative": "1", 138 "UMask": "0x1" 139 }, 140 { 141 "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that have any type of response.", 142 "CollectPEBSRecord": "2", 143 "Counter": "0,1,2,3", 144 "EventCode": "0xB7, 0xBB", 145 "EventName": "OCR.DEMAND_RFO.ANY_RESPONSE", 146 "MSRIndex": "0x1a6,0x1a7", 147 "MSRValue": "0x10002", 148 "Offcore": "1", 149 "PEBScounters": "0,1,2,3", 150 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 151 "SampleAfterValue": "100003", 152 "Speculative": "1", 153 "UMask": "0x1" 154 }, 155 { 156 "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that DRAM supplied the request.", 157 "CollectPEBSRecord": "2", 158 "Counter": "0,1,2,3", 159 "EventCode": "0xB7, 0xBB", 160 "EventName": "OCR.DEMAND_RFO.DRAM", 161 "MSRIndex": "0x1a6,0x1a7", 162 "MSRValue": "0x184000002", 163 "Offcore": "1", 164 "PEBScounters": "0,1,2,3", 165 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 166 "SampleAfterValue": "100003", 167 "Speculative": "1", 168 "UMask": "0x1" 169 }, 170 { 171 "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that DRAM supplied the request.", 172 "CollectPEBSRecord": "2", 173 "Counter": "0,1,2,3", 174 "EventCode": "0xB7, 0xBB", 175 "EventName": "OCR.DEMAND_RFO.LOCAL_DRAM", 176 "MSRIndex": "0x1a6,0x1a7", 177 "MSRValue": "0x184000002", 178 "Offcore": "1", 179 "PEBScounters": "0,1,2,3", 180 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 181 "SampleAfterValue": "100003", 182 "Speculative": "1", 183 "UMask": "0x1" 184 }, 185 { 186 "BriefDescription": "Counts L1 data cache prefetch requests and software prefetches (except PREFETCHW) that have any type of response.", 187 "CollectPEBSRecord": "2", 188 "Counter": "0,1,2,3", 189 "EventCode": "0xB7, 0xBB", 190 "EventName": "OCR.HWPF_L1D_AND_SWPF.ANY_RESPONSE", 191 "MSRIndex": "0x1a6,0x1a7", 192 "MSRValue": "0x10400", 193 "Offcore": "1", 194 "PEBScounters": "0,1,2,3", 195 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 196 "SampleAfterValue": "100003", 197 "Speculative": "1", 198 "UMask": "0x1" 199 }, 200 { 201 "BriefDescription": "Counts L1 data cache prefetch requests and software prefetches (except PREFETCHW) that DRAM supplied the request.", 202 "CollectPEBSRecord": "2", 203 "Counter": "0,1,2,3", 204 "EventCode": "0xB7, 0xBB", 205 "EventName": "OCR.HWPF_L1D_AND_SWPF.DRAM", 206 "MSRIndex": "0x1a6,0x1a7", 207 "MSRValue": "0x184000400", 208 "Offcore": "1", 209 "PEBScounters": "0,1,2,3", 210 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 211 "SampleAfterValue": "100003", 212 "Speculative": "1", 213 "UMask": "0x1" 214 }, 215 { 216 "BriefDescription": "Counts L1 data cache prefetch requests and software prefetches (except PREFETCHW) that DRAM supplied the request.", 217 "CollectPEBSRecord": "2", 218 "Counter": "0,1,2,3", 219 "EventCode": "0xB7, 0xBB", 220 "EventName": "OCR.HWPF_L1D_AND_SWPF.LOCAL_DRAM", 221 "MSRIndex": "0x1a6,0x1a7", 222 "MSRValue": "0x184000400", 223 "Offcore": "1", 224 "PEBScounters": "0,1,2,3", 225 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 226 "SampleAfterValue": "100003", 227 "Speculative": "1", 228 "UMask": "0x1" 229 }, 230 { 231 "BriefDescription": "Counts hardware prefetch data reads (which bring data to L2) that have any type of response.", 232 "CollectPEBSRecord": "2", 233 "Counter": "0,1,2,3", 234 "EventCode": "0xB7, 0xBB", 235 "EventName": "OCR.HWPF_L2_DATA_RD.ANY_RESPONSE", 236 "MSRIndex": "0x1a6,0x1a7", 237 "MSRValue": "0x10010", 238 "Offcore": "1", 239 "PEBScounters": "0,1,2,3", 240 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 241 "SampleAfterValue": "100003", 242 "Speculative": "1", 243 "UMask": "0x1" 244 }, 245 { 246 "BriefDescription": "Counts hardware prefetch data reads (which bring data to L2) that DRAM supplied the request.", 247 "CollectPEBSRecord": "2", 248 "Counter": "0,1,2,3", 249 "EventCode": "0xB7, 0xBB", 250 "EventName": "OCR.HWPF_L2_DATA_RD.DRAM", 251 "MSRIndex": "0x1a6,0x1a7", 252 "MSRValue": "0x184000010", 253 "Offcore": "1", 254 "PEBScounters": "0,1,2,3", 255 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 256 "SampleAfterValue": "100003", 257 "Speculative": "1", 258 "UMask": "0x1" 259 }, 260 { 261 "BriefDescription": "Counts hardware prefetch data reads (which bring data to L2) that DRAM supplied the request.", 262 "CollectPEBSRecord": "2", 263 "Counter": "0,1,2,3", 264 "EventCode": "0xB7, 0xBB", 265 "EventName": "OCR.HWPF_L2_DATA_RD.LOCAL_DRAM", 266 "MSRIndex": "0x1a6,0x1a7", 267 "MSRValue": "0x184000010", 268 "Offcore": "1", 269 "PEBScounters": "0,1,2,3", 270 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 271 "SampleAfterValue": "100003", 272 "Speculative": "1", 273 "UMask": "0x1" 274 }, 275 { 276 "BriefDescription": "Counts hardware prefetch RFOs (which bring data to L2) that have any type of response.", 277 "CollectPEBSRecord": "2", 278 "Counter": "0,1,2,3", 279 "EventCode": "0xB7, 0xBB", 280 "EventName": "OCR.HWPF_L2_RFO.ANY_RESPONSE", 281 "MSRIndex": "0x1a6,0x1a7", 282 "MSRValue": "0x10020", 283 "Offcore": "1", 284 "PEBScounters": "0,1,2,3", 285 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 286 "SampleAfterValue": "100003", 287 "Speculative": "1", 288 "UMask": "0x1" 289 }, 290 { 291 "BriefDescription": "Counts hardware prefetch RFOs (which bring data to L2) that DRAM supplied the request.", 292 "CollectPEBSRecord": "2", 293 "Counter": "0,1,2,3", 294 "EventCode": "0xB7, 0xBB", 295 "EventName": "OCR.HWPF_L2_RFO.DRAM", 296 "MSRIndex": "0x1a6,0x1a7", 297 "MSRValue": "0x184000020", 298 "Offcore": "1", 299 "PEBScounters": "0,1,2,3", 300 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 301 "SampleAfterValue": "100003", 302 "Speculative": "1", 303 "UMask": "0x1" 304 }, 305 { 306 "BriefDescription": "Counts hardware prefetch RFOs (which bring data to L2) that DRAM supplied the request.", 307 "CollectPEBSRecord": "2", 308 "Counter": "0,1,2,3", 309 "EventCode": "0xB7, 0xBB", 310 "EventName": "OCR.HWPF_L2_RFO.LOCAL_DRAM", 311 "MSRIndex": "0x1a6,0x1a7", 312 "MSRValue": "0x184000020", 313 "Offcore": "1", 314 "PEBScounters": "0,1,2,3", 315 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 316 "SampleAfterValue": "100003", 317 "Speculative": "1", 318 "UMask": "0x1" 319 }, 320 { 321 "BriefDescription": "Counts miscellaneous requests, such as I/O and un-cacheable accesses that have any type of response.", 322 "CollectPEBSRecord": "2", 323 "Counter": "0,1,2,3", 324 "EventCode": "0xB7, 0xBB", 325 "EventName": "OCR.OTHER.ANY_RESPONSE", 326 "MSRIndex": "0x1a6,0x1a7", 327 "MSRValue": "0x18000", 328 "Offcore": "1", 329 "PEBScounters": "0,1,2,3", 330 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 331 "SampleAfterValue": "100003", 332 "Speculative": "1", 333 "UMask": "0x1" 334 }, 335 { 336 "BriefDescription": "Counts miscellaneous requests, such as I/O and un-cacheable accesses that DRAM supplied the request.", 337 "CollectPEBSRecord": "2", 338 "Counter": "0,1,2,3", 339 "EventCode": "0xB7, 0xBB", 340 "EventName": "OCR.OTHER.DRAM", 341 "MSRIndex": "0x1a6,0x1a7", 342 "MSRValue": "0x184008000", 343 "Offcore": "1", 344 "PEBScounters": "0,1,2,3", 345 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 346 "SampleAfterValue": "100003", 347 "Speculative": "1", 348 "UMask": "0x1" 349 }, 350 { 351 "BriefDescription": "Counts miscellaneous requests, such as I/O and un-cacheable accesses that DRAM supplied the request.", 352 "CollectPEBSRecord": "2", 353 "Counter": "0,1,2,3", 354 "EventCode": "0xB7, 0xBB", 355 "EventName": "OCR.OTHER.LOCAL_DRAM", 356 "MSRIndex": "0x1a6,0x1a7", 357 "MSRValue": "0x184008000", 358 "Offcore": "1", 359 "PEBScounters": "0,1,2,3", 360 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 361 "SampleAfterValue": "100003", 362 "Speculative": "1", 363 "UMask": "0x1" 364 }, 365 { 366 "BriefDescription": "Counts streaming stores that have any type of response.", 367 "CollectPEBSRecord": "2", 368 "Counter": "0,1,2,3", 369 "EventCode": "0xB7, 0xBB", 370 "EventName": "OCR.STREAMING_WR.ANY_RESPONSE", 371 "MSRIndex": "0x1a6,0x1a7", 372 "MSRValue": "0x10800", 373 "Offcore": "1", 374 "PEBScounters": "0,1,2,3", 375 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 376 "SampleAfterValue": "100003", 377 "Speculative": "1", 378 "UMask": "0x1" 379 }, 380 { 381 "BriefDescription": "Counts streaming stores that DRAM supplied the request.", 382 "CollectPEBSRecord": "2", 383 "Counter": "0,1,2,3", 384 "EventCode": "0xB7, 0xBB", 385 "EventName": "OCR.STREAMING_WR.DRAM", 386 "MSRIndex": "0x1a6,0x1a7", 387 "MSRValue": "0x184000800", 388 "Offcore": "1", 389 "PEBScounters": "0,1,2,3", 390 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 391 "SampleAfterValue": "100003", 392 "Speculative": "1", 393 "UMask": "0x1" 394 }, 395 { 396 "BriefDescription": "Counts streaming stores that DRAM supplied the request.", 397 "CollectPEBSRecord": "2", 398 "Counter": "0,1,2,3", 399 "EventCode": "0xB7, 0xBB", 400 "EventName": "OCR.STREAMING_WR.LOCAL_DRAM", 401 "MSRIndex": "0x1a6,0x1a7", 402 "MSRValue": "0x184000800", 403 "Offcore": "1", 404 "PEBScounters": "0,1,2,3", 405 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 406 "SampleAfterValue": "100003", 407 "Speculative": "1", 408 "UMask": "0x1" 409 } 410]