1b115df07SHaiyan Song[ 2b115df07SHaiyan Song { 3*dd7415ceSIan Rogers "BriefDescription": "Core cycles where the core was running in a manner where Turbo may be clipped to the Non-AVX turbo schedule.", 4*dd7415ceSIan Rogers "EventCode": "0x28", 5*dd7415ceSIan Rogers "EventName": "CORE_POWER.LVL0_TURBO_LICENSE", 6*dd7415ceSIan Rogers "PublicDescription": "Counts Core cycles where the core was running with power-delivery for baseline license level 0. This includes non-AVX codes, SSE, AVX 128-bit, and low-current AVX 256-bit codes.", 7*dd7415ceSIan Rogers "SampleAfterValue": "200003", 8*dd7415ceSIan Rogers "UMask": "0x7" 971fbc431SJin Yao }, 1071fbc431SJin Yao { 1171fbc431SJin Yao "BriefDescription": "Core cycles where the core was running in a manner where Turbo may be clipped to the AVX2 turbo schedule.", 1271fbc431SJin Yao "EventCode": "0x28", 1371fbc431SJin Yao "EventName": "CORE_POWER.LVL1_TURBO_LICENSE", 1471fbc431SJin Yao "PublicDescription": "Counts Core cycles where the core was running with power-delivery for license level 1. This includes high current AVX 256-bit instructions as well as low current AVX 512-bit instructions.", 1571fbc431SJin Yao "SampleAfterValue": "200003", 1671fbc431SJin Yao "UMask": "0x18" 1771fbc431SJin Yao }, 1871fbc431SJin Yao { 19*dd7415ceSIan Rogers "BriefDescription": "Core cycles where the core was running in a manner where Turbo may be clipped to the AVX512 turbo schedule.", 20*dd7415ceSIan Rogers "EventCode": "0x28", 21*dd7415ceSIan Rogers "EventName": "CORE_POWER.LVL2_TURBO_LICENSE", 22*dd7415ceSIan Rogers "PublicDescription": "Core cycles where the core was running with power-delivery for license level 2 (introduced in Skylake Server microarchtecture). This includes high current AVX 512-bit instructions.", 23*dd7415ceSIan Rogers "SampleAfterValue": "200003", 24*dd7415ceSIan Rogers "UMask": "0x20" 2571fbc431SJin Yao }, 2671fbc431SJin Yao { 27*dd7415ceSIan Rogers "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that have any type of response.", 2871fbc431SJin Yao "EventCode": "0xB7, 0xBB", 29*dd7415ceSIan Rogers "EventName": "OCR.DEMAND_CODE_RD.ANY_RESPONSE", 3071fbc431SJin Yao "MSRIndex": "0x1a6,0x1a7", 31*dd7415ceSIan Rogers "MSRValue": "0x10004", 3271fbc431SJin Yao "SampleAfterValue": "100003", 3371fbc431SJin Yao "UMask": "0x1" 3471fbc431SJin Yao }, 3571fbc431SJin Yao { 3671fbc431SJin Yao "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that DRAM supplied the request.", 3771fbc431SJin Yao "EventCode": "0xB7, 0xBB", 3871fbc431SJin Yao "EventName": "OCR.DEMAND_CODE_RD.DRAM", 3971fbc431SJin Yao "MSRIndex": "0x1a6,0x1a7", 40*dd7415ceSIan Rogers "MSRValue": "0x184000004", 4171fbc431SJin Yao "SampleAfterValue": "100003", 4271fbc431SJin Yao "UMask": "0x1" 4371fbc431SJin Yao }, 4471fbc431SJin Yao { 45*dd7415ceSIan Rogers "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that DRAM supplied the request.", 46*dd7415ceSIan Rogers "EventCode": "0xB7, 0xBB", 47*dd7415ceSIan Rogers "EventName": "OCR.DEMAND_CODE_RD.LOCAL_DRAM", 48*dd7415ceSIan Rogers "MSRIndex": "0x1a6,0x1a7", 49*dd7415ceSIan Rogers "MSRValue": "0x184000004", 50*dd7415ceSIan Rogers "SampleAfterValue": "100003", 51*dd7415ceSIan Rogers "UMask": "0x1" 52*dd7415ceSIan Rogers }, 53*dd7415ceSIan Rogers { 54*dd7415ceSIan Rogers "BriefDescription": "Counts demand data reads that have any type of response.", 55*dd7415ceSIan Rogers "EventCode": "0xB7, 0xBB", 56*dd7415ceSIan Rogers "EventName": "OCR.DEMAND_DATA_RD.ANY_RESPONSE", 57*dd7415ceSIan Rogers "MSRIndex": "0x1a6,0x1a7", 58*dd7415ceSIan Rogers "MSRValue": "0x10001", 59*dd7415ceSIan Rogers "SampleAfterValue": "100003", 60*dd7415ceSIan Rogers "UMask": "0x1" 61*dd7415ceSIan Rogers }, 62*dd7415ceSIan Rogers { 63*dd7415ceSIan Rogers "BriefDescription": "Counts demand data reads that DRAM supplied the request.", 64*dd7415ceSIan Rogers "EventCode": "0xB7, 0xBB", 65*dd7415ceSIan Rogers "EventName": "OCR.DEMAND_DATA_RD.DRAM", 66*dd7415ceSIan Rogers "MSRIndex": "0x1a6,0x1a7", 67*dd7415ceSIan Rogers "MSRValue": "0x184000001", 68*dd7415ceSIan Rogers "SampleAfterValue": "100003", 69*dd7415ceSIan Rogers "UMask": "0x1" 70*dd7415ceSIan Rogers }, 71*dd7415ceSIan Rogers { 72*dd7415ceSIan Rogers "BriefDescription": "Counts demand data reads that DRAM supplied the request.", 73*dd7415ceSIan Rogers "EventCode": "0xB7, 0xBB", 74*dd7415ceSIan Rogers "EventName": "OCR.DEMAND_DATA_RD.LOCAL_DRAM", 75*dd7415ceSIan Rogers "MSRIndex": "0x1a6,0x1a7", 76*dd7415ceSIan Rogers "MSRValue": "0x184000001", 77*dd7415ceSIan Rogers "SampleAfterValue": "100003", 78*dd7415ceSIan Rogers "UMask": "0x1" 79*dd7415ceSIan Rogers }, 80*dd7415ceSIan Rogers { 81*dd7415ceSIan Rogers "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that have any type of response.", 82*dd7415ceSIan Rogers "EventCode": "0xB7, 0xBB", 83*dd7415ceSIan Rogers "EventName": "OCR.DEMAND_RFO.ANY_RESPONSE", 84*dd7415ceSIan Rogers "MSRIndex": "0x1a6,0x1a7", 85*dd7415ceSIan Rogers "MSRValue": "0x10002", 86*dd7415ceSIan Rogers "SampleAfterValue": "100003", 87*dd7415ceSIan Rogers "UMask": "0x1" 88*dd7415ceSIan Rogers }, 89*dd7415ceSIan Rogers { 90*dd7415ceSIan Rogers "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that DRAM supplied the request.", 91*dd7415ceSIan Rogers "EventCode": "0xB7, 0xBB", 92*dd7415ceSIan Rogers "EventName": "OCR.DEMAND_RFO.DRAM", 93*dd7415ceSIan Rogers "MSRIndex": "0x1a6,0x1a7", 94*dd7415ceSIan Rogers "MSRValue": "0x184000002", 95*dd7415ceSIan Rogers "SampleAfterValue": "100003", 96*dd7415ceSIan Rogers "UMask": "0x1" 97*dd7415ceSIan Rogers }, 98*dd7415ceSIan Rogers { 9971fbc431SJin Yao "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that DRAM supplied the request.", 10071fbc431SJin Yao "EventCode": "0xB7, 0xBB", 10171fbc431SJin Yao "EventName": "OCR.DEMAND_RFO.LOCAL_DRAM", 10271fbc431SJin Yao "MSRIndex": "0x1a6,0x1a7", 103*dd7415ceSIan Rogers "MSRValue": "0x184000002", 10471fbc431SJin Yao "SampleAfterValue": "100003", 10571fbc431SJin Yao "UMask": "0x1" 10671fbc431SJin Yao }, 10771fbc431SJin Yao { 108*dd7415ceSIan Rogers "BriefDescription": "Counts L1 data cache prefetch requests and software prefetches (except PREFETCHW) that have any type of response.", 109*dd7415ceSIan Rogers "EventCode": "0xB7, 0xBB", 110*dd7415ceSIan Rogers "EventName": "OCR.HWPF_L1D_AND_SWPF.ANY_RESPONSE", 111*dd7415ceSIan Rogers "MSRIndex": "0x1a6,0x1a7", 112*dd7415ceSIan Rogers "MSRValue": "0x10400", 113*dd7415ceSIan Rogers "SampleAfterValue": "100003", 114*dd7415ceSIan Rogers "UMask": "0x1" 115*dd7415ceSIan Rogers }, 116*dd7415ceSIan Rogers { 117*dd7415ceSIan Rogers "BriefDescription": "Counts L1 data cache prefetch requests and software prefetches (except PREFETCHW) that DRAM supplied the request.", 118*dd7415ceSIan Rogers "EventCode": "0xB7, 0xBB", 119*dd7415ceSIan Rogers "EventName": "OCR.HWPF_L1D_AND_SWPF.DRAM", 120*dd7415ceSIan Rogers "MSRIndex": "0x1a6,0x1a7", 121*dd7415ceSIan Rogers "MSRValue": "0x184000400", 122*dd7415ceSIan Rogers "SampleAfterValue": "100003", 123*dd7415ceSIan Rogers "UMask": "0x1" 124*dd7415ceSIan Rogers }, 125*dd7415ceSIan Rogers { 126*dd7415ceSIan Rogers "BriefDescription": "Counts L1 data cache prefetch requests and software prefetches (except PREFETCHW) that DRAM supplied the request.", 127*dd7415ceSIan Rogers "EventCode": "0xB7, 0xBB", 128*dd7415ceSIan Rogers "EventName": "OCR.HWPF_L1D_AND_SWPF.LOCAL_DRAM", 129*dd7415ceSIan Rogers "MSRIndex": "0x1a6,0x1a7", 130*dd7415ceSIan Rogers "MSRValue": "0x184000400", 131*dd7415ceSIan Rogers "SampleAfterValue": "100003", 132*dd7415ceSIan Rogers "UMask": "0x1" 133*dd7415ceSIan Rogers }, 134*dd7415ceSIan Rogers { 135*dd7415ceSIan Rogers "BriefDescription": "Counts hardware prefetch data reads (which bring data to L2) that have any type of response.", 136*dd7415ceSIan Rogers "EventCode": "0xB7, 0xBB", 137*dd7415ceSIan Rogers "EventName": "OCR.HWPF_L2_DATA_RD.ANY_RESPONSE", 138*dd7415ceSIan Rogers "MSRIndex": "0x1a6,0x1a7", 139*dd7415ceSIan Rogers "MSRValue": "0x10010", 140*dd7415ceSIan Rogers "SampleAfterValue": "100003", 141*dd7415ceSIan Rogers "UMask": "0x1" 142*dd7415ceSIan Rogers }, 143*dd7415ceSIan Rogers { 144*dd7415ceSIan Rogers "BriefDescription": "Counts hardware prefetch data reads (which bring data to L2) that DRAM supplied the request.", 145*dd7415ceSIan Rogers "EventCode": "0xB7, 0xBB", 146*dd7415ceSIan Rogers "EventName": "OCR.HWPF_L2_DATA_RD.DRAM", 147*dd7415ceSIan Rogers "MSRIndex": "0x1a6,0x1a7", 148*dd7415ceSIan Rogers "MSRValue": "0x184000010", 149*dd7415ceSIan Rogers "SampleAfterValue": "100003", 150*dd7415ceSIan Rogers "UMask": "0x1" 151*dd7415ceSIan Rogers }, 152*dd7415ceSIan Rogers { 153*dd7415ceSIan Rogers "BriefDescription": "Counts hardware prefetch data reads (which bring data to L2) that DRAM supplied the request.", 154*dd7415ceSIan Rogers "EventCode": "0xB7, 0xBB", 155*dd7415ceSIan Rogers "EventName": "OCR.HWPF_L2_DATA_RD.LOCAL_DRAM", 156*dd7415ceSIan Rogers "MSRIndex": "0x1a6,0x1a7", 157*dd7415ceSIan Rogers "MSRValue": "0x184000010", 158*dd7415ceSIan Rogers "SampleAfterValue": "100003", 159*dd7415ceSIan Rogers "UMask": "0x1" 160*dd7415ceSIan Rogers }, 161*dd7415ceSIan Rogers { 162*dd7415ceSIan Rogers "BriefDescription": "Counts hardware prefetch RFOs (which bring data to L2) that have any type of response.", 163*dd7415ceSIan Rogers "EventCode": "0xB7, 0xBB", 164*dd7415ceSIan Rogers "EventName": "OCR.HWPF_L2_RFO.ANY_RESPONSE", 165*dd7415ceSIan Rogers "MSRIndex": "0x1a6,0x1a7", 166*dd7415ceSIan Rogers "MSRValue": "0x10020", 167*dd7415ceSIan Rogers "SampleAfterValue": "100003", 168*dd7415ceSIan Rogers "UMask": "0x1" 169*dd7415ceSIan Rogers }, 170*dd7415ceSIan Rogers { 171*dd7415ceSIan Rogers "BriefDescription": "Counts hardware prefetch RFOs (which bring data to L2) that DRAM supplied the request.", 172*dd7415ceSIan Rogers "EventCode": "0xB7, 0xBB", 173*dd7415ceSIan Rogers "EventName": "OCR.HWPF_L2_RFO.DRAM", 174*dd7415ceSIan Rogers "MSRIndex": "0x1a6,0x1a7", 175*dd7415ceSIan Rogers "MSRValue": "0x184000020", 176*dd7415ceSIan Rogers "SampleAfterValue": "100003", 177*dd7415ceSIan Rogers "UMask": "0x1" 178*dd7415ceSIan Rogers }, 179*dd7415ceSIan Rogers { 180*dd7415ceSIan Rogers "BriefDescription": "Counts hardware prefetch RFOs (which bring data to L2) that DRAM supplied the request.", 181*dd7415ceSIan Rogers "EventCode": "0xB7, 0xBB", 182*dd7415ceSIan Rogers "EventName": "OCR.HWPF_L2_RFO.LOCAL_DRAM", 183*dd7415ceSIan Rogers "MSRIndex": "0x1a6,0x1a7", 184*dd7415ceSIan Rogers "MSRValue": "0x184000020", 185*dd7415ceSIan Rogers "SampleAfterValue": "100003", 186*dd7415ceSIan Rogers "UMask": "0x1" 187*dd7415ceSIan Rogers }, 188*dd7415ceSIan Rogers { 189*dd7415ceSIan Rogers "BriefDescription": "Counts miscellaneous requests, such as I/O and un-cacheable accesses that have any type of response.", 190*dd7415ceSIan Rogers "EventCode": "0xB7, 0xBB", 191*dd7415ceSIan Rogers "EventName": "OCR.OTHER.ANY_RESPONSE", 192*dd7415ceSIan Rogers "MSRIndex": "0x1a6,0x1a7", 193*dd7415ceSIan Rogers "MSRValue": "0x18000", 194*dd7415ceSIan Rogers "SampleAfterValue": "100003", 195*dd7415ceSIan Rogers "UMask": "0x1" 196*dd7415ceSIan Rogers }, 197*dd7415ceSIan Rogers { 198*dd7415ceSIan Rogers "BriefDescription": "Counts miscellaneous requests, such as I/O and un-cacheable accesses that DRAM supplied the request.", 199*dd7415ceSIan Rogers "EventCode": "0xB7, 0xBB", 200*dd7415ceSIan Rogers "EventName": "OCR.OTHER.DRAM", 201*dd7415ceSIan Rogers "MSRIndex": "0x1a6,0x1a7", 202*dd7415ceSIan Rogers "MSRValue": "0x184008000", 203*dd7415ceSIan Rogers "SampleAfterValue": "100003", 204*dd7415ceSIan Rogers "UMask": "0x1" 205*dd7415ceSIan Rogers }, 206*dd7415ceSIan Rogers { 207*dd7415ceSIan Rogers "BriefDescription": "Counts miscellaneous requests, such as I/O and un-cacheable accesses that DRAM supplied the request.", 208*dd7415ceSIan Rogers "EventCode": "0xB7, 0xBB", 209*dd7415ceSIan Rogers "EventName": "OCR.OTHER.LOCAL_DRAM", 210*dd7415ceSIan Rogers "MSRIndex": "0x1a6,0x1a7", 211*dd7415ceSIan Rogers "MSRValue": "0x184008000", 212*dd7415ceSIan Rogers "SampleAfterValue": "100003", 213*dd7415ceSIan Rogers "UMask": "0x1" 214*dd7415ceSIan Rogers }, 215*dd7415ceSIan Rogers { 216*dd7415ceSIan Rogers "BriefDescription": "Counts streaming stores that have any type of response.", 217*dd7415ceSIan Rogers "EventCode": "0xB7, 0xBB", 218*dd7415ceSIan Rogers "EventName": "OCR.STREAMING_WR.ANY_RESPONSE", 219*dd7415ceSIan Rogers "MSRIndex": "0x1a6,0x1a7", 220*dd7415ceSIan Rogers "MSRValue": "0x10800", 221*dd7415ceSIan Rogers "SampleAfterValue": "100003", 222*dd7415ceSIan Rogers "UMask": "0x1" 223*dd7415ceSIan Rogers }, 224*dd7415ceSIan Rogers { 225*dd7415ceSIan Rogers "BriefDescription": "Counts streaming stores that DRAM supplied the request.", 226*dd7415ceSIan Rogers "EventCode": "0xB7, 0xBB", 227*dd7415ceSIan Rogers "EventName": "OCR.STREAMING_WR.DRAM", 228*dd7415ceSIan Rogers "MSRIndex": "0x1a6,0x1a7", 229*dd7415ceSIan Rogers "MSRValue": "0x184000800", 230*dd7415ceSIan Rogers "SampleAfterValue": "100003", 231*dd7415ceSIan Rogers "UMask": "0x1" 232*dd7415ceSIan Rogers }, 233*dd7415ceSIan Rogers { 234*dd7415ceSIan Rogers "BriefDescription": "Counts streaming stores that DRAM supplied the request.", 235*dd7415ceSIan Rogers "EventCode": "0xB7, 0xBB", 236*dd7415ceSIan Rogers "EventName": "OCR.STREAMING_WR.LOCAL_DRAM", 237*dd7415ceSIan Rogers "MSRIndex": "0x1a6,0x1a7", 238*dd7415ceSIan Rogers "MSRValue": "0x184000800", 239*dd7415ceSIan Rogers "SampleAfterValue": "100003", 240*dd7415ceSIan Rogers "UMask": "0x1" 241b115df07SHaiyan Song } 242b115df07SHaiyan Song] 243