1b115df07SHaiyan Song[ 2b115df07SHaiyan Song { 3*dd7415ceSIan Rogers "BriefDescription": "Cycles while L3 cache miss demand load is outstanding.", 4b115df07SHaiyan Song "CollectPEBSRecord": "2", 5b115df07SHaiyan Song "Counter": "0,1,2,3", 6*dd7415ceSIan Rogers "CounterMask": "2", 7*dd7415ceSIan Rogers "EventCode": "0xA3", 8*dd7415ceSIan Rogers "EventName": "CYCLE_ACTIVITY.CYCLES_L3_MISS", 9b115df07SHaiyan Song "PEBScounters": "0,1,2,3", 10*dd7415ceSIan Rogers "SampleAfterValue": "1000003", 1171fbc431SJin Yao "Speculative": "1", 12*dd7415ceSIan Rogers "UMask": "0x2" 13*dd7415ceSIan Rogers }, 14*dd7415ceSIan Rogers { 15*dd7415ceSIan Rogers "BriefDescription": "Execution stalls while L3 cache miss demand load is outstanding.", 16*dd7415ceSIan Rogers "CollectPEBSRecord": "2", 17*dd7415ceSIan Rogers "Counter": "0,1,2,3", 18*dd7415ceSIan Rogers "CounterMask": "6", 19*dd7415ceSIan Rogers "EventCode": "0xa3", 20*dd7415ceSIan Rogers "EventName": "CYCLE_ACTIVITY.STALLS_L3_MISS", 21*dd7415ceSIan Rogers "PEBScounters": "0,1,2,3", 22*dd7415ceSIan Rogers "SampleAfterValue": "1000003", 23*dd7415ceSIan Rogers "Speculative": "1", 24*dd7415ceSIan Rogers "UMask": "0x6" 25b115df07SHaiyan Song }, 26b115df07SHaiyan Song { 2771fbc431SJin Yao "BriefDescription": "Number of times an HLE execution aborted due to any reasons (multiple categories may count as one).", 28b115df07SHaiyan Song "CollectPEBSRecord": "2", 29b115df07SHaiyan Song "Counter": "0,1,2,3,4,5,6,7", 30b115df07SHaiyan Song "EventCode": "0xc8", 31b115df07SHaiyan Song "EventName": "HLE_RETIRED.ABORTED", 32b115df07SHaiyan Song "PEBScounters": "0,1,2,3,4,5,6,7", 3371fbc431SJin Yao "PublicDescription": "Counts the number of times HLE abort was triggered.", 34b115df07SHaiyan Song "SampleAfterValue": "100003", 3571fbc431SJin Yao "UMask": "0x4" 36b115df07SHaiyan Song }, 37b115df07SHaiyan Song { 38*dd7415ceSIan Rogers "BriefDescription": "Number of times an HLE execution aborted due to unfriendly events (such as interrupts).", 39b115df07SHaiyan Song "CollectPEBSRecord": "2", 40*dd7415ceSIan Rogers "Counter": "0,1,2,3,4,5,6,7", 41*dd7415ceSIan Rogers "EventCode": "0xc8", 42*dd7415ceSIan Rogers "EventName": "HLE_RETIRED.ABORTED_EVENTS", 43*dd7415ceSIan Rogers "PEBScounters": "0,1,2,3,4,5,6,7", 44*dd7415ceSIan Rogers "PublicDescription": "Counts the number of times an HLE execution aborted due to unfriendly events (such as interrupts).", 45*dd7415ceSIan Rogers "SampleAfterValue": "100003", 46*dd7415ceSIan Rogers "UMask": "0x80" 47*dd7415ceSIan Rogers }, 48*dd7415ceSIan Rogers { 49*dd7415ceSIan Rogers "BriefDescription": "Number of times an HLE execution aborted due to various memory events (e.g., read/write capacity and conflicts).", 50*dd7415ceSIan Rogers "CollectPEBSRecord": "2", 51*dd7415ceSIan Rogers "Counter": "0,1,2,3,4,5,6,7", 52*dd7415ceSIan Rogers "EventCode": "0xc8", 53*dd7415ceSIan Rogers "EventName": "HLE_RETIRED.ABORTED_MEM", 54*dd7415ceSIan Rogers "PEBScounters": "0,1,2,3,4,5,6,7", 55*dd7415ceSIan Rogers "PublicDescription": "Counts the number of times an HLE execution aborted due to various memory events (e.g., read/write capacity and conflicts).", 56*dd7415ceSIan Rogers "SampleAfterValue": "100003", 57*dd7415ceSIan Rogers "UMask": "0x8" 58*dd7415ceSIan Rogers }, 59*dd7415ceSIan Rogers { 60*dd7415ceSIan Rogers "BriefDescription": "Number of times an HLE execution aborted due to HLE-unfriendly instructions and certain unfriendly events (such as AD assists etc.).", 61*dd7415ceSIan Rogers "CollectPEBSRecord": "2", 62*dd7415ceSIan Rogers "Counter": "0,1,2,3,4,5,6,7", 63*dd7415ceSIan Rogers "EventCode": "0xc8", 64*dd7415ceSIan Rogers "EventName": "HLE_RETIRED.ABORTED_UNFRIENDLY", 65*dd7415ceSIan Rogers "PEBScounters": "0,1,2,3,4,5,6,7", 66*dd7415ceSIan Rogers "PublicDescription": "Counts the number of times an HLE execution aborted due to HLE-unfriendly instructions and certain unfriendly events (such as AD assists etc.).", 67*dd7415ceSIan Rogers "SampleAfterValue": "100003", 68*dd7415ceSIan Rogers "UMask": "0x20" 69*dd7415ceSIan Rogers }, 70*dd7415ceSIan Rogers { 71*dd7415ceSIan Rogers "BriefDescription": "Number of times an HLE execution successfully committed", 72*dd7415ceSIan Rogers "CollectPEBSRecord": "2", 73*dd7415ceSIan Rogers "Counter": "0,1,2,3,4,5,6,7", 74*dd7415ceSIan Rogers "EventCode": "0xc8", 75*dd7415ceSIan Rogers "EventName": "HLE_RETIRED.COMMIT", 76*dd7415ceSIan Rogers "PEBScounters": "0,1,2,3,4,5,6,7", 77*dd7415ceSIan Rogers "PublicDescription": "Counts the number of times HLE commit succeeded.", 78*dd7415ceSIan Rogers "SampleAfterValue": "100003", 79*dd7415ceSIan Rogers "UMask": "0x2" 80*dd7415ceSIan Rogers }, 81*dd7415ceSIan Rogers { 82*dd7415ceSIan Rogers "BriefDescription": "Number of times an HLE execution started.", 83*dd7415ceSIan Rogers "CollectPEBSRecord": "2", 84*dd7415ceSIan Rogers "Counter": "0,1,2,3,4,5,6,7", 85*dd7415ceSIan Rogers "EventCode": "0xc8", 86*dd7415ceSIan Rogers "EventName": "HLE_RETIRED.START", 87*dd7415ceSIan Rogers "PEBScounters": "0,1,2,3,4,5,6,7", 88*dd7415ceSIan Rogers "PublicDescription": "Counts the number of times we entered an HLE region. Does not count nested transactions.", 89*dd7415ceSIan Rogers "SampleAfterValue": "100003", 90*dd7415ceSIan Rogers "UMask": "0x1" 91*dd7415ceSIan Rogers }, 92*dd7415ceSIan Rogers { 93*dd7415ceSIan Rogers "BriefDescription": "Number of machine clears due to memory ordering conflicts.", 94*dd7415ceSIan Rogers "CollectPEBSRecord": "2", 95*dd7415ceSIan Rogers "Counter": "0,1,2,3,4,5,6,7", 96*dd7415ceSIan Rogers "EventCode": "0xc3", 97*dd7415ceSIan Rogers "EventName": "MACHINE_CLEARS.MEMORY_ORDERING", 98*dd7415ceSIan Rogers "PEBScounters": "0,1,2,3,4,5,6,7", 99*dd7415ceSIan Rogers "PublicDescription": "Counts the number of Machine Clears detected dye to memory ordering. Memory Ordering Machine Clears may apply when a memory read may not conform to the memory ordering rules of the x86 architecture", 10071fbc431SJin Yao "SampleAfterValue": "100003", 10171fbc431SJin Yao "Speculative": "1", 102*dd7415ceSIan Rogers "UMask": "0x2" 103*dd7415ceSIan Rogers }, 104*dd7415ceSIan Rogers { 105*dd7415ceSIan Rogers "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 128 cycles.", 106*dd7415ceSIan Rogers "CollectPEBSRecord": "2", 107*dd7415ceSIan Rogers "Counter": "0,1,2,3,4,5,6,7", 108*dd7415ceSIan Rogers "Data_LA": "1", 109*dd7415ceSIan Rogers "EventCode": "0xcd", 110*dd7415ceSIan Rogers "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_128", 111*dd7415ceSIan Rogers "MSRIndex": "0x3F6", 112*dd7415ceSIan Rogers "MSRValue": "0x80", 113*dd7415ceSIan Rogers "PEBS": "2", 114*dd7415ceSIan Rogers "PEBScounters": "0,1,2,3,4,5,6,7", 115*dd7415ceSIan Rogers "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 128 cycles. Reported latency may be longer than just the memory latency.", 116*dd7415ceSIan Rogers "SampleAfterValue": "1009", 117*dd7415ceSIan Rogers "TakenAlone": "1", 11871fbc431SJin Yao "UMask": "0x1" 119b115df07SHaiyan Song }, 120b115df07SHaiyan Song { 12171fbc431SJin Yao "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 16 cycles.", 122b115df07SHaiyan Song "CollectPEBSRecord": "2", 123b115df07SHaiyan Song "Counter": "0,1,2,3,4,5,6,7", 12471fbc431SJin Yao "Data_LA": "1", 12571fbc431SJin Yao "EventCode": "0xcd", 126b115df07SHaiyan Song "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_16", 127b115df07SHaiyan Song "MSRIndex": "0x3F6", 12871fbc431SJin Yao "MSRValue": "0x10", 12971fbc431SJin Yao "PEBS": "2", 13071fbc431SJin Yao "PEBScounters": "0,1,2,3,4,5,6,7", 13171fbc431SJin Yao "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 16 cycles. Reported latency may be longer than just the memory latency.", 132b115df07SHaiyan Song "SampleAfterValue": "20011", 13371fbc431SJin Yao "TakenAlone": "1", 13471fbc431SJin Yao "UMask": "0x1" 135b115df07SHaiyan Song }, 136b115df07SHaiyan Song { 137*dd7415ceSIan Rogers "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 256 cycles.", 138b115df07SHaiyan Song "CollectPEBSRecord": "2", 139*dd7415ceSIan Rogers "Counter": "0,1,2,3,4,5,6,7", 140*dd7415ceSIan Rogers "Data_LA": "1", 141*dd7415ceSIan Rogers "EventCode": "0xcd", 142*dd7415ceSIan Rogers "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_256", 143*dd7415ceSIan Rogers "MSRIndex": "0x3F6", 144*dd7415ceSIan Rogers "MSRValue": "0x100", 145*dd7415ceSIan Rogers "PEBS": "2", 146*dd7415ceSIan Rogers "PEBScounters": "0,1,2,3,4,5,6,7", 147*dd7415ceSIan Rogers "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 256 cycles. Reported latency may be longer than just the memory latency.", 148*dd7415ceSIan Rogers "SampleAfterValue": "503", 149*dd7415ceSIan Rogers "TakenAlone": "1", 15071fbc431SJin Yao "UMask": "0x1" 151b115df07SHaiyan Song }, 152b115df07SHaiyan Song { 153*dd7415ceSIan Rogers "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 32 cycles.", 154b115df07SHaiyan Song "CollectPEBSRecord": "2", 155b115df07SHaiyan Song "Counter": "0,1,2,3,4,5,6,7", 156*dd7415ceSIan Rogers "Data_LA": "1", 157*dd7415ceSIan Rogers "EventCode": "0xcd", 158*dd7415ceSIan Rogers "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_32", 159*dd7415ceSIan Rogers "MSRIndex": "0x3F6", 160*dd7415ceSIan Rogers "MSRValue": "0x20", 161*dd7415ceSIan Rogers "PEBS": "2", 162b115df07SHaiyan Song "PEBScounters": "0,1,2,3,4,5,6,7", 163*dd7415ceSIan Rogers "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 32 cycles. Reported latency may be longer than just the memory latency.", 164*dd7415ceSIan Rogers "SampleAfterValue": "100007", 165*dd7415ceSIan Rogers "TakenAlone": "1", 166*dd7415ceSIan Rogers "UMask": "0x1" 167b115df07SHaiyan Song }, 168b115df07SHaiyan Song { 169*dd7415ceSIan Rogers "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 4 cycles.", 170b115df07SHaiyan Song "CollectPEBSRecord": "2", 171b115df07SHaiyan Song "Counter": "0,1,2,3,4,5,6,7", 172*dd7415ceSIan Rogers "Data_LA": "1", 173*dd7415ceSIan Rogers "EventCode": "0xcd", 174*dd7415ceSIan Rogers "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_4", 175*dd7415ceSIan Rogers "MSRIndex": "0x3F6", 176*dd7415ceSIan Rogers "MSRValue": "0x4", 177*dd7415ceSIan Rogers "PEBS": "2", 178b115df07SHaiyan Song "PEBScounters": "0,1,2,3,4,5,6,7", 179*dd7415ceSIan Rogers "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 4 cycles. Reported latency may be longer than just the memory latency.", 18071fbc431SJin Yao "SampleAfterValue": "100003", 181*dd7415ceSIan Rogers "TakenAlone": "1", 18271fbc431SJin Yao "UMask": "0x1" 18371fbc431SJin Yao }, 18471fbc431SJin Yao { 18571fbc431SJin Yao "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 512 cycles.", 18671fbc431SJin Yao "CollectPEBSRecord": "2", 18771fbc431SJin Yao "Counter": "0,1,2,3,4,5,6,7", 18871fbc431SJin Yao "Data_LA": "1", 18971fbc431SJin Yao "EventCode": "0xcd", 190b115df07SHaiyan Song "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_512", 191b115df07SHaiyan Song "MSRIndex": "0x3F6", 19271fbc431SJin Yao "MSRValue": "0x200", 19371fbc431SJin Yao "PEBS": "2", 19471fbc431SJin Yao "PEBScounters": "0,1,2,3,4,5,6,7", 19571fbc431SJin Yao "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 512 cycles. Reported latency may be longer than just the memory latency.", 196b115df07SHaiyan Song "SampleAfterValue": "101", 19771fbc431SJin Yao "TakenAlone": "1", 19871fbc431SJin Yao "UMask": "0x1" 19971fbc431SJin Yao }, 20071fbc431SJin Yao { 201*dd7415ceSIan Rogers "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 64 cycles.", 20271fbc431SJin Yao "CollectPEBSRecord": "2", 20371fbc431SJin Yao "Counter": "0,1,2,3,4,5,6,7", 204*dd7415ceSIan Rogers "Data_LA": "1", 205*dd7415ceSIan Rogers "EventCode": "0xcd", 206*dd7415ceSIan Rogers "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_64", 207*dd7415ceSIan Rogers "MSRIndex": "0x3F6", 208*dd7415ceSIan Rogers "MSRValue": "0x40", 209*dd7415ceSIan Rogers "PEBS": "2", 21071fbc431SJin Yao "PEBScounters": "0,1,2,3,4,5,6,7", 211*dd7415ceSIan Rogers "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 64 cycles. Reported latency may be longer than just the memory latency.", 212*dd7415ceSIan Rogers "SampleAfterValue": "2003", 213*dd7415ceSIan Rogers "TakenAlone": "1", 214*dd7415ceSIan Rogers "UMask": "0x1" 21571fbc431SJin Yao }, 21671fbc431SJin Yao { 217*dd7415ceSIan Rogers "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 8 cycles.", 21871fbc431SJin Yao "CollectPEBSRecord": "2", 21971fbc431SJin Yao "Counter": "0,1,2,3,4,5,6,7", 220*dd7415ceSIan Rogers "Data_LA": "1", 221*dd7415ceSIan Rogers "EventCode": "0xcd", 222*dd7415ceSIan Rogers "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_8", 223*dd7415ceSIan Rogers "MSRIndex": "0x3F6", 224*dd7415ceSIan Rogers "MSRValue": "0x8", 225*dd7415ceSIan Rogers "PEBS": "2", 22671fbc431SJin Yao "PEBScounters": "0,1,2,3,4,5,6,7", 227*dd7415ceSIan Rogers "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 8 cycles. Reported latency may be longer than just the memory latency.", 228*dd7415ceSIan Rogers "SampleAfterValue": "50021", 229*dd7415ceSIan Rogers "TakenAlone": "1", 230*dd7415ceSIan Rogers "UMask": "0x1" 23171fbc431SJin Yao }, 23271fbc431SJin Yao { 233*dd7415ceSIan Rogers "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that was not supplied by the L3 cache.", 23471fbc431SJin Yao "CollectPEBSRecord": "2", 23571fbc431SJin Yao "Counter": "0,1,2,3", 23671fbc431SJin Yao "EventCode": "0xB7, 0xBB", 237*dd7415ceSIan Rogers "EventName": "OCR.DEMAND_CODE_RD.L3_MISS", 23871fbc431SJin Yao "MSRIndex": "0x1a6,0x1a7", 239*dd7415ceSIan Rogers "MSRValue": "0x3FFFC00004", 24071fbc431SJin Yao "Offcore": "1", 24171fbc431SJin Yao "PEBScounters": "0,1,2,3", 24271fbc431SJin Yao "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 24371fbc431SJin Yao "SampleAfterValue": "100003", 24471fbc431SJin Yao "Speculative": "1", 24571fbc431SJin Yao "UMask": "0x1" 24671fbc431SJin Yao }, 24771fbc431SJin Yao { 248*dd7415ceSIan Rogers "BriefDescription": "Counts demand data reads that was not supplied by the L3 cache.", 24971fbc431SJin Yao "CollectPEBSRecord": "2", 25071fbc431SJin Yao "Counter": "0,1,2,3", 25171fbc431SJin Yao "EventCode": "0xB7, 0xBB", 252*dd7415ceSIan Rogers "EventName": "OCR.DEMAND_DATA_RD.L3_MISS", 25371fbc431SJin Yao "MSRIndex": "0x1a6,0x1a7", 254*dd7415ceSIan Rogers "MSRValue": "0x3FFFC00001", 255*dd7415ceSIan Rogers "Offcore": "1", 256*dd7415ceSIan Rogers "PEBScounters": "0,1,2,3", 257*dd7415ceSIan Rogers "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 258*dd7415ceSIan Rogers "SampleAfterValue": "100003", 259*dd7415ceSIan Rogers "Speculative": "1", 260*dd7415ceSIan Rogers "UMask": "0x1" 261*dd7415ceSIan Rogers }, 262*dd7415ceSIan Rogers { 263*dd7415ceSIan Rogers "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that was not supplied by the L3 cache.", 264*dd7415ceSIan Rogers "CollectPEBSRecord": "2", 265*dd7415ceSIan Rogers "Counter": "0,1,2,3", 266*dd7415ceSIan Rogers "EventCode": "0xB7, 0xBB", 267*dd7415ceSIan Rogers "EventName": "OCR.DEMAND_RFO.L3_MISS", 268*dd7415ceSIan Rogers "MSRIndex": "0x1a6,0x1a7", 269*dd7415ceSIan Rogers "MSRValue": "0x3FFFC00002", 270*dd7415ceSIan Rogers "Offcore": "1", 271*dd7415ceSIan Rogers "PEBScounters": "0,1,2,3", 272*dd7415ceSIan Rogers "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 273*dd7415ceSIan Rogers "SampleAfterValue": "100003", 274*dd7415ceSIan Rogers "Speculative": "1", 275*dd7415ceSIan Rogers "UMask": "0x1" 276*dd7415ceSIan Rogers }, 277*dd7415ceSIan Rogers { 278*dd7415ceSIan Rogers "BriefDescription": "Counts L1 data cache prefetch requests and software prefetches (except PREFETCHW) that was not supplied by the L3 cache.", 279*dd7415ceSIan Rogers "CollectPEBSRecord": "2", 280*dd7415ceSIan Rogers "Counter": "0,1,2,3", 281*dd7415ceSIan Rogers "EventCode": "0xB7, 0xBB", 282*dd7415ceSIan Rogers "EventName": "OCR.HWPF_L1D_AND_SWPF.L3_MISS", 283*dd7415ceSIan Rogers "MSRIndex": "0x1a6,0x1a7", 284*dd7415ceSIan Rogers "MSRValue": "0x3FFFC00400", 285*dd7415ceSIan Rogers "Offcore": "1", 286*dd7415ceSIan Rogers "PEBScounters": "0,1,2,3", 287*dd7415ceSIan Rogers "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 288*dd7415ceSIan Rogers "SampleAfterValue": "100003", 289*dd7415ceSIan Rogers "Speculative": "1", 290*dd7415ceSIan Rogers "UMask": "0x1" 291*dd7415ceSIan Rogers }, 292*dd7415ceSIan Rogers { 293*dd7415ceSIan Rogers "BriefDescription": "Counts hardware prefetch data reads (which bring data to L2) that was not supplied by the L3 cache.", 294*dd7415ceSIan Rogers "CollectPEBSRecord": "2", 295*dd7415ceSIan Rogers "Counter": "0,1,2,3", 296*dd7415ceSIan Rogers "EventCode": "0xB7, 0xBB", 297*dd7415ceSIan Rogers "EventName": "OCR.HWPF_L2_DATA_RD.L3_MISS", 298*dd7415ceSIan Rogers "MSRIndex": "0x1a6,0x1a7", 299*dd7415ceSIan Rogers "MSRValue": "0x3FFFC00010", 30071fbc431SJin Yao "Offcore": "1", 30171fbc431SJin Yao "PEBScounters": "0,1,2,3", 30271fbc431SJin Yao "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 30371fbc431SJin Yao "SampleAfterValue": "100003", 30471fbc431SJin Yao "Speculative": "1", 30571fbc431SJin Yao "UMask": "0x1" 30671fbc431SJin Yao }, 30771fbc431SJin Yao { 30871fbc431SJin Yao "BriefDescription": "Counts hardware prefetch RFOs (which bring data to L2) that was not supplied by the L3 cache.", 30971fbc431SJin Yao "CollectPEBSRecord": "2", 31071fbc431SJin Yao "Counter": "0,1,2,3", 31171fbc431SJin Yao "EventCode": "0xB7, 0xBB", 31271fbc431SJin Yao "EventName": "OCR.HWPF_L2_RFO.L3_MISS", 31371fbc431SJin Yao "MSRIndex": "0x1a6,0x1a7", 31471fbc431SJin Yao "MSRValue": "0x3FFFC00020", 31571fbc431SJin Yao "Offcore": "1", 31671fbc431SJin Yao "PEBScounters": "0,1,2,3", 31771fbc431SJin Yao "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 31871fbc431SJin Yao "SampleAfterValue": "100003", 31971fbc431SJin Yao "Speculative": "1", 32071fbc431SJin Yao "UMask": "0x1" 32171fbc431SJin Yao }, 32271fbc431SJin Yao { 323*dd7415ceSIan Rogers "BriefDescription": "Counts miscellaneous requests, such as I/O and un-cacheable accesses that was not supplied by the L3 cache.", 324*dd7415ceSIan Rogers "CollectPEBSRecord": "2", 325*dd7415ceSIan Rogers "Counter": "0,1,2,3", 326*dd7415ceSIan Rogers "EventCode": "0xB7, 0xBB", 327*dd7415ceSIan Rogers "EventName": "OCR.OTHER.L3_MISS", 328*dd7415ceSIan Rogers "MSRIndex": "0x1a6,0x1a7", 329*dd7415ceSIan Rogers "MSRValue": "0x3FFFC08000", 330*dd7415ceSIan Rogers "Offcore": "1", 331*dd7415ceSIan Rogers "PEBScounters": "0,1,2,3", 332*dd7415ceSIan Rogers "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 333*dd7415ceSIan Rogers "SampleAfterValue": "100003", 334*dd7415ceSIan Rogers "Speculative": "1", 335*dd7415ceSIan Rogers "UMask": "0x1" 336*dd7415ceSIan Rogers }, 337*dd7415ceSIan Rogers { 338*dd7415ceSIan Rogers "BriefDescription": "Counts streaming stores that was not supplied by the L3 cache.", 339*dd7415ceSIan Rogers "CollectPEBSRecord": "2", 340*dd7415ceSIan Rogers "Counter": "0,1,2,3", 341*dd7415ceSIan Rogers "EventCode": "0xB7, 0xBB", 342*dd7415ceSIan Rogers "EventName": "OCR.STREAMING_WR.L3_MISS", 343*dd7415ceSIan Rogers "MSRIndex": "0x1a6,0x1a7", 344*dd7415ceSIan Rogers "MSRValue": "0x3FFFC00800", 345*dd7415ceSIan Rogers "Offcore": "1", 346*dd7415ceSIan Rogers "PEBScounters": "0,1,2,3", 347*dd7415ceSIan Rogers "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 348*dd7415ceSIan Rogers "SampleAfterValue": "100003", 349*dd7415ceSIan Rogers "Speculative": "1", 350*dd7415ceSIan Rogers "UMask": "0x1" 351*dd7415ceSIan Rogers }, 352*dd7415ceSIan Rogers { 353*dd7415ceSIan Rogers "BriefDescription": "Counts demand data read requests that miss the L3 cache.", 35471fbc431SJin Yao "CollectPEBSRecord": "2", 35571fbc431SJin Yao "Counter": "0,1,2,3", 35671fbc431SJin Yao "EventCode": "0xb0", 35771fbc431SJin Yao "EventName": "OFFCORE_REQUESTS.L3_MISS_DEMAND_DATA_RD", 35871fbc431SJin Yao "PEBScounters": "0,1,2,3", 35971fbc431SJin Yao "SampleAfterValue": "100003", 36071fbc431SJin Yao "Speculative": "1", 36171fbc431SJin Yao "UMask": "0x10" 36271fbc431SJin Yao }, 36371fbc431SJin Yao { 364*dd7415ceSIan Rogers "BriefDescription": "Cycles where at least one demand data read request known to have missed the L3 cache is pending.", 36571fbc431SJin Yao "CollectPEBSRecord": "2", 36671fbc431SJin Yao "Counter": "0,1,2,3", 367*dd7415ceSIan Rogers "CounterMask": "1", 368*dd7415ceSIan Rogers "EventCode": "0x60", 369*dd7415ceSIan Rogers "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_L3_MISS_DEMAND_DATA_RD", 37071fbc431SJin Yao "PEBScounters": "0,1,2,3", 371*dd7415ceSIan Rogers "PublicDescription": "Cycles where at least one demand data read request known to have missed the L3 cache is pending. Note that this does not capture all elapsed cycles while requests are outstanding - only cycles from when the requests were known to have missed the L3 cache.", 37271fbc431SJin Yao "SampleAfterValue": "1000003", 37371fbc431SJin Yao "Speculative": "1", 374*dd7415ceSIan Rogers "UMask": "0x10" 37571fbc431SJin Yao }, 37671fbc431SJin Yao { 37771fbc431SJin Yao "BriefDescription": "Number of times an RTM execution aborted.", 37871fbc431SJin Yao "CollectPEBSRecord": "2", 37971fbc431SJin Yao "Counter": "0,1,2,3,4,5,6,7", 38071fbc431SJin Yao "EventCode": "0xc9", 38171fbc431SJin Yao "EventName": "RTM_RETIRED.ABORTED", 38271fbc431SJin Yao "PEBScounters": "0,1,2,3,4,5,6,7", 38371fbc431SJin Yao "PublicDescription": "Counts the number of times RTM abort was triggered.", 38471fbc431SJin Yao "SampleAfterValue": "100003", 38571fbc431SJin Yao "UMask": "0x4" 38671fbc431SJin Yao }, 38771fbc431SJin Yao { 388*dd7415ceSIan Rogers "BriefDescription": "Number of times an RTM execution aborted due to none of the previous 4 categories (e.g. interrupt)", 389*dd7415ceSIan Rogers "CollectPEBSRecord": "2", 390*dd7415ceSIan Rogers "Counter": "0,1,2,3,4,5,6,7", 391*dd7415ceSIan Rogers "EventCode": "0xc9", 392*dd7415ceSIan Rogers "EventName": "RTM_RETIRED.ABORTED_EVENTS", 393*dd7415ceSIan Rogers "PEBScounters": "0,1,2,3,4,5,6,7", 394*dd7415ceSIan Rogers "PublicDescription": "Counts the number of times an RTM execution aborted due to none of the previous 4 categories (e.g. interrupt).", 395*dd7415ceSIan Rogers "SampleAfterValue": "100003", 396*dd7415ceSIan Rogers "UMask": "0x80" 397*dd7415ceSIan Rogers }, 398*dd7415ceSIan Rogers { 399*dd7415ceSIan Rogers "BriefDescription": "Number of times an RTM execution aborted due to various memory events (e.g. read/write capacity and conflicts)", 400*dd7415ceSIan Rogers "CollectPEBSRecord": "2", 401*dd7415ceSIan Rogers "Counter": "0,1,2,3,4,5,6,7", 402*dd7415ceSIan Rogers "EventCode": "0xc9", 403*dd7415ceSIan Rogers "EventName": "RTM_RETIRED.ABORTED_MEM", 404*dd7415ceSIan Rogers "PEBScounters": "0,1,2,3,4,5,6,7", 405*dd7415ceSIan Rogers "PublicDescription": "Counts the number of times an RTM execution aborted due to various memory events (e.g. read/write capacity and conflicts).", 406*dd7415ceSIan Rogers "SampleAfterValue": "100003", 407*dd7415ceSIan Rogers "UMask": "0x8" 408*dd7415ceSIan Rogers }, 409*dd7415ceSIan Rogers { 410*dd7415ceSIan Rogers "BriefDescription": "Number of times an RTM execution aborted due to incompatible memory type", 411*dd7415ceSIan Rogers "CollectPEBSRecord": "2", 412*dd7415ceSIan Rogers "Counter": "0,1,2,3,4,5,6,7", 413*dd7415ceSIan Rogers "EventCode": "0xc9", 414*dd7415ceSIan Rogers "EventName": "RTM_RETIRED.ABORTED_MEMTYPE", 415*dd7415ceSIan Rogers "PEBScounters": "0,1,2,3,4,5,6,7", 416*dd7415ceSIan Rogers "PublicDescription": "Counts the number of times an RTM execution aborted due to incompatible memory type.", 417*dd7415ceSIan Rogers "SampleAfterValue": "100003", 418*dd7415ceSIan Rogers "UMask": "0x40" 419*dd7415ceSIan Rogers }, 420*dd7415ceSIan Rogers { 421*dd7415ceSIan Rogers "BriefDescription": "Number of times an RTM execution aborted due to HLE-unfriendly instructions", 422*dd7415ceSIan Rogers "CollectPEBSRecord": "2", 423*dd7415ceSIan Rogers "Counter": "0,1,2,3,4,5,6,7", 424*dd7415ceSIan Rogers "EventCode": "0xc9", 425*dd7415ceSIan Rogers "EventName": "RTM_RETIRED.ABORTED_UNFRIENDLY", 426*dd7415ceSIan Rogers "PEBScounters": "0,1,2,3,4,5,6,7", 427*dd7415ceSIan Rogers "PublicDescription": "Counts the number of times an RTM execution aborted due to HLE-unfriendly instructions.", 428*dd7415ceSIan Rogers "SampleAfterValue": "100003", 429*dd7415ceSIan Rogers "UMask": "0x20" 430*dd7415ceSIan Rogers }, 431*dd7415ceSIan Rogers { 432*dd7415ceSIan Rogers "BriefDescription": "Number of times an RTM execution successfully committed", 433*dd7415ceSIan Rogers "CollectPEBSRecord": "2", 434*dd7415ceSIan Rogers "Counter": "0,1,2,3,4,5,6,7", 435*dd7415ceSIan Rogers "EventCode": "0xc9", 436*dd7415ceSIan Rogers "EventName": "RTM_RETIRED.COMMIT", 437*dd7415ceSIan Rogers "PEBScounters": "0,1,2,3,4,5,6,7", 438*dd7415ceSIan Rogers "PublicDescription": "Counts the number of times RTM commit succeeded.", 439*dd7415ceSIan Rogers "SampleAfterValue": "100003", 440*dd7415ceSIan Rogers "UMask": "0x2" 441*dd7415ceSIan Rogers }, 442*dd7415ceSIan Rogers { 44371fbc431SJin Yao "BriefDescription": "Number of times an RTM execution started.", 44471fbc431SJin Yao "CollectPEBSRecord": "2", 44571fbc431SJin Yao "Counter": "0,1,2,3,4,5,6,7", 44671fbc431SJin Yao "EventCode": "0xc9", 44771fbc431SJin Yao "EventName": "RTM_RETIRED.START", 44871fbc431SJin Yao "PEBScounters": "0,1,2,3,4,5,6,7", 44971fbc431SJin Yao "PublicDescription": "Counts the number of times we entered an RTM region. Does not count nested transactions.", 45071fbc431SJin Yao "SampleAfterValue": "100003", 45171fbc431SJin Yao "UMask": "0x1" 45271fbc431SJin Yao }, 45371fbc431SJin Yao { 454*dd7415ceSIan Rogers "BriefDescription": "Counts the number of times a class of instructions that may cause a transactional abort was executed inside a transactional region", 45571fbc431SJin Yao "CollectPEBSRecord": "2", 45671fbc431SJin Yao "Counter": "0,1,2,3,4,5,6,7", 457*dd7415ceSIan Rogers "EventCode": "0x5d", 458*dd7415ceSIan Rogers "EventName": "TX_EXEC.MISC2", 45971fbc431SJin Yao "PEBScounters": "0,1,2,3,4,5,6,7", 460*dd7415ceSIan Rogers "PublicDescription": "Counts Unfriendly TSX abort triggered by a vzeroupper instruction.", 46171fbc431SJin Yao "SampleAfterValue": "100003", 462*dd7415ceSIan Rogers "Speculative": "1", 463*dd7415ceSIan Rogers "UMask": "0x2" 464*dd7415ceSIan Rogers }, 465*dd7415ceSIan Rogers { 466*dd7415ceSIan Rogers "BriefDescription": "Number of times an instruction execution caused the transactional nest count supported to be exceeded", 467*dd7415ceSIan Rogers "CollectPEBSRecord": "2", 468*dd7415ceSIan Rogers "Counter": "0,1,2,3,4,5,6,7", 469*dd7415ceSIan Rogers "EventCode": "0x5d", 470*dd7415ceSIan Rogers "EventName": "TX_EXEC.MISC3", 471*dd7415ceSIan Rogers "PEBScounters": "0,1,2,3,4,5,6,7", 472*dd7415ceSIan Rogers "PublicDescription": "Counts Unfriendly TSX abort triggered by a nest count that is too deep.", 473*dd7415ceSIan Rogers "SampleAfterValue": "100003", 474*dd7415ceSIan Rogers "Speculative": "1", 475*dd7415ceSIan Rogers "UMask": "0x4" 476*dd7415ceSIan Rogers }, 477*dd7415ceSIan Rogers { 478*dd7415ceSIan Rogers "BriefDescription": "Speculatively counts the number of TSX aborts due to a data capacity limitation for transactional reads", 479*dd7415ceSIan Rogers "CollectPEBSRecord": "2", 480*dd7415ceSIan Rogers "Counter": "0,1,2,3", 481*dd7415ceSIan Rogers "EventCode": "0x54", 482*dd7415ceSIan Rogers "EventName": "TX_MEM.ABORT_CAPACITY_READ", 483*dd7415ceSIan Rogers "PEBScounters": "0,1,2,3", 484*dd7415ceSIan Rogers "PublicDescription": "Speculatively counts the number of Transactional Synchronization Extensions (TSX) aborts due to a data capacity limitation for transactional reads", 485*dd7415ceSIan Rogers "SampleAfterValue": "100003", 486*dd7415ceSIan Rogers "Speculative": "1", 487*dd7415ceSIan Rogers "UMask": "0x80" 488*dd7415ceSIan Rogers }, 489*dd7415ceSIan Rogers { 490*dd7415ceSIan Rogers "BriefDescription": "Speculatively counts the number of TSX aborts due to a data capacity limitation for transactional writes.", 491*dd7415ceSIan Rogers "CollectPEBSRecord": "2", 492*dd7415ceSIan Rogers "Counter": "0,1,2,3", 493*dd7415ceSIan Rogers "EventCode": "0x54", 494*dd7415ceSIan Rogers "EventName": "TX_MEM.ABORT_CAPACITY_WRITE", 495*dd7415ceSIan Rogers "PEBScounters": "0,1,2,3", 496*dd7415ceSIan Rogers "PublicDescription": "Speculatively counts the number of Transactional Synchronization Extensions (TSX) aborts due to a data capacity limitation for transactional writes.", 497*dd7415ceSIan Rogers "SampleAfterValue": "100003", 498*dd7415ceSIan Rogers "Speculative": "1", 499*dd7415ceSIan Rogers "UMask": "0x2" 500*dd7415ceSIan Rogers }, 501*dd7415ceSIan Rogers { 502*dd7415ceSIan Rogers "BriefDescription": "Number of times a transactional abort was signaled due to a data conflict on a transactionally accessed address", 503*dd7415ceSIan Rogers "CollectPEBSRecord": "2", 504*dd7415ceSIan Rogers "Counter": "0,1,2,3", 505*dd7415ceSIan Rogers "EventCode": "0x54", 506*dd7415ceSIan Rogers "EventName": "TX_MEM.ABORT_CONFLICT", 507*dd7415ceSIan Rogers "PEBScounters": "0,1,2,3", 508*dd7415ceSIan Rogers "PublicDescription": "Counts the number of times a TSX line had a cache conflict.", 509*dd7415ceSIan Rogers "SampleAfterValue": "100003", 510*dd7415ceSIan Rogers "Speculative": "1", 511*dd7415ceSIan Rogers "UMask": "0x1" 512*dd7415ceSIan Rogers }, 513*dd7415ceSIan Rogers { 514*dd7415ceSIan Rogers "BriefDescription": "Number of times an HLE transactional execution aborted due to XRELEASE lock not satisfying the address and value requirements in the elision buffer", 515*dd7415ceSIan Rogers "CollectPEBSRecord": "2", 516*dd7415ceSIan Rogers "Counter": "0,1,2,3", 517*dd7415ceSIan Rogers "EventCode": "0x54", 518*dd7415ceSIan Rogers "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_MISMATCH", 519*dd7415ceSIan Rogers "PEBScounters": "0,1,2,3", 520*dd7415ceSIan Rogers "PublicDescription": "Counts the number of times a TSX Abort was triggered due to release/commit but data and address mismatch.", 521*dd7415ceSIan Rogers "SampleAfterValue": "100003", 522*dd7415ceSIan Rogers "Speculative": "1", 523*dd7415ceSIan Rogers "UMask": "0x10" 524*dd7415ceSIan Rogers }, 525*dd7415ceSIan Rogers { 526*dd7415ceSIan Rogers "BriefDescription": "Number of times an HLE transactional execution aborted due to NoAllocatedElisionBuffer being non-zero.", 527*dd7415ceSIan Rogers "CollectPEBSRecord": "2", 528*dd7415ceSIan Rogers "Counter": "0,1,2,3", 529*dd7415ceSIan Rogers "EventCode": "0x54", 530*dd7415ceSIan Rogers "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_NOT_EMPTY", 531*dd7415ceSIan Rogers "PEBScounters": "0,1,2,3", 532*dd7415ceSIan Rogers "PublicDescription": "Counts the number of times a TSX Abort was triggered due to commit but Lock Buffer not empty.", 533*dd7415ceSIan Rogers "SampleAfterValue": "100003", 534*dd7415ceSIan Rogers "Speculative": "1", 535*dd7415ceSIan Rogers "UMask": "0x8" 536*dd7415ceSIan Rogers }, 537*dd7415ceSIan Rogers { 538*dd7415ceSIan Rogers "BriefDescription": "Number of times an HLE transactional execution aborted due to an unsupported read alignment from the elision buffer.", 539*dd7415ceSIan Rogers "CollectPEBSRecord": "2", 540*dd7415ceSIan Rogers "Counter": "0,1,2,3", 541*dd7415ceSIan Rogers "EventCode": "0x54", 542*dd7415ceSIan Rogers "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_UNSUPPORTED_ALIGNMENT", 543*dd7415ceSIan Rogers "PEBScounters": "0,1,2,3", 544*dd7415ceSIan Rogers "PublicDescription": "Counts the number of times a TSX Abort was triggered due to attempting an unsupported alignment from Lock Buffer.", 545*dd7415ceSIan Rogers "SampleAfterValue": "100003", 546*dd7415ceSIan Rogers "Speculative": "1", 54771fbc431SJin Yao "UMask": "0x20" 54871fbc431SJin Yao }, 54971fbc431SJin Yao { 55071fbc431SJin Yao "BriefDescription": "Number of times a HLE transactional region aborted due to a non XRELEASE prefixed instruction writing to an elided lock in the elision buffer", 55171fbc431SJin Yao "CollectPEBSRecord": "2", 55271fbc431SJin Yao "Counter": "0,1,2,3", 55371fbc431SJin Yao "EventCode": "0x54", 55471fbc431SJin Yao "EventName": "TX_MEM.ABORT_HLE_STORE_TO_ELIDED_LOCK", 55571fbc431SJin Yao "PEBScounters": "0,1,2,3", 55671fbc431SJin Yao "PublicDescription": "Counts the number of times a TSX Abort was triggered due to a non-release/commit store to lock.", 55771fbc431SJin Yao "SampleAfterValue": "100003", 55871fbc431SJin Yao "Speculative": "1", 55971fbc431SJin Yao "UMask": "0x4" 560*dd7415ceSIan Rogers }, 561*dd7415ceSIan Rogers { 562*dd7415ceSIan Rogers "BriefDescription": "Number of times HLE lock could not be elided due to ElisionBufferAvailable being zero.", 563*dd7415ceSIan Rogers "CollectPEBSRecord": "2", 564*dd7415ceSIan Rogers "Counter": "0,1,2,3", 565*dd7415ceSIan Rogers "EventCode": "0x54", 566*dd7415ceSIan Rogers "EventName": "TX_MEM.HLE_ELISION_BUFFER_FULL", 567*dd7415ceSIan Rogers "PEBScounters": "0,1,2,3", 568*dd7415ceSIan Rogers "PublicDescription": "Counts the number of times we could not allocate Lock Buffer.", 569*dd7415ceSIan Rogers "SampleAfterValue": "100003", 570*dd7415ceSIan Rogers "Speculative": "1", 571*dd7415ceSIan Rogers "UMask": "0x40" 572b115df07SHaiyan Song } 573b115df07SHaiyan Song]