1[
2    {
3        "BriefDescription": "Counts all microcode FP assists.",
4        "CollectPEBSRecord": "2",
5        "Counter": "0,1,2,3,4,5,6,7",
6        "EventCode": "0xc1",
7        "EventName": "ASSISTS.FP",
8        "PEBScounters": "0,1,2,3,4,5,6,7",
9        "PublicDescription": "Counts all microcode Floating Point assists.",
10        "SampleAfterValue": "100003",
11        "Speculative": "1",
12        "UMask": "0x2"
13    },
14    {
15        "BriefDescription": "Counts number of SSE/AVX computational 128-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 2 computation operations, one for each element.  Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
16        "CollectPEBSRecord": "2",
17        "Counter": "0,1,2,3,4,5,6,7",
18        "EventCode": "0xc7",
19        "EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE",
20        "PEBScounters": "0,1,2,3,4,5,6,7",
21        "PublicDescription": "Number of SSE/AVX computational 128-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 2 computation operations, one for each element.  Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
22        "SampleAfterValue": "100003",
23        "UMask": "0x4"
24    },
25    {
26        "BriefDescription": "Number of SSE/AVX computational 128-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 4 computation operations, one for each element.  Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
27        "CollectPEBSRecord": "2",
28        "Counter": "0,1,2,3,4,5,6,7",
29        "EventCode": "0xc7",
30        "EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE",
31        "PEBScounters": "0,1,2,3,4,5,6,7",
32        "PublicDescription": "Number of SSE/AVX computational 128-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 4 computation operations, one for each element.  Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
33        "SampleAfterValue": "100003",
34        "UMask": "0x8"
35    },
36    {
37        "BriefDescription": "Counts number of SSE/AVX computational 256-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 4 computation operations, one for each element.  Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT FM(N)ADD/SUB.  FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
38        "CollectPEBSRecord": "2",
39        "Counter": "0,1,2,3,4,5,6,7",
40        "EventCode": "0xc7",
41        "EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE",
42        "PEBScounters": "0,1,2,3,4,5,6,7",
43        "PublicDescription": "Number of SSE/AVX computational 256-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 4 computation operations, one for each element.  Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT FM(N)ADD/SUB.  FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
44        "SampleAfterValue": "100003",
45        "UMask": "0x10"
46    },
47    {
48        "BriefDescription": "Counts number of SSE/AVX computational 256-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 8 computation operations, one for each element.  Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
49        "CollectPEBSRecord": "2",
50        "Counter": "0,1,2,3,4,5,6,7",
51        "EventCode": "0xc7",
52        "EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE",
53        "PEBScounters": "0,1,2,3,4,5,6,7",
54        "PublicDescription": "Number of SSE/AVX computational 256-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 8 computation operations, one for each element.  Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
55        "SampleAfterValue": "100003",
56        "UMask": "0x20"
57    },
58    {
59        "BriefDescription": "Counts number of SSE/AVX computational 512-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 8 computation operations, one for each element.  Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14 RCP14 FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
60        "CollectPEBSRecord": "2",
61        "Counter": "0,1,2,3,4,5,6,7",
62        "EventCode": "0xc7",
63        "EventName": "FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE",
64        "PEBScounters": "0,1,2,3,4,5,6,7",
65        "PublicDescription": "Number of SSE/AVX computational 512-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 8 computation operations, one for each element.  Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14 RCP14 FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
66        "SampleAfterValue": "100003",
67        "UMask": "0x40"
68    },
69    {
70        "BriefDescription": "Counts number of SSE/AVX computational 512-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 16 computation operations, one for each element.  Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14 RCP14 FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
71        "CollectPEBSRecord": "2",
72        "Counter": "0,1,2,3,4,5,6,7",
73        "EventCode": "0xc7",
74        "EventName": "FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE",
75        "PEBScounters": "0,1,2,3,4,5,6,7",
76        "PublicDescription": "Number of SSE/AVX computational 512-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 16 computation operations, one for each element.  Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14 RCP14 FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
77        "SampleAfterValue": "100003",
78        "UMask": "0x80"
79    },
80    {
81        "BriefDescription": "Counts number of SSE/AVX computational scalar double precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 1 computational operation. Applies to SSE* and AVX* scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB.  FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
82        "CollectPEBSRecord": "2",
83        "Counter": "0,1,2,3,4,5,6,7",
84        "EventCode": "0xc7",
85        "EventName": "FP_ARITH_INST_RETIRED.SCALAR_DOUBLE",
86        "PEBScounters": "0,1,2,3,4,5,6,7",
87        "PublicDescription": "Number of SSE/AVX computational scalar double precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 1 computational operation. Applies to SSE* and AVX* scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB.  FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
88        "SampleAfterValue": "100003",
89        "UMask": "0x1"
90    },
91    {
92        "BriefDescription": "Counts number of SSE/AVX computational scalar single precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 1 computational operation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB.  FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
93        "CollectPEBSRecord": "2",
94        "Counter": "0,1,2,3,4,5,6,7",
95        "EventCode": "0xc7",
96        "EventName": "FP_ARITH_INST_RETIRED.SCALAR_SINGLE",
97        "PEBScounters": "0,1,2,3,4,5,6,7",
98        "PublicDescription": "Number of SSE/AVX computational scalar single precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 1 computational operation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB.  FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
99        "SampleAfterValue": "100003",
100        "UMask": "0x2"
101    }
102]