1ede00740SAndi Kleen[ 2ede00740SAndi Kleen { 3ede00740SAndi Kleen "BriefDescription": "Load misses in all DTLB levels that cause page walks", 4ede00740SAndi Kleen "Counter": "0,1,2,3", 5*f16c3236SIan Rogers "CounterHTOff": "0,1,2,3,4,5,6,7", 6*f16c3236SIan Rogers "EventCode": "0x08", 7ede00740SAndi Kleen "EventName": "DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK", 8ede00740SAndi Kleen "PublicDescription": "Misses in all TLB levels that cause a page walk of any page size.", 9ede00740SAndi Kleen "SampleAfterValue": "100003", 10*f16c3236SIan Rogers "UMask": "0x1" 11ede00740SAndi Kleen }, 12ede00740SAndi Kleen { 13ede00740SAndi Kleen "BriefDescription": "DTLB demand load misses with low part of linear-to-physical address translation missed", 14ede00740SAndi Kleen "Counter": "0,1,2,3", 15*f16c3236SIan Rogers "CounterHTOff": "0,1,2,3,4,5,6,7", 16*f16c3236SIan Rogers "EventCode": "0x08", 17ede00740SAndi Kleen "EventName": "DTLB_LOAD_MISSES.PDE_CACHE_MISS", 18ede00740SAndi Kleen "PublicDescription": "DTLB demand load misses with low part of linear-to-physical address translation missed.", 19ede00740SAndi Kleen "SampleAfterValue": "100003", 20*f16c3236SIan Rogers "UMask": "0x80" 21ede00740SAndi Kleen }, 22ede00740SAndi Kleen { 23*f16c3236SIan Rogers "BriefDescription": "Load operations that miss the first DTLB level but hit the second and do not cause page walks", 24*f16c3236SIan Rogers "Counter": "0,1,2,3", 25*f16c3236SIan Rogers "CounterHTOff": "0,1,2,3,4,5,6,7", 26*f16c3236SIan Rogers "EventCode": "0x08", 27*f16c3236SIan Rogers "EventName": "DTLB_LOAD_MISSES.STLB_HIT", 28*f16c3236SIan Rogers "PublicDescription": "Number of cache load STLB hits. No page walk.", 29*f16c3236SIan Rogers "SampleAfterValue": "2000003", 30*f16c3236SIan Rogers "UMask": "0x60" 31*f16c3236SIan Rogers }, 32*f16c3236SIan Rogers { 33*f16c3236SIan Rogers "BriefDescription": "Load misses that miss the DTLB and hit the STLB (2M)", 34*f16c3236SIan Rogers "Counter": "0,1,2,3", 35*f16c3236SIan Rogers "CounterHTOff": "0,1,2,3,4,5,6,7", 36*f16c3236SIan Rogers "EventCode": "0x08", 37*f16c3236SIan Rogers "EventName": "DTLB_LOAD_MISSES.STLB_HIT_2M", 38*f16c3236SIan Rogers "PublicDescription": "This event counts load operations from a 2M page that miss the first DTLB level but hit the second and do not cause page walks.", 39*f16c3236SIan Rogers "SampleAfterValue": "2000003", 40*f16c3236SIan Rogers "UMask": "0x40" 41*f16c3236SIan Rogers }, 42*f16c3236SIan Rogers { 43*f16c3236SIan Rogers "BriefDescription": "Load misses that miss the DTLB and hit the STLB (4K)", 44*f16c3236SIan Rogers "Counter": "0,1,2,3", 45*f16c3236SIan Rogers "CounterHTOff": "0,1,2,3,4,5,6,7", 46*f16c3236SIan Rogers "EventCode": "0x08", 47*f16c3236SIan Rogers "EventName": "DTLB_LOAD_MISSES.STLB_HIT_4K", 48*f16c3236SIan Rogers "PublicDescription": "This event counts load operations from a 4K page that miss the first DTLB level but hit the second and do not cause page walks.", 49*f16c3236SIan Rogers "SampleAfterValue": "2000003", 50*f16c3236SIan Rogers "UMask": "0x20" 51*f16c3236SIan Rogers }, 52*f16c3236SIan Rogers { 53*f16c3236SIan Rogers "BriefDescription": "Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes of any page size.", 54*f16c3236SIan Rogers "Counter": "0,1,2,3", 55*f16c3236SIan Rogers "CounterHTOff": "0,1,2,3,4,5,6,7", 56*f16c3236SIan Rogers "EventCode": "0x08", 57*f16c3236SIan Rogers "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED", 58*f16c3236SIan Rogers "PublicDescription": "Completed page walks in any TLB of any page size due to demand load misses.", 59*f16c3236SIan Rogers "SampleAfterValue": "100003", 60*f16c3236SIan Rogers "UMask": "0xe" 61*f16c3236SIan Rogers }, 62*f16c3236SIan Rogers { 63*f16c3236SIan Rogers "BriefDescription": "Load miss in all TLB levels causes a page walk that completes. (1G)", 64*f16c3236SIan Rogers "Counter": "0,1,2,3", 65*f16c3236SIan Rogers "CounterHTOff": "0,1,2,3,4,5,6,7", 66*f16c3236SIan Rogers "EventCode": "0x08", 67*f16c3236SIan Rogers "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_1G", 68*f16c3236SIan Rogers "SampleAfterValue": "2000003", 69*f16c3236SIan Rogers "UMask": "0x8" 70*f16c3236SIan Rogers }, 71*f16c3236SIan Rogers { 72*f16c3236SIan Rogers "BriefDescription": "Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes (2M/4M).", 73*f16c3236SIan Rogers "Counter": "0,1,2,3", 74*f16c3236SIan Rogers "CounterHTOff": "0,1,2,3,4,5,6,7", 75*f16c3236SIan Rogers "EventCode": "0x08", 76*f16c3236SIan Rogers "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M", 77*f16c3236SIan Rogers "PublicDescription": "Completed page walks due to demand load misses that caused 2M/4M page walks in any TLB levels.", 78*f16c3236SIan Rogers "SampleAfterValue": "2000003", 79*f16c3236SIan Rogers "UMask": "0x4" 80*f16c3236SIan Rogers }, 81*f16c3236SIan Rogers { 82*f16c3236SIan Rogers "BriefDescription": "Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes (4K).", 83*f16c3236SIan Rogers "Counter": "0,1,2,3", 84*f16c3236SIan Rogers "CounterHTOff": "0,1,2,3,4,5,6,7", 85*f16c3236SIan Rogers "EventCode": "0x08", 86*f16c3236SIan Rogers "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_4K", 87*f16c3236SIan Rogers "PublicDescription": "Completed page walks due to demand load misses that caused 4K page walks in any TLB levels.", 88*f16c3236SIan Rogers "SampleAfterValue": "2000003", 89*f16c3236SIan Rogers "UMask": "0x2" 90*f16c3236SIan Rogers }, 91*f16c3236SIan Rogers { 92*f16c3236SIan Rogers "BriefDescription": "Cycles when PMH is busy with page walks", 93*f16c3236SIan Rogers "Counter": "0,1,2,3", 94*f16c3236SIan Rogers "CounterHTOff": "0,1,2,3,4,5,6,7", 95*f16c3236SIan Rogers "EventCode": "0x08", 96*f16c3236SIan Rogers "EventName": "DTLB_LOAD_MISSES.WALK_DURATION", 97*f16c3236SIan Rogers "PublicDescription": "This event counts cycles when the page miss handler (PMH) is servicing page walks caused by DTLB load misses.", 98*f16c3236SIan Rogers "SampleAfterValue": "2000003", 99*f16c3236SIan Rogers "UMask": "0x10" 100*f16c3236SIan Rogers }, 101*f16c3236SIan Rogers { 102ede00740SAndi Kleen "BriefDescription": "Store misses in all DTLB levels that cause page walks", 103ede00740SAndi Kleen "Counter": "0,1,2,3", 104*f16c3236SIan Rogers "CounterHTOff": "0,1,2,3,4,5,6,7", 105*f16c3236SIan Rogers "EventCode": "0x49", 106ede00740SAndi Kleen "EventName": "DTLB_STORE_MISSES.MISS_CAUSES_A_WALK", 107ede00740SAndi Kleen "PublicDescription": "Miss in all TLB levels causes a page walk of any page size (4K/2M/4M/1G).", 108ede00740SAndi Kleen "SampleAfterValue": "100003", 109*f16c3236SIan Rogers "UMask": "0x1" 110ede00740SAndi Kleen }, 111ede00740SAndi Kleen { 112ede00740SAndi Kleen "BriefDescription": "DTLB store misses with low part of linear-to-physical address translation missed", 113ede00740SAndi Kleen "Counter": "0,1,2,3", 114*f16c3236SIan Rogers "CounterHTOff": "0,1,2,3,4,5,6,7", 115*f16c3236SIan Rogers "EventCode": "0x49", 116ede00740SAndi Kleen "EventName": "DTLB_STORE_MISSES.PDE_CACHE_MISS", 117ede00740SAndi Kleen "PublicDescription": "DTLB store misses with low part of linear-to-physical address translation missed.", 118ede00740SAndi Kleen "SampleAfterValue": "100003", 119*f16c3236SIan Rogers "UMask": "0x80" 120ede00740SAndi Kleen }, 121ede00740SAndi Kleen { 122*f16c3236SIan Rogers "BriefDescription": "Store operations that miss the first TLB level but hit the second and do not cause page walks", 123ede00740SAndi Kleen "Counter": "0,1,2,3", 124*f16c3236SIan Rogers "CounterHTOff": "0,1,2,3,4,5,6,7", 125*f16c3236SIan Rogers "EventCode": "0x49", 126*f16c3236SIan Rogers "EventName": "DTLB_STORE_MISSES.STLB_HIT", 127*f16c3236SIan Rogers "PublicDescription": "Store operations that miss the first TLB level but hit the second and do not cause page walks.", 128ede00740SAndi Kleen "SampleAfterValue": "100003", 129*f16c3236SIan Rogers "UMask": "0x60" 130ede00740SAndi Kleen }, 131ede00740SAndi Kleen { 132*f16c3236SIan Rogers "BriefDescription": "Store misses that miss the DTLB and hit the STLB (2M)", 133ede00740SAndi Kleen "Counter": "0,1,2,3", 134*f16c3236SIan Rogers "CounterHTOff": "0,1,2,3,4,5,6,7", 135*f16c3236SIan Rogers "EventCode": "0x49", 136*f16c3236SIan Rogers "EventName": "DTLB_STORE_MISSES.STLB_HIT_2M", 137*f16c3236SIan Rogers "PublicDescription": "This event counts store operations from a 2M page that miss the first DTLB level but hit the second and do not cause page walks.", 138ede00740SAndi Kleen "SampleAfterValue": "100003", 139*f16c3236SIan Rogers "UMask": "0x40" 140ede00740SAndi Kleen }, 141ede00740SAndi Kleen { 142*f16c3236SIan Rogers "BriefDescription": "Store misses that miss the DTLB and hit the STLB (4K)", 143ede00740SAndi Kleen "Counter": "0,1,2,3", 144*f16c3236SIan Rogers "CounterHTOff": "0,1,2,3,4,5,6,7", 145*f16c3236SIan Rogers "EventCode": "0x49", 146*f16c3236SIan Rogers "EventName": "DTLB_STORE_MISSES.STLB_HIT_4K", 147*f16c3236SIan Rogers "PublicDescription": "This event counts store operations from a 4K page that miss the first DTLB level but hit the second and do not cause page walks.", 148ede00740SAndi Kleen "SampleAfterValue": "100003", 149*f16c3236SIan Rogers "UMask": "0x20" 150ede00740SAndi Kleen }, 151ede00740SAndi Kleen { 152*f16c3236SIan Rogers "BriefDescription": "Store misses in all DTLB levels that cause completed page walks", 153ede00740SAndi Kleen "Counter": "0,1,2,3", 154*f16c3236SIan Rogers "CounterHTOff": "0,1,2,3,4,5,6,7", 155*f16c3236SIan Rogers "EventCode": "0x49", 156*f16c3236SIan Rogers "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED", 157*f16c3236SIan Rogers "PublicDescription": "Completed page walks due to store miss in any TLB levels of any page size (4K/2M/4M/1G).", 158ede00740SAndi Kleen "SampleAfterValue": "100003", 159*f16c3236SIan Rogers "UMask": "0xe" 160ede00740SAndi Kleen }, 161ede00740SAndi Kleen { 162*f16c3236SIan Rogers "BriefDescription": "Store misses in all DTLB levels that cause completed page walks. (1G)", 163032c16b2SAndi Kleen "Counter": "0,1,2,3", 164*f16c3236SIan Rogers "CounterHTOff": "0,1,2,3,4,5,6,7", 165*f16c3236SIan Rogers "EventCode": "0x49", 166*f16c3236SIan Rogers "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_1G", 167032c16b2SAndi Kleen "SampleAfterValue": "100003", 168*f16c3236SIan Rogers "UMask": "0x8" 169032c16b2SAndi Kleen }, 170032c16b2SAndi Kleen { 171*f16c3236SIan Rogers "BriefDescription": "Store misses in all DTLB levels that cause completed page walks (2M/4M)", 172*f16c3236SIan Rogers "Counter": "0,1,2,3", 173*f16c3236SIan Rogers "CounterHTOff": "0,1,2,3,4,5,6,7", 174*f16c3236SIan Rogers "EventCode": "0x49", 175*f16c3236SIan Rogers "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_2M_4M", 176*f16c3236SIan Rogers "PublicDescription": "Completed page walks due to store misses in one or more TLB levels of 2M/4M page structure.", 177*f16c3236SIan Rogers "SampleAfterValue": "100003", 178*f16c3236SIan Rogers "UMask": "0x4" 179*f16c3236SIan Rogers }, 180*f16c3236SIan Rogers { 181*f16c3236SIan Rogers "BriefDescription": "Store miss in all TLB levels causes a page walk that completes. (4K)", 182*f16c3236SIan Rogers "Counter": "0,1,2,3", 183*f16c3236SIan Rogers "CounterHTOff": "0,1,2,3,4,5,6,7", 184*f16c3236SIan Rogers "EventCode": "0x49", 185*f16c3236SIan Rogers "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_4K", 186*f16c3236SIan Rogers "PublicDescription": "Completed page walks due to store misses in one or more TLB levels of 4K page structure.", 187*f16c3236SIan Rogers "SampleAfterValue": "100003", 188*f16c3236SIan Rogers "UMask": "0x2" 189*f16c3236SIan Rogers }, 190*f16c3236SIan Rogers { 191ede00740SAndi Kleen "BriefDescription": "Cycles when PMH is busy with page walks", 192ede00740SAndi Kleen "Counter": "0,1,2,3", 193*f16c3236SIan Rogers "CounterHTOff": "0,1,2,3,4,5,6,7", 194*f16c3236SIan Rogers "EventCode": "0x49", 195*f16c3236SIan Rogers "EventName": "DTLB_STORE_MISSES.WALK_DURATION", 196*f16c3236SIan Rogers "PublicDescription": "This event counts cycles when the page miss handler (PMH) is servicing page walks caused by DTLB store misses.", 197ede00740SAndi Kleen "SampleAfterValue": "100003", 198*f16c3236SIan Rogers "UMask": "0x10" 199ede00740SAndi Kleen }, 200ede00740SAndi Kleen { 201*f16c3236SIan Rogers "BriefDescription": "Cycle count for an Extended Page table walk.", 202ede00740SAndi Kleen "Counter": "0,1,2,3", 203*f16c3236SIan Rogers "CounterHTOff": "0,1,2,3,4,5,6,7", 204*f16c3236SIan Rogers "EventCode": "0x4f", 205*f16c3236SIan Rogers "EventName": "EPT.WALK_CYCLES", 206*f16c3236SIan Rogers "SampleAfterValue": "2000003", 207*f16c3236SIan Rogers "UMask": "0x10" 208ede00740SAndi Kleen }, 209ede00740SAndi Kleen { 210ede00740SAndi Kleen "BriefDescription": "Flushing of the Instruction TLB (ITLB) pages, includes 4k/2M/4M pages.", 211ede00740SAndi Kleen "Counter": "0,1,2,3", 212*f16c3236SIan Rogers "CounterHTOff": "0,1,2,3,4,5,6,7", 213*f16c3236SIan Rogers "EventCode": "0xae", 214ede00740SAndi Kleen "EventName": "ITLB.ITLB_FLUSH", 215ede00740SAndi Kleen "PublicDescription": "Counts the number of ITLB flushes, includes 4k/2M/4M pages.", 216ede00740SAndi Kleen "SampleAfterValue": "100003", 217*f16c3236SIan Rogers "UMask": "0x1" 218ede00740SAndi Kleen }, 219ede00740SAndi Kleen { 220*f16c3236SIan Rogers "BriefDescription": "Misses at all ITLB levels that cause page walks", 221*f16c3236SIan Rogers "Counter": "0,1,2,3", 222*f16c3236SIan Rogers "CounterHTOff": "0,1,2,3,4,5,6,7", 223*f16c3236SIan Rogers "EventCode": "0x85", 224*f16c3236SIan Rogers "EventName": "ITLB_MISSES.MISS_CAUSES_A_WALK", 225*f16c3236SIan Rogers "PublicDescription": "Misses in ITLB that causes a page walk of any page size.", 226*f16c3236SIan Rogers "SampleAfterValue": "100003", 227*f16c3236SIan Rogers "UMask": "0x1" 228*f16c3236SIan Rogers }, 229*f16c3236SIan Rogers { 230*f16c3236SIan Rogers "BriefDescription": "Operations that miss the first ITLB level but hit the second and do not cause any page walks", 231*f16c3236SIan Rogers "Counter": "0,1,2,3", 232*f16c3236SIan Rogers "CounterHTOff": "0,1,2,3,4,5,6,7", 233*f16c3236SIan Rogers "EventCode": "0x85", 234*f16c3236SIan Rogers "EventName": "ITLB_MISSES.STLB_HIT", 235*f16c3236SIan Rogers "PublicDescription": "ITLB misses that hit STLB. No page walk.", 236*f16c3236SIan Rogers "SampleAfterValue": "100003", 237*f16c3236SIan Rogers "UMask": "0x60" 238*f16c3236SIan Rogers }, 239*f16c3236SIan Rogers { 240*f16c3236SIan Rogers "BriefDescription": "Code misses that miss the DTLB and hit the STLB (2M)", 241*f16c3236SIan Rogers "Counter": "0,1,2,3", 242*f16c3236SIan Rogers "CounterHTOff": "0,1,2,3,4,5,6,7", 243*f16c3236SIan Rogers "EventCode": "0x85", 244*f16c3236SIan Rogers "EventName": "ITLB_MISSES.STLB_HIT_2M", 245*f16c3236SIan Rogers "PublicDescription": "ITLB misses that hit STLB (2M).", 246*f16c3236SIan Rogers "SampleAfterValue": "100003", 247*f16c3236SIan Rogers "UMask": "0x40" 248*f16c3236SIan Rogers }, 249*f16c3236SIan Rogers { 250*f16c3236SIan Rogers "BriefDescription": "Core misses that miss the DTLB and hit the STLB (4K)", 251*f16c3236SIan Rogers "Counter": "0,1,2,3", 252*f16c3236SIan Rogers "CounterHTOff": "0,1,2,3,4,5,6,7", 253*f16c3236SIan Rogers "EventCode": "0x85", 254*f16c3236SIan Rogers "EventName": "ITLB_MISSES.STLB_HIT_4K", 255*f16c3236SIan Rogers "PublicDescription": "ITLB misses that hit STLB (4K).", 256*f16c3236SIan Rogers "SampleAfterValue": "100003", 257*f16c3236SIan Rogers "UMask": "0x20" 258*f16c3236SIan Rogers }, 259*f16c3236SIan Rogers { 260*f16c3236SIan Rogers "BriefDescription": "Misses in all ITLB levels that cause completed page walks", 261*f16c3236SIan Rogers "Counter": "0,1,2,3", 262*f16c3236SIan Rogers "CounterHTOff": "0,1,2,3,4,5,6,7", 263*f16c3236SIan Rogers "EventCode": "0x85", 264*f16c3236SIan Rogers "EventName": "ITLB_MISSES.WALK_COMPLETED", 265*f16c3236SIan Rogers "PublicDescription": "Completed page walks in ITLB of any page size.", 266*f16c3236SIan Rogers "SampleAfterValue": "100003", 267*f16c3236SIan Rogers "UMask": "0xe" 268*f16c3236SIan Rogers }, 269*f16c3236SIan Rogers { 270*f16c3236SIan Rogers "BriefDescription": "Store miss in all TLB levels causes a page walk that completes. (1G)", 271*f16c3236SIan Rogers "Counter": "0,1,2,3", 272*f16c3236SIan Rogers "CounterHTOff": "0,1,2,3,4,5,6,7", 273*f16c3236SIan Rogers "EventCode": "0x85", 274*f16c3236SIan Rogers "EventName": "ITLB_MISSES.WALK_COMPLETED_1G", 275*f16c3236SIan Rogers "SampleAfterValue": "100003", 276*f16c3236SIan Rogers "UMask": "0x8" 277*f16c3236SIan Rogers }, 278*f16c3236SIan Rogers { 279*f16c3236SIan Rogers "BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (2M/4M)", 280*f16c3236SIan Rogers "Counter": "0,1,2,3", 281*f16c3236SIan Rogers "CounterHTOff": "0,1,2,3,4,5,6,7", 282*f16c3236SIan Rogers "EventCode": "0x85", 283*f16c3236SIan Rogers "EventName": "ITLB_MISSES.WALK_COMPLETED_2M_4M", 284*f16c3236SIan Rogers "PublicDescription": "Completed page walks due to misses in ITLB 2M/4M page entries.", 285*f16c3236SIan Rogers "SampleAfterValue": "100003", 286*f16c3236SIan Rogers "UMask": "0x4" 287*f16c3236SIan Rogers }, 288*f16c3236SIan Rogers { 289*f16c3236SIan Rogers "BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (4K)", 290*f16c3236SIan Rogers "Counter": "0,1,2,3", 291*f16c3236SIan Rogers "CounterHTOff": "0,1,2,3,4,5,6,7", 292*f16c3236SIan Rogers "EventCode": "0x85", 293*f16c3236SIan Rogers "EventName": "ITLB_MISSES.WALK_COMPLETED_4K", 294*f16c3236SIan Rogers "PublicDescription": "Completed page walks due to misses in ITLB 4K page entries.", 295*f16c3236SIan Rogers "SampleAfterValue": "100003", 296*f16c3236SIan Rogers "UMask": "0x2" 297*f16c3236SIan Rogers }, 298*f16c3236SIan Rogers { 299*f16c3236SIan Rogers "BriefDescription": "Cycles when PMH is busy with page walks", 300*f16c3236SIan Rogers "Counter": "0,1,2,3", 301*f16c3236SIan Rogers "CounterHTOff": "0,1,2,3,4,5,6,7", 302*f16c3236SIan Rogers "EventCode": "0x85", 303*f16c3236SIan Rogers "EventName": "ITLB_MISSES.WALK_DURATION", 304*f16c3236SIan Rogers "PublicDescription": "This event counts cycles when the page miss handler (PMH) is servicing page walks caused by ITLB misses.", 305*f16c3236SIan Rogers "SampleAfterValue": "100003", 306*f16c3236SIan Rogers "UMask": "0x10" 307*f16c3236SIan Rogers }, 308*f16c3236SIan Rogers { 309ede00740SAndi Kleen "BriefDescription": "Number of DTLB page walker hits in the L1+FB", 310ede00740SAndi Kleen "Counter": "0,1,2,3", 311*f16c3236SIan Rogers "CounterHTOff": "0,1,2,3", 312*f16c3236SIan Rogers "EventCode": "0xBC", 313ede00740SAndi Kleen "EventName": "PAGE_WALKER_LOADS.DTLB_L1", 314ede00740SAndi Kleen "PublicDescription": "Number of DTLB page walker loads that hit in the L1+FB.", 315ede00740SAndi Kleen "SampleAfterValue": "2000003", 316*f16c3236SIan Rogers "UMask": "0x11" 317ede00740SAndi Kleen }, 318ede00740SAndi Kleen { 319ede00740SAndi Kleen "BriefDescription": "Number of DTLB page walker hits in the L2", 320ede00740SAndi Kleen "Counter": "0,1,2,3", 321*f16c3236SIan Rogers "CounterHTOff": "0,1,2,3", 322*f16c3236SIan Rogers "EventCode": "0xBC", 323ede00740SAndi Kleen "EventName": "PAGE_WALKER_LOADS.DTLB_L2", 324ede00740SAndi Kleen "PublicDescription": "Number of DTLB page walker loads that hit in the L2.", 325ede00740SAndi Kleen "SampleAfterValue": "2000003", 326*f16c3236SIan Rogers "UMask": "0x12" 327ede00740SAndi Kleen }, 328ede00740SAndi Kleen { 329ede00740SAndi Kleen "BriefDescription": "Number of DTLB page walker hits in the L3 + XSNP", 330ede00740SAndi Kleen "Counter": "0,1,2,3", 331*f16c3236SIan Rogers "CounterHTOff": "0,1,2,3", 332ede00740SAndi Kleen "Errata": "HSD25", 333*f16c3236SIan Rogers "EventCode": "0xBC", 334*f16c3236SIan Rogers "EventName": "PAGE_WALKER_LOADS.DTLB_L3", 335ede00740SAndi Kleen "PublicDescription": "Number of DTLB page walker loads that hit in the L3.", 336ede00740SAndi Kleen "SampleAfterValue": "2000003", 337*f16c3236SIan Rogers "UMask": "0x14" 338ede00740SAndi Kleen }, 339ede00740SAndi Kleen { 340ede00740SAndi Kleen "BriefDescription": "Number of DTLB page walker hits in Memory", 341ede00740SAndi Kleen "Counter": "0,1,2,3", 342*f16c3236SIan Rogers "CounterHTOff": "0,1,2,3", 343ede00740SAndi Kleen "Errata": "HSD25", 344*f16c3236SIan Rogers "EventCode": "0xBC", 345*f16c3236SIan Rogers "EventName": "PAGE_WALKER_LOADS.DTLB_MEMORY", 346ede00740SAndi Kleen "PublicDescription": "Number of DTLB page walker loads from memory.", 347ede00740SAndi Kleen "SampleAfterValue": "2000003", 348*f16c3236SIan Rogers "UMask": "0x18" 349ede00740SAndi Kleen }, 350ede00740SAndi Kleen { 351*f16c3236SIan Rogers "BriefDescription": "Counts the number of Extended Page Table walks from the DTLB that hit in the L1 and FB.", 352*f16c3236SIan Rogers "Counter": "0,1,2,3", 353*f16c3236SIan Rogers "CounterHTOff": "0,1,2,3", 354ede00740SAndi Kleen "EventCode": "0xBC", 355*f16c3236SIan Rogers "EventName": "PAGE_WALKER_LOADS.EPT_DTLB_L1", 356*f16c3236SIan Rogers "SampleAfterValue": "2000003", 357*f16c3236SIan Rogers "UMask": "0x41" 358*f16c3236SIan Rogers }, 359*f16c3236SIan Rogers { 360*f16c3236SIan Rogers "BriefDescription": "Counts the number of Extended Page Table walks from the DTLB that hit in the L2.", 361*f16c3236SIan Rogers "Counter": "0,1,2,3", 362*f16c3236SIan Rogers "CounterHTOff": "0,1,2,3", 363*f16c3236SIan Rogers "EventCode": "0xBC", 364*f16c3236SIan Rogers "EventName": "PAGE_WALKER_LOADS.EPT_DTLB_L2", 365*f16c3236SIan Rogers "SampleAfterValue": "2000003", 366*f16c3236SIan Rogers "UMask": "0x42" 367*f16c3236SIan Rogers }, 368*f16c3236SIan Rogers { 369*f16c3236SIan Rogers "BriefDescription": "Counts the number of Extended Page Table walks from the DTLB that hit in the L3.", 370*f16c3236SIan Rogers "Counter": "0,1,2,3", 371*f16c3236SIan Rogers "CounterHTOff": "0,1,2,3", 372*f16c3236SIan Rogers "EventCode": "0xBC", 373*f16c3236SIan Rogers "EventName": "PAGE_WALKER_LOADS.EPT_DTLB_L3", 374*f16c3236SIan Rogers "SampleAfterValue": "2000003", 375*f16c3236SIan Rogers "UMask": "0x44" 376*f16c3236SIan Rogers }, 377*f16c3236SIan Rogers { 378*f16c3236SIan Rogers "BriefDescription": "Counts the number of Extended Page Table walks from the DTLB that hit in memory.", 379*f16c3236SIan Rogers "Counter": "0,1,2,3", 380*f16c3236SIan Rogers "CounterHTOff": "0,1,2,3", 381*f16c3236SIan Rogers "EventCode": "0xBC", 382*f16c3236SIan Rogers "EventName": "PAGE_WALKER_LOADS.EPT_DTLB_MEMORY", 383*f16c3236SIan Rogers "SampleAfterValue": "2000003", 384*f16c3236SIan Rogers "UMask": "0x48" 385*f16c3236SIan Rogers }, 386*f16c3236SIan Rogers { 387*f16c3236SIan Rogers "BriefDescription": "Counts the number of Extended Page Table walks from the ITLB that hit in the L1 and FB.", 388*f16c3236SIan Rogers "Counter": "0,1,2,3", 389*f16c3236SIan Rogers "CounterHTOff": "0,1,2,3", 390*f16c3236SIan Rogers "EventCode": "0xBC", 391*f16c3236SIan Rogers "EventName": "PAGE_WALKER_LOADS.EPT_ITLB_L1", 392*f16c3236SIan Rogers "SampleAfterValue": "2000003", 393*f16c3236SIan Rogers "UMask": "0x81" 394*f16c3236SIan Rogers }, 395*f16c3236SIan Rogers { 396*f16c3236SIan Rogers "BriefDescription": "Counts the number of Extended Page Table walks from the ITLB that hit in the L2.", 397*f16c3236SIan Rogers "Counter": "0,1,2,3", 398*f16c3236SIan Rogers "CounterHTOff": "0,1,2,3", 399*f16c3236SIan Rogers "EventCode": "0xBC", 400*f16c3236SIan Rogers "EventName": "PAGE_WALKER_LOADS.EPT_ITLB_L2", 401*f16c3236SIan Rogers "SampleAfterValue": "2000003", 402*f16c3236SIan Rogers "UMask": "0x82" 403*f16c3236SIan Rogers }, 404*f16c3236SIan Rogers { 405*f16c3236SIan Rogers "BriefDescription": "Counts the number of Extended Page Table walks from the ITLB that hit in the L2.", 406*f16c3236SIan Rogers "Counter": "0,1,2,3", 407*f16c3236SIan Rogers "CounterHTOff": "0,1,2,3", 408*f16c3236SIan Rogers "EventCode": "0xBC", 409*f16c3236SIan Rogers "EventName": "PAGE_WALKER_LOADS.EPT_ITLB_L3", 410*f16c3236SIan Rogers "SampleAfterValue": "2000003", 411*f16c3236SIan Rogers "UMask": "0x84" 412*f16c3236SIan Rogers }, 413*f16c3236SIan Rogers { 414*f16c3236SIan Rogers "BriefDescription": "Counts the number of Extended Page Table walks from the ITLB that hit in memory.", 415*f16c3236SIan Rogers "Counter": "0,1,2,3", 416*f16c3236SIan Rogers "CounterHTOff": "0,1,2,3", 417*f16c3236SIan Rogers "EventCode": "0xBC", 418*f16c3236SIan Rogers "EventName": "PAGE_WALKER_LOADS.EPT_ITLB_MEMORY", 419*f16c3236SIan Rogers "SampleAfterValue": "2000003", 420*f16c3236SIan Rogers "UMask": "0x88" 421*f16c3236SIan Rogers }, 422*f16c3236SIan Rogers { 423032c16b2SAndi Kleen "BriefDescription": "Number of ITLB page walker hits in the L1+FB", 424032c16b2SAndi Kleen "Counter": "0,1,2,3", 425*f16c3236SIan Rogers "CounterHTOff": "0,1,2,3", 426*f16c3236SIan Rogers "EventCode": "0xBC", 427032c16b2SAndi Kleen "EventName": "PAGE_WALKER_LOADS.ITLB_L1", 428032c16b2SAndi Kleen "PublicDescription": "Number of ITLB page walker loads that hit in the L1+FB.", 429032c16b2SAndi Kleen "SampleAfterValue": "2000003", 430*f16c3236SIan Rogers "UMask": "0x21" 431032c16b2SAndi Kleen }, 432032c16b2SAndi Kleen { 433032c16b2SAndi Kleen "BriefDescription": "Number of ITLB page walker hits in the L2", 434032c16b2SAndi Kleen "Counter": "0,1,2,3", 435*f16c3236SIan Rogers "CounterHTOff": "0,1,2,3", 436*f16c3236SIan Rogers "EventCode": "0xBC", 437032c16b2SAndi Kleen "EventName": "PAGE_WALKER_LOADS.ITLB_L2", 438032c16b2SAndi Kleen "PublicDescription": "Number of ITLB page walker loads that hit in the L2.", 439032c16b2SAndi Kleen "SampleAfterValue": "2000003", 440*f16c3236SIan Rogers "UMask": "0x22" 441032c16b2SAndi Kleen }, 442032c16b2SAndi Kleen { 443032c16b2SAndi Kleen "BriefDescription": "Number of ITLB page walker hits in the L3 + XSNP", 444032c16b2SAndi Kleen "Counter": "0,1,2,3", 445*f16c3236SIan Rogers "CounterHTOff": "0,1,2,3", 446032c16b2SAndi Kleen "Errata": "HSD25", 447*f16c3236SIan Rogers "EventCode": "0xBC", 448*f16c3236SIan Rogers "EventName": "PAGE_WALKER_LOADS.ITLB_L3", 449032c16b2SAndi Kleen "PublicDescription": "Number of ITLB page walker loads that hit in the L3.", 450032c16b2SAndi Kleen "SampleAfterValue": "2000003", 451*f16c3236SIan Rogers "UMask": "0x24" 452032c16b2SAndi Kleen }, 453032c16b2SAndi Kleen { 454ede00740SAndi Kleen "BriefDescription": "Number of ITLB page walker hits in Memory", 455ede00740SAndi Kleen "Counter": "0,1,2,3", 456*f16c3236SIan Rogers "CounterHTOff": "0,1,2,3", 457ede00740SAndi Kleen "Errata": "HSD25", 458*f16c3236SIan Rogers "EventCode": "0xBC", 459*f16c3236SIan Rogers "EventName": "PAGE_WALKER_LOADS.ITLB_MEMORY", 460ede00740SAndi Kleen "PublicDescription": "Number of ITLB page walker loads from memory.", 461ede00740SAndi Kleen "SampleAfterValue": "2000003", 462*f16c3236SIan Rogers "UMask": "0x28" 463ede00740SAndi Kleen }, 464ede00740SAndi Kleen { 465ede00740SAndi Kleen "BriefDescription": "DTLB flush attempts of the thread-specific entries", 466ede00740SAndi Kleen "Counter": "0,1,2,3", 467*f16c3236SIan Rogers "CounterHTOff": "0,1,2,3,4,5,6,7", 468*f16c3236SIan Rogers "EventCode": "0xBD", 469ede00740SAndi Kleen "EventName": "TLB_FLUSH.DTLB_THREAD", 470ede00740SAndi Kleen "PublicDescription": "DTLB flush attempts of the thread-specific entries.", 471ede00740SAndi Kleen "SampleAfterValue": "100003", 472*f16c3236SIan Rogers "UMask": "0x1" 473ede00740SAndi Kleen }, 474ede00740SAndi Kleen { 475ede00740SAndi Kleen "BriefDescription": "STLB flush attempts", 476ede00740SAndi Kleen "Counter": "0,1,2,3", 477*f16c3236SIan Rogers "CounterHTOff": "0,1,2,3,4,5,6,7", 478*f16c3236SIan Rogers "EventCode": "0xBD", 479ede00740SAndi Kleen "EventName": "TLB_FLUSH.STLB_ANY", 480ede00740SAndi Kleen "PublicDescription": "Count number of STLB flush attempts.", 481ede00740SAndi Kleen "SampleAfterValue": "100003", 482*f16c3236SIan Rogers "UMask": "0x20" 483ede00740SAndi Kleen } 484ede00740SAndi Kleen]