1[ 2 { 3 "BriefDescription": "DRAM Activate Count; Activate due to Read", 4 "Counter": "0,1,2,3", 5 "EventCode": "0x1", 6 "EventName": "UNC_M_ACT_COUNT.RD", 7 "PerPkg": "1", 8 "UMask": "0x1", 9 "Unit": "iMC" 10 }, 11 { 12 "BriefDescription": "DRAM Activate Count; Activate due to Write", 13 "Counter": "0,1,2,3", 14 "EventCode": "0x1", 15 "EventName": "UNC_M_ACT_COUNT.WR", 16 "PerPkg": "1", 17 "UMask": "0x2", 18 "Unit": "iMC" 19 }, 20 { 21 "BriefDescription": "DRAM Activate Count; Activate due to Write", 22 "Counter": "0,1,2,3", 23 "EventCode": "0x1", 24 "EventName": "UNC_M_ACT_COUNT.BYP", 25 "PerPkg": "1", 26 "UMask": "0x8", 27 "Unit": "iMC" 28 }, 29 { 30 "BriefDescription": "ACT command issued by 2 cycle bypass", 31 "Counter": "0,1,2,3", 32 "EventCode": "0xA1", 33 "EventName": "UNC_M_BYP_CMDS.ACT", 34 "PerPkg": "1", 35 "UMask": "0x1", 36 "Unit": "iMC" 37 }, 38 { 39 "BriefDescription": "CAS command issued by 2 cycle bypass", 40 "Counter": "0,1,2,3", 41 "EventCode": "0xA1", 42 "EventName": "UNC_M_BYP_CMDS.CAS", 43 "PerPkg": "1", 44 "UMask": "0x2", 45 "Unit": "iMC" 46 }, 47 { 48 "BriefDescription": "PRE command issued by 2 cycle bypass", 49 "Counter": "0,1,2,3", 50 "EventCode": "0xA1", 51 "EventName": "UNC_M_BYP_CMDS.PRE", 52 "PerPkg": "1", 53 "UMask": "0x4", 54 "Unit": "iMC" 55 }, 56 { 57 "BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; All DRAM RD_CAS (w/ and w/out auto-pre)", 58 "Counter": "0,1,2,3", 59 "EventCode": "0x4", 60 "EventName": "UNC_M_CAS_COUNT.RD_REG", 61 "PerPkg": "1", 62 "UMask": "0x1", 63 "Unit": "iMC" 64 }, 65 { 66 "BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; Underfill Read Issued", 67 "Counter": "0,1,2,3", 68 "EventCode": "0x4", 69 "EventName": "UNC_M_CAS_COUNT.RD_UNDERFILL", 70 "PerPkg": "1", 71 "UMask": "0x2", 72 "Unit": "iMC" 73 }, 74 { 75 "BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; All DRAM Reads (RD_CAS + Underfills)", 76 "Counter": "0,1,2,3", 77 "EventCode": "0x4", 78 "EventName": "UNC_M_CAS_COUNT.RD", 79 "PerPkg": "1", 80 "UMask": "0x3", 81 "Unit": "iMC" 82 }, 83 { 84 "BriefDescription": "read requests to memory controller. Derived from unc_m_cas_count.rd", 85 "Counter": "0,1,2,3", 86 "EventCode": "0x4", 87 "EventName": "LLC_MISSES.MEM_READ", 88 "PerPkg": "1", 89 "ScaleUnit": "64Bytes", 90 "UMask": "0x3", 91 "Unit": "iMC" 92 }, 93 { 94 "BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; DRAM WR_CAS (w/ and w/out auto-pre) in Write Major Mode", 95 "Counter": "0,1,2,3", 96 "EventCode": "0x4", 97 "EventName": "UNC_M_CAS_COUNT.WR_WMM", 98 "PerPkg": "1", 99 "UMask": "0x4", 100 "Unit": "iMC" 101 }, 102 { 103 "BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; DRAM WR_CAS (w/ and w/out auto-pre) in Read Major Mode", 104 "Counter": "0,1,2,3", 105 "EventCode": "0x4", 106 "EventName": "UNC_M_CAS_COUNT.WR_RMM", 107 "PerPkg": "1", 108 "UMask": "0x8", 109 "Unit": "iMC" 110 }, 111 { 112 "BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; All DRAM WR_CAS (both Modes)", 113 "Counter": "0,1,2,3", 114 "EventCode": "0x4", 115 "EventName": "UNC_M_CAS_COUNT.WR", 116 "PerPkg": "1", 117 "UMask": "0xC", 118 "Unit": "iMC" 119 }, 120 { 121 "BriefDescription": "write requests to memory controller. Derived from unc_m_cas_count.wr", 122 "Counter": "0,1,2,3", 123 "EventCode": "0x4", 124 "EventName": "LLC_MISSES.MEM_WRITE", 125 "PerPkg": "1", 126 "ScaleUnit": "64Bytes", 127 "UMask": "0xC", 128 "Unit": "iMC" 129 }, 130 { 131 "BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; All DRAM WR_CAS (w/ and w/out auto-pre)", 132 "Counter": "0,1,2,3", 133 "EventCode": "0x4", 134 "EventName": "UNC_M_CAS_COUNT.ALL", 135 "PerPkg": "1", 136 "UMask": "0xF", 137 "Unit": "iMC" 138 }, 139 { 140 "BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; Read CAS issued in WMM", 141 "Counter": "0,1,2,3", 142 "EventCode": "0x4", 143 "EventName": "UNC_M_CAS_COUNT.RD_WMM", 144 "PerPkg": "1", 145 "UMask": "0x10", 146 "Unit": "iMC" 147 }, 148 { 149 "BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; Read CAS issued in RMM", 150 "Counter": "0,1,2,3", 151 "EventCode": "0x4", 152 "EventName": "UNC_M_CAS_COUNT.RD_RMM", 153 "PerPkg": "1", 154 "UMask": "0x20", 155 "Unit": "iMC" 156 }, 157 { 158 "BriefDescription": "DRAM Clockticks", 159 "Counter": "0,1,2,3", 160 "EventName": "UNC_M_CLOCKTICKS", 161 "PerPkg": "1", 162 "Unit": "iMC" 163 }, 164 { 165 "BriefDescription": "DRAM Precharge All Commands", 166 "Counter": "0,1,2,3", 167 "EventCode": "0x6", 168 "EventName": "UNC_M_DRAM_PRE_ALL", 169 "PerPkg": "1", 170 "Unit": "iMC" 171 }, 172 { 173 "BriefDescription": "Number of DRAM Refreshes Issued", 174 "Counter": "0,1,2,3", 175 "EventCode": "0x5", 176 "EventName": "UNC_M_DRAM_REFRESH.PANIC", 177 "PerPkg": "1", 178 "UMask": "0x2", 179 "Unit": "iMC" 180 }, 181 { 182 "BriefDescription": "Number of DRAM Refreshes Issued", 183 "Counter": "0,1,2,3", 184 "EventCode": "0x5", 185 "EventName": "UNC_M_DRAM_REFRESH.HIGH", 186 "PerPkg": "1", 187 "UMask": "0x4", 188 "Unit": "iMC" 189 }, 190 { 191 "BriefDescription": "ECC Correctable Errors", 192 "Counter": "0,1,2,3", 193 "EventCode": "0x9", 194 "EventName": "UNC_M_ECC_CORRECTABLE_ERRORS", 195 "PerPkg": "1", 196 "Unit": "iMC" 197 }, 198 { 199 "BriefDescription": "Cycles in a Major Mode; Read Major Mode", 200 "Counter": "0,1,2,3", 201 "EventCode": "0x7", 202 "EventName": "UNC_M_MAJOR_MODES.READ", 203 "PerPkg": "1", 204 "UMask": "0x1", 205 "Unit": "iMC" 206 }, 207 { 208 "BriefDescription": "Cycles in a Major Mode; Write Major Mode", 209 "Counter": "0,1,2,3", 210 "EventCode": "0x7", 211 "EventName": "UNC_M_MAJOR_MODES.WRITE", 212 "PerPkg": "1", 213 "UMask": "0x2", 214 "Unit": "iMC" 215 }, 216 { 217 "BriefDescription": "Cycles in a Major Mode; Partial Major Mode", 218 "Counter": "0,1,2,3", 219 "EventCode": "0x7", 220 "EventName": "UNC_M_MAJOR_MODES.PARTIAL", 221 "PerPkg": "1", 222 "UMask": "0x4", 223 "Unit": "iMC" 224 }, 225 { 226 "BriefDescription": "Cycles in a Major Mode; Isoch Major Mode", 227 "Counter": "0,1,2,3", 228 "EventCode": "0x7", 229 "EventName": "UNC_M_MAJOR_MODES.ISOCH", 230 "PerPkg": "1", 231 "UMask": "0x8", 232 "Unit": "iMC" 233 }, 234 { 235 "BriefDescription": "Channel DLLOFF Cycles", 236 "Counter": "0,1,2,3", 237 "EventCode": "0x84", 238 "EventName": "UNC_M_POWER_CHANNEL_DLLOFF", 239 "PerPkg": "1", 240 "Unit": "iMC" 241 }, 242 { 243 "BriefDescription": "Channel PPD Cycles", 244 "Counter": "0,1,2,3", 245 "EventCode": "0x85", 246 "EventName": "UNC_M_POWER_CHANNEL_PPD", 247 "PerPkg": "1", 248 "Unit": "iMC" 249 }, 250 { 251 "BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID", 252 "Counter": "0,1,2,3", 253 "EventCode": "0x83", 254 "EventName": "UNC_M_POWER_CKE_CYCLES.RANK0", 255 "PerPkg": "1", 256 "UMask": "0x1", 257 "Unit": "iMC" 258 }, 259 { 260 "BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID", 261 "Counter": "0,1,2,3", 262 "EventCode": "0x83", 263 "EventName": "UNC_M_POWER_CKE_CYCLES.RANK1", 264 "PerPkg": "1", 265 "UMask": "0x2", 266 "Unit": "iMC" 267 }, 268 { 269 "BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID", 270 "Counter": "0,1,2,3", 271 "EventCode": "0x83", 272 "EventName": "UNC_M_POWER_CKE_CYCLES.RANK2", 273 "PerPkg": "1", 274 "UMask": "0x4", 275 "Unit": "iMC" 276 }, 277 { 278 "BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID", 279 "Counter": "0,1,2,3", 280 "EventCode": "0x83", 281 "EventName": "UNC_M_POWER_CKE_CYCLES.RANK3", 282 "PerPkg": "1", 283 "UMask": "0x8", 284 "Unit": "iMC" 285 }, 286 { 287 "BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID", 288 "Counter": "0,1,2,3", 289 "EventCode": "0x83", 290 "EventName": "UNC_M_POWER_CKE_CYCLES.RANK4", 291 "PerPkg": "1", 292 "UMask": "0x10", 293 "Unit": "iMC" 294 }, 295 { 296 "BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID", 297 "Counter": "0,1,2,3", 298 "EventCode": "0x83", 299 "EventName": "UNC_M_POWER_CKE_CYCLES.RANK5", 300 "PerPkg": "1", 301 "UMask": "0x20", 302 "Unit": "iMC" 303 }, 304 { 305 "BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID", 306 "Counter": "0,1,2,3", 307 "EventCode": "0x83", 308 "EventName": "UNC_M_POWER_CKE_CYCLES.RANK6", 309 "PerPkg": "1", 310 "UMask": "0x40", 311 "Unit": "iMC" 312 }, 313 { 314 "BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID", 315 "Counter": "0,1,2,3", 316 "EventCode": "0x83", 317 "EventName": "UNC_M_POWER_CKE_CYCLES.RANK7", 318 "PerPkg": "1", 319 "UMask": "0x80", 320 "Unit": "iMC" 321 }, 322 { 323 "BriefDescription": "Critical Throttle Cycles", 324 "Counter": "0,1,2,3", 325 "EventCode": "0x86", 326 "EventName": "UNC_M_POWER_CRITICAL_THROTTLE_CYCLES", 327 "PerPkg": "1", 328 "Unit": "iMC" 329 }, 330 { 331 "BriefDescription": "UNC_M_POWER_PCU_THROTTLING", 332 "Counter": "0,1,2,3", 333 "EventCode": "0x42", 334 "EventName": "UNC_M_POWER_PCU_THROTTLING", 335 "PerPkg": "1", 336 "Unit": "iMC" 337 }, 338 { 339 "BriefDescription": "Clock-Enabled Self-Refresh", 340 "Counter": "0,1,2,3", 341 "EventCode": "0x43", 342 "EventName": "UNC_M_POWER_SELF_REFRESH", 343 "PerPkg": "1", 344 "Unit": "iMC" 345 }, 346 { 347 "BriefDescription": "Throttle Cycles for Rank 0; DIMM ID", 348 "Counter": "0,1,2,3", 349 "EventCode": "0x41", 350 "EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK0", 351 "PerPkg": "1", 352 "UMask": "0x1", 353 "Unit": "iMC" 354 }, 355 { 356 "BriefDescription": "Throttle Cycles for Rank 0; DIMM ID", 357 "Counter": "0,1,2,3", 358 "EventCode": "0x41", 359 "EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK1", 360 "PerPkg": "1", 361 "UMask": "0x2", 362 "Unit": "iMC" 363 }, 364 { 365 "BriefDescription": "Throttle Cycles for Rank 0; DIMM ID", 366 "Counter": "0,1,2,3", 367 "EventCode": "0x41", 368 "EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK2", 369 "PerPkg": "1", 370 "UMask": "0x4", 371 "Unit": "iMC" 372 }, 373 { 374 "BriefDescription": "Throttle Cycles for Rank 0; DIMM ID", 375 "Counter": "0,1,2,3", 376 "EventCode": "0x41", 377 "EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK3", 378 "PerPkg": "1", 379 "UMask": "0x8", 380 "Unit": "iMC" 381 }, 382 { 383 "BriefDescription": "Throttle Cycles for Rank 0; DIMM ID", 384 "Counter": "0,1,2,3", 385 "EventCode": "0x41", 386 "EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK4", 387 "PerPkg": "1", 388 "UMask": "0x10", 389 "Unit": "iMC" 390 }, 391 { 392 "BriefDescription": "Throttle Cycles for Rank 0; DIMM ID", 393 "Counter": "0,1,2,3", 394 "EventCode": "0x41", 395 "EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK5", 396 "PerPkg": "1", 397 "UMask": "0x20", 398 "Unit": "iMC" 399 }, 400 { 401 "BriefDescription": "Throttle Cycles for Rank 0; DIMM ID", 402 "Counter": "0,1,2,3", 403 "EventCode": "0x41", 404 "EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK6", 405 "PerPkg": "1", 406 "UMask": "0x40", 407 "Unit": "iMC" 408 }, 409 { 410 "BriefDescription": "Throttle Cycles for Rank 0; DIMM ID", 411 "Counter": "0,1,2,3", 412 "EventCode": "0x41", 413 "EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK7", 414 "PerPkg": "1", 415 "UMask": "0x80", 416 "Unit": "iMC" 417 }, 418 { 419 "BriefDescription": "Read Preemption Count; Read over Read Preemption", 420 "Counter": "0,1,2,3", 421 "EventCode": "0x8", 422 "EventName": "UNC_M_PREEMPTION.RD_PREEMPT_RD", 423 "PerPkg": "1", 424 "UMask": "0x1", 425 "Unit": "iMC" 426 }, 427 { 428 "BriefDescription": "Read Preemption Count; Read over Write Preemption", 429 "Counter": "0,1,2,3", 430 "EventCode": "0x8", 431 "EventName": "UNC_M_PREEMPTION.RD_PREEMPT_WR", 432 "PerPkg": "1", 433 "UMask": "0x2", 434 "Unit": "iMC" 435 }, 436 { 437 "BriefDescription": "DRAM Precharge commands.; Precharges due to page miss", 438 "Counter": "0,1,2,3", 439 "EventCode": "0x2", 440 "EventName": "UNC_M_PRE_COUNT.PAGE_MISS", 441 "PerPkg": "1", 442 "UMask": "0x1", 443 "Unit": "iMC" 444 }, 445 { 446 "BriefDescription": "DRAM Precharge commands.; Precharge due to timer expiration", 447 "Counter": "0,1,2,3", 448 "EventCode": "0x2", 449 "EventName": "UNC_M_PRE_COUNT.PAGE_CLOSE", 450 "PerPkg": "1", 451 "UMask": "0x2", 452 "Unit": "iMC" 453 }, 454 { 455 "BriefDescription": "DRAM Precharge commands.; Precharge due to read", 456 "Counter": "0,1,2,3", 457 "EventCode": "0x2", 458 "EventName": "UNC_M_PRE_COUNT.RD", 459 "PerPkg": "1", 460 "UMask": "0x4", 461 "Unit": "iMC" 462 }, 463 { 464 "BriefDescription": "DRAM Precharge commands.; Precharge due to write", 465 "Counter": "0,1,2,3", 466 "EventCode": "0x2", 467 "EventName": "UNC_M_PRE_COUNT.WR", 468 "PerPkg": "1", 469 "UMask": "0x8", 470 "Unit": "iMC" 471 }, 472 { 473 "BriefDescription": "DRAM Precharge commands.; Precharge due to bypass", 474 "Counter": "0,1,2,3", 475 "EventCode": "0x2", 476 "EventName": "UNC_M_PRE_COUNT.BYP", 477 "PerPkg": "1", 478 "UMask": "0x10", 479 "Unit": "iMC" 480 }, 481 { 482 "BriefDescription": "Read CAS issued with LOW priority", 483 "Counter": "0,1,2,3", 484 "EventCode": "0xA0", 485 "EventName": "UNC_M_RD_CAS_PRIO.LOW", 486 "PerPkg": "1", 487 "UMask": "0x1", 488 "Unit": "iMC" 489 }, 490 { 491 "BriefDescription": "Read CAS issued with MEDIUM priority", 492 "Counter": "0,1,2,3", 493 "EventCode": "0xA0", 494 "EventName": "UNC_M_RD_CAS_PRIO.MED", 495 "PerPkg": "1", 496 "UMask": "0x2", 497 "Unit": "iMC" 498 }, 499 { 500 "BriefDescription": "Read CAS issued with HIGH priority", 501 "Counter": "0,1,2,3", 502 "EventCode": "0xA0", 503 "EventName": "UNC_M_RD_CAS_PRIO.HIGH", 504 "PerPkg": "1", 505 "UMask": "0x4", 506 "Unit": "iMC" 507 }, 508 { 509 "BriefDescription": "Read CAS issued with PANIC NON ISOCH priority (starved)", 510 "Counter": "0,1,2,3", 511 "EventCode": "0xA0", 512 "EventName": "UNC_M_RD_CAS_PRIO.PANIC", 513 "PerPkg": "1", 514 "UMask": "0x8", 515 "Unit": "iMC" 516 }, 517 { 518 "BriefDescription": "RD_CAS Access to Rank 0; Bank 1", 519 "Counter": "0,1,2,3", 520 "EventCode": "0xB0", 521 "EventName": "UNC_M_RD_CAS_RANK0.BANK1", 522 "PerPkg": "1", 523 "UMask": "0x1", 524 "Unit": "iMC" 525 }, 526 { 527 "BriefDescription": "RD_CAS Access to Rank 0; Bank 2", 528 "Counter": "0,1,2,3", 529 "EventCode": "0xB0", 530 "EventName": "UNC_M_RD_CAS_RANK0.BANK2", 531 "PerPkg": "1", 532 "UMask": "0x2", 533 "Unit": "iMC" 534 }, 535 { 536 "BriefDescription": "RD_CAS Access to Rank 0; Bank 4", 537 "Counter": "0,1,2,3", 538 "EventCode": "0xB0", 539 "EventName": "UNC_M_RD_CAS_RANK0.BANK4", 540 "PerPkg": "1", 541 "UMask": "0x4", 542 "Unit": "iMC" 543 }, 544 { 545 "BriefDescription": "RD_CAS Access to Rank 0; Bank 8", 546 "Counter": "0,1,2,3", 547 "EventCode": "0xB0", 548 "EventName": "UNC_M_RD_CAS_RANK0.BANK8", 549 "PerPkg": "1", 550 "UMask": "0x8", 551 "Unit": "iMC" 552 }, 553 { 554 "BriefDescription": "RD_CAS Access to Rank 0; All Banks", 555 "Counter": "0,1,2,3", 556 "EventCode": "0xB0", 557 "EventName": "UNC_M_RD_CAS_RANK0.ALLBANKS", 558 "PerPkg": "1", 559 "UMask": "0x10", 560 "Unit": "iMC" 561 }, 562 { 563 "BriefDescription": "RD_CAS Access to Rank 0; Bank 0", 564 "Counter": "0,1,2,3", 565 "EventCode": "0xB0", 566 "EventName": "UNC_M_RD_CAS_RANK0.BANK0", 567 "PerPkg": "1", 568 "Unit": "iMC" 569 }, 570 { 571 "BriefDescription": "RD_CAS Access to Rank 0; Bank 3", 572 "Counter": "0,1,2,3", 573 "EventCode": "0xB0", 574 "EventName": "UNC_M_RD_CAS_RANK0.BANK3", 575 "PerPkg": "1", 576 "UMask": "0x3", 577 "Unit": "iMC" 578 }, 579 { 580 "BriefDescription": "RD_CAS Access to Rank 0; Bank 5", 581 "Counter": "0,1,2,3", 582 "EventCode": "0xB0", 583 "EventName": "UNC_M_RD_CAS_RANK0.BANK5", 584 "PerPkg": "1", 585 "UMask": "0x5", 586 "Unit": "iMC" 587 }, 588 { 589 "BriefDescription": "RD_CAS Access to Rank 0; Bank 6", 590 "Counter": "0,1,2,3", 591 "EventCode": "0xB0", 592 "EventName": "UNC_M_RD_CAS_RANK0.BANK6", 593 "PerPkg": "1", 594 "UMask": "0x6", 595 "Unit": "iMC" 596 }, 597 { 598 "BriefDescription": "RD_CAS Access to Rank 0; Bank 7", 599 "Counter": "0,1,2,3", 600 "EventCode": "0xB0", 601 "EventName": "UNC_M_RD_CAS_RANK0.BANK7", 602 "PerPkg": "1", 603 "UMask": "0x7", 604 "Unit": "iMC" 605 }, 606 { 607 "BriefDescription": "RD_CAS Access to Rank 0; Bank 9", 608 "Counter": "0,1,2,3", 609 "EventCode": "0xB0", 610 "EventName": "UNC_M_RD_CAS_RANK0.BANK9", 611 "PerPkg": "1", 612 "UMask": "0x9", 613 "Unit": "iMC" 614 }, 615 { 616 "BriefDescription": "RD_CAS Access to Rank 0; Bank 10", 617 "Counter": "0,1,2,3", 618 "EventCode": "0xB0", 619 "EventName": "UNC_M_RD_CAS_RANK0.BANK10", 620 "PerPkg": "1", 621 "UMask": "0xA", 622 "Unit": "iMC" 623 }, 624 { 625 "BriefDescription": "RD_CAS Access to Rank 0; Bank 11", 626 "Counter": "0,1,2,3", 627 "EventCode": "0xB0", 628 "EventName": "UNC_M_RD_CAS_RANK0.BANK11", 629 "PerPkg": "1", 630 "UMask": "0xB", 631 "Unit": "iMC" 632 }, 633 { 634 "BriefDescription": "RD_CAS Access to Rank 0; Bank 12", 635 "Counter": "0,1,2,3", 636 "EventCode": "0xB0", 637 "EventName": "UNC_M_RD_CAS_RANK0.BANK12", 638 "PerPkg": "1", 639 "UMask": "0xC", 640 "Unit": "iMC" 641 }, 642 { 643 "BriefDescription": "RD_CAS Access to Rank 0; Bank 13", 644 "Counter": "0,1,2,3", 645 "EventCode": "0xB0", 646 "EventName": "UNC_M_RD_CAS_RANK0.BANK13", 647 "PerPkg": "1", 648 "UMask": "0xD", 649 "Unit": "iMC" 650 }, 651 { 652 "BriefDescription": "RD_CAS Access to Rank 0; Bank 14", 653 "Counter": "0,1,2,3", 654 "EventCode": "0xB0", 655 "EventName": "UNC_M_RD_CAS_RANK0.BANK14", 656 "PerPkg": "1", 657 "UMask": "0xE", 658 "Unit": "iMC" 659 }, 660 { 661 "BriefDescription": "RD_CAS Access to Rank 0; Bank 15", 662 "Counter": "0,1,2,3", 663 "EventCode": "0xB0", 664 "EventName": "UNC_M_RD_CAS_RANK0.BANK15", 665 "PerPkg": "1", 666 "UMask": "0xF", 667 "Unit": "iMC" 668 }, 669 { 670 "BriefDescription": "RD_CAS Access to Rank 0; Bank Group 0 (Banks 0-3)", 671 "Counter": "0,1,2,3", 672 "EventCode": "0xB0", 673 "EventName": "UNC_M_RD_CAS_RANK0.BANKG0", 674 "PerPkg": "1", 675 "UMask": "0x11", 676 "Unit": "iMC" 677 }, 678 { 679 "BriefDescription": "RD_CAS Access to Rank 0; Bank Group 1 (Banks 4-7)", 680 "Counter": "0,1,2,3", 681 "EventCode": "0xB0", 682 "EventName": "UNC_M_RD_CAS_RANK0.BANKG1", 683 "PerPkg": "1", 684 "UMask": "0x12", 685 "Unit": "iMC" 686 }, 687 { 688 "BriefDescription": "RD_CAS Access to Rank 0; Bank Group 2 (Banks 8-11)", 689 "Counter": "0,1,2,3", 690 "EventCode": "0xB0", 691 "EventName": "UNC_M_RD_CAS_RANK0.BANKG2", 692 "PerPkg": "1", 693 "UMask": "0x13", 694 "Unit": "iMC" 695 }, 696 { 697 "BriefDescription": "RD_CAS Access to Rank 0; Bank Group 3 (Banks 12-15)", 698 "Counter": "0,1,2,3", 699 "EventCode": "0xB0", 700 "EventName": "UNC_M_RD_CAS_RANK0.BANKG3", 701 "PerPkg": "1", 702 "UMask": "0x14", 703 "Unit": "iMC" 704 }, 705 { 706 "BriefDescription": "RD_CAS Access to Rank 1; Bank 1", 707 "Counter": "0,1,2,3", 708 "EventCode": "0xB1", 709 "EventName": "UNC_M_RD_CAS_RANK1.BANK1", 710 "PerPkg": "1", 711 "UMask": "0x1", 712 "Unit": "iMC" 713 }, 714 { 715 "BriefDescription": "RD_CAS Access to Rank 1; Bank 2", 716 "Counter": "0,1,2,3", 717 "EventCode": "0xB1", 718 "EventName": "UNC_M_RD_CAS_RANK1.BANK2", 719 "PerPkg": "1", 720 "UMask": "0x2", 721 "Unit": "iMC" 722 }, 723 { 724 "BriefDescription": "RD_CAS Access to Rank 1; Bank 4", 725 "Counter": "0,1,2,3", 726 "EventCode": "0xB1", 727 "EventName": "UNC_M_RD_CAS_RANK1.BANK4", 728 "PerPkg": "1", 729 "UMask": "0x4", 730 "Unit": "iMC" 731 }, 732 { 733 "BriefDescription": "RD_CAS Access to Rank 1; Bank 8", 734 "Counter": "0,1,2,3", 735 "EventCode": "0xB1", 736 "EventName": "UNC_M_RD_CAS_RANK1.BANK8", 737 "PerPkg": "1", 738 "UMask": "0x8", 739 "Unit": "iMC" 740 }, 741 { 742 "BriefDescription": "RD_CAS Access to Rank 1; All Banks", 743 "Counter": "0,1,2,3", 744 "EventCode": "0xB1", 745 "EventName": "UNC_M_RD_CAS_RANK1.ALLBANKS", 746 "PerPkg": "1", 747 "UMask": "0x10", 748 "Unit": "iMC" 749 }, 750 { 751 "BriefDescription": "RD_CAS Access to Rank 1; Bank 0", 752 "Counter": "0,1,2,3", 753 "EventCode": "0xB1", 754 "EventName": "UNC_M_RD_CAS_RANK1.BANK0", 755 "PerPkg": "1", 756 "Unit": "iMC" 757 }, 758 { 759 "BriefDescription": "RD_CAS Access to Rank 1; Bank 3", 760 "Counter": "0,1,2,3", 761 "EventCode": "0xB1", 762 "EventName": "UNC_M_RD_CAS_RANK1.BANK3", 763 "PerPkg": "1", 764 "UMask": "0x3", 765 "Unit": "iMC" 766 }, 767 { 768 "BriefDescription": "RD_CAS Access to Rank 1; Bank 5", 769 "Counter": "0,1,2,3", 770 "EventCode": "0xB1", 771 "EventName": "UNC_M_RD_CAS_RANK1.BANK5", 772 "PerPkg": "1", 773 "UMask": "0x5", 774 "Unit": "iMC" 775 }, 776 { 777 "BriefDescription": "RD_CAS Access to Rank 1; Bank 6", 778 "Counter": "0,1,2,3", 779 "EventCode": "0xB1", 780 "EventName": "UNC_M_RD_CAS_RANK1.BANK6", 781 "PerPkg": "1", 782 "UMask": "0x6", 783 "Unit": "iMC" 784 }, 785 { 786 "BriefDescription": "RD_CAS Access to Rank 1; Bank 7", 787 "Counter": "0,1,2,3", 788 "EventCode": "0xB1", 789 "EventName": "UNC_M_RD_CAS_RANK1.BANK7", 790 "PerPkg": "1", 791 "UMask": "0x7", 792 "Unit": "iMC" 793 }, 794 { 795 "BriefDescription": "RD_CAS Access to Rank 1; Bank 9", 796 "Counter": "0,1,2,3", 797 "EventCode": "0xB1", 798 "EventName": "UNC_M_RD_CAS_RANK1.BANK9", 799 "PerPkg": "1", 800 "UMask": "0x9", 801 "Unit": "iMC" 802 }, 803 { 804 "BriefDescription": "RD_CAS Access to Rank 1; Bank 10", 805 "Counter": "0,1,2,3", 806 "EventCode": "0xB1", 807 "EventName": "UNC_M_RD_CAS_RANK1.BANK10", 808 "PerPkg": "1", 809 "UMask": "0xA", 810 "Unit": "iMC" 811 }, 812 { 813 "BriefDescription": "RD_CAS Access to Rank 1; Bank 11", 814 "Counter": "0,1,2,3", 815 "EventCode": "0xB1", 816 "EventName": "UNC_M_RD_CAS_RANK1.BANK11", 817 "PerPkg": "1", 818 "UMask": "0xB", 819 "Unit": "iMC" 820 }, 821 { 822 "BriefDescription": "RD_CAS Access to Rank 1; Bank 12", 823 "Counter": "0,1,2,3", 824 "EventCode": "0xB1", 825 "EventName": "UNC_M_RD_CAS_RANK1.BANK12", 826 "PerPkg": "1", 827 "UMask": "0xC", 828 "Unit": "iMC" 829 }, 830 { 831 "BriefDescription": "RD_CAS Access to Rank 1; Bank 13", 832 "Counter": "0,1,2,3", 833 "EventCode": "0xB1", 834 "EventName": "UNC_M_RD_CAS_RANK1.BANK13", 835 "PerPkg": "1", 836 "UMask": "0xD", 837 "Unit": "iMC" 838 }, 839 { 840 "BriefDescription": "RD_CAS Access to Rank 1; Bank 14", 841 "Counter": "0,1,2,3", 842 "EventCode": "0xB1", 843 "EventName": "UNC_M_RD_CAS_RANK1.BANK14", 844 "PerPkg": "1", 845 "UMask": "0xE", 846 "Unit": "iMC" 847 }, 848 { 849 "BriefDescription": "RD_CAS Access to Rank 1; Bank 15", 850 "Counter": "0,1,2,3", 851 "EventCode": "0xB1", 852 "EventName": "UNC_M_RD_CAS_RANK1.BANK15", 853 "PerPkg": "1", 854 "UMask": "0xF", 855 "Unit": "iMC" 856 }, 857 { 858 "BriefDescription": "RD_CAS Access to Rank 1; Bank Group 0 (Banks 0-3)", 859 "Counter": "0,1,2,3", 860 "EventCode": "0xB1", 861 "EventName": "UNC_M_RD_CAS_RANK1.BANKG0", 862 "PerPkg": "1", 863 "UMask": "0x11", 864 "Unit": "iMC" 865 }, 866 { 867 "BriefDescription": "RD_CAS Access to Rank 1; Bank Group 1 (Banks 4-7)", 868 "Counter": "0,1,2,3", 869 "EventCode": "0xB1", 870 "EventName": "UNC_M_RD_CAS_RANK1.BANKG1", 871 "PerPkg": "1", 872 "UMask": "0x12", 873 "Unit": "iMC" 874 }, 875 { 876 "BriefDescription": "RD_CAS Access to Rank 1; Bank Group 2 (Banks 8-11)", 877 "Counter": "0,1,2,3", 878 "EventCode": "0xB1", 879 "EventName": "UNC_M_RD_CAS_RANK1.BANKG2", 880 "PerPkg": "1", 881 "UMask": "0x13", 882 "Unit": "iMC" 883 }, 884 { 885 "BriefDescription": "RD_CAS Access to Rank 1; Bank Group 3 (Banks 12-15)", 886 "Counter": "0,1,2,3", 887 "EventCode": "0xB1", 888 "EventName": "UNC_M_RD_CAS_RANK1.BANKG3", 889 "PerPkg": "1", 890 "UMask": "0x14", 891 "Unit": "iMC" 892 }, 893 { 894 "BriefDescription": "RD_CAS Access to Rank 2; Bank 0", 895 "Counter": "0,1,2,3", 896 "EventCode": "0xB2", 897 "EventName": "UNC_M_RD_CAS_RANK2.BANK0", 898 "PerPkg": "1", 899 "Unit": "iMC" 900 }, 901 { 902 "BriefDescription": "RD_CAS Access to Rank 4; Bank 1", 903 "Counter": "0,1,2,3", 904 "EventCode": "0xB4", 905 "EventName": "UNC_M_RD_CAS_RANK4.BANK1", 906 "PerPkg": "1", 907 "UMask": "0x1", 908 "Unit": "iMC" 909 }, 910 { 911 "BriefDescription": "RD_CAS Access to Rank 4; Bank 2", 912 "Counter": "0,1,2,3", 913 "EventCode": "0xB4", 914 "EventName": "UNC_M_RD_CAS_RANK4.BANK2", 915 "PerPkg": "1", 916 "UMask": "0x2", 917 "Unit": "iMC" 918 }, 919 { 920 "BriefDescription": "RD_CAS Access to Rank 4; Bank 4", 921 "Counter": "0,1,2,3", 922 "EventCode": "0xB4", 923 "EventName": "UNC_M_RD_CAS_RANK4.BANK4", 924 "PerPkg": "1", 925 "UMask": "0x4", 926 "Unit": "iMC" 927 }, 928 { 929 "BriefDescription": "RD_CAS Access to Rank 4; Bank 8", 930 "Counter": "0,1,2,3", 931 "EventCode": "0xB4", 932 "EventName": "UNC_M_RD_CAS_RANK4.BANK8", 933 "PerPkg": "1", 934 "UMask": "0x8", 935 "Unit": "iMC" 936 }, 937 { 938 "BriefDescription": "RD_CAS Access to Rank 4; All Banks", 939 "Counter": "0,1,2,3", 940 "EventCode": "0xB4", 941 "EventName": "UNC_M_RD_CAS_RANK4.ALLBANKS", 942 "PerPkg": "1", 943 "UMask": "0x10", 944 "Unit": "iMC" 945 }, 946 { 947 "BriefDescription": "RD_CAS Access to Rank 4; Bank 0", 948 "Counter": "0,1,2,3", 949 "EventCode": "0xB4", 950 "EventName": "UNC_M_RD_CAS_RANK4.BANK0", 951 "PerPkg": "1", 952 "Unit": "iMC" 953 }, 954 { 955 "BriefDescription": "RD_CAS Access to Rank 4; Bank 3", 956 "Counter": "0,1,2,3", 957 "EventCode": "0xB4", 958 "EventName": "UNC_M_RD_CAS_RANK4.BANK3", 959 "PerPkg": "1", 960 "UMask": "0x3", 961 "Unit": "iMC" 962 }, 963 { 964 "BriefDescription": "RD_CAS Access to Rank 4; Bank 5", 965 "Counter": "0,1,2,3", 966 "EventCode": "0xB4", 967 "EventName": "UNC_M_RD_CAS_RANK4.BANK5", 968 "PerPkg": "1", 969 "UMask": "0x5", 970 "Unit": "iMC" 971 }, 972 { 973 "BriefDescription": "RD_CAS Access to Rank 4; Bank 6", 974 "Counter": "0,1,2,3", 975 "EventCode": "0xB4", 976 "EventName": "UNC_M_RD_CAS_RANK4.BANK6", 977 "PerPkg": "1", 978 "UMask": "0x6", 979 "Unit": "iMC" 980 }, 981 { 982 "BriefDescription": "RD_CAS Access to Rank 4; Bank 7", 983 "Counter": "0,1,2,3", 984 "EventCode": "0xB4", 985 "EventName": "UNC_M_RD_CAS_RANK4.BANK7", 986 "PerPkg": "1", 987 "UMask": "0x7", 988 "Unit": "iMC" 989 }, 990 { 991 "BriefDescription": "RD_CAS Access to Rank 4; Bank 9", 992 "Counter": "0,1,2,3", 993 "EventCode": "0xB4", 994 "EventName": "UNC_M_RD_CAS_RANK4.BANK9", 995 "PerPkg": "1", 996 "UMask": "0x9", 997 "Unit": "iMC" 998 }, 999 { 1000 "BriefDescription": "RD_CAS Access to Rank 4; Bank 10", 1001 "Counter": "0,1,2,3", 1002 "EventCode": "0xB4", 1003 "EventName": "UNC_M_RD_CAS_RANK4.BANK10", 1004 "PerPkg": "1", 1005 "UMask": "0xA", 1006 "Unit": "iMC" 1007 }, 1008 { 1009 "BriefDescription": "RD_CAS Access to Rank 4; Bank 11", 1010 "Counter": "0,1,2,3", 1011 "EventCode": "0xB4", 1012 "EventName": "UNC_M_RD_CAS_RANK4.BANK11", 1013 "PerPkg": "1", 1014 "UMask": "0xB", 1015 "Unit": "iMC" 1016 }, 1017 { 1018 "BriefDescription": "RD_CAS Access to Rank 4; Bank 12", 1019 "Counter": "0,1,2,3", 1020 "EventCode": "0xB4", 1021 "EventName": "UNC_M_RD_CAS_RANK4.BANK12", 1022 "PerPkg": "1", 1023 "UMask": "0xC", 1024 "Unit": "iMC" 1025 }, 1026 { 1027 "BriefDescription": "RD_CAS Access to Rank 4; Bank 13", 1028 "Counter": "0,1,2,3", 1029 "EventCode": "0xB4", 1030 "EventName": "UNC_M_RD_CAS_RANK4.BANK13", 1031 "PerPkg": "1", 1032 "UMask": "0xD", 1033 "Unit": "iMC" 1034 }, 1035 { 1036 "BriefDescription": "RD_CAS Access to Rank 4; Bank 14", 1037 "Counter": "0,1,2,3", 1038 "EventCode": "0xB4", 1039 "EventName": "UNC_M_RD_CAS_RANK4.BANK14", 1040 "PerPkg": "1", 1041 "UMask": "0xE", 1042 "Unit": "iMC" 1043 }, 1044 { 1045 "BriefDescription": "RD_CAS Access to Rank 4; Bank 15", 1046 "Counter": "0,1,2,3", 1047 "EventCode": "0xB4", 1048 "EventName": "UNC_M_RD_CAS_RANK4.BANK15", 1049 "PerPkg": "1", 1050 "UMask": "0xF", 1051 "Unit": "iMC" 1052 }, 1053 { 1054 "BriefDescription": "RD_CAS Access to Rank 4; Bank Group 0 (Banks 0-3)", 1055 "Counter": "0,1,2,3", 1056 "EventCode": "0xB4", 1057 "EventName": "UNC_M_RD_CAS_RANK4.BANKG0", 1058 "PerPkg": "1", 1059 "UMask": "0x11", 1060 "Unit": "iMC" 1061 }, 1062 { 1063 "BriefDescription": "RD_CAS Access to Rank 4; Bank Group 1 (Banks 4-7)", 1064 "Counter": "0,1,2,3", 1065 "EventCode": "0xB4", 1066 "EventName": "UNC_M_RD_CAS_RANK4.BANKG1", 1067 "PerPkg": "1", 1068 "UMask": "0x12", 1069 "Unit": "iMC" 1070 }, 1071 { 1072 "BriefDescription": "RD_CAS Access to Rank 4; Bank Group 2 (Banks 8-11)", 1073 "Counter": "0,1,2,3", 1074 "EventCode": "0xB4", 1075 "EventName": "UNC_M_RD_CAS_RANK4.BANKG2", 1076 "PerPkg": "1", 1077 "UMask": "0x13", 1078 "Unit": "iMC" 1079 }, 1080 { 1081 "BriefDescription": "RD_CAS Access to Rank 4; Bank Group 3 (Banks 12-15)", 1082 "Counter": "0,1,2,3", 1083 "EventCode": "0xB4", 1084 "EventName": "UNC_M_RD_CAS_RANK4.BANKG3", 1085 "PerPkg": "1", 1086 "UMask": "0x14", 1087 "Unit": "iMC" 1088 }, 1089 { 1090 "BriefDescription": "RD_CAS Access to Rank 5; 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Bank 0", 1136 "Counter": "0,1,2,3", 1137 "EventCode": "0xB5", 1138 "EventName": "UNC_M_RD_CAS_RANK5.BANK0", 1139 "PerPkg": "1", 1140 "Unit": "iMC" 1141 }, 1142 { 1143 "BriefDescription": "RD_CAS Access to Rank 5; Bank 3", 1144 "Counter": "0,1,2,3", 1145 "EventCode": "0xB5", 1146 "EventName": "UNC_M_RD_CAS_RANK5.BANK3", 1147 "PerPkg": "1", 1148 "UMask": "0x3", 1149 "Unit": "iMC" 1150 }, 1151 { 1152 "BriefDescription": "RD_CAS Access to Rank 5; Bank 5", 1153 "Counter": "0,1,2,3", 1154 "EventCode": "0xB5", 1155 "EventName": "UNC_M_RD_CAS_RANK5.BANK5", 1156 "PerPkg": "1", 1157 "UMask": "0x5", 1158 "Unit": "iMC" 1159 }, 1160 { 1161 "BriefDescription": "RD_CAS Access to Rank 5; Bank 6", 1162 "Counter": "0,1,2,3", 1163 "EventCode": "0xB5", 1164 "EventName": "UNC_M_RD_CAS_RANK5.BANK6", 1165 "PerPkg": "1", 1166 "UMask": "0x6", 1167 "Unit": "iMC" 1168 }, 1169 { 1170 "BriefDescription": "RD_CAS Access to Rank 5; Bank 7", 1171 "Counter": "0,1,2,3", 1172 "EventCode": "0xB5", 1173 "EventName": "UNC_M_RD_CAS_RANK5.BANK7", 1174 "PerPkg": "1", 1175 "UMask": "0x7", 1176 "Unit": "iMC" 1177 }, 1178 { 1179 "BriefDescription": "RD_CAS Access to Rank 5; Bank 9", 1180 "Counter": "0,1,2,3", 1181 "EventCode": "0xB5", 1182 "EventName": "UNC_M_RD_CAS_RANK5.BANK9", 1183 "PerPkg": "1", 1184 "UMask": "0x9", 1185 "Unit": "iMC" 1186 }, 1187 { 1188 "BriefDescription": "RD_CAS Access to Rank 5; Bank 10", 1189 "Counter": "0,1,2,3", 1190 "EventCode": "0xB5", 1191 "EventName": "UNC_M_RD_CAS_RANK5.BANK10", 1192 "PerPkg": "1", 1193 "UMask": "0xA", 1194 "Unit": "iMC" 1195 }, 1196 { 1197 "BriefDescription": "RD_CAS Access to Rank 5; Bank 11", 1198 "Counter": "0,1,2,3", 1199 "EventCode": "0xB5", 1200 "EventName": "UNC_M_RD_CAS_RANK5.BANK11", 1201 "PerPkg": "1", 1202 "UMask": "0xB", 1203 "Unit": "iMC" 1204 }, 1205 { 1206 "BriefDescription": "RD_CAS Access to Rank 5; Bank 12", 1207 "Counter": "0,1,2,3", 1208 "EventCode": "0xB5", 1209 "EventName": "UNC_M_RD_CAS_RANK5.BANK12", 1210 "PerPkg": "1", 1211 "UMask": "0xC", 1212 "Unit": "iMC" 1213 }, 1214 { 1215 "BriefDescription": "RD_CAS Access to Rank 5; Bank 13", 1216 "Counter": "0,1,2,3", 1217 "EventCode": "0xB5", 1218 "EventName": "UNC_M_RD_CAS_RANK5.BANK13", 1219 "PerPkg": "1", 1220 "UMask": "0xD", 1221 "Unit": "iMC" 1222 }, 1223 { 1224 "BriefDescription": "RD_CAS Access to Rank 5; Bank 14", 1225 "Counter": "0,1,2,3", 1226 "EventCode": "0xB5", 1227 "EventName": "UNC_M_RD_CAS_RANK5.BANK14", 1228 "PerPkg": "1", 1229 "UMask": "0xE", 1230 "Unit": "iMC" 1231 }, 1232 { 1233 "BriefDescription": "RD_CAS Access to Rank 5; Bank 15", 1234 "Counter": "0,1,2,3", 1235 "EventCode": "0xB5", 1236 "EventName": "UNC_M_RD_CAS_RANK5.BANK15", 1237 "PerPkg": "1", 1238 "UMask": "0xF", 1239 "Unit": "iMC" 1240 }, 1241 { 1242 "BriefDescription": "RD_CAS Access to Rank 5; Bank Group 0 (Banks 0-3)", 1243 "Counter": "0,1,2,3", 1244 "EventCode": "0xB5", 1245 "EventName": "UNC_M_RD_CAS_RANK5.BANKG0", 1246 "PerPkg": "1", 1247 "UMask": "0x11", 1248 "Unit": "iMC" 1249 }, 1250 { 1251 "BriefDescription": "RD_CAS Access to Rank 5; Bank Group 1 (Banks 4-7)", 1252 "Counter": "0,1,2,3", 1253 "EventCode": "0xB5", 1254 "EventName": "UNC_M_RD_CAS_RANK5.BANKG1", 1255 "PerPkg": "1", 1256 "UMask": "0x12", 1257 "Unit": "iMC" 1258 }, 1259 { 1260 "BriefDescription": "RD_CAS Access to Rank 5; Bank Group 2 (Banks 8-11)", 1261 "Counter": "0,1,2,3", 1262 "EventCode": "0xB5", 1263 "EventName": "UNC_M_RD_CAS_RANK5.BANKG2", 1264 "PerPkg": "1", 1265 "UMask": "0x13", 1266 "Unit": "iMC" 1267 }, 1268 { 1269 "BriefDescription": "RD_CAS Access to Rank 5; Bank Group 3 (Banks 12-15)", 1270 "Counter": "0,1,2,3", 1271 "EventCode": "0xB5", 1272 "EventName": "UNC_M_RD_CAS_RANK5.BANKG3", 1273 "PerPkg": "1", 1274 "UMask": "0x14", 1275 "Unit": "iMC" 1276 }, 1277 { 1278 "BriefDescription": "RD_CAS Access to Rank 6; Bank 1", 1279 "Counter": "0,1,2,3", 1280 "EventCode": "0xB6", 1281 "EventName": "UNC_M_RD_CAS_RANK6.BANK1", 1282 "PerPkg": "1", 1283 "UMask": "0x1", 1284 "Unit": "iMC" 1285 }, 1286 { 1287 "BriefDescription": "RD_CAS Access to Rank 6; Bank 2", 1288 "Counter": "0,1,2,3", 1289 "EventCode": "0xB6", 1290 "EventName": "UNC_M_RD_CAS_RANK6.BANK2", 1291 "PerPkg": "1", 1292 "UMask": "0x2", 1293 "Unit": "iMC" 1294 }, 1295 { 1296 "BriefDescription": "RD_CAS Access to Rank 6; Bank 4", 1297 "Counter": "0,1,2,3", 1298 "EventCode": "0xB6", 1299 "EventName": "UNC_M_RD_CAS_RANK6.BANK4", 1300 "PerPkg": "1", 1301 "UMask": "0x4", 1302 "Unit": "iMC" 1303 }, 1304 { 1305 "BriefDescription": "RD_CAS Access to Rank 6; Bank 8", 1306 "Counter": "0,1,2,3", 1307 "EventCode": "0xB6", 1308 "EventName": "UNC_M_RD_CAS_RANK6.BANK8", 1309 "PerPkg": "1", 1310 "UMask": "0x8", 1311 "Unit": "iMC" 1312 }, 1313 { 1314 "BriefDescription": "RD_CAS Access to Rank 6; All Banks", 1315 "Counter": "0,1,2,3", 1316 "EventCode": "0xB6", 1317 "EventName": "UNC_M_RD_CAS_RANK6.ALLBANKS", 1318 "PerPkg": "1", 1319 "UMask": "0x10", 1320 "Unit": "iMC" 1321 }, 1322 { 1323 "BriefDescription": "RD_CAS Access to Rank 6; Bank 0", 1324 "Counter": "0,1,2,3", 1325 "EventCode": "0xB6", 1326 "EventName": "UNC_M_RD_CAS_RANK6.BANK0", 1327 "PerPkg": "1", 1328 "Unit": "iMC" 1329 }, 1330 { 1331 "BriefDescription": "RD_CAS Access to Rank 6; Bank 3", 1332 "Counter": "0,1,2,3", 1333 "EventCode": "0xB6", 1334 "EventName": "UNC_M_RD_CAS_RANK6.BANK3", 1335 "PerPkg": "1", 1336 "UMask": "0x3", 1337 "Unit": "iMC" 1338 }, 1339 { 1340 "BriefDescription": "RD_CAS Access to Rank 6; Bank 5", 1341 "Counter": "0,1,2,3", 1342 "EventCode": "0xB6", 1343 "EventName": "UNC_M_RD_CAS_RANK6.BANK5", 1344 "PerPkg": "1", 1345 "UMask": "0x5", 1346 "Unit": "iMC" 1347 }, 1348 { 1349 "BriefDescription": "RD_CAS Access to Rank 6; Bank 6", 1350 "Counter": "0,1,2,3", 1351 "EventCode": "0xB6", 1352 "EventName": "UNC_M_RD_CAS_RANK6.BANK6", 1353 "PerPkg": "1", 1354 "UMask": "0x6", 1355 "Unit": "iMC" 1356 }, 1357 { 1358 "BriefDescription": "RD_CAS Access to Rank 6; Bank 7", 1359 "Counter": "0,1,2,3", 1360 "EventCode": "0xB6", 1361 "EventName": "UNC_M_RD_CAS_RANK6.BANK7", 1362 "PerPkg": "1", 1363 "UMask": "0x7", 1364 "Unit": "iMC" 1365 }, 1366 { 1367 "BriefDescription": "RD_CAS Access to Rank 6; Bank 9", 1368 "Counter": "0,1,2,3", 1369 "EventCode": "0xB6", 1370 "EventName": "UNC_M_RD_CAS_RANK6.BANK9", 1371 "PerPkg": "1", 1372 "UMask": "0x9", 1373 "Unit": "iMC" 1374 }, 1375 { 1376 "BriefDescription": "RD_CAS Access to Rank 6; Bank 10", 1377 "Counter": "0,1,2,3", 1378 "EventCode": "0xB6", 1379 "EventName": "UNC_M_RD_CAS_RANK6.BANK10", 1380 "PerPkg": "1", 1381 "UMask": "0xA", 1382 "Unit": "iMC" 1383 }, 1384 { 1385 "BriefDescription": "RD_CAS Access to Rank 6; Bank 11", 1386 "Counter": "0,1,2,3", 1387 "EventCode": "0xB6", 1388 "EventName": "UNC_M_RD_CAS_RANK6.BANK11", 1389 "PerPkg": "1", 1390 "UMask": "0xB", 1391 "Unit": "iMC" 1392 }, 1393 { 1394 "BriefDescription": "RD_CAS Access to Rank 6; Bank 12", 1395 "Counter": "0,1,2,3", 1396 "EventCode": "0xB6", 1397 "EventName": "UNC_M_RD_CAS_RANK6.BANK12", 1398 "PerPkg": "1", 1399 "UMask": "0xC", 1400 "Unit": "iMC" 1401 }, 1402 { 1403 "BriefDescription": "RD_CAS Access to Rank 6; Bank 13", 1404 "Counter": "0,1,2,3", 1405 "EventCode": "0xB6", 1406 "EventName": "UNC_M_RD_CAS_RANK6.BANK13", 1407 "PerPkg": "1", 1408 "UMask": "0xD", 1409 "Unit": "iMC" 1410 }, 1411 { 1412 "BriefDescription": "RD_CAS Access to Rank 6; Bank 14", 1413 "Counter": "0,1,2,3", 1414 "EventCode": "0xB6", 1415 "EventName": "UNC_M_RD_CAS_RANK6.BANK14", 1416 "PerPkg": "1", 1417 "UMask": "0xE", 1418 "Unit": "iMC" 1419 }, 1420 { 1421 "BriefDescription": "RD_CAS Access to Rank 6; Bank 15", 1422 "Counter": "0,1,2,3", 1423 "EventCode": "0xB6", 1424 "EventName": "UNC_M_RD_CAS_RANK6.BANK15", 1425 "PerPkg": "1", 1426 "UMask": "0xF", 1427 "Unit": "iMC" 1428 }, 1429 { 1430 "BriefDescription": "RD_CAS Access to Rank 6; Bank Group 0 (Banks 0-3)", 1431 "Counter": "0,1,2,3", 1432 "EventCode": "0xB6", 1433 "EventName": "UNC_M_RD_CAS_RANK6.BANKG0", 1434 "PerPkg": "1", 1435 "UMask": "0x11", 1436 "Unit": "iMC" 1437 }, 1438 { 1439 "BriefDescription": "RD_CAS Access to Rank 6; Bank Group 1 (Banks 4-7)", 1440 "Counter": "0,1,2,3", 1441 "EventCode": "0xB6", 1442 "EventName": "UNC_M_RD_CAS_RANK6.BANKG1", 1443 "PerPkg": "1", 1444 "UMask": "0x12", 1445 "Unit": "iMC" 1446 }, 1447 { 1448 "BriefDescription": "RD_CAS Access to Rank 6; Bank Group 2 (Banks 8-11)", 1449 "Counter": "0,1,2,3", 1450 "EventCode": "0xB6", 1451 "EventName": "UNC_M_RD_CAS_RANK6.BANKG2", 1452 "PerPkg": "1", 1453 "UMask": "0x13", 1454 "Unit": "iMC" 1455 }, 1456 { 1457 "BriefDescription": "RD_CAS Access to Rank 6; Bank Group 3 (Banks 12-15)", 1458 "Counter": "0,1,2,3", 1459 "EventCode": "0xB6", 1460 "EventName": "UNC_M_RD_CAS_RANK6.BANKG3", 1461 "PerPkg": "1", 1462 "UMask": "0x14", 1463 "Unit": "iMC" 1464 }, 1465 { 1466 "BriefDescription": "RD_CAS Access to Rank 7; Bank 1", 1467 "Counter": "0,1,2,3", 1468 "EventCode": "0xB7", 1469 "EventName": "UNC_M_RD_CAS_RANK7.BANK1", 1470 "PerPkg": "1", 1471 "UMask": "0x1", 1472 "Unit": "iMC" 1473 }, 1474 { 1475 "BriefDescription": "RD_CAS Access to Rank 7; Bank 2", 1476 "Counter": "0,1,2,3", 1477 "EventCode": "0xB7", 1478 "EventName": "UNC_M_RD_CAS_RANK7.BANK2", 1479 "PerPkg": "1", 1480 "UMask": "0x2", 1481 "Unit": "iMC" 1482 }, 1483 { 1484 "BriefDescription": "RD_CAS Access to Rank 7; Bank 4", 1485 "Counter": "0,1,2,3", 1486 "EventCode": "0xB7", 1487 "EventName": "UNC_M_RD_CAS_RANK7.BANK4", 1488 "PerPkg": "1", 1489 "UMask": "0x4", 1490 "Unit": "iMC" 1491 }, 1492 { 1493 "BriefDescription": "RD_CAS Access to Rank 7; Bank 8", 1494 "Counter": "0,1,2,3", 1495 "EventCode": "0xB7", 1496 "EventName": "UNC_M_RD_CAS_RANK7.BANK8", 1497 "PerPkg": "1", 1498 "UMask": "0x8", 1499 "Unit": "iMC" 1500 }, 1501 { 1502 "BriefDescription": "RD_CAS Access to Rank 7; All Banks", 1503 "Counter": "0,1,2,3", 1504 "EventCode": "0xB7", 1505 "EventName": "UNC_M_RD_CAS_RANK7.ALLBANKS", 1506 "PerPkg": "1", 1507 "UMask": "0x10", 1508 "Unit": "iMC" 1509 }, 1510 { 1511 "BriefDescription": "RD_CAS Access to Rank 7; Bank 0", 1512 "Counter": "0,1,2,3", 1513 "EventCode": "0xB7", 1514 "EventName": "UNC_M_RD_CAS_RANK7.BANK0", 1515 "PerPkg": "1", 1516 "Unit": "iMC" 1517 }, 1518 { 1519 "BriefDescription": "RD_CAS Access to Rank 7; Bank 3", 1520 "Counter": "0,1,2,3", 1521 "EventCode": "0xB7", 1522 "EventName": "UNC_M_RD_CAS_RANK7.BANK3", 1523 "PerPkg": "1", 1524 "UMask": "0x3", 1525 "Unit": "iMC" 1526 }, 1527 { 1528 "BriefDescription": "RD_CAS Access to Rank 7; Bank 5", 1529 "Counter": "0,1,2,3", 1530 "EventCode": "0xB7", 1531 "EventName": "UNC_M_RD_CAS_RANK7.BANK5", 1532 "PerPkg": "1", 1533 "UMask": "0x5", 1534 "Unit": "iMC" 1535 }, 1536 { 1537 "BriefDescription": "RD_CAS Access to Rank 7; Bank 6", 1538 "Counter": "0,1,2,3", 1539 "EventCode": "0xB7", 1540 "EventName": "UNC_M_RD_CAS_RANK7.BANK6", 1541 "PerPkg": "1", 1542 "UMask": "0x6", 1543 "Unit": "iMC" 1544 }, 1545 { 1546 "BriefDescription": "RD_CAS Access to Rank 7; Bank 7", 1547 "Counter": "0,1,2,3", 1548 "EventCode": "0xB7", 1549 "EventName": "UNC_M_RD_CAS_RANK7.BANK7", 1550 "PerPkg": "1", 1551 "UMask": "0x7", 1552 "Unit": "iMC" 1553 }, 1554 { 1555 "BriefDescription": "RD_CAS Access to Rank 7; Bank 9", 1556 "Counter": "0,1,2,3", 1557 "EventCode": "0xB7", 1558 "EventName": "UNC_M_RD_CAS_RANK7.BANK9", 1559 "PerPkg": "1", 1560 "UMask": "0x9", 1561 "Unit": "iMC" 1562 }, 1563 { 1564 "BriefDescription": "RD_CAS Access to Rank 7; Bank 10", 1565 "Counter": "0,1,2,3", 1566 "EventCode": "0xB7", 1567 "EventName": "UNC_M_RD_CAS_RANK7.BANK10", 1568 "PerPkg": "1", 1569 "UMask": "0xA", 1570 "Unit": "iMC" 1571 }, 1572 { 1573 "BriefDescription": "RD_CAS Access to Rank 7; Bank 11", 1574 "Counter": "0,1,2,3", 1575 "EventCode": "0xB7", 1576 "EventName": "UNC_M_RD_CAS_RANK7.BANK11", 1577 "PerPkg": "1", 1578 "UMask": "0xB", 1579 "Unit": "iMC" 1580 }, 1581 { 1582 "BriefDescription": "RD_CAS Access to Rank 7; Bank 12", 1583 "Counter": "0,1,2,3", 1584 "EventCode": "0xB7", 1585 "EventName": "UNC_M_RD_CAS_RANK7.BANK12", 1586 "PerPkg": "1", 1587 "UMask": "0xC", 1588 "Unit": "iMC" 1589 }, 1590 { 1591 "BriefDescription": "RD_CAS Access to Rank 7; Bank 13", 1592 "Counter": "0,1,2,3", 1593 "EventCode": "0xB7", 1594 "EventName": "UNC_M_RD_CAS_RANK7.BANK13", 1595 "PerPkg": "1", 1596 "UMask": "0xD", 1597 "Unit": "iMC" 1598 }, 1599 { 1600 "BriefDescription": "RD_CAS Access to Rank 7; Bank 14", 1601 "Counter": "0,1,2,3", 1602 "EventCode": "0xB7", 1603 "EventName": "UNC_M_RD_CAS_RANK7.BANK14", 1604 "PerPkg": "1", 1605 "UMask": "0xE", 1606 "Unit": "iMC" 1607 }, 1608 { 1609 "BriefDescription": "RD_CAS Access to Rank 7; Bank 15", 1610 "Counter": "0,1,2,3", 1611 "EventCode": "0xB7", 1612 "EventName": "UNC_M_RD_CAS_RANK7.BANK15", 1613 "PerPkg": "1", 1614 "UMask": "0xF", 1615 "Unit": "iMC" 1616 }, 1617 { 1618 "BriefDescription": "RD_CAS Access to Rank 7; Bank Group 0 (Banks 0-3)", 1619 "Counter": "0,1,2,3", 1620 "EventCode": "0xB7", 1621 "EventName": "UNC_M_RD_CAS_RANK7.BANKG0", 1622 "PerPkg": "1", 1623 "UMask": "0x11", 1624 "Unit": "iMC" 1625 }, 1626 { 1627 "BriefDescription": "RD_CAS Access to Rank 7; Bank Group 1 (Banks 4-7)", 1628 "Counter": "0,1,2,3", 1629 "EventCode": "0xB7", 1630 "EventName": "UNC_M_RD_CAS_RANK7.BANKG1", 1631 "PerPkg": "1", 1632 "UMask": "0x12", 1633 "Unit": "iMC" 1634 }, 1635 { 1636 "BriefDescription": "RD_CAS Access to Rank 7; Bank Group 2 (Banks 8-11)", 1637 "Counter": "0,1,2,3", 1638 "EventCode": "0xB7", 1639 "EventName": "UNC_M_RD_CAS_RANK7.BANKG2", 1640 "PerPkg": "1", 1641 "UMask": "0x13", 1642 "Unit": "iMC" 1643 }, 1644 { 1645 "BriefDescription": "RD_CAS Access to Rank 7; Bank Group 3 (Banks 12-15)", 1646 "Counter": "0,1,2,3", 1647 "EventCode": "0xB7", 1648 "EventName": "UNC_M_RD_CAS_RANK7.BANKG3", 1649 "PerPkg": "1", 1650 "UMask": "0x14", 1651 "Unit": "iMC" 1652 }, 1653 { 1654 "BriefDescription": "Read Pending Queue Not Empty", 1655 "Counter": "0,1,2,3", 1656 "EventCode": "0x11", 1657 "EventName": "UNC_M_RPQ_CYCLES_NE", 1658 "PerPkg": "1", 1659 "Unit": "iMC" 1660 }, 1661 { 1662 "BriefDescription": "Read Pending Queue Allocations", 1663 "Counter": "0,1,2,3", 1664 "EventCode": "0x10", 1665 "EventName": "UNC_M_RPQ_INSERTS", 1666 "PerPkg": "1", 1667 "Unit": "iMC" 1668 }, 1669 { 1670 "BriefDescription": "VMSE MXB write buffer occupancy", 1671 "Counter": "0,1,2,3", 1672 "EventCode": "0x91", 1673 "EventName": "UNC_M_VMSE_MXB_WR_OCCUPANCY", 1674 "PerPkg": "1", 1675 "Unit": "iMC" 1676 }, 1677 { 1678 "BriefDescription": "VMSE WR PUSH issued; VMSE write PUSH issued in WMM", 1679 "Counter": "0,1,2,3", 1680 "EventCode": "0x90", 1681 "EventName": "UNC_M_VMSE_WR_PUSH.WMM", 1682 "PerPkg": "1", 1683 "UMask": "0x1", 1684 "Unit": "iMC" 1685 }, 1686 { 1687 "BriefDescription": "VMSE WR PUSH issued; VMSE write PUSH issued in RMM", 1688 "Counter": "0,1,2,3", 1689 "EventCode": "0x90", 1690 "EventName": "UNC_M_VMSE_WR_PUSH.RMM", 1691 "PerPkg": "1", 1692 "UMask": "0x2", 1693 "Unit": "iMC" 1694 }, 1695 { 1696 "BriefDescription": "Transition from WMM to RMM because of low threshold; Transition from WMM to RMM because of starve counter", 1697 "Counter": "0,1,2,3", 1698 "EventCode": "0xC0", 1699 "EventName": "UNC_M_WMM_TO_RMM.LOW_THRESH", 1700 "PerPkg": "1", 1701 "UMask": "0x1", 1702 "Unit": "iMC" 1703 }, 1704 { 1705 "BriefDescription": "Transition from WMM to RMM because of low threshold", 1706 "Counter": "0,1,2,3", 1707 "EventCode": "0xC0", 1708 "EventName": "UNC_M_WMM_TO_RMM.STARVE", 1709 "PerPkg": "1", 1710 "UMask": "0x2", 1711 "Unit": "iMC" 1712 }, 1713 { 1714 "BriefDescription": "Transition from WMM to RMM because of low threshold", 1715 "Counter": "0,1,2,3", 1716 "EventCode": "0xC0", 1717 "EventName": "UNC_M_WMM_TO_RMM.VMSE_RETRY", 1718 "PerPkg": "1", 1719 "UMask": "0x4", 1720 "Unit": "iMC" 1721 }, 1722 { 1723 "BriefDescription": "Write Pending Queue Full Cycles", 1724 "Counter": "0,1,2,3", 1725 "EventCode": "0x22", 1726 "EventName": "UNC_M_WPQ_CYCLES_FULL", 1727 "PerPkg": "1", 1728 "Unit": "iMC" 1729 }, 1730 { 1731 "BriefDescription": "Write Pending Queue Not Empty", 1732 "Counter": "0,1,2,3", 1733 "EventCode": "0x21", 1734 "EventName": "UNC_M_WPQ_CYCLES_NE", 1735 "PerPkg": "1", 1736 "Unit": "iMC" 1737 }, 1738 { 1739 "BriefDescription": "Write Pending Queue CAM Match", 1740 "Counter": "0,1,2,3", 1741 "EventCode": "0x23", 1742 "EventName": "UNC_M_WPQ_READ_HIT", 1743 "PerPkg": "1", 1744 "Unit": "iMC" 1745 }, 1746 { 1747 "BriefDescription": "Write Pending Queue CAM Match", 1748 "Counter": "0,1,2,3", 1749 "EventCode": "0x24", 1750 "EventName": "UNC_M_WPQ_WRITE_HIT", 1751 "PerPkg": "1", 1752 "Unit": "iMC" 1753 }, 1754 { 1755 "BriefDescription": "Not getting the requested Major Mode", 1756 "Counter": "0,1,2,3", 1757 "EventCode": "0xC1", 1758 "EventName": "UNC_M_WRONG_MM", 1759 "PerPkg": "1", 1760 "Unit": "iMC" 1761 }, 1762 { 1763 "BriefDescription": "WR_CAS Access to Rank 0; Bank 1", 1764 "Counter": "0,1,2,3", 1765 "EventCode": "0xB8", 1766 "EventName": "UNC_M_WR_CAS_RANK0.BANK1", 1767 "PerPkg": "1", 1768 "UMask": "0x1", 1769 "Unit": "iMC" 1770 }, 1771 { 1772 "BriefDescription": "WR_CAS Access to Rank 0; Bank 2", 1773 "Counter": "0,1,2,3", 1774 "EventCode": "0xB8", 1775 "EventName": "UNC_M_WR_CAS_RANK0.BANK2", 1776 "PerPkg": "1", 1777 "UMask": "0x2", 1778 "Unit": "iMC" 1779 }, 1780 { 1781 "BriefDescription": "WR_CAS Access to Rank 0; Bank 4", 1782 "Counter": "0,1,2,3", 1783 "EventCode": "0xB8", 1784 "EventName": "UNC_M_WR_CAS_RANK0.BANK4", 1785 "PerPkg": "1", 1786 "UMask": "0x4", 1787 "Unit": "iMC" 1788 }, 1789 { 1790 "BriefDescription": "WR_CAS Access to Rank 0; Bank 8", 1791 "Counter": "0,1,2,3", 1792 "EventCode": "0xB8", 1793 "EventName": "UNC_M_WR_CAS_RANK0.BANK8", 1794 "PerPkg": "1", 1795 "UMask": "0x8", 1796 "Unit": "iMC" 1797 }, 1798 { 1799 "BriefDescription": "WR_CAS Access to Rank 0; All Banks", 1800 "Counter": "0,1,2,3", 1801 "EventCode": "0xB8", 1802 "EventName": "UNC_M_WR_CAS_RANK0.ALLBANKS", 1803 "PerPkg": "1", 1804 "UMask": "0x10", 1805 "Unit": "iMC" 1806 }, 1807 { 1808 "BriefDescription": "WR_CAS Access to Rank 0; Bank 0", 1809 "Counter": "0,1,2,3", 1810 "EventCode": "0xB8", 1811 "EventName": "UNC_M_WR_CAS_RANK0.BANK0", 1812 "PerPkg": "1", 1813 "Unit": "iMC" 1814 }, 1815 { 1816 "BriefDescription": "WR_CAS Access to Rank 0; Bank 3", 1817 "Counter": "0,1,2,3", 1818 "EventCode": "0xB8", 1819 "EventName": "UNC_M_WR_CAS_RANK0.BANK3", 1820 "PerPkg": "1", 1821 "UMask": "0x3", 1822 "Unit": "iMC" 1823 }, 1824 { 1825 "BriefDescription": "WR_CAS Access to Rank 0; Bank 5", 1826 "Counter": "0,1,2,3", 1827 "EventCode": "0xB8", 1828 "EventName": "UNC_M_WR_CAS_RANK0.BANK5", 1829 "PerPkg": "1", 1830 "UMask": "0x5", 1831 "Unit": "iMC" 1832 }, 1833 { 1834 "BriefDescription": "WR_CAS Access to Rank 0; Bank 6", 1835 "Counter": "0,1,2,3", 1836 "EventCode": "0xB8", 1837 "EventName": "UNC_M_WR_CAS_RANK0.BANK6", 1838 "PerPkg": "1", 1839 "UMask": "0x6", 1840 "Unit": "iMC" 1841 }, 1842 { 1843 "BriefDescription": "WR_CAS Access to Rank 0; Bank 7", 1844 "Counter": "0,1,2,3", 1845 "EventCode": "0xB8", 1846 "EventName": "UNC_M_WR_CAS_RANK0.BANK7", 1847 "PerPkg": "1", 1848 "UMask": "0x7", 1849 "Unit": "iMC" 1850 }, 1851 { 1852 "BriefDescription": "WR_CAS Access to Rank 0; Bank 9", 1853 "Counter": "0,1,2,3", 1854 "EventCode": "0xB8", 1855 "EventName": "UNC_M_WR_CAS_RANK0.BANK9", 1856 "PerPkg": "1", 1857 "UMask": "0x9", 1858 "Unit": "iMC" 1859 }, 1860 { 1861 "BriefDescription": "WR_CAS Access to Rank 0; Bank 10", 1862 "Counter": "0,1,2,3", 1863 "EventCode": "0xB8", 1864 "EventName": "UNC_M_WR_CAS_RANK0.BANK10", 1865 "PerPkg": "1", 1866 "UMask": "0xA", 1867 "Unit": "iMC" 1868 }, 1869 { 1870 "BriefDescription": "WR_CAS Access to Rank 0; Bank 11", 1871 "Counter": "0,1,2,3", 1872 "EventCode": "0xB8", 1873 "EventName": "UNC_M_WR_CAS_RANK0.BANK11", 1874 "PerPkg": "1", 1875 "UMask": "0xB", 1876 "Unit": "iMC" 1877 }, 1878 { 1879 "BriefDescription": "WR_CAS Access to Rank 0; Bank 12", 1880 "Counter": "0,1,2,3", 1881 "EventCode": "0xB8", 1882 "EventName": "UNC_M_WR_CAS_RANK0.BANK12", 1883 "PerPkg": "1", 1884 "UMask": "0xC", 1885 "Unit": "iMC" 1886 }, 1887 { 1888 "BriefDescription": "WR_CAS Access to Rank 0; Bank 13", 1889 "Counter": "0,1,2,3", 1890 "EventCode": "0xB8", 1891 "EventName": "UNC_M_WR_CAS_RANK0.BANK13", 1892 "PerPkg": "1", 1893 "UMask": "0xD", 1894 "Unit": "iMC" 1895 }, 1896 { 1897 "BriefDescription": "WR_CAS Access to Rank 0; Bank 14", 1898 "Counter": "0,1,2,3", 1899 "EventCode": "0xB8", 1900 "EventName": "UNC_M_WR_CAS_RANK0.BANK14", 1901 "PerPkg": "1", 1902 "UMask": "0xE", 1903 "Unit": "iMC" 1904 }, 1905 { 1906 "BriefDescription": "WR_CAS Access to Rank 0; Bank 15", 1907 "Counter": "0,1,2,3", 1908 "EventCode": "0xB8", 1909 "EventName": "UNC_M_WR_CAS_RANK0.BANK15", 1910 "PerPkg": "1", 1911 "UMask": "0xF", 1912 "Unit": "iMC" 1913 }, 1914 { 1915 "BriefDescription": "WR_CAS Access to Rank 0; Bank Group 0 (Banks 0-3)", 1916 "Counter": "0,1,2,3", 1917 "EventCode": "0xB8", 1918 "EventName": "UNC_M_WR_CAS_RANK0.BANKG0", 1919 "PerPkg": "1", 1920 "UMask": "0x11", 1921 "Unit": "iMC" 1922 }, 1923 { 1924 "BriefDescription": "WR_CAS Access to Rank 0; Bank Group 1 (Banks 4-7)", 1925 "Counter": "0,1,2,3", 1926 "EventCode": "0xB8", 1927 "EventName": "UNC_M_WR_CAS_RANK0.BANKG1", 1928 "PerPkg": "1", 1929 "UMask": "0x12", 1930 "Unit": "iMC" 1931 }, 1932 { 1933 "BriefDescription": "WR_CAS Access to Rank 0; Bank Group 2 (Banks 8-11)", 1934 "Counter": "0,1,2,3", 1935 "EventCode": "0xB8", 1936 "EventName": "UNC_M_WR_CAS_RANK0.BANKG2", 1937 "PerPkg": "1", 1938 "UMask": "0x13", 1939 "Unit": "iMC" 1940 }, 1941 { 1942 "BriefDescription": "WR_CAS Access to Rank 0; Bank Group 3 (Banks 12-15)", 1943 "Counter": "0,1,2,3", 1944 "EventCode": "0xB8", 1945 "EventName": "UNC_M_WR_CAS_RANK0.BANKG3", 1946 "PerPkg": "1", 1947 "UMask": "0x14", 1948 "Unit": "iMC" 1949 }, 1950 { 1951 "BriefDescription": "WR_CAS Access to Rank 1; Bank 1", 1952 "Counter": "0,1,2,3", 1953 "EventCode": "0xB9", 1954 "EventName": "UNC_M_WR_CAS_RANK1.BANK1", 1955 "PerPkg": "1", 1956 "UMask": "0x1", 1957 "Unit": "iMC" 1958 }, 1959 { 1960 "BriefDescription": "WR_CAS Access to Rank 1; Bank 2", 1961 "Counter": "0,1,2,3", 1962 "EventCode": "0xB9", 1963 "EventName": "UNC_M_WR_CAS_RANK1.BANK2", 1964 "PerPkg": "1", 1965 "UMask": "0x2", 1966 "Unit": "iMC" 1967 }, 1968 { 1969 "BriefDescription": "WR_CAS Access to Rank 1; Bank 4", 1970 "Counter": "0,1,2,3", 1971 "EventCode": "0xB9", 1972 "EventName": "UNC_M_WR_CAS_RANK1.BANK4", 1973 "PerPkg": "1", 1974 "UMask": "0x4", 1975 "Unit": "iMC" 1976 }, 1977 { 1978 "BriefDescription": "WR_CAS Access to Rank 1; Bank 8", 1979 "Counter": "0,1,2,3", 1980 "EventCode": "0xB9", 1981 "EventName": "UNC_M_WR_CAS_RANK1.BANK8", 1982 "PerPkg": "1", 1983 "UMask": "0x8", 1984 "Unit": "iMC" 1985 }, 1986 { 1987 "BriefDescription": "WR_CAS Access to Rank 1; All Banks", 1988 "Counter": "0,1,2,3", 1989 "EventCode": "0xB9", 1990 "EventName": "UNC_M_WR_CAS_RANK1.ALLBANKS", 1991 "PerPkg": "1", 1992 "UMask": "0x10", 1993 "Unit": "iMC" 1994 }, 1995 { 1996 "BriefDescription": "WR_CAS Access to Rank 1; Bank 0", 1997 "Counter": "0,1,2,3", 1998 "EventCode": "0xB9", 1999 "EventName": "UNC_M_WR_CAS_RANK1.BANK0", 2000 "PerPkg": "1", 2001 "Unit": "iMC" 2002 }, 2003 { 2004 "BriefDescription": "WR_CAS Access to Rank 1; Bank 3", 2005 "Counter": "0,1,2,3", 2006 "EventCode": "0xB9", 2007 "EventName": "UNC_M_WR_CAS_RANK1.BANK3", 2008 "PerPkg": "1", 2009 "UMask": "0x3", 2010 "Unit": "iMC" 2011 }, 2012 { 2013 "BriefDescription": "WR_CAS Access to Rank 1; Bank 5", 2014 "Counter": "0,1,2,3", 2015 "EventCode": "0xB9", 2016 "EventName": "UNC_M_WR_CAS_RANK1.BANK5", 2017 "PerPkg": "1", 2018 "UMask": "0x5", 2019 "Unit": "iMC" 2020 }, 2021 { 2022 "BriefDescription": "WR_CAS Access to Rank 1; Bank 6", 2023 "Counter": "0,1,2,3", 2024 "EventCode": "0xB9", 2025 "EventName": "UNC_M_WR_CAS_RANK1.BANK6", 2026 "PerPkg": "1", 2027 "UMask": "0x6", 2028 "Unit": "iMC" 2029 }, 2030 { 2031 "BriefDescription": "WR_CAS Access to Rank 1; Bank 7", 2032 "Counter": "0,1,2,3", 2033 "EventCode": "0xB9", 2034 "EventName": "UNC_M_WR_CAS_RANK1.BANK7", 2035 "PerPkg": "1", 2036 "UMask": "0x7", 2037 "Unit": "iMC" 2038 }, 2039 { 2040 "BriefDescription": "WR_CAS Access to Rank 1; Bank 9", 2041 "Counter": "0,1,2,3", 2042 "EventCode": "0xB9", 2043 "EventName": "UNC_M_WR_CAS_RANK1.BANK9", 2044 "PerPkg": "1", 2045 "UMask": "0x9", 2046 "Unit": "iMC" 2047 }, 2048 { 2049 "BriefDescription": "WR_CAS Access to Rank 1; Bank 10", 2050 "Counter": "0,1,2,3", 2051 "EventCode": "0xB9", 2052 "EventName": "UNC_M_WR_CAS_RANK1.BANK10", 2053 "PerPkg": "1", 2054 "UMask": "0xA", 2055 "Unit": "iMC" 2056 }, 2057 { 2058 "BriefDescription": "WR_CAS Access to Rank 1; Bank 11", 2059 "Counter": "0,1,2,3", 2060 "EventCode": "0xB9", 2061 "EventName": "UNC_M_WR_CAS_RANK1.BANK11", 2062 "PerPkg": "1", 2063 "UMask": "0xB", 2064 "Unit": "iMC" 2065 }, 2066 { 2067 "BriefDescription": "WR_CAS Access to Rank 1; Bank 12", 2068 "Counter": "0,1,2,3", 2069 "EventCode": "0xB9", 2070 "EventName": "UNC_M_WR_CAS_RANK1.BANK12", 2071 "PerPkg": "1", 2072 "UMask": "0xC", 2073 "Unit": "iMC" 2074 }, 2075 { 2076 "BriefDescription": "WR_CAS Access to Rank 1; Bank 13", 2077 "Counter": "0,1,2,3", 2078 "EventCode": "0xB9", 2079 "EventName": "UNC_M_WR_CAS_RANK1.BANK13", 2080 "PerPkg": "1", 2081 "UMask": "0xD", 2082 "Unit": "iMC" 2083 }, 2084 { 2085 "BriefDescription": "WR_CAS Access to Rank 1; Bank 14", 2086 "Counter": "0,1,2,3", 2087 "EventCode": "0xB9", 2088 "EventName": "UNC_M_WR_CAS_RANK1.BANK14", 2089 "PerPkg": "1", 2090 "UMask": "0xE", 2091 "Unit": "iMC" 2092 }, 2093 { 2094 "BriefDescription": "WR_CAS Access to Rank 1; Bank 15", 2095 "Counter": "0,1,2,3", 2096 "EventCode": "0xB9", 2097 "EventName": "UNC_M_WR_CAS_RANK1.BANK15", 2098 "PerPkg": "1", 2099 "UMask": "0xF", 2100 "Unit": "iMC" 2101 }, 2102 { 2103 "BriefDescription": "WR_CAS Access to Rank 1; Bank Group 0 (Banks 0-3)", 2104 "Counter": "0,1,2,3", 2105 "EventCode": "0xB9", 2106 "EventName": "UNC_M_WR_CAS_RANK1.BANKG0", 2107 "PerPkg": "1", 2108 "UMask": "0x11", 2109 "Unit": "iMC" 2110 }, 2111 { 2112 "BriefDescription": "WR_CAS Access to Rank 1; Bank Group 1 (Banks 4-7)", 2113 "Counter": "0,1,2,3", 2114 "EventCode": "0xB9", 2115 "EventName": "UNC_M_WR_CAS_RANK1.BANKG1", 2116 "PerPkg": "1", 2117 "UMask": "0x12", 2118 "Unit": "iMC" 2119 }, 2120 { 2121 "BriefDescription": "WR_CAS Access to Rank 1; Bank Group 2 (Banks 8-11)", 2122 "Counter": "0,1,2,3", 2123 "EventCode": "0xB9", 2124 "EventName": "UNC_M_WR_CAS_RANK1.BANKG2", 2125 "PerPkg": "1", 2126 "UMask": "0x13", 2127 "Unit": "iMC" 2128 }, 2129 { 2130 "BriefDescription": "WR_CAS Access to Rank 1; Bank Group 3 (Banks 12-15)", 2131 "Counter": "0,1,2,3", 2132 "EventCode": "0xB9", 2133 "EventName": "UNC_M_WR_CAS_RANK1.BANKG3", 2134 "PerPkg": "1", 2135 "UMask": "0x14", 2136 "Unit": "iMC" 2137 }, 2138 { 2139 "BriefDescription": "WR_CAS Access to Rank 4; Bank 1", 2140 "Counter": "0,1,2,3", 2141 "EventCode": "0xBC", 2142 "EventName": "UNC_M_WR_CAS_RANK4.BANK1", 2143 "PerPkg": "1", 2144 "UMask": "0x1", 2145 "Unit": "iMC" 2146 }, 2147 { 2148 "BriefDescription": "WR_CAS Access to Rank 4; Bank 2", 2149 "Counter": "0,1,2,3", 2150 "EventCode": "0xBC", 2151 "EventName": "UNC_M_WR_CAS_RANK4.BANK2", 2152 "PerPkg": "1", 2153 "UMask": "0x2", 2154 "Unit": "iMC" 2155 }, 2156 { 2157 "BriefDescription": "WR_CAS Access to Rank 4; Bank 4", 2158 "Counter": "0,1,2,3", 2159 "EventCode": "0xBC", 2160 "EventName": "UNC_M_WR_CAS_RANK4.BANK4", 2161 "PerPkg": "1", 2162 "UMask": "0x4", 2163 "Unit": "iMC" 2164 }, 2165 { 2166 "BriefDescription": "WR_CAS Access to Rank 4; Bank 8", 2167 "Counter": "0,1,2,3", 2168 "EventCode": "0xBC", 2169 "EventName": "UNC_M_WR_CAS_RANK4.BANK8", 2170 "PerPkg": "1", 2171 "UMask": "0x8", 2172 "Unit": "iMC" 2173 }, 2174 { 2175 "BriefDescription": "WR_CAS Access to Rank 4; All Banks", 2176 "Counter": "0,1,2,3", 2177 "EventCode": "0xBC", 2178 "EventName": "UNC_M_WR_CAS_RANK4.ALLBANKS", 2179 "PerPkg": "1", 2180 "UMask": "0x10", 2181 "Unit": "iMC" 2182 }, 2183 { 2184 "BriefDescription": "WR_CAS Access to Rank 4; Bank 0", 2185 "Counter": "0,1,2,3", 2186 "EventCode": "0xBC", 2187 "EventName": "UNC_M_WR_CAS_RANK4.BANK0", 2188 "PerPkg": "1", 2189 "Unit": "iMC" 2190 }, 2191 { 2192 "BriefDescription": "WR_CAS Access to Rank 4; Bank 3", 2193 "Counter": "0,1,2,3", 2194 "EventCode": "0xBC", 2195 "EventName": "UNC_M_WR_CAS_RANK4.BANK3", 2196 "PerPkg": "1", 2197 "UMask": "0x3", 2198 "Unit": "iMC" 2199 }, 2200 { 2201 "BriefDescription": "WR_CAS Access to Rank 4; Bank 5", 2202 "Counter": "0,1,2,3", 2203 "EventCode": "0xBC", 2204 "EventName": "UNC_M_WR_CAS_RANK4.BANK5", 2205 "PerPkg": "1", 2206 "UMask": "0x5", 2207 "Unit": "iMC" 2208 }, 2209 { 2210 "BriefDescription": "WR_CAS Access to Rank 4; Bank 6", 2211 "Counter": "0,1,2,3", 2212 "EventCode": "0xBC", 2213 "EventName": "UNC_M_WR_CAS_RANK4.BANK6", 2214 "PerPkg": "1", 2215 "UMask": "0x6", 2216 "Unit": "iMC" 2217 }, 2218 { 2219 "BriefDescription": "WR_CAS Access to Rank 4; Bank 7", 2220 "Counter": "0,1,2,3", 2221 "EventCode": "0xBC", 2222 "EventName": "UNC_M_WR_CAS_RANK4.BANK7", 2223 "PerPkg": "1", 2224 "UMask": "0x7", 2225 "Unit": "iMC" 2226 }, 2227 { 2228 "BriefDescription": "WR_CAS Access to Rank 4; Bank 9", 2229 "Counter": "0,1,2,3", 2230 "EventCode": "0xBC", 2231 "EventName": "UNC_M_WR_CAS_RANK4.BANK9", 2232 "PerPkg": "1", 2233 "UMask": "0x9", 2234 "Unit": "iMC" 2235 }, 2236 { 2237 "BriefDescription": "WR_CAS Access to Rank 4; Bank 10", 2238 "Counter": "0,1,2,3", 2239 "EventCode": "0xBC", 2240 "EventName": "UNC_M_WR_CAS_RANK4.BANK10", 2241 "PerPkg": "1", 2242 "UMask": "0xA", 2243 "Unit": "iMC" 2244 }, 2245 { 2246 "BriefDescription": "WR_CAS Access to Rank 4; Bank 11", 2247 "Counter": "0,1,2,3", 2248 "EventCode": "0xBC", 2249 "EventName": "UNC_M_WR_CAS_RANK4.BANK11", 2250 "PerPkg": "1", 2251 "UMask": "0xB", 2252 "Unit": "iMC" 2253 }, 2254 { 2255 "BriefDescription": "WR_CAS Access to Rank 4; Bank 12", 2256 "Counter": "0,1,2,3", 2257 "EventCode": "0xBC", 2258 "EventName": "UNC_M_WR_CAS_RANK4.BANK12", 2259 "PerPkg": "1", 2260 "UMask": "0xC", 2261 "Unit": "iMC" 2262 }, 2263 { 2264 "BriefDescription": "WR_CAS Access to Rank 4; Bank 13", 2265 "Counter": "0,1,2,3", 2266 "EventCode": "0xBC", 2267 "EventName": "UNC_M_WR_CAS_RANK4.BANK13", 2268 "PerPkg": "1", 2269 "UMask": "0xD", 2270 "Unit": "iMC" 2271 }, 2272 { 2273 "BriefDescription": "WR_CAS Access to Rank 4; Bank 14", 2274 "Counter": "0,1,2,3", 2275 "EventCode": "0xBC", 2276 "EventName": "UNC_M_WR_CAS_RANK4.BANK14", 2277 "PerPkg": "1", 2278 "UMask": "0xE", 2279 "Unit": "iMC" 2280 }, 2281 { 2282 "BriefDescription": "WR_CAS Access to Rank 4; Bank 15", 2283 "Counter": "0,1,2,3", 2284 "EventCode": "0xBC", 2285 "EventName": "UNC_M_WR_CAS_RANK4.BANK15", 2286 "PerPkg": "1", 2287 "UMask": "0xF", 2288 "Unit": "iMC" 2289 }, 2290 { 2291 "BriefDescription": "WR_CAS Access to Rank 4; Bank Group 0 (Banks 0-3)", 2292 "Counter": "0,1,2,3", 2293 "EventCode": "0xBC", 2294 "EventName": "UNC_M_WR_CAS_RANK4.BANKG0", 2295 "PerPkg": "1", 2296 "UMask": "0x11", 2297 "Unit": "iMC" 2298 }, 2299 { 2300 "BriefDescription": "WR_CAS Access to Rank 4; Bank Group 1 (Banks 4-7)", 2301 "Counter": "0,1,2,3", 2302 "EventCode": "0xBC", 2303 "EventName": "UNC_M_WR_CAS_RANK4.BANKG1", 2304 "PerPkg": "1", 2305 "UMask": "0x12", 2306 "Unit": "iMC" 2307 }, 2308 { 2309 "BriefDescription": "WR_CAS Access to Rank 4; Bank Group 2 (Banks 8-11)", 2310 "Counter": "0,1,2,3", 2311 "EventCode": "0xBC", 2312 "EventName": "UNC_M_WR_CAS_RANK4.BANKG2", 2313 "PerPkg": "1", 2314 "UMask": "0x13", 2315 "Unit": "iMC" 2316 }, 2317 { 2318 "BriefDescription": "WR_CAS Access to Rank 4; Bank Group 3 (Banks 12-15)", 2319 "Counter": "0,1,2,3", 2320 "EventCode": "0xBC", 2321 "EventName": "UNC_M_WR_CAS_RANK4.BANKG3", 2322 "PerPkg": "1", 2323 "UMask": "0x14", 2324 "Unit": "iMC" 2325 }, 2326 { 2327 "BriefDescription": "WR_CAS Access to Rank 5; Bank 1", 2328 "Counter": "0,1,2,3", 2329 "EventCode": "0xBD", 2330 "EventName": "UNC_M_WR_CAS_RANK5.BANK1", 2331 "PerPkg": "1", 2332 "UMask": "0x1", 2333 "Unit": "iMC" 2334 }, 2335 { 2336 "BriefDescription": "WR_CAS Access to Rank 5; Bank 2", 2337 "Counter": "0,1,2,3", 2338 "EventCode": "0xBD", 2339 "EventName": "UNC_M_WR_CAS_RANK5.BANK2", 2340 "PerPkg": "1", 2341 "UMask": "0x2", 2342 "Unit": "iMC" 2343 }, 2344 { 2345 "BriefDescription": "WR_CAS Access to Rank 5; Bank 4", 2346 "Counter": "0,1,2,3", 2347 "EventCode": "0xBD", 2348 "EventName": "UNC_M_WR_CAS_RANK5.BANK4", 2349 "PerPkg": "1", 2350 "UMask": "0x4", 2351 "Unit": "iMC" 2352 }, 2353 { 2354 "BriefDescription": "WR_CAS Access to Rank 5; Bank 8", 2355 "Counter": "0,1,2,3", 2356 "EventCode": "0xBD", 2357 "EventName": "UNC_M_WR_CAS_RANK5.BANK8", 2358 "PerPkg": "1", 2359 "UMask": "0x8", 2360 "Unit": "iMC" 2361 }, 2362 { 2363 "BriefDescription": "WR_CAS Access to Rank 5; All Banks", 2364 "Counter": "0,1,2,3", 2365 "EventCode": "0xBD", 2366 "EventName": "UNC_M_WR_CAS_RANK5.ALLBANKS", 2367 "PerPkg": "1", 2368 "UMask": "0x10", 2369 "Unit": "iMC" 2370 }, 2371 { 2372 "BriefDescription": "WR_CAS Access to Rank 5; Bank 0", 2373 "Counter": "0,1,2,3", 2374 "EventCode": "0xBD", 2375 "EventName": "UNC_M_WR_CAS_RANK5.BANK0", 2376 "PerPkg": "1", 2377 "Unit": "iMC" 2378 }, 2379 { 2380 "BriefDescription": "WR_CAS Access to Rank 5; Bank 3", 2381 "Counter": "0,1,2,3", 2382 "EventCode": "0xBD", 2383 "EventName": "UNC_M_WR_CAS_RANK5.BANK3", 2384 "PerPkg": "1", 2385 "UMask": "0x3", 2386 "Unit": "iMC" 2387 }, 2388 { 2389 "BriefDescription": "WR_CAS Access to Rank 5; Bank 5", 2390 "Counter": "0,1,2,3", 2391 "EventCode": "0xBD", 2392 "EventName": "UNC_M_WR_CAS_RANK5.BANK5", 2393 "PerPkg": "1", 2394 "UMask": "0x5", 2395 "Unit": "iMC" 2396 }, 2397 { 2398 "BriefDescription": "WR_CAS Access to Rank 5; Bank 6", 2399 "Counter": "0,1,2,3", 2400 "EventCode": "0xBD", 2401 "EventName": "UNC_M_WR_CAS_RANK5.BANK6", 2402 "PerPkg": "1", 2403 "UMask": "0x6", 2404 "Unit": "iMC" 2405 }, 2406 { 2407 "BriefDescription": "WR_CAS Access to Rank 5; Bank 7", 2408 "Counter": "0,1,2,3", 2409 "EventCode": "0xBD", 2410 "EventName": "UNC_M_WR_CAS_RANK5.BANK7", 2411 "PerPkg": "1", 2412 "UMask": "0x7", 2413 "Unit": "iMC" 2414 }, 2415 { 2416 "BriefDescription": "WR_CAS Access to Rank 5; Bank 9", 2417 "Counter": "0,1,2,3", 2418 "EventCode": "0xBD", 2419 "EventName": "UNC_M_WR_CAS_RANK5.BANK9", 2420 "PerPkg": "1", 2421 "UMask": "0x9", 2422 "Unit": "iMC" 2423 }, 2424 { 2425 "BriefDescription": "WR_CAS Access to Rank 5; Bank 10", 2426 "Counter": "0,1,2,3", 2427 "EventCode": "0xBD", 2428 "EventName": "UNC_M_WR_CAS_RANK5.BANK10", 2429 "PerPkg": "1", 2430 "UMask": "0xA", 2431 "Unit": "iMC" 2432 }, 2433 { 2434 "BriefDescription": "WR_CAS Access to Rank 5; Bank 11", 2435 "Counter": "0,1,2,3", 2436 "EventCode": "0xBD", 2437 "EventName": "UNC_M_WR_CAS_RANK5.BANK11", 2438 "PerPkg": "1", 2439 "UMask": "0xB", 2440 "Unit": "iMC" 2441 }, 2442 { 2443 "BriefDescription": "WR_CAS Access to Rank 5; Bank 12", 2444 "Counter": "0,1,2,3", 2445 "EventCode": "0xBD", 2446 "EventName": "UNC_M_WR_CAS_RANK5.BANK12", 2447 "PerPkg": "1", 2448 "UMask": "0xC", 2449 "Unit": "iMC" 2450 }, 2451 { 2452 "BriefDescription": "WR_CAS Access to Rank 5; Bank 13", 2453 "Counter": "0,1,2,3", 2454 "EventCode": "0xBD", 2455 "EventName": "UNC_M_WR_CAS_RANK5.BANK13", 2456 "PerPkg": "1", 2457 "UMask": "0xD", 2458 "Unit": "iMC" 2459 }, 2460 { 2461 "BriefDescription": "WR_CAS Access to Rank 5; Bank 14", 2462 "Counter": "0,1,2,3", 2463 "EventCode": "0xBD", 2464 "EventName": "UNC_M_WR_CAS_RANK5.BANK14", 2465 "PerPkg": "1", 2466 "UMask": "0xE", 2467 "Unit": "iMC" 2468 }, 2469 { 2470 "BriefDescription": "WR_CAS Access to Rank 5; Bank 15", 2471 "Counter": "0,1,2,3", 2472 "EventCode": "0xBD", 2473 "EventName": "UNC_M_WR_CAS_RANK5.BANK15", 2474 "PerPkg": "1", 2475 "UMask": "0xF", 2476 "Unit": "iMC" 2477 }, 2478 { 2479 "BriefDescription": "WR_CAS Access to Rank 5; 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