1ede00740SAndi Kleen[ 2ede00740SAndi Kleen { 3ede00740SAndi Kleen "BriefDescription": "Number of times an HLE execution aborted due to any reasons (multiple categories may count as one).", 4ede00740SAndi Kleen "Counter": "0,1,2,3", 5*f16c3236SIan Rogers "CounterHTOff": "0,1,2,3,4,5,6,7", 6*f16c3236SIan Rogers "EventCode": "0xc8", 7ede00740SAndi Kleen "EventName": "HLE_RETIRED.ABORTED", 8*f16c3236SIan Rogers "PEBS": "1", 9ede00740SAndi Kleen "SampleAfterValue": "2000003", 10*f16c3236SIan Rogers "UMask": "0x4" 11ede00740SAndi Kleen }, 12ede00740SAndi Kleen { 13ede00740SAndi Kleen "BriefDescription": "Number of times an HLE execution aborted due to various memory events (e.g., read/write capacity and conflicts).", 14ede00740SAndi Kleen "Counter": "0,1,2,3", 15*f16c3236SIan Rogers "CounterHTOff": "0,1,2,3,4,5,6,7", 16*f16c3236SIan Rogers "EventCode": "0xc8", 17ede00740SAndi Kleen "EventName": "HLE_RETIRED.ABORTED_MISC1", 18ede00740SAndi Kleen "SampleAfterValue": "2000003", 19*f16c3236SIan Rogers "UMask": "0x8" 20ede00740SAndi Kleen }, 21ede00740SAndi Kleen { 22ede00740SAndi Kleen "BriefDescription": "Number of times an HLE execution aborted due to uncommon conditions.", 23ede00740SAndi Kleen "Counter": "0,1,2,3", 24*f16c3236SIan Rogers "CounterHTOff": "0,1,2,3,4,5,6,7", 25*f16c3236SIan Rogers "EventCode": "0xc8", 26ede00740SAndi Kleen "EventName": "HLE_RETIRED.ABORTED_MISC2", 27ede00740SAndi Kleen "SampleAfterValue": "2000003", 28*f16c3236SIan Rogers "UMask": "0x10" 29ede00740SAndi Kleen }, 30ede00740SAndi Kleen { 31ede00740SAndi Kleen "BriefDescription": "Number of times an HLE execution aborted due to HLE-unfriendly instructions.", 32ede00740SAndi Kleen "Counter": "0,1,2,3", 33*f16c3236SIan Rogers "CounterHTOff": "0,1,2,3,4,5,6,7", 34*f16c3236SIan Rogers "EventCode": "0xc8", 35ede00740SAndi Kleen "EventName": "HLE_RETIRED.ABORTED_MISC3", 36ede00740SAndi Kleen "SampleAfterValue": "2000003", 37*f16c3236SIan Rogers "UMask": "0x20" 38ede00740SAndi Kleen }, 39ede00740SAndi Kleen { 40ede00740SAndi Kleen "BriefDescription": "Number of times an HLE execution aborted due to incompatible memory type.", 41ede00740SAndi Kleen "Counter": "0,1,2,3", 42*f16c3236SIan Rogers "CounterHTOff": "0,1,2,3,4,5,6,7", 43ede00740SAndi Kleen "Errata": "HSD65", 44*f16c3236SIan Rogers "EventCode": "0xc8", 45*f16c3236SIan Rogers "EventName": "HLE_RETIRED.ABORTED_MISC4", 46ede00740SAndi Kleen "SampleAfterValue": "2000003", 47*f16c3236SIan Rogers "UMask": "0x40" 48ede00740SAndi Kleen }, 49ede00740SAndi Kleen { 50ede00740SAndi Kleen "BriefDescription": "Number of times an HLE execution aborted due to none of the previous 4 categories (e.g. interrupts)", 51ede00740SAndi Kleen "Counter": "0,1,2,3", 52*f16c3236SIan Rogers "CounterHTOff": "0,1,2,3,4,5,6,7", 53*f16c3236SIan Rogers "EventCode": "0xc8", 54ede00740SAndi Kleen "EventName": "HLE_RETIRED.ABORTED_MISC5", 55ede00740SAndi Kleen "PublicDescription": "Number of times an HLE execution aborted due to none of the previous 4 categories (e.g. interrupts).", 56ede00740SAndi Kleen "SampleAfterValue": "2000003", 57*f16c3236SIan Rogers "UMask": "0x80" 58ede00740SAndi Kleen }, 59ede00740SAndi Kleen { 60*f16c3236SIan Rogers "BriefDescription": "Number of times an HLE execution successfully committed.", 61ede00740SAndi Kleen "Counter": "0,1,2,3", 62*f16c3236SIan Rogers "CounterHTOff": "0,1,2,3,4,5,6,7", 63*f16c3236SIan Rogers "EventCode": "0xc8", 64*f16c3236SIan Rogers "EventName": "HLE_RETIRED.COMMIT", 65ede00740SAndi Kleen "SampleAfterValue": "2000003", 66*f16c3236SIan Rogers "UMask": "0x2" 67ede00740SAndi Kleen }, 68ede00740SAndi Kleen { 69*f16c3236SIan Rogers "BriefDescription": "Number of times an HLE execution started.", 70ede00740SAndi Kleen "Counter": "0,1,2,3", 71*f16c3236SIan Rogers "CounterHTOff": "0,1,2,3,4,5,6,7", 72*f16c3236SIan Rogers "EventCode": "0xC8", 73*f16c3236SIan Rogers "EventName": "HLE_RETIRED.START", 74ede00740SAndi Kleen "SampleAfterValue": "2000003", 75*f16c3236SIan Rogers "UMask": "0x1" 76ede00740SAndi Kleen }, 77ede00740SAndi Kleen { 78*f16c3236SIan Rogers "BriefDescription": "Counts the number of machine clears due to memory order conflicts.", 79*f16c3236SIan Rogers "Counter": "0,1,2,3", 80*f16c3236SIan Rogers "CounterHTOff": "0,1,2,3,4,5,6,7", 81*f16c3236SIan Rogers "EventCode": "0xC3", 82*f16c3236SIan Rogers "EventName": "MACHINE_CLEARS.MEMORY_ORDERING", 83*f16c3236SIan Rogers "PublicDescription": "This event counts the number of memory ordering machine clears detected. Memory ordering machine clears can result from memory address aliasing or snoops from another hardware thread or core to data inflight in the pipeline. Machine clears can have a significant performance impact if they are happening frequently.", 84*f16c3236SIan Rogers "SampleAfterValue": "100003", 85*f16c3236SIan Rogers "UMask": "0x2" 86*f16c3236SIan Rogers }, 87*f16c3236SIan Rogers { 88*f16c3236SIan Rogers "BriefDescription": "Randomly selected loads with latency value being above 128.", 89*f16c3236SIan Rogers "Counter": "3", 90*f16c3236SIan Rogers "CounterHTOff": "3", 91*f16c3236SIan Rogers "Data_LA": "1", 92*f16c3236SIan Rogers "Errata": "HSD76, HSD25, HSM26", 93*f16c3236SIan Rogers "EventCode": "0xcd", 94*f16c3236SIan Rogers "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_128", 95*f16c3236SIan Rogers "MSRIndex": "0x3F6", 96*f16c3236SIan Rogers "MSRValue": "0x80", 97*f16c3236SIan Rogers "PEBS": "2", 98*f16c3236SIan Rogers "SampleAfterValue": "1009", 99*f16c3236SIan Rogers "TakenAlone": "1", 100*f16c3236SIan Rogers "UMask": "0x1" 101*f16c3236SIan Rogers }, 102*f16c3236SIan Rogers { 103*f16c3236SIan Rogers "BriefDescription": "Randomly selected loads with latency value being above 16.", 104*f16c3236SIan Rogers "Counter": "3", 105*f16c3236SIan Rogers "CounterHTOff": "3", 106*f16c3236SIan Rogers "Data_LA": "1", 107*f16c3236SIan Rogers "Errata": "HSD76, HSD25, HSM26", 108*f16c3236SIan Rogers "EventCode": "0xcd", 109*f16c3236SIan Rogers "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_16", 110*f16c3236SIan Rogers "MSRIndex": "0x3F6", 111*f16c3236SIan Rogers "MSRValue": "0x10", 112*f16c3236SIan Rogers "PEBS": "2", 113*f16c3236SIan Rogers "SampleAfterValue": "20011", 114*f16c3236SIan Rogers "TakenAlone": "1", 115*f16c3236SIan Rogers "UMask": "0x1" 116*f16c3236SIan Rogers }, 117*f16c3236SIan Rogers { 118*f16c3236SIan Rogers "BriefDescription": "Randomly selected loads with latency value being above 256.", 119*f16c3236SIan Rogers "Counter": "3", 120*f16c3236SIan Rogers "CounterHTOff": "3", 121*f16c3236SIan Rogers "Data_LA": "1", 122*f16c3236SIan Rogers "Errata": "HSD76, HSD25, HSM26", 123*f16c3236SIan Rogers "EventCode": "0xcd", 124*f16c3236SIan Rogers "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_256", 125*f16c3236SIan Rogers "MSRIndex": "0x3F6", 126*f16c3236SIan Rogers "MSRValue": "0x100", 127*f16c3236SIan Rogers "PEBS": "2", 128*f16c3236SIan Rogers "SampleAfterValue": "503", 129*f16c3236SIan Rogers "TakenAlone": "1", 130*f16c3236SIan Rogers "UMask": "0x1" 131*f16c3236SIan Rogers }, 132*f16c3236SIan Rogers { 133*f16c3236SIan Rogers "BriefDescription": "Randomly selected loads with latency value being above 32.", 134*f16c3236SIan Rogers "Counter": "3", 135*f16c3236SIan Rogers "CounterHTOff": "3", 136*f16c3236SIan Rogers "Data_LA": "1", 137*f16c3236SIan Rogers "Errata": "HSD76, HSD25, HSM26", 138*f16c3236SIan Rogers "EventCode": "0xcd", 139*f16c3236SIan Rogers "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_32", 140*f16c3236SIan Rogers "MSRIndex": "0x3F6", 141*f16c3236SIan Rogers "MSRValue": "0x20", 142*f16c3236SIan Rogers "PEBS": "2", 143*f16c3236SIan Rogers "SampleAfterValue": "100003", 144*f16c3236SIan Rogers "TakenAlone": "1", 145*f16c3236SIan Rogers "UMask": "0x1" 146*f16c3236SIan Rogers }, 147*f16c3236SIan Rogers { 148*f16c3236SIan Rogers "BriefDescription": "Randomly selected loads with latency value being above 4.", 149*f16c3236SIan Rogers "Counter": "3", 150*f16c3236SIan Rogers "CounterHTOff": "3", 151*f16c3236SIan Rogers "Data_LA": "1", 152*f16c3236SIan Rogers "Errata": "HSD76, HSD25, HSM26", 153*f16c3236SIan Rogers "EventCode": "0xcd", 154*f16c3236SIan Rogers "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_4", 155*f16c3236SIan Rogers "MSRIndex": "0x3F6", 156*f16c3236SIan Rogers "MSRValue": "0x4", 157*f16c3236SIan Rogers "PEBS": "2", 158*f16c3236SIan Rogers "SampleAfterValue": "100003", 159*f16c3236SIan Rogers "TakenAlone": "1", 160*f16c3236SIan Rogers "UMask": "0x1" 161*f16c3236SIan Rogers }, 162*f16c3236SIan Rogers { 163*f16c3236SIan Rogers "BriefDescription": "Randomly selected loads with latency value being above 512.", 164*f16c3236SIan Rogers "Counter": "3", 165*f16c3236SIan Rogers "CounterHTOff": "3", 166*f16c3236SIan Rogers "Data_LA": "1", 167*f16c3236SIan Rogers "Errata": "HSD76, HSD25, HSM26", 168*f16c3236SIan Rogers "EventCode": "0xcd", 169*f16c3236SIan Rogers "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_512", 170*f16c3236SIan Rogers "MSRIndex": "0x3F6", 171*f16c3236SIan Rogers "MSRValue": "0x200", 172*f16c3236SIan Rogers "PEBS": "2", 173*f16c3236SIan Rogers "SampleAfterValue": "101", 174*f16c3236SIan Rogers "TakenAlone": "1", 175*f16c3236SIan Rogers "UMask": "0x1" 176*f16c3236SIan Rogers }, 177*f16c3236SIan Rogers { 178*f16c3236SIan Rogers "BriefDescription": "Randomly selected loads with latency value being above 64.", 179*f16c3236SIan Rogers "Counter": "3", 180*f16c3236SIan Rogers "CounterHTOff": "3", 181*f16c3236SIan Rogers "Data_LA": "1", 182*f16c3236SIan Rogers "Errata": "HSD76, HSD25, HSM26", 183*f16c3236SIan Rogers "EventCode": "0xcd", 184*f16c3236SIan Rogers "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_64", 185*f16c3236SIan Rogers "MSRIndex": "0x3F6", 186*f16c3236SIan Rogers "MSRValue": "0x40", 187*f16c3236SIan Rogers "PEBS": "2", 188*f16c3236SIan Rogers "SampleAfterValue": "2003", 189*f16c3236SIan Rogers "TakenAlone": "1", 190*f16c3236SIan Rogers "UMask": "0x1" 191*f16c3236SIan Rogers }, 192*f16c3236SIan Rogers { 193*f16c3236SIan Rogers "BriefDescription": "Randomly selected loads with latency value being above 8.", 194*f16c3236SIan Rogers "Counter": "3", 195*f16c3236SIan Rogers "CounterHTOff": "3", 196*f16c3236SIan Rogers "Data_LA": "1", 197*f16c3236SIan Rogers "Errata": "HSD76, HSD25, HSM26", 198*f16c3236SIan Rogers "EventCode": "0xcd", 199*f16c3236SIan Rogers "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_8", 200*f16c3236SIan Rogers "MSRIndex": "0x3F6", 201*f16c3236SIan Rogers "MSRValue": "0x8", 202*f16c3236SIan Rogers "PEBS": "2", 203*f16c3236SIan Rogers "SampleAfterValue": "50021", 204*f16c3236SIan Rogers "TakenAlone": "1", 205*f16c3236SIan Rogers "UMask": "0x1" 206*f16c3236SIan Rogers }, 207*f16c3236SIan Rogers { 208*f16c3236SIan Rogers "BriefDescription": "Speculative cache line split load uops dispatched to L1 cache", 209*f16c3236SIan Rogers "Counter": "0,1,2,3", 210*f16c3236SIan Rogers "CounterHTOff": "0,1,2,3,4,5,6,7", 211*f16c3236SIan Rogers "EventCode": "0x05", 212*f16c3236SIan Rogers "EventName": "MISALIGN_MEM_REF.LOADS", 213*f16c3236SIan Rogers "PublicDescription": "Speculative cache-line split load uops dispatched to L1D.", 214*f16c3236SIan Rogers "SampleAfterValue": "2000003", 215*f16c3236SIan Rogers "UMask": "0x1" 216*f16c3236SIan Rogers }, 217*f16c3236SIan Rogers { 218*f16c3236SIan Rogers "BriefDescription": "Speculative cache line split STA uops dispatched to L1 cache", 219*f16c3236SIan Rogers "Counter": "0,1,2,3", 220*f16c3236SIan Rogers "CounterHTOff": "0,1,2,3,4,5,6,7", 221*f16c3236SIan Rogers "EventCode": "0x05", 222*f16c3236SIan Rogers "EventName": "MISALIGN_MEM_REF.STORES", 223*f16c3236SIan Rogers "PublicDescription": "Speculative cache-line split store-address uops dispatched to L1D.", 224*f16c3236SIan Rogers "SampleAfterValue": "2000003", 225*f16c3236SIan Rogers "UMask": "0x2" 226*f16c3236SIan Rogers }, 227*f16c3236SIan Rogers { 228*f16c3236SIan Rogers "BriefDescription": "Counts all demand & prefetch code reads miss in the L3", 229*f16c3236SIan Rogers "Counter": "0,1,2,3", 230*f16c3236SIan Rogers "CounterHTOff": "0,1,2,3", 231*f16c3236SIan Rogers "EventCode": "0xB7, 0xBB", 232*f16c3236SIan Rogers "EventName": "OFFCORE_RESPONSE.ALL_CODE_RD.LLC_MISS.ANY_RESPONSE", 233*f16c3236SIan Rogers "MSRIndex": "0x1a6,0x1a7", 234*f16c3236SIan Rogers "MSRValue": "0x3FBFC00244", 235*f16c3236SIan Rogers "Offcore": "1", 236*f16c3236SIan Rogers "PublicDescription": "Counts all demand & prefetch code reads miss in the L3", 237*f16c3236SIan Rogers "SampleAfterValue": "100003", 238*f16c3236SIan Rogers "UMask": "0x1" 239*f16c3236SIan Rogers }, 240*f16c3236SIan Rogers { 241*f16c3236SIan Rogers "BriefDescription": "Counts all demand & prefetch code reads miss the L3 and the data is returned from local dram", 242*f16c3236SIan Rogers "Counter": "0,1,2,3", 243*f16c3236SIan Rogers "CounterHTOff": "0,1,2,3", 244*f16c3236SIan Rogers "EventCode": "0xB7, 0xBB", 245*f16c3236SIan Rogers "EventName": "OFFCORE_RESPONSE.ALL_CODE_RD.LLC_MISS.LOCAL_DRAM", 246*f16c3236SIan Rogers "MSRIndex": "0x1a6,0x1a7", 247*f16c3236SIan Rogers "MSRValue": "0x0600400244", 248*f16c3236SIan Rogers "Offcore": "1", 249*f16c3236SIan Rogers "PublicDescription": "Counts all demand & prefetch code reads miss the L3 and the data is returned from local dram", 250*f16c3236SIan Rogers "SampleAfterValue": "100003", 251*f16c3236SIan Rogers "UMask": "0x1" 252*f16c3236SIan Rogers }, 253*f16c3236SIan Rogers { 254*f16c3236SIan Rogers "BriefDescription": "Counts all demand & prefetch data reads miss in the L3", 255*f16c3236SIan Rogers "Counter": "0,1,2,3", 256*f16c3236SIan Rogers "CounterHTOff": "0,1,2,3", 257*f16c3236SIan Rogers "EventCode": "0xB7, 0xBB", 258*f16c3236SIan Rogers "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_MISS.ANY_RESPONSE", 259*f16c3236SIan Rogers "MSRIndex": "0x1a6,0x1a7", 260*f16c3236SIan Rogers "MSRValue": "0x3FBFC00091", 261*f16c3236SIan Rogers "Offcore": "1", 262*f16c3236SIan Rogers "PublicDescription": "Counts all demand & prefetch data reads miss in the L3", 263*f16c3236SIan Rogers "SampleAfterValue": "100003", 264*f16c3236SIan Rogers "UMask": "0x1" 265*f16c3236SIan Rogers }, 266*f16c3236SIan Rogers { 267*f16c3236SIan Rogers "BriefDescription": "Counts all demand & prefetch data reads miss the L3 and the data is returned from local dram", 268*f16c3236SIan Rogers "Counter": "0,1,2,3", 269*f16c3236SIan Rogers "CounterHTOff": "0,1,2,3", 270*f16c3236SIan Rogers "EventCode": "0xB7, 0xBB", 271*f16c3236SIan Rogers "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_MISS.LOCAL_DRAM", 272*f16c3236SIan Rogers "MSRIndex": "0x1a6,0x1a7", 273*f16c3236SIan Rogers "MSRValue": "0x0600400091", 274*f16c3236SIan Rogers "Offcore": "1", 275*f16c3236SIan Rogers "PublicDescription": "Counts all demand & prefetch data reads miss the L3 and the data is returned from local dram", 276*f16c3236SIan Rogers "SampleAfterValue": "100003", 277*f16c3236SIan Rogers "UMask": "0x1" 278*f16c3236SIan Rogers }, 279*f16c3236SIan Rogers { 280*f16c3236SIan Rogers "BriefDescription": "Counts all demand & prefetch data reads miss the L3 and the data is returned from remote dram", 281*f16c3236SIan Rogers "Counter": "0,1,2,3", 282*f16c3236SIan Rogers "CounterHTOff": "0,1,2,3", 283*f16c3236SIan Rogers "EventCode": "0xB7, 0xBB", 284*f16c3236SIan Rogers "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_MISS.REMOTE_DRAM", 285*f16c3236SIan Rogers "MSRIndex": "0x1a6,0x1a7", 286*f16c3236SIan Rogers "MSRValue": "0x063F800091", 287*f16c3236SIan Rogers "Offcore": "1", 288*f16c3236SIan Rogers "PublicDescription": "Counts all demand & prefetch data reads miss the L3 and the data is returned from remote dram", 289*f16c3236SIan Rogers "SampleAfterValue": "100003", 290*f16c3236SIan Rogers "UMask": "0x1" 291*f16c3236SIan Rogers }, 292*f16c3236SIan Rogers { 293*f16c3236SIan Rogers "BriefDescription": "Counts all demand & prefetch data reads miss the L3 and the modified data is transferred from remote cache", 294*f16c3236SIan Rogers "Counter": "0,1,2,3", 295*f16c3236SIan Rogers "CounterHTOff": "0,1,2,3", 296*f16c3236SIan Rogers "EventCode": "0xB7, 0xBB", 297*f16c3236SIan Rogers "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_MISS.REMOTE_HITM", 298*f16c3236SIan Rogers "MSRIndex": "0x1a6,0x1a7", 299*f16c3236SIan Rogers "MSRValue": "0x103FC00091", 300*f16c3236SIan Rogers "Offcore": "1", 301*f16c3236SIan Rogers "PublicDescription": "Counts all demand & prefetch data reads miss the L3 and the modified data is transferred from remote cache", 302*f16c3236SIan Rogers "SampleAfterValue": "100003", 303*f16c3236SIan Rogers "UMask": "0x1" 304*f16c3236SIan Rogers }, 305*f16c3236SIan Rogers { 306*f16c3236SIan Rogers "BriefDescription": "Counts all demand & prefetch data reads miss the L3 and clean or shared data is transferred from remote cache", 307*f16c3236SIan Rogers "Counter": "0,1,2,3", 308*f16c3236SIan Rogers "CounterHTOff": "0,1,2,3", 309*f16c3236SIan Rogers "EventCode": "0xB7, 0xBB", 310*f16c3236SIan Rogers "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_MISS.REMOTE_HIT_FORWARD", 311*f16c3236SIan Rogers "MSRIndex": "0x1a6,0x1a7", 312*f16c3236SIan Rogers "MSRValue": "0x083FC00091", 313*f16c3236SIan Rogers "Offcore": "1", 314*f16c3236SIan Rogers "PublicDescription": "Counts all demand & prefetch data reads miss the L3 and clean or shared data is transferred from remote cache", 315*f16c3236SIan Rogers "SampleAfterValue": "100003", 316*f16c3236SIan Rogers "UMask": "0x1" 317*f16c3236SIan Rogers }, 318*f16c3236SIan Rogers { 319*f16c3236SIan Rogers "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) miss in the L3", 320*f16c3236SIan Rogers "Counter": "0,1,2,3", 321*f16c3236SIan Rogers "CounterHTOff": "0,1,2,3", 322*f16c3236SIan Rogers "EventCode": "0xB7, 0xBB", 323*f16c3236SIan Rogers "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_MISS.ANY_RESPONSE", 324*f16c3236SIan Rogers "MSRIndex": "0x1a6,0x1a7", 325*f16c3236SIan Rogers "MSRValue": "0x3FBFC007F7", 326*f16c3236SIan Rogers "Offcore": "1", 327*f16c3236SIan Rogers "PublicDescription": "Counts all data/code/rfo reads (demand & prefetch) miss in the L3", 328*f16c3236SIan Rogers "SampleAfterValue": "100003", 329*f16c3236SIan Rogers "UMask": "0x1" 330*f16c3236SIan Rogers }, 331*f16c3236SIan Rogers { 332*f16c3236SIan Rogers "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) miss the L3 and the data is returned from local dram", 333*f16c3236SIan Rogers "Counter": "0,1,2,3", 334*f16c3236SIan Rogers "CounterHTOff": "0,1,2,3", 335*f16c3236SIan Rogers "EventCode": "0xB7, 0xBB", 336*f16c3236SIan Rogers "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_MISS.LOCAL_DRAM", 337*f16c3236SIan Rogers "MSRIndex": "0x1a6,0x1a7", 338*f16c3236SIan Rogers "MSRValue": "0x06004007F7", 339*f16c3236SIan Rogers "Offcore": "1", 340*f16c3236SIan Rogers "PublicDescription": "Counts all data/code/rfo reads (demand & prefetch) miss the L3 and the data is returned from local dram", 341*f16c3236SIan Rogers "SampleAfterValue": "100003", 342*f16c3236SIan Rogers "UMask": "0x1" 343*f16c3236SIan Rogers }, 344*f16c3236SIan Rogers { 345*f16c3236SIan Rogers "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) miss the L3 and the data is returned from remote dram", 346*f16c3236SIan Rogers "Counter": "0,1,2,3", 347*f16c3236SIan Rogers "CounterHTOff": "0,1,2,3", 348*f16c3236SIan Rogers "EventCode": "0xB7, 0xBB", 349*f16c3236SIan Rogers "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_MISS.REMOTE_DRAM", 350*f16c3236SIan Rogers "MSRIndex": "0x1a6,0x1a7", 351*f16c3236SIan Rogers "MSRValue": "0x063F8007F7", 352*f16c3236SIan Rogers "Offcore": "1", 353*f16c3236SIan Rogers "PublicDescription": "Counts all data/code/rfo reads (demand & prefetch) miss the L3 and the data is returned from remote dram", 354*f16c3236SIan Rogers "SampleAfterValue": "100003", 355*f16c3236SIan Rogers "UMask": "0x1" 356*f16c3236SIan Rogers }, 357*f16c3236SIan Rogers { 358*f16c3236SIan Rogers "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) miss the L3 and the modified data is transferred from remote cache", 359*f16c3236SIan Rogers "Counter": "0,1,2,3", 360*f16c3236SIan Rogers "CounterHTOff": "0,1,2,3", 361*f16c3236SIan Rogers "EventCode": "0xB7, 0xBB", 362*f16c3236SIan Rogers "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_MISS.REMOTE_HITM", 363*f16c3236SIan Rogers "MSRIndex": "0x1a6,0x1a7", 364*f16c3236SIan Rogers "MSRValue": "0x103FC007F7", 365*f16c3236SIan Rogers "Offcore": "1", 366*f16c3236SIan Rogers "PublicDescription": "Counts all data/code/rfo reads (demand & prefetch) miss the L3 and the modified data is transferred from remote cache", 367*f16c3236SIan Rogers "SampleAfterValue": "100003", 368*f16c3236SIan Rogers "UMask": "0x1" 369*f16c3236SIan Rogers }, 370*f16c3236SIan Rogers { 371*f16c3236SIan Rogers "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) miss the L3 and clean or shared data is transferred from remote cache", 372*f16c3236SIan Rogers "Counter": "0,1,2,3", 373*f16c3236SIan Rogers "CounterHTOff": "0,1,2,3", 374*f16c3236SIan Rogers "EventCode": "0xB7, 0xBB", 375*f16c3236SIan Rogers "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_MISS.REMOTE_HIT_FORWARD", 376*f16c3236SIan Rogers "MSRIndex": "0x1a6,0x1a7", 377*f16c3236SIan Rogers "MSRValue": "0x083FC007F7", 378*f16c3236SIan Rogers "Offcore": "1", 379*f16c3236SIan Rogers "PublicDescription": "Counts all data/code/rfo reads (demand & prefetch) miss the L3 and clean or shared data is transferred from remote cache", 380*f16c3236SIan Rogers "SampleAfterValue": "100003", 381*f16c3236SIan Rogers "UMask": "0x1" 382*f16c3236SIan Rogers }, 383*f16c3236SIan Rogers { 384*f16c3236SIan Rogers "BriefDescription": "Counts all requests miss in the L3", 385*f16c3236SIan Rogers "Counter": "0,1,2,3", 386*f16c3236SIan Rogers "CounterHTOff": "0,1,2,3", 387*f16c3236SIan Rogers "EventCode": "0xB7, 0xBB", 388*f16c3236SIan Rogers "EventName": "OFFCORE_RESPONSE.ALL_REQUESTS.LLC_MISS.ANY_RESPONSE", 389*f16c3236SIan Rogers "MSRIndex": "0x1a6,0x1a7", 390*f16c3236SIan Rogers "MSRValue": "0x3FBFC08FFF", 391*f16c3236SIan Rogers "Offcore": "1", 392*f16c3236SIan Rogers "PublicDescription": "Counts all requests miss in the L3", 393*f16c3236SIan Rogers "SampleAfterValue": "100003", 394*f16c3236SIan Rogers "UMask": "0x1" 395*f16c3236SIan Rogers }, 396*f16c3236SIan Rogers { 397*f16c3236SIan Rogers "BriefDescription": "Counts all demand & prefetch RFOs miss in the L3", 398*f16c3236SIan Rogers "Counter": "0,1,2,3", 399*f16c3236SIan Rogers "CounterHTOff": "0,1,2,3", 400*f16c3236SIan Rogers "EventCode": "0xB7, 0xBB", 401*f16c3236SIan Rogers "EventName": "OFFCORE_RESPONSE.ALL_RFO.LLC_MISS.ANY_RESPONSE", 402*f16c3236SIan Rogers "MSRIndex": "0x1a6,0x1a7", 403*f16c3236SIan Rogers "MSRValue": "0x3FBFC00122", 404*f16c3236SIan Rogers "Offcore": "1", 405*f16c3236SIan Rogers "PublicDescription": "Counts all demand & prefetch RFOs miss in the L3", 406*f16c3236SIan Rogers "SampleAfterValue": "100003", 407*f16c3236SIan Rogers "UMask": "0x1" 408*f16c3236SIan Rogers }, 409*f16c3236SIan Rogers { 410*f16c3236SIan Rogers "BriefDescription": "Counts all demand & prefetch RFOs miss the L3 and the data is returned from local dram", 411*f16c3236SIan Rogers "Counter": "0,1,2,3", 412*f16c3236SIan Rogers "CounterHTOff": "0,1,2,3", 413*f16c3236SIan Rogers "EventCode": "0xB7, 0xBB", 414*f16c3236SIan Rogers "EventName": "OFFCORE_RESPONSE.ALL_RFO.LLC_MISS.LOCAL_DRAM", 415*f16c3236SIan Rogers "MSRIndex": "0x1a6,0x1a7", 416*f16c3236SIan Rogers "MSRValue": "0x0600400122", 417*f16c3236SIan Rogers "Offcore": "1", 418*f16c3236SIan Rogers "PublicDescription": "Counts all demand & prefetch RFOs miss the L3 and the data is returned from local dram", 419*f16c3236SIan Rogers "SampleAfterValue": "100003", 420*f16c3236SIan Rogers "UMask": "0x1" 421*f16c3236SIan Rogers }, 422*f16c3236SIan Rogers { 423*f16c3236SIan Rogers "BriefDescription": "Counts all demand code reads miss in the L3", 424*f16c3236SIan Rogers "Counter": "0,1,2,3", 425*f16c3236SIan Rogers "CounterHTOff": "0,1,2,3", 426*f16c3236SIan Rogers "EventCode": "0xB7, 0xBB", 427*f16c3236SIan Rogers "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_MISS.ANY_RESPONSE", 428*f16c3236SIan Rogers "MSRIndex": "0x1a6,0x1a7", 429*f16c3236SIan Rogers "MSRValue": "0x3FBFC00004", 430*f16c3236SIan Rogers "Offcore": "1", 431*f16c3236SIan Rogers "PublicDescription": "Counts all demand code reads miss in the L3", 432*f16c3236SIan Rogers "SampleAfterValue": "100003", 433*f16c3236SIan Rogers "UMask": "0x1" 434*f16c3236SIan Rogers }, 435*f16c3236SIan Rogers { 436*f16c3236SIan Rogers "BriefDescription": "Counts all demand code reads miss the L3 and the data is returned from local dram", 437*f16c3236SIan Rogers "Counter": "0,1,2,3", 438*f16c3236SIan Rogers "CounterHTOff": "0,1,2,3", 439*f16c3236SIan Rogers "EventCode": "0xB7, 0xBB", 440*f16c3236SIan Rogers "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_MISS.LOCAL_DRAM", 441*f16c3236SIan Rogers "MSRIndex": "0x1a6,0x1a7", 442*f16c3236SIan Rogers "MSRValue": "0x0600400004", 443*f16c3236SIan Rogers "Offcore": "1", 444*f16c3236SIan Rogers "PublicDescription": "Counts all demand code reads miss the L3 and the data is returned from local dram", 445*f16c3236SIan Rogers "SampleAfterValue": "100003", 446*f16c3236SIan Rogers "UMask": "0x1" 447*f16c3236SIan Rogers }, 448*f16c3236SIan Rogers { 449*f16c3236SIan Rogers "BriefDescription": "Counts demand data reads miss in the L3", 450*f16c3236SIan Rogers "Counter": "0,1,2,3", 451*f16c3236SIan Rogers "CounterHTOff": "0,1,2,3", 452*f16c3236SIan Rogers "EventCode": "0xB7, 0xBB", 453*f16c3236SIan Rogers "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_MISS.ANY_RESPONSE", 454*f16c3236SIan Rogers "MSRIndex": "0x1a6,0x1a7", 455*f16c3236SIan Rogers "MSRValue": "0x3FBFC00001", 456*f16c3236SIan Rogers "Offcore": "1", 457*f16c3236SIan Rogers "PublicDescription": "Counts demand data reads miss in the L3", 458*f16c3236SIan Rogers "SampleAfterValue": "100003", 459*f16c3236SIan Rogers "UMask": "0x1" 460*f16c3236SIan Rogers }, 461*f16c3236SIan Rogers { 462*f16c3236SIan Rogers "BriefDescription": "Counts demand data reads miss the L3 and the data is returned from local dram", 463*f16c3236SIan Rogers "Counter": "0,1,2,3", 464*f16c3236SIan Rogers "CounterHTOff": "0,1,2,3", 465*f16c3236SIan Rogers "EventCode": "0xB7, 0xBB", 466*f16c3236SIan Rogers "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_MISS.LOCAL_DRAM", 467*f16c3236SIan Rogers "MSRIndex": "0x1a6,0x1a7", 468*f16c3236SIan Rogers "MSRValue": "0x0600400001", 469*f16c3236SIan Rogers "Offcore": "1", 470*f16c3236SIan Rogers "PublicDescription": "Counts demand data reads miss the L3 and the data is returned from local dram", 471*f16c3236SIan Rogers "SampleAfterValue": "100003", 472*f16c3236SIan Rogers "UMask": "0x1" 473*f16c3236SIan Rogers }, 474*f16c3236SIan Rogers { 475*f16c3236SIan Rogers "BriefDescription": "Counts all demand data writes (RFOs) miss in the L3", 476*f16c3236SIan Rogers "Counter": "0,1,2,3", 477*f16c3236SIan Rogers "CounterHTOff": "0,1,2,3", 478*f16c3236SIan Rogers "EventCode": "0xB7, 0xBB", 479*f16c3236SIan Rogers "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_MISS.ANY_RESPONSE", 480*f16c3236SIan Rogers "MSRIndex": "0x1a6,0x1a7", 481*f16c3236SIan Rogers "MSRValue": "0x3FBFC00002", 482*f16c3236SIan Rogers "Offcore": "1", 483*f16c3236SIan Rogers "PublicDescription": "Counts all demand data writes (RFOs) miss in the L3", 484*f16c3236SIan Rogers "SampleAfterValue": "100003", 485*f16c3236SIan Rogers "UMask": "0x1" 486*f16c3236SIan Rogers }, 487*f16c3236SIan Rogers { 488*f16c3236SIan Rogers "BriefDescription": "Counts all demand data writes (RFOs) miss the L3 and the data is returned from local dram", 489*f16c3236SIan Rogers "Counter": "0,1,2,3", 490*f16c3236SIan Rogers "CounterHTOff": "0,1,2,3", 491*f16c3236SIan Rogers "EventCode": "0xB7, 0xBB", 492*f16c3236SIan Rogers "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_MISS.LOCAL_DRAM", 493*f16c3236SIan Rogers "MSRIndex": "0x1a6,0x1a7", 494*f16c3236SIan Rogers "MSRValue": "0x0600400002", 495*f16c3236SIan Rogers "Offcore": "1", 496*f16c3236SIan Rogers "PublicDescription": "Counts all demand data writes (RFOs) miss the L3 and the data is returned from local dram", 497*f16c3236SIan Rogers "SampleAfterValue": "100003", 498*f16c3236SIan Rogers "UMask": "0x1" 499*f16c3236SIan Rogers }, 500*f16c3236SIan Rogers { 501*f16c3236SIan Rogers "BriefDescription": "Counts all demand data writes (RFOs) miss the L3 and the modified data is transferred from remote cache", 502*f16c3236SIan Rogers "Counter": "0,1,2,3", 503*f16c3236SIan Rogers "CounterHTOff": "0,1,2,3", 504*f16c3236SIan Rogers "EventCode": "0xB7, 0xBB", 505*f16c3236SIan Rogers "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_MISS.REMOTE_HITM", 506*f16c3236SIan Rogers "MSRIndex": "0x1a6,0x1a7", 507*f16c3236SIan Rogers "MSRValue": "0x103FC00002", 508*f16c3236SIan Rogers "Offcore": "1", 509*f16c3236SIan Rogers "PublicDescription": "Counts all demand data writes (RFOs) miss the L3 and the modified data is transferred from remote cache", 510*f16c3236SIan Rogers "SampleAfterValue": "100003", 511*f16c3236SIan Rogers "UMask": "0x1" 512*f16c3236SIan Rogers }, 513*f16c3236SIan Rogers { 514*f16c3236SIan Rogers "BriefDescription": "Counts all prefetch (that bring data to LLC only) code reads miss in the L3", 515*f16c3236SIan Rogers "Counter": "0,1,2,3", 516*f16c3236SIan Rogers "CounterHTOff": "0,1,2,3", 517*f16c3236SIan Rogers "EventCode": "0xB7, 0xBB", 518*f16c3236SIan Rogers "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.LLC_MISS.ANY_RESPONSE", 519*f16c3236SIan Rogers "MSRIndex": "0x1a6,0x1a7", 520*f16c3236SIan Rogers "MSRValue": "0x3FBFC00040", 521*f16c3236SIan Rogers "Offcore": "1", 522*f16c3236SIan Rogers "PublicDescription": "Counts all prefetch (that bring data to LLC only) code reads miss in the L3", 523*f16c3236SIan Rogers "SampleAfterValue": "100003", 524*f16c3236SIan Rogers "UMask": "0x1" 525*f16c3236SIan Rogers }, 526*f16c3236SIan Rogers { 527*f16c3236SIan Rogers "BriefDescription": "Counts prefetch (that bring data to L2) data reads miss in the L3", 528*f16c3236SIan Rogers "Counter": "0,1,2,3", 529*f16c3236SIan Rogers "CounterHTOff": "0,1,2,3", 530*f16c3236SIan Rogers "EventCode": "0xB7, 0xBB", 531*f16c3236SIan Rogers "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_MISS.ANY_RESPONSE", 532*f16c3236SIan Rogers "MSRIndex": "0x1a6,0x1a7", 533*f16c3236SIan Rogers "MSRValue": "0x3FBFC00010", 534*f16c3236SIan Rogers "Offcore": "1", 535*f16c3236SIan Rogers "PublicDescription": "Counts prefetch (that bring data to L2) data reads miss in the L3", 536*f16c3236SIan Rogers "SampleAfterValue": "100003", 537*f16c3236SIan Rogers "UMask": "0x1" 538*f16c3236SIan Rogers }, 539*f16c3236SIan Rogers { 540*f16c3236SIan Rogers "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs miss in the L3", 541*f16c3236SIan Rogers "Counter": "0,1,2,3", 542*f16c3236SIan Rogers "CounterHTOff": "0,1,2,3", 543*f16c3236SIan Rogers "EventCode": "0xB7, 0xBB", 544*f16c3236SIan Rogers "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.LLC_MISS.ANY_RESPONSE", 545*f16c3236SIan Rogers "MSRIndex": "0x1a6,0x1a7", 546*f16c3236SIan Rogers "MSRValue": "0x3FBFC00020", 547*f16c3236SIan Rogers "Offcore": "1", 548*f16c3236SIan Rogers "PublicDescription": "Counts all prefetch (that bring data to L2) RFOs miss in the L3", 549*f16c3236SIan Rogers "SampleAfterValue": "100003", 550*f16c3236SIan Rogers "UMask": "0x1" 551*f16c3236SIan Rogers }, 552*f16c3236SIan Rogers { 553*f16c3236SIan Rogers "BriefDescription": "Counts prefetch (that bring data to LLC only) code reads miss in the L3", 554*f16c3236SIan Rogers "Counter": "0,1,2,3", 555*f16c3236SIan Rogers "CounterHTOff": "0,1,2,3", 556*f16c3236SIan Rogers "EventCode": "0xB7, 0xBB", 557*f16c3236SIan Rogers "EventName": "OFFCORE_RESPONSE.PF_LLC_CODE_RD.LLC_MISS.ANY_RESPONSE", 558*f16c3236SIan Rogers "MSRIndex": "0x1a6,0x1a7", 559*f16c3236SIan Rogers "MSRValue": "0x3FBFC00200", 560*f16c3236SIan Rogers "Offcore": "1", 561*f16c3236SIan Rogers "PublicDescription": "Counts prefetch (that bring data to LLC only) code reads miss in the L3", 562*f16c3236SIan Rogers "SampleAfterValue": "100003", 563*f16c3236SIan Rogers "UMask": "0x1" 564*f16c3236SIan Rogers }, 565*f16c3236SIan Rogers { 566*f16c3236SIan Rogers "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads miss in the L3", 567*f16c3236SIan Rogers "Counter": "0,1,2,3", 568*f16c3236SIan Rogers "CounterHTOff": "0,1,2,3", 569*f16c3236SIan Rogers "EventCode": "0xB7, 0xBB", 570*f16c3236SIan Rogers "EventName": "OFFCORE_RESPONSE.PF_LLC_DATA_RD.LLC_MISS.ANY_RESPONSE", 571*f16c3236SIan Rogers "MSRIndex": "0x1a6,0x1a7", 572*f16c3236SIan Rogers "MSRValue": "0x3FBFC00080", 573*f16c3236SIan Rogers "Offcore": "1", 574*f16c3236SIan Rogers "PublicDescription": "Counts all prefetch (that bring data to LLC only) data reads miss in the L3", 575*f16c3236SIan Rogers "SampleAfterValue": "100003", 576*f16c3236SIan Rogers "UMask": "0x1" 577*f16c3236SIan Rogers }, 578*f16c3236SIan Rogers { 579*f16c3236SIan Rogers "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs miss in the L3", 580*f16c3236SIan Rogers "Counter": "0,1,2,3", 581*f16c3236SIan Rogers "CounterHTOff": "0,1,2,3", 582*f16c3236SIan Rogers "EventCode": "0xB7, 0xBB", 583*f16c3236SIan Rogers "EventName": "OFFCORE_RESPONSE.PF_LLC_RFO.LLC_MISS.ANY_RESPONSE", 584*f16c3236SIan Rogers "MSRIndex": "0x1a6,0x1a7", 585*f16c3236SIan Rogers "MSRValue": "0x3FBFC00100", 586*f16c3236SIan Rogers "Offcore": "1", 587*f16c3236SIan Rogers "PublicDescription": "Counts all prefetch (that bring data to LLC only) RFOs miss in the L3", 588*f16c3236SIan Rogers "SampleAfterValue": "100003", 589*f16c3236SIan Rogers "UMask": "0x1" 590*f16c3236SIan Rogers }, 591*f16c3236SIan Rogers { 592ede00740SAndi Kleen "BriefDescription": "Number of times an RTM execution aborted due to any reasons (multiple categories may count as one).", 593ede00740SAndi Kleen "Counter": "0,1,2,3", 594*f16c3236SIan Rogers "CounterHTOff": "0,1,2,3", 595*f16c3236SIan Rogers "EventCode": "0xc9", 596ede00740SAndi Kleen "EventName": "RTM_RETIRED.ABORTED", 597*f16c3236SIan Rogers "PEBS": "1", 598ede00740SAndi Kleen "SampleAfterValue": "2000003", 599*f16c3236SIan Rogers "UMask": "0x4" 600ede00740SAndi Kleen }, 601ede00740SAndi Kleen { 602ede00740SAndi Kleen "BriefDescription": "Number of times an RTM execution aborted due to various memory events (e.g. read/write capacity and conflicts)", 603ede00740SAndi Kleen "Counter": "0,1,2,3", 604*f16c3236SIan Rogers "CounterHTOff": "0,1,2,3", 605*f16c3236SIan Rogers "EventCode": "0xc9", 606ede00740SAndi Kleen "EventName": "RTM_RETIRED.ABORTED_MISC1", 607ede00740SAndi Kleen "PublicDescription": "Number of times an RTM execution aborted due to various memory events (e.g. read/write capacity and conflicts).", 608ede00740SAndi Kleen "SampleAfterValue": "2000003", 609*f16c3236SIan Rogers "UMask": "0x8" 610ede00740SAndi Kleen }, 611ede00740SAndi Kleen { 612ede00740SAndi Kleen "BriefDescription": "Number of times an RTM execution aborted due to various memory events (e.g., read/write capacity and conflicts).", 613ede00740SAndi Kleen "Counter": "0,1,2,3", 614*f16c3236SIan Rogers "CounterHTOff": "0,1,2,3", 615*f16c3236SIan Rogers "EventCode": "0xc9", 616ede00740SAndi Kleen "EventName": "RTM_RETIRED.ABORTED_MISC2", 617ede00740SAndi Kleen "SampleAfterValue": "2000003", 618*f16c3236SIan Rogers "UMask": "0x10" 619ede00740SAndi Kleen }, 620ede00740SAndi Kleen { 621ede00740SAndi Kleen "BriefDescription": "Number of times an RTM execution aborted due to HLE-unfriendly instructions.", 622ede00740SAndi Kleen "Counter": "0,1,2,3", 623*f16c3236SIan Rogers "CounterHTOff": "0,1,2,3", 624*f16c3236SIan Rogers "EventCode": "0xc9", 625ede00740SAndi Kleen "EventName": "RTM_RETIRED.ABORTED_MISC3", 626ede00740SAndi Kleen "SampleAfterValue": "2000003", 627*f16c3236SIan Rogers "UMask": "0x20" 628ede00740SAndi Kleen }, 629ede00740SAndi Kleen { 630ede00740SAndi Kleen "BriefDescription": "Number of times an RTM execution aborted due to incompatible memory type.", 631ede00740SAndi Kleen "Counter": "0,1,2,3", 632*f16c3236SIan Rogers "CounterHTOff": "0,1,2,3", 633ede00740SAndi Kleen "Errata": "HSD65", 634*f16c3236SIan Rogers "EventCode": "0xc9", 635*f16c3236SIan Rogers "EventName": "RTM_RETIRED.ABORTED_MISC4", 636ede00740SAndi Kleen "SampleAfterValue": "2000003", 637*f16c3236SIan Rogers "UMask": "0x40" 638ede00740SAndi Kleen }, 639ede00740SAndi Kleen { 640ede00740SAndi Kleen "BriefDescription": "Number of times an RTM execution aborted due to none of the previous 4 categories (e.g. interrupt)", 641ede00740SAndi Kleen "Counter": "0,1,2,3", 642*f16c3236SIan Rogers "CounterHTOff": "0,1,2,3", 643*f16c3236SIan Rogers "EventCode": "0xc9", 644ede00740SAndi Kleen "EventName": "RTM_RETIRED.ABORTED_MISC5", 645ede00740SAndi Kleen "PublicDescription": "Number of times an RTM execution aborted due to none of the previous 4 categories (e.g. interrupt).", 646ede00740SAndi Kleen "SampleAfterValue": "2000003", 647*f16c3236SIan Rogers "UMask": "0x80" 648ede00740SAndi Kleen }, 649ede00740SAndi Kleen { 650*f16c3236SIan Rogers "BriefDescription": "Number of times an RTM execution successfully committed.", 651ede00740SAndi Kleen "Counter": "0,1,2,3", 652*f16c3236SIan Rogers "CounterHTOff": "0,1,2,3", 653*f16c3236SIan Rogers "EventCode": "0xc9", 654*f16c3236SIan Rogers "EventName": "RTM_RETIRED.COMMIT", 655*f16c3236SIan Rogers "SampleAfterValue": "2000003", 656*f16c3236SIan Rogers "UMask": "0x2" 657ede00740SAndi Kleen }, 658ede00740SAndi Kleen { 659*f16c3236SIan Rogers "BriefDescription": "Number of times an RTM execution started.", 660ede00740SAndi Kleen "Counter": "0,1,2,3", 661*f16c3236SIan Rogers "CounterHTOff": "0,1,2,3", 662*f16c3236SIan Rogers "EventCode": "0xC9", 663*f16c3236SIan Rogers "EventName": "RTM_RETIRED.START", 664*f16c3236SIan Rogers "SampleAfterValue": "2000003", 665*f16c3236SIan Rogers "UMask": "0x1" 666ede00740SAndi Kleen }, 667ede00740SAndi Kleen { 668*f16c3236SIan Rogers "BriefDescription": "Counts the number of times a class of instructions that may cause a transactional abort was executed. Since this is the count of execution, it may not always cause a transactional abort.", 669ede00740SAndi Kleen "Counter": "0,1,2,3", 670*f16c3236SIan Rogers "CounterHTOff": "0,1,2,3,4,5,6,7", 671*f16c3236SIan Rogers "EventCode": "0x5d", 672*f16c3236SIan Rogers "EventName": "TX_EXEC.MISC1", 673*f16c3236SIan Rogers "SampleAfterValue": "2000003", 674*f16c3236SIan Rogers "UMask": "0x1" 675ede00740SAndi Kleen }, 676ede00740SAndi Kleen { 677*f16c3236SIan Rogers "BriefDescription": "Counts the number of times a class of instructions (e.g., vzeroupper) that may cause a transactional abort was executed inside a transactional region.", 678ede00740SAndi Kleen "Counter": "0,1,2,3", 679*f16c3236SIan Rogers "CounterHTOff": "0,1,2,3,4,5,6,7", 680*f16c3236SIan Rogers "EventCode": "0x5d", 681*f16c3236SIan Rogers "EventName": "TX_EXEC.MISC2", 682*f16c3236SIan Rogers "SampleAfterValue": "2000003", 683*f16c3236SIan Rogers "UMask": "0x2" 684ede00740SAndi Kleen }, 685ede00740SAndi Kleen { 686*f16c3236SIan Rogers "BriefDescription": "Counts the number of times an instruction execution caused the transactional nest count supported to be exceeded.", 687ede00740SAndi Kleen "Counter": "0,1,2,3", 688*f16c3236SIan Rogers "CounterHTOff": "0,1,2,3,4,5,6,7", 689*f16c3236SIan Rogers "EventCode": "0x5d", 690*f16c3236SIan Rogers "EventName": "TX_EXEC.MISC3", 691*f16c3236SIan Rogers "SampleAfterValue": "2000003", 692*f16c3236SIan Rogers "UMask": "0x4" 693ede00740SAndi Kleen }, 694ede00740SAndi Kleen { 695*f16c3236SIan Rogers "BriefDescription": "Counts the number of times a XBEGIN instruction was executed inside an HLE transactional region.", 696ede00740SAndi Kleen "Counter": "0,1,2,3", 697*f16c3236SIan Rogers "CounterHTOff": "0,1,2,3,4,5,6,7", 698*f16c3236SIan Rogers "EventCode": "0x5d", 699*f16c3236SIan Rogers "EventName": "TX_EXEC.MISC4", 700*f16c3236SIan Rogers "SampleAfterValue": "2000003", 701*f16c3236SIan Rogers "UMask": "0x8" 702ede00740SAndi Kleen }, 703ede00740SAndi Kleen { 704*f16c3236SIan Rogers "BriefDescription": "Counts the number of times an HLE XACQUIRE instruction was executed inside an RTM transactional region.", 705ede00740SAndi Kleen "Counter": "0,1,2,3", 706*f16c3236SIan Rogers "CounterHTOff": "0,1,2,3,4,5,6,7", 707*f16c3236SIan Rogers "EventCode": "0x5d", 708*f16c3236SIan Rogers "EventName": "TX_EXEC.MISC5", 709*f16c3236SIan Rogers "SampleAfterValue": "2000003", 710*f16c3236SIan Rogers "UMask": "0x10" 711ede00740SAndi Kleen }, 712ede00740SAndi Kleen { 713*f16c3236SIan Rogers "BriefDescription": "Number of times a transactional abort was signaled due to a data capacity limitation for transactional writes.", 714ede00740SAndi Kleen "Counter": "0,1,2,3", 715*f16c3236SIan Rogers "CounterHTOff": "0,1,2,3,4,5,6,7", 716*f16c3236SIan Rogers "EventCode": "0x54", 717*f16c3236SIan Rogers "EventName": "TX_MEM.ABORT_CAPACITY_WRITE", 718*f16c3236SIan Rogers "SampleAfterValue": "2000003", 719*f16c3236SIan Rogers "UMask": "0x2" 720ede00740SAndi Kleen }, 721ede00740SAndi Kleen { 722*f16c3236SIan Rogers "BriefDescription": "Number of times a transactional abort was signaled due to a data conflict on a transactionally accessed address.", 723ede00740SAndi Kleen "Counter": "0,1,2,3", 724*f16c3236SIan Rogers "CounterHTOff": "0,1,2,3,4,5,6,7", 725*f16c3236SIan Rogers "EventCode": "0x54", 726*f16c3236SIan Rogers "EventName": "TX_MEM.ABORT_CONFLICT", 727*f16c3236SIan Rogers "SampleAfterValue": "2000003", 728*f16c3236SIan Rogers "UMask": "0x1" 729ede00740SAndi Kleen }, 730ede00740SAndi Kleen { 731*f16c3236SIan Rogers "BriefDescription": "Number of times an HLE transactional execution aborted due to XRELEASE lock not satisfying the address and value requirements in the elision buffer.", 732ede00740SAndi Kleen "Counter": "0,1,2,3", 733*f16c3236SIan Rogers "CounterHTOff": "0,1,2,3,4,5,6,7", 734*f16c3236SIan Rogers "EventCode": "0x54", 735*f16c3236SIan Rogers "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_MISMATCH", 736*f16c3236SIan Rogers "SampleAfterValue": "2000003", 737*f16c3236SIan Rogers "UMask": "0x10" 738ede00740SAndi Kleen }, 739ede00740SAndi Kleen { 740*f16c3236SIan Rogers "BriefDescription": "Number of times an HLE transactional execution aborted due to NoAllocatedElisionBuffer being non-zero.", 741ede00740SAndi Kleen "Counter": "0,1,2,3", 742*f16c3236SIan Rogers "CounterHTOff": "0,1,2,3,4,5,6,7", 743*f16c3236SIan Rogers "EventCode": "0x54", 744*f16c3236SIan Rogers "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_NOT_EMPTY", 745*f16c3236SIan Rogers "SampleAfterValue": "2000003", 746*f16c3236SIan Rogers "UMask": "0x8" 747ede00740SAndi Kleen }, 748ede00740SAndi Kleen { 749*f16c3236SIan Rogers "BriefDescription": "Number of times an HLE transactional execution aborted due to an unsupported read alignment from the elision buffer.", 750ede00740SAndi Kleen "Counter": "0,1,2,3", 751*f16c3236SIan Rogers "CounterHTOff": "0,1,2,3,4,5,6,7", 752*f16c3236SIan Rogers "EventCode": "0x54", 753*f16c3236SIan Rogers "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_UNSUPPORTED_ALIGNMENT", 754*f16c3236SIan Rogers "SampleAfterValue": "2000003", 755*f16c3236SIan Rogers "UMask": "0x20" 756ede00740SAndi Kleen }, 757ede00740SAndi Kleen { 758*f16c3236SIan Rogers "BriefDescription": "Number of times a HLE transactional region aborted due to a non XRELEASE prefixed instruction writing to an elided lock in the elision buffer.", 759ede00740SAndi Kleen "Counter": "0,1,2,3", 760*f16c3236SIan Rogers "CounterHTOff": "0,1,2,3,4,5,6,7", 761*f16c3236SIan Rogers "EventCode": "0x54", 762*f16c3236SIan Rogers "EventName": "TX_MEM.ABORT_HLE_STORE_TO_ELIDED_LOCK", 763*f16c3236SIan Rogers "SampleAfterValue": "2000003", 764*f16c3236SIan Rogers "UMask": "0x4" 765ede00740SAndi Kleen }, 766ede00740SAndi Kleen { 767*f16c3236SIan Rogers "BriefDescription": "Number of times HLE lock could not be elided due to ElisionBufferAvailable being zero.", 768ede00740SAndi Kleen "Counter": "0,1,2,3", 769*f16c3236SIan Rogers "CounterHTOff": "0,1,2,3,4,5,6,7", 770*f16c3236SIan Rogers "EventCode": "0x54", 771*f16c3236SIan Rogers "EventName": "TX_MEM.HLE_ELISION_BUFFER_FULL", 772*f16c3236SIan Rogers "SampleAfterValue": "2000003", 773*f16c3236SIan Rogers "UMask": "0x40" 774ede00740SAndi Kleen } 775ede00740SAndi Kleen]