1ede00740SAndi Kleen[ 2ede00740SAndi Kleen { 3ede00740SAndi Kleen "BriefDescription": "Number of times an HLE execution aborted due to any reasons (multiple categories may count as one).", 4ede00740SAndi Kleen "Counter": "0,1,2,3", 5f16c3236SIan Rogers "CounterHTOff": "0,1,2,3,4,5,6,7", 6f16c3236SIan Rogers "EventCode": "0xc8", 7ede00740SAndi Kleen "EventName": "HLE_RETIRED.ABORTED", 8f16c3236SIan Rogers "PEBS": "1", 9ede00740SAndi Kleen "SampleAfterValue": "2000003", 10f16c3236SIan Rogers "UMask": "0x4" 11ede00740SAndi Kleen }, 12ede00740SAndi Kleen { 13ede00740SAndi Kleen "BriefDescription": "Number of times an HLE execution aborted due to various memory events (e.g., read/write capacity and conflicts).", 14ede00740SAndi Kleen "Counter": "0,1,2,3", 15f16c3236SIan Rogers "CounterHTOff": "0,1,2,3,4,5,6,7", 16f16c3236SIan Rogers "EventCode": "0xc8", 17ede00740SAndi Kleen "EventName": "HLE_RETIRED.ABORTED_MISC1", 18ede00740SAndi Kleen "SampleAfterValue": "2000003", 19f16c3236SIan Rogers "UMask": "0x8" 20ede00740SAndi Kleen }, 21ede00740SAndi Kleen { 22ede00740SAndi Kleen "BriefDescription": "Number of times an HLE execution aborted due to uncommon conditions.", 23ede00740SAndi Kleen "Counter": "0,1,2,3", 24f16c3236SIan Rogers "CounterHTOff": "0,1,2,3,4,5,6,7", 25f16c3236SIan Rogers "EventCode": "0xc8", 26ede00740SAndi Kleen "EventName": "HLE_RETIRED.ABORTED_MISC2", 27ede00740SAndi Kleen "SampleAfterValue": "2000003", 28f16c3236SIan Rogers "UMask": "0x10" 29ede00740SAndi Kleen }, 30ede00740SAndi Kleen { 31ede00740SAndi Kleen "BriefDescription": "Number of times an HLE execution aborted due to HLE-unfriendly instructions.", 32ede00740SAndi Kleen "Counter": "0,1,2,3", 33f16c3236SIan Rogers "CounterHTOff": "0,1,2,3,4,5,6,7", 34f16c3236SIan Rogers "EventCode": "0xc8", 35ede00740SAndi Kleen "EventName": "HLE_RETIRED.ABORTED_MISC3", 36ede00740SAndi Kleen "SampleAfterValue": "2000003", 37f16c3236SIan Rogers "UMask": "0x20" 38ede00740SAndi Kleen }, 39ede00740SAndi Kleen { 40ede00740SAndi Kleen "BriefDescription": "Number of times an HLE execution aborted due to incompatible memory type.", 41ede00740SAndi Kleen "Counter": "0,1,2,3", 42f16c3236SIan Rogers "CounterHTOff": "0,1,2,3,4,5,6,7", 43ede00740SAndi Kleen "Errata": "HSD65", 44f16c3236SIan Rogers "EventCode": "0xc8", 45f16c3236SIan Rogers "EventName": "HLE_RETIRED.ABORTED_MISC4", 46ede00740SAndi Kleen "SampleAfterValue": "2000003", 47f16c3236SIan Rogers "UMask": "0x40" 48ede00740SAndi Kleen }, 49ede00740SAndi Kleen { 50ede00740SAndi Kleen "BriefDescription": "Number of times an HLE execution aborted due to none of the previous 4 categories (e.g. interrupts)", 51ede00740SAndi Kleen "Counter": "0,1,2,3", 52f16c3236SIan Rogers "CounterHTOff": "0,1,2,3,4,5,6,7", 53f16c3236SIan Rogers "EventCode": "0xc8", 54ede00740SAndi Kleen "EventName": "HLE_RETIRED.ABORTED_MISC5", 55ede00740SAndi Kleen "PublicDescription": "Number of times an HLE execution aborted due to none of the previous 4 categories (e.g. interrupts).", 56ede00740SAndi Kleen "SampleAfterValue": "2000003", 57f16c3236SIan Rogers "UMask": "0x80" 58ede00740SAndi Kleen }, 59ede00740SAndi Kleen { 60f16c3236SIan Rogers "BriefDescription": "Number of times an HLE execution successfully committed.", 61ede00740SAndi Kleen "Counter": "0,1,2,3", 62f16c3236SIan Rogers "CounterHTOff": "0,1,2,3,4,5,6,7", 63f16c3236SIan Rogers "EventCode": "0xc8", 64f16c3236SIan Rogers "EventName": "HLE_RETIRED.COMMIT", 65ede00740SAndi Kleen "SampleAfterValue": "2000003", 66f16c3236SIan Rogers "UMask": "0x2" 67ede00740SAndi Kleen }, 68ede00740SAndi Kleen { 69f16c3236SIan Rogers "BriefDescription": "Number of times an HLE execution started.", 70ede00740SAndi Kleen "Counter": "0,1,2,3", 71f16c3236SIan Rogers "CounterHTOff": "0,1,2,3,4,5,6,7", 72f16c3236SIan Rogers "EventCode": "0xC8", 73f16c3236SIan Rogers "EventName": "HLE_RETIRED.START", 74ede00740SAndi Kleen "SampleAfterValue": "2000003", 75f16c3236SIan Rogers "UMask": "0x1" 76ede00740SAndi Kleen }, 77ede00740SAndi Kleen { 78f16c3236SIan Rogers "BriefDescription": "Counts the number of machine clears due to memory order conflicts.", 79f16c3236SIan Rogers "Counter": "0,1,2,3", 80f16c3236SIan Rogers "CounterHTOff": "0,1,2,3,4,5,6,7", 81f16c3236SIan Rogers "EventCode": "0xC3", 82f16c3236SIan Rogers "EventName": "MACHINE_CLEARS.MEMORY_ORDERING", 83f16c3236SIan Rogers "PublicDescription": "This event counts the number of memory ordering machine clears detected. Memory ordering machine clears can result from memory address aliasing or snoops from another hardware thread or core to data inflight in the pipeline. Machine clears can have a significant performance impact if they are happening frequently.", 84f16c3236SIan Rogers "SampleAfterValue": "100003", 85f16c3236SIan Rogers "UMask": "0x2" 86f16c3236SIan Rogers }, 87f16c3236SIan Rogers { 88f16c3236SIan Rogers "BriefDescription": "Randomly selected loads with latency value being above 128.", 89f16c3236SIan Rogers "Counter": "3", 90f16c3236SIan Rogers "CounterHTOff": "3", 91f16c3236SIan Rogers "Data_LA": "1", 92f16c3236SIan Rogers "Errata": "HSD76, HSD25, HSM26", 93f16c3236SIan Rogers "EventCode": "0xcd", 94f16c3236SIan Rogers "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_128", 95f16c3236SIan Rogers "MSRIndex": "0x3F6", 96f16c3236SIan Rogers "MSRValue": "0x80", 97f16c3236SIan Rogers "PEBS": "2", 98f16c3236SIan Rogers "SampleAfterValue": "1009", 99f16c3236SIan Rogers "TakenAlone": "1", 100f16c3236SIan Rogers "UMask": "0x1" 101f16c3236SIan Rogers }, 102f16c3236SIan Rogers { 103f16c3236SIan Rogers "BriefDescription": "Randomly selected loads with latency value being above 16.", 104f16c3236SIan Rogers "Counter": "3", 105f16c3236SIan Rogers "CounterHTOff": "3", 106f16c3236SIan Rogers "Data_LA": "1", 107f16c3236SIan Rogers "Errata": "HSD76, HSD25, HSM26", 108f16c3236SIan Rogers "EventCode": "0xcd", 109f16c3236SIan Rogers "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_16", 110f16c3236SIan Rogers "MSRIndex": "0x3F6", 111f16c3236SIan Rogers "MSRValue": "0x10", 112f16c3236SIan Rogers "PEBS": "2", 113f16c3236SIan Rogers "SampleAfterValue": "20011", 114f16c3236SIan Rogers "TakenAlone": "1", 115f16c3236SIan Rogers "UMask": "0x1" 116f16c3236SIan Rogers }, 117f16c3236SIan Rogers { 118f16c3236SIan Rogers "BriefDescription": "Randomly selected loads with latency value being above 256.", 119f16c3236SIan Rogers "Counter": "3", 120f16c3236SIan Rogers "CounterHTOff": "3", 121f16c3236SIan Rogers "Data_LA": "1", 122f16c3236SIan Rogers "Errata": "HSD76, HSD25, HSM26", 123f16c3236SIan Rogers "EventCode": "0xcd", 124f16c3236SIan Rogers "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_256", 125f16c3236SIan Rogers "MSRIndex": "0x3F6", 126f16c3236SIan Rogers "MSRValue": "0x100", 127f16c3236SIan Rogers "PEBS": "2", 128f16c3236SIan Rogers "SampleAfterValue": "503", 129f16c3236SIan Rogers "TakenAlone": "1", 130f16c3236SIan Rogers "UMask": "0x1" 131f16c3236SIan Rogers }, 132f16c3236SIan Rogers { 133f16c3236SIan Rogers "BriefDescription": "Randomly selected loads with latency value being above 32.", 134f16c3236SIan Rogers "Counter": "3", 135f16c3236SIan Rogers "CounterHTOff": "3", 136f16c3236SIan Rogers "Data_LA": "1", 137f16c3236SIan Rogers "Errata": "HSD76, HSD25, HSM26", 138f16c3236SIan Rogers "EventCode": "0xcd", 139f16c3236SIan Rogers "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_32", 140f16c3236SIan Rogers "MSRIndex": "0x3F6", 141f16c3236SIan Rogers "MSRValue": "0x20", 142f16c3236SIan Rogers "PEBS": "2", 143f16c3236SIan Rogers "SampleAfterValue": "100003", 144f16c3236SIan Rogers "TakenAlone": "1", 145f16c3236SIan Rogers "UMask": "0x1" 146f16c3236SIan Rogers }, 147f16c3236SIan Rogers { 148f16c3236SIan Rogers "BriefDescription": "Randomly selected loads with latency value being above 4.", 149f16c3236SIan Rogers "Counter": "3", 150f16c3236SIan Rogers "CounterHTOff": "3", 151f16c3236SIan Rogers "Data_LA": "1", 152f16c3236SIan Rogers "Errata": "HSD76, HSD25, HSM26", 153f16c3236SIan Rogers "EventCode": "0xcd", 154f16c3236SIan Rogers "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_4", 155f16c3236SIan Rogers "MSRIndex": "0x3F6", 156f16c3236SIan Rogers "MSRValue": "0x4", 157f16c3236SIan Rogers "PEBS": "2", 158f16c3236SIan Rogers "SampleAfterValue": "100003", 159f16c3236SIan Rogers "TakenAlone": "1", 160f16c3236SIan Rogers "UMask": "0x1" 161f16c3236SIan Rogers }, 162f16c3236SIan Rogers { 163f16c3236SIan Rogers "BriefDescription": "Randomly selected loads with latency value being above 512.", 164f16c3236SIan Rogers "Counter": "3", 165f16c3236SIan Rogers "CounterHTOff": "3", 166f16c3236SIan Rogers "Data_LA": "1", 167f16c3236SIan Rogers "Errata": "HSD76, HSD25, HSM26", 168f16c3236SIan Rogers "EventCode": "0xcd", 169f16c3236SIan Rogers "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_512", 170f16c3236SIan Rogers "MSRIndex": "0x3F6", 171f16c3236SIan Rogers "MSRValue": "0x200", 172f16c3236SIan Rogers "PEBS": "2", 173f16c3236SIan Rogers "SampleAfterValue": "101", 174f16c3236SIan Rogers "TakenAlone": "1", 175f16c3236SIan Rogers "UMask": "0x1" 176f16c3236SIan Rogers }, 177f16c3236SIan Rogers { 178f16c3236SIan Rogers "BriefDescription": "Randomly selected loads with latency value being above 64.", 179f16c3236SIan Rogers "Counter": "3", 180f16c3236SIan Rogers "CounterHTOff": "3", 181f16c3236SIan Rogers "Data_LA": "1", 182f16c3236SIan Rogers "Errata": "HSD76, HSD25, HSM26", 183f16c3236SIan Rogers "EventCode": "0xcd", 184f16c3236SIan Rogers "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_64", 185f16c3236SIan Rogers "MSRIndex": "0x3F6", 186f16c3236SIan Rogers "MSRValue": "0x40", 187f16c3236SIan Rogers "PEBS": "2", 188f16c3236SIan Rogers "SampleAfterValue": "2003", 189f16c3236SIan Rogers "TakenAlone": "1", 190f16c3236SIan Rogers "UMask": "0x1" 191f16c3236SIan Rogers }, 192f16c3236SIan Rogers { 193f16c3236SIan Rogers "BriefDescription": "Randomly selected loads with latency value being above 8.", 194f16c3236SIan Rogers "Counter": "3", 195f16c3236SIan Rogers "CounterHTOff": "3", 196f16c3236SIan Rogers "Data_LA": "1", 197f16c3236SIan Rogers "Errata": "HSD76, HSD25, HSM26", 198f16c3236SIan Rogers "EventCode": "0xcd", 199f16c3236SIan Rogers "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_8", 200f16c3236SIan Rogers "MSRIndex": "0x3F6", 201f16c3236SIan Rogers "MSRValue": "0x8", 202f16c3236SIan Rogers "PEBS": "2", 203f16c3236SIan Rogers "SampleAfterValue": "50021", 204f16c3236SIan Rogers "TakenAlone": "1", 205f16c3236SIan Rogers "UMask": "0x1" 206f16c3236SIan Rogers }, 207f16c3236SIan Rogers { 208f16c3236SIan Rogers "BriefDescription": "Speculative cache line split load uops dispatched to L1 cache", 209f16c3236SIan Rogers "Counter": "0,1,2,3", 210f16c3236SIan Rogers "CounterHTOff": "0,1,2,3,4,5,6,7", 211f16c3236SIan Rogers "EventCode": "0x05", 212f16c3236SIan Rogers "EventName": "MISALIGN_MEM_REF.LOADS", 213f16c3236SIan Rogers "PublicDescription": "Speculative cache-line split load uops dispatched to L1D.", 214f16c3236SIan Rogers "SampleAfterValue": "2000003", 215f16c3236SIan Rogers "UMask": "0x1" 216f16c3236SIan Rogers }, 217f16c3236SIan Rogers { 218f16c3236SIan Rogers "BriefDescription": "Speculative cache line split STA uops dispatched to L1 cache", 219f16c3236SIan Rogers "Counter": "0,1,2,3", 220f16c3236SIan Rogers "CounterHTOff": "0,1,2,3,4,5,6,7", 221f16c3236SIan Rogers "EventCode": "0x05", 222f16c3236SIan Rogers "EventName": "MISALIGN_MEM_REF.STORES", 223f16c3236SIan Rogers "PublicDescription": "Speculative cache-line split store-address uops dispatched to L1D.", 224f16c3236SIan Rogers "SampleAfterValue": "2000003", 225f16c3236SIan Rogers "UMask": "0x2" 226f16c3236SIan Rogers }, 227f16c3236SIan Rogers { 228f16c3236SIan Rogers "BriefDescription": "Counts all demand & prefetch code reads miss in the L3", 229f16c3236SIan Rogers "Counter": "0,1,2,3", 230f16c3236SIan Rogers "CounterHTOff": "0,1,2,3", 231f16c3236SIan Rogers "EventCode": "0xB7, 0xBB", 232f16c3236SIan Rogers "EventName": "OFFCORE_RESPONSE.ALL_CODE_RD.LLC_MISS.ANY_RESPONSE", 233f16c3236SIan Rogers "MSRIndex": "0x1a6,0x1a7", 234f16c3236SIan Rogers "MSRValue": "0x3FBFC00244", 235f16c3236SIan Rogers "Offcore": "1", 236f16c3236SIan Rogers "SampleAfterValue": "100003", 237f16c3236SIan Rogers "UMask": "0x1" 238f16c3236SIan Rogers }, 239f16c3236SIan Rogers { 240f16c3236SIan Rogers "BriefDescription": "Counts all demand & prefetch code reads miss the L3 and the data is returned from local dram", 241f16c3236SIan Rogers "Counter": "0,1,2,3", 242f16c3236SIan Rogers "CounterHTOff": "0,1,2,3", 243f16c3236SIan Rogers "EventCode": "0xB7, 0xBB", 244f16c3236SIan Rogers "EventName": "OFFCORE_RESPONSE.ALL_CODE_RD.LLC_MISS.LOCAL_DRAM", 245f16c3236SIan Rogers "MSRIndex": "0x1a6,0x1a7", 246*bedd1738SZhengjun Xing "MSRValue": "0x600400244", 247f16c3236SIan Rogers "Offcore": "1", 248f16c3236SIan Rogers "SampleAfterValue": "100003", 249f16c3236SIan Rogers "UMask": "0x1" 250f16c3236SIan Rogers }, 251f16c3236SIan Rogers { 252f16c3236SIan Rogers "BriefDescription": "Counts all demand & prefetch data reads miss in the L3", 253f16c3236SIan Rogers "Counter": "0,1,2,3", 254f16c3236SIan Rogers "CounterHTOff": "0,1,2,3", 255f16c3236SIan Rogers "EventCode": "0xB7, 0xBB", 256f16c3236SIan Rogers "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_MISS.ANY_RESPONSE", 257f16c3236SIan Rogers "MSRIndex": "0x1a6,0x1a7", 258f16c3236SIan Rogers "MSRValue": "0x3FBFC00091", 259f16c3236SIan Rogers "Offcore": "1", 260f16c3236SIan Rogers "SampleAfterValue": "100003", 261f16c3236SIan Rogers "UMask": "0x1" 262f16c3236SIan Rogers }, 263f16c3236SIan Rogers { 264f16c3236SIan Rogers "BriefDescription": "Counts all demand & prefetch data reads miss the L3 and the data is returned from local dram", 265f16c3236SIan Rogers "Counter": "0,1,2,3", 266f16c3236SIan Rogers "CounterHTOff": "0,1,2,3", 267f16c3236SIan Rogers "EventCode": "0xB7, 0xBB", 268f16c3236SIan Rogers "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_MISS.LOCAL_DRAM", 269f16c3236SIan Rogers "MSRIndex": "0x1a6,0x1a7", 270*bedd1738SZhengjun Xing "MSRValue": "0x600400091", 271f16c3236SIan Rogers "Offcore": "1", 272f16c3236SIan Rogers "SampleAfterValue": "100003", 273f16c3236SIan Rogers "UMask": "0x1" 274f16c3236SIan Rogers }, 275f16c3236SIan Rogers { 276f16c3236SIan Rogers "BriefDescription": "Counts all demand & prefetch data reads miss the L3 and the data is returned from remote dram", 277f16c3236SIan Rogers "Counter": "0,1,2,3", 278f16c3236SIan Rogers "CounterHTOff": "0,1,2,3", 279f16c3236SIan Rogers "EventCode": "0xB7, 0xBB", 280f16c3236SIan Rogers "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_MISS.REMOTE_DRAM", 281f16c3236SIan Rogers "MSRIndex": "0x1a6,0x1a7", 282*bedd1738SZhengjun Xing "MSRValue": "0x63F800091", 283f16c3236SIan Rogers "Offcore": "1", 284f16c3236SIan Rogers "SampleAfterValue": "100003", 285f16c3236SIan Rogers "UMask": "0x1" 286f16c3236SIan Rogers }, 287f16c3236SIan Rogers { 288f16c3236SIan Rogers "BriefDescription": "Counts all demand & prefetch data reads miss the L3 and the modified data is transferred from remote cache", 289f16c3236SIan Rogers "Counter": "0,1,2,3", 290f16c3236SIan Rogers "CounterHTOff": "0,1,2,3", 291f16c3236SIan Rogers "EventCode": "0xB7, 0xBB", 292f16c3236SIan Rogers "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_MISS.REMOTE_HITM", 293f16c3236SIan Rogers "MSRIndex": "0x1a6,0x1a7", 294f16c3236SIan Rogers "MSRValue": "0x103FC00091", 295f16c3236SIan Rogers "Offcore": "1", 296f16c3236SIan Rogers "SampleAfterValue": "100003", 297f16c3236SIan Rogers "UMask": "0x1" 298f16c3236SIan Rogers }, 299f16c3236SIan Rogers { 300f16c3236SIan Rogers "BriefDescription": "Counts all demand & prefetch data reads miss the L3 and clean or shared data is transferred from remote cache", 301f16c3236SIan Rogers "Counter": "0,1,2,3", 302f16c3236SIan Rogers "CounterHTOff": "0,1,2,3", 303f16c3236SIan Rogers "EventCode": "0xB7, 0xBB", 304f16c3236SIan Rogers "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_MISS.REMOTE_HIT_FORWARD", 305f16c3236SIan Rogers "MSRIndex": "0x1a6,0x1a7", 306*bedd1738SZhengjun Xing "MSRValue": "0x83FC00091", 307f16c3236SIan Rogers "Offcore": "1", 308f16c3236SIan Rogers "SampleAfterValue": "100003", 309f16c3236SIan Rogers "UMask": "0x1" 310f16c3236SIan Rogers }, 311f16c3236SIan Rogers { 312f16c3236SIan Rogers "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) miss in the L3", 313f16c3236SIan Rogers "Counter": "0,1,2,3", 314f16c3236SIan Rogers "CounterHTOff": "0,1,2,3", 315f16c3236SIan Rogers "EventCode": "0xB7, 0xBB", 316f16c3236SIan Rogers "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_MISS.ANY_RESPONSE", 317f16c3236SIan Rogers "MSRIndex": "0x1a6,0x1a7", 318f16c3236SIan Rogers "MSRValue": "0x3FBFC007F7", 319f16c3236SIan Rogers "Offcore": "1", 320f16c3236SIan Rogers "SampleAfterValue": "100003", 321f16c3236SIan Rogers "UMask": "0x1" 322f16c3236SIan Rogers }, 323f16c3236SIan Rogers { 324f16c3236SIan Rogers "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) miss the L3 and the data is returned from local dram", 325f16c3236SIan Rogers "Counter": "0,1,2,3", 326f16c3236SIan Rogers "CounterHTOff": "0,1,2,3", 327f16c3236SIan Rogers "EventCode": "0xB7, 0xBB", 328f16c3236SIan Rogers "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_MISS.LOCAL_DRAM", 329f16c3236SIan Rogers "MSRIndex": "0x1a6,0x1a7", 330*bedd1738SZhengjun Xing "MSRValue": "0x6004007F7", 331f16c3236SIan Rogers "Offcore": "1", 332f16c3236SIan Rogers "SampleAfterValue": "100003", 333f16c3236SIan Rogers "UMask": "0x1" 334f16c3236SIan Rogers }, 335f16c3236SIan Rogers { 336f16c3236SIan Rogers "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) miss the L3 and the data is returned from remote dram", 337f16c3236SIan Rogers "Counter": "0,1,2,3", 338f16c3236SIan Rogers "CounterHTOff": "0,1,2,3", 339f16c3236SIan Rogers "EventCode": "0xB7, 0xBB", 340f16c3236SIan Rogers "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_MISS.REMOTE_DRAM", 341f16c3236SIan Rogers "MSRIndex": "0x1a6,0x1a7", 342*bedd1738SZhengjun Xing "MSRValue": "0x63F8007F7", 343f16c3236SIan Rogers "Offcore": "1", 344f16c3236SIan Rogers "SampleAfterValue": "100003", 345f16c3236SIan Rogers "UMask": "0x1" 346f16c3236SIan Rogers }, 347f16c3236SIan Rogers { 348f16c3236SIan Rogers "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) miss the L3 and the modified data is transferred from remote cache", 349f16c3236SIan Rogers "Counter": "0,1,2,3", 350f16c3236SIan Rogers "CounterHTOff": "0,1,2,3", 351f16c3236SIan Rogers "EventCode": "0xB7, 0xBB", 352f16c3236SIan Rogers "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_MISS.REMOTE_HITM", 353f16c3236SIan Rogers "MSRIndex": "0x1a6,0x1a7", 354f16c3236SIan Rogers "MSRValue": "0x103FC007F7", 355f16c3236SIan Rogers "Offcore": "1", 356f16c3236SIan Rogers "SampleAfterValue": "100003", 357f16c3236SIan Rogers "UMask": "0x1" 358f16c3236SIan Rogers }, 359f16c3236SIan Rogers { 360f16c3236SIan Rogers "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) miss the L3 and clean or shared data is transferred from remote cache", 361f16c3236SIan Rogers "Counter": "0,1,2,3", 362f16c3236SIan Rogers "CounterHTOff": "0,1,2,3", 363f16c3236SIan Rogers "EventCode": "0xB7, 0xBB", 364f16c3236SIan Rogers "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_MISS.REMOTE_HIT_FORWARD", 365f16c3236SIan Rogers "MSRIndex": "0x1a6,0x1a7", 366*bedd1738SZhengjun Xing "MSRValue": "0x83FC007F7", 367f16c3236SIan Rogers "Offcore": "1", 368f16c3236SIan Rogers "SampleAfterValue": "100003", 369f16c3236SIan Rogers "UMask": "0x1" 370f16c3236SIan Rogers }, 371f16c3236SIan Rogers { 372f16c3236SIan Rogers "BriefDescription": "Counts all requests miss in the L3", 373f16c3236SIan Rogers "Counter": "0,1,2,3", 374f16c3236SIan Rogers "CounterHTOff": "0,1,2,3", 375f16c3236SIan Rogers "EventCode": "0xB7, 0xBB", 376f16c3236SIan Rogers "EventName": "OFFCORE_RESPONSE.ALL_REQUESTS.LLC_MISS.ANY_RESPONSE", 377f16c3236SIan Rogers "MSRIndex": "0x1a6,0x1a7", 378f16c3236SIan Rogers "MSRValue": "0x3FBFC08FFF", 379f16c3236SIan Rogers "Offcore": "1", 380f16c3236SIan Rogers "SampleAfterValue": "100003", 381f16c3236SIan Rogers "UMask": "0x1" 382f16c3236SIan Rogers }, 383f16c3236SIan Rogers { 384f16c3236SIan Rogers "BriefDescription": "Counts all demand & prefetch RFOs miss in the L3", 385f16c3236SIan Rogers "Counter": "0,1,2,3", 386f16c3236SIan Rogers "CounterHTOff": "0,1,2,3", 387f16c3236SIan Rogers "EventCode": "0xB7, 0xBB", 388f16c3236SIan Rogers "EventName": "OFFCORE_RESPONSE.ALL_RFO.LLC_MISS.ANY_RESPONSE", 389f16c3236SIan Rogers "MSRIndex": "0x1a6,0x1a7", 390f16c3236SIan Rogers "MSRValue": "0x3FBFC00122", 391f16c3236SIan Rogers "Offcore": "1", 392f16c3236SIan Rogers "SampleAfterValue": "100003", 393f16c3236SIan Rogers "UMask": "0x1" 394f16c3236SIan Rogers }, 395f16c3236SIan Rogers { 396f16c3236SIan Rogers "BriefDescription": "Counts all demand & prefetch RFOs miss the L3 and the data is returned from local dram", 397f16c3236SIan Rogers "Counter": "0,1,2,3", 398f16c3236SIan Rogers "CounterHTOff": "0,1,2,3", 399f16c3236SIan Rogers "EventCode": "0xB7, 0xBB", 400f16c3236SIan Rogers "EventName": "OFFCORE_RESPONSE.ALL_RFO.LLC_MISS.LOCAL_DRAM", 401f16c3236SIan Rogers "MSRIndex": "0x1a6,0x1a7", 402*bedd1738SZhengjun Xing "MSRValue": "0x600400122", 403f16c3236SIan Rogers "Offcore": "1", 404f16c3236SIan Rogers "SampleAfterValue": "100003", 405f16c3236SIan Rogers "UMask": "0x1" 406f16c3236SIan Rogers }, 407f16c3236SIan Rogers { 408f16c3236SIan Rogers "BriefDescription": "Counts all demand code reads miss in the L3", 409f16c3236SIan Rogers "Counter": "0,1,2,3", 410f16c3236SIan Rogers "CounterHTOff": "0,1,2,3", 411f16c3236SIan Rogers "EventCode": "0xB7, 0xBB", 412f16c3236SIan Rogers "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_MISS.ANY_RESPONSE", 413f16c3236SIan Rogers "MSRIndex": "0x1a6,0x1a7", 414f16c3236SIan Rogers "MSRValue": "0x3FBFC00004", 415f16c3236SIan Rogers "Offcore": "1", 416f16c3236SIan Rogers "SampleAfterValue": "100003", 417f16c3236SIan Rogers "UMask": "0x1" 418f16c3236SIan Rogers }, 419f16c3236SIan Rogers { 420f16c3236SIan Rogers "BriefDescription": "Counts all demand code reads miss the L3 and the data is returned from local dram", 421f16c3236SIan Rogers "Counter": "0,1,2,3", 422f16c3236SIan Rogers "CounterHTOff": "0,1,2,3", 423f16c3236SIan Rogers "EventCode": "0xB7, 0xBB", 424f16c3236SIan Rogers "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_MISS.LOCAL_DRAM", 425f16c3236SIan Rogers "MSRIndex": "0x1a6,0x1a7", 426*bedd1738SZhengjun Xing "MSRValue": "0x600400004", 427f16c3236SIan Rogers "Offcore": "1", 428f16c3236SIan Rogers "SampleAfterValue": "100003", 429f16c3236SIan Rogers "UMask": "0x1" 430f16c3236SIan Rogers }, 431f16c3236SIan Rogers { 432f16c3236SIan Rogers "BriefDescription": "Counts demand data reads miss in the L3", 433f16c3236SIan Rogers "Counter": "0,1,2,3", 434f16c3236SIan Rogers "CounterHTOff": "0,1,2,3", 435f16c3236SIan Rogers "EventCode": "0xB7, 0xBB", 436f16c3236SIan Rogers "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_MISS.ANY_RESPONSE", 437f16c3236SIan Rogers "MSRIndex": "0x1a6,0x1a7", 438f16c3236SIan Rogers "MSRValue": "0x3FBFC00001", 439f16c3236SIan Rogers "Offcore": "1", 440f16c3236SIan Rogers "SampleAfterValue": "100003", 441f16c3236SIan Rogers "UMask": "0x1" 442f16c3236SIan Rogers }, 443f16c3236SIan Rogers { 444f16c3236SIan Rogers "BriefDescription": "Counts demand data reads miss the L3 and the data is returned from local dram", 445f16c3236SIan Rogers "Counter": "0,1,2,3", 446f16c3236SIan Rogers "CounterHTOff": "0,1,2,3", 447f16c3236SIan Rogers "EventCode": "0xB7, 0xBB", 448f16c3236SIan Rogers "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_MISS.LOCAL_DRAM", 449f16c3236SIan Rogers "MSRIndex": "0x1a6,0x1a7", 450*bedd1738SZhengjun Xing "MSRValue": "0x600400001", 451f16c3236SIan Rogers "Offcore": "1", 452f16c3236SIan Rogers "SampleAfterValue": "100003", 453f16c3236SIan Rogers "UMask": "0x1" 454f16c3236SIan Rogers }, 455f16c3236SIan Rogers { 456f16c3236SIan Rogers "BriefDescription": "Counts all demand data writes (RFOs) miss in the L3", 457f16c3236SIan Rogers "Counter": "0,1,2,3", 458f16c3236SIan Rogers "CounterHTOff": "0,1,2,3", 459f16c3236SIan Rogers "EventCode": "0xB7, 0xBB", 460f16c3236SIan Rogers "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_MISS.ANY_RESPONSE", 461f16c3236SIan Rogers "MSRIndex": "0x1a6,0x1a7", 462f16c3236SIan Rogers "MSRValue": "0x3FBFC00002", 463f16c3236SIan Rogers "Offcore": "1", 464f16c3236SIan Rogers "SampleAfterValue": "100003", 465f16c3236SIan Rogers "UMask": "0x1" 466f16c3236SIan Rogers }, 467f16c3236SIan Rogers { 468f16c3236SIan Rogers "BriefDescription": "Counts all demand data writes (RFOs) miss the L3 and the data is returned from local dram", 469f16c3236SIan Rogers "Counter": "0,1,2,3", 470f16c3236SIan Rogers "CounterHTOff": "0,1,2,3", 471f16c3236SIan Rogers "EventCode": "0xB7, 0xBB", 472f16c3236SIan Rogers "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_MISS.LOCAL_DRAM", 473f16c3236SIan Rogers "MSRIndex": "0x1a6,0x1a7", 474*bedd1738SZhengjun Xing "MSRValue": "0x600400002", 475f16c3236SIan Rogers "Offcore": "1", 476f16c3236SIan Rogers "SampleAfterValue": "100003", 477f16c3236SIan Rogers "UMask": "0x1" 478f16c3236SIan Rogers }, 479f16c3236SIan Rogers { 480f16c3236SIan Rogers "BriefDescription": "Counts all demand data writes (RFOs) miss the L3 and the modified data is transferred from remote cache", 481f16c3236SIan Rogers "Counter": "0,1,2,3", 482f16c3236SIan Rogers "CounterHTOff": "0,1,2,3", 483f16c3236SIan Rogers "EventCode": "0xB7, 0xBB", 484f16c3236SIan Rogers "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_MISS.REMOTE_HITM", 485f16c3236SIan Rogers "MSRIndex": "0x1a6,0x1a7", 486f16c3236SIan Rogers "MSRValue": "0x103FC00002", 487f16c3236SIan Rogers "Offcore": "1", 488f16c3236SIan Rogers "SampleAfterValue": "100003", 489f16c3236SIan Rogers "UMask": "0x1" 490f16c3236SIan Rogers }, 491f16c3236SIan Rogers { 492f16c3236SIan Rogers "BriefDescription": "Counts all prefetch (that bring data to LLC only) code reads miss in the L3", 493f16c3236SIan Rogers "Counter": "0,1,2,3", 494f16c3236SIan Rogers "CounterHTOff": "0,1,2,3", 495f16c3236SIan Rogers "EventCode": "0xB7, 0xBB", 496f16c3236SIan Rogers "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.LLC_MISS.ANY_RESPONSE", 497f16c3236SIan Rogers "MSRIndex": "0x1a6,0x1a7", 498f16c3236SIan Rogers "MSRValue": "0x3FBFC00040", 499f16c3236SIan Rogers "Offcore": "1", 500f16c3236SIan Rogers "SampleAfterValue": "100003", 501f16c3236SIan Rogers "UMask": "0x1" 502f16c3236SIan Rogers }, 503f16c3236SIan Rogers { 504f16c3236SIan Rogers "BriefDescription": "Counts prefetch (that bring data to L2) data reads miss in the L3", 505f16c3236SIan Rogers "Counter": "0,1,2,3", 506f16c3236SIan Rogers "CounterHTOff": "0,1,2,3", 507f16c3236SIan Rogers "EventCode": "0xB7, 0xBB", 508f16c3236SIan Rogers "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_MISS.ANY_RESPONSE", 509f16c3236SIan Rogers "MSRIndex": "0x1a6,0x1a7", 510f16c3236SIan Rogers "MSRValue": "0x3FBFC00010", 511f16c3236SIan Rogers "Offcore": "1", 512f16c3236SIan Rogers "SampleAfterValue": "100003", 513f16c3236SIan Rogers "UMask": "0x1" 514f16c3236SIan Rogers }, 515f16c3236SIan Rogers { 516f16c3236SIan Rogers "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs miss in the L3", 517f16c3236SIan Rogers "Counter": "0,1,2,3", 518f16c3236SIan Rogers "CounterHTOff": "0,1,2,3", 519f16c3236SIan Rogers "EventCode": "0xB7, 0xBB", 520f16c3236SIan Rogers "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.LLC_MISS.ANY_RESPONSE", 521f16c3236SIan Rogers "MSRIndex": "0x1a6,0x1a7", 522f16c3236SIan Rogers "MSRValue": "0x3FBFC00020", 523f16c3236SIan Rogers "Offcore": "1", 524f16c3236SIan Rogers "SampleAfterValue": "100003", 525f16c3236SIan Rogers "UMask": "0x1" 526f16c3236SIan Rogers }, 527f16c3236SIan Rogers { 528f16c3236SIan Rogers "BriefDescription": "Counts prefetch (that bring data to LLC only) code reads miss in the L3", 529f16c3236SIan Rogers "Counter": "0,1,2,3", 530f16c3236SIan Rogers "CounterHTOff": "0,1,2,3", 531f16c3236SIan Rogers "EventCode": "0xB7, 0xBB", 532f16c3236SIan Rogers "EventName": "OFFCORE_RESPONSE.PF_LLC_CODE_RD.LLC_MISS.ANY_RESPONSE", 533f16c3236SIan Rogers "MSRIndex": "0x1a6,0x1a7", 534f16c3236SIan Rogers "MSRValue": "0x3FBFC00200", 535f16c3236SIan Rogers "Offcore": "1", 536f16c3236SIan Rogers "SampleAfterValue": "100003", 537f16c3236SIan Rogers "UMask": "0x1" 538f16c3236SIan Rogers }, 539f16c3236SIan Rogers { 540f16c3236SIan Rogers "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads miss in the L3", 541f16c3236SIan Rogers "Counter": "0,1,2,3", 542f16c3236SIan Rogers "CounterHTOff": "0,1,2,3", 543f16c3236SIan Rogers "EventCode": "0xB7, 0xBB", 544f16c3236SIan Rogers "EventName": "OFFCORE_RESPONSE.PF_LLC_DATA_RD.LLC_MISS.ANY_RESPONSE", 545f16c3236SIan Rogers "MSRIndex": "0x1a6,0x1a7", 546f16c3236SIan Rogers "MSRValue": "0x3FBFC00080", 547f16c3236SIan Rogers "Offcore": "1", 548f16c3236SIan Rogers "SampleAfterValue": "100003", 549f16c3236SIan Rogers "UMask": "0x1" 550f16c3236SIan Rogers }, 551f16c3236SIan Rogers { 552f16c3236SIan Rogers "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs miss in the L3", 553f16c3236SIan Rogers "Counter": "0,1,2,3", 554f16c3236SIan Rogers "CounterHTOff": "0,1,2,3", 555f16c3236SIan Rogers "EventCode": "0xB7, 0xBB", 556f16c3236SIan Rogers "EventName": "OFFCORE_RESPONSE.PF_LLC_RFO.LLC_MISS.ANY_RESPONSE", 557f16c3236SIan Rogers "MSRIndex": "0x1a6,0x1a7", 558f16c3236SIan Rogers "MSRValue": "0x3FBFC00100", 559f16c3236SIan Rogers "Offcore": "1", 560f16c3236SIan Rogers "SampleAfterValue": "100003", 561f16c3236SIan Rogers "UMask": "0x1" 562f16c3236SIan Rogers }, 563f16c3236SIan Rogers { 564ede00740SAndi Kleen "BriefDescription": "Number of times an RTM execution aborted due to any reasons (multiple categories may count as one).", 565ede00740SAndi Kleen "Counter": "0,1,2,3", 566f16c3236SIan Rogers "CounterHTOff": "0,1,2,3", 567f16c3236SIan Rogers "EventCode": "0xc9", 568ede00740SAndi Kleen "EventName": "RTM_RETIRED.ABORTED", 569f16c3236SIan Rogers "PEBS": "1", 570ede00740SAndi Kleen "SampleAfterValue": "2000003", 571f16c3236SIan Rogers "UMask": "0x4" 572ede00740SAndi Kleen }, 573ede00740SAndi Kleen { 574ede00740SAndi Kleen "BriefDescription": "Number of times an RTM execution aborted due to various memory events (e.g. read/write capacity and conflicts)", 575ede00740SAndi Kleen "Counter": "0,1,2,3", 576f16c3236SIan Rogers "CounterHTOff": "0,1,2,3", 577f16c3236SIan Rogers "EventCode": "0xc9", 578ede00740SAndi Kleen "EventName": "RTM_RETIRED.ABORTED_MISC1", 579ede00740SAndi Kleen "PublicDescription": "Number of times an RTM execution aborted due to various memory events (e.g. read/write capacity and conflicts).", 580ede00740SAndi Kleen "SampleAfterValue": "2000003", 581f16c3236SIan Rogers "UMask": "0x8" 582ede00740SAndi Kleen }, 583ede00740SAndi Kleen { 584ede00740SAndi Kleen "BriefDescription": "Number of times an RTM execution aborted due to various memory events (e.g., read/write capacity and conflicts).", 585ede00740SAndi Kleen "Counter": "0,1,2,3", 586f16c3236SIan Rogers "CounterHTOff": "0,1,2,3", 587f16c3236SIan Rogers "EventCode": "0xc9", 588ede00740SAndi Kleen "EventName": "RTM_RETIRED.ABORTED_MISC2", 589ede00740SAndi Kleen "SampleAfterValue": "2000003", 590f16c3236SIan Rogers "UMask": "0x10" 591ede00740SAndi Kleen }, 592ede00740SAndi Kleen { 593ede00740SAndi Kleen "BriefDescription": "Number of times an RTM execution aborted due to HLE-unfriendly instructions.", 594ede00740SAndi Kleen "Counter": "0,1,2,3", 595f16c3236SIan Rogers "CounterHTOff": "0,1,2,3", 596f16c3236SIan Rogers "EventCode": "0xc9", 597ede00740SAndi Kleen "EventName": "RTM_RETIRED.ABORTED_MISC3", 598ede00740SAndi Kleen "SampleAfterValue": "2000003", 599f16c3236SIan Rogers "UMask": "0x20" 600ede00740SAndi Kleen }, 601ede00740SAndi Kleen { 602ede00740SAndi Kleen "BriefDescription": "Number of times an RTM execution aborted due to incompatible memory type.", 603ede00740SAndi Kleen "Counter": "0,1,2,3", 604f16c3236SIan Rogers "CounterHTOff": "0,1,2,3", 605ede00740SAndi Kleen "Errata": "HSD65", 606f16c3236SIan Rogers "EventCode": "0xc9", 607f16c3236SIan Rogers "EventName": "RTM_RETIRED.ABORTED_MISC4", 608ede00740SAndi Kleen "SampleAfterValue": "2000003", 609f16c3236SIan Rogers "UMask": "0x40" 610ede00740SAndi Kleen }, 611ede00740SAndi Kleen { 612ede00740SAndi Kleen "BriefDescription": "Number of times an RTM execution aborted due to none of the previous 4 categories (e.g. interrupt)", 613ede00740SAndi Kleen "Counter": "0,1,2,3", 614f16c3236SIan Rogers "CounterHTOff": "0,1,2,3", 615f16c3236SIan Rogers "EventCode": "0xc9", 616ede00740SAndi Kleen "EventName": "RTM_RETIRED.ABORTED_MISC5", 617ede00740SAndi Kleen "PublicDescription": "Number of times an RTM execution aborted due to none of the previous 4 categories (e.g. interrupt).", 618ede00740SAndi Kleen "SampleAfterValue": "2000003", 619f16c3236SIan Rogers "UMask": "0x80" 620ede00740SAndi Kleen }, 621ede00740SAndi Kleen { 622f16c3236SIan Rogers "BriefDescription": "Number of times an RTM execution successfully committed.", 623ede00740SAndi Kleen "Counter": "0,1,2,3", 624f16c3236SIan Rogers "CounterHTOff": "0,1,2,3", 625f16c3236SIan Rogers "EventCode": "0xc9", 626f16c3236SIan Rogers "EventName": "RTM_RETIRED.COMMIT", 627f16c3236SIan Rogers "SampleAfterValue": "2000003", 628f16c3236SIan Rogers "UMask": "0x2" 629ede00740SAndi Kleen }, 630ede00740SAndi Kleen { 631f16c3236SIan Rogers "BriefDescription": "Number of times an RTM execution started.", 632ede00740SAndi Kleen "Counter": "0,1,2,3", 633f16c3236SIan Rogers "CounterHTOff": "0,1,2,3", 634f16c3236SIan Rogers "EventCode": "0xC9", 635f16c3236SIan Rogers "EventName": "RTM_RETIRED.START", 636f16c3236SIan Rogers "SampleAfterValue": "2000003", 637f16c3236SIan Rogers "UMask": "0x1" 638ede00740SAndi Kleen }, 639ede00740SAndi Kleen { 640f16c3236SIan Rogers "BriefDescription": "Counts the number of times a class of instructions that may cause a transactional abort was executed. Since this is the count of execution, it may not always cause a transactional abort.", 641ede00740SAndi Kleen "Counter": "0,1,2,3", 642f16c3236SIan Rogers "CounterHTOff": "0,1,2,3,4,5,6,7", 643f16c3236SIan Rogers "EventCode": "0x5d", 644f16c3236SIan Rogers "EventName": "TX_EXEC.MISC1", 645f16c3236SIan Rogers "SampleAfterValue": "2000003", 646f16c3236SIan Rogers "UMask": "0x1" 647ede00740SAndi Kleen }, 648ede00740SAndi Kleen { 649f16c3236SIan Rogers "BriefDescription": "Counts the number of times a class of instructions (e.g., vzeroupper) that may cause a transactional abort was executed inside a transactional region.", 650ede00740SAndi Kleen "Counter": "0,1,2,3", 651f16c3236SIan Rogers "CounterHTOff": "0,1,2,3,4,5,6,7", 652f16c3236SIan Rogers "EventCode": "0x5d", 653f16c3236SIan Rogers "EventName": "TX_EXEC.MISC2", 654f16c3236SIan Rogers "SampleAfterValue": "2000003", 655f16c3236SIan Rogers "UMask": "0x2" 656ede00740SAndi Kleen }, 657ede00740SAndi Kleen { 658f16c3236SIan Rogers "BriefDescription": "Counts the number of times an instruction execution caused the transactional nest count supported to be exceeded.", 659ede00740SAndi Kleen "Counter": "0,1,2,3", 660f16c3236SIan Rogers "CounterHTOff": "0,1,2,3,4,5,6,7", 661f16c3236SIan Rogers "EventCode": "0x5d", 662f16c3236SIan Rogers "EventName": "TX_EXEC.MISC3", 663f16c3236SIan Rogers "SampleAfterValue": "2000003", 664f16c3236SIan Rogers "UMask": "0x4" 665ede00740SAndi Kleen }, 666ede00740SAndi Kleen { 667f16c3236SIan Rogers "BriefDescription": "Counts the number of times a XBEGIN instruction was executed inside an HLE transactional region.", 668ede00740SAndi Kleen "Counter": "0,1,2,3", 669f16c3236SIan Rogers "CounterHTOff": "0,1,2,3,4,5,6,7", 670f16c3236SIan Rogers "EventCode": "0x5d", 671f16c3236SIan Rogers "EventName": "TX_EXEC.MISC4", 672f16c3236SIan Rogers "SampleAfterValue": "2000003", 673f16c3236SIan Rogers "UMask": "0x8" 674ede00740SAndi Kleen }, 675ede00740SAndi Kleen { 676f16c3236SIan Rogers "BriefDescription": "Counts the number of times an HLE XACQUIRE instruction was executed inside an RTM transactional region.", 677ede00740SAndi Kleen "Counter": "0,1,2,3", 678f16c3236SIan Rogers "CounterHTOff": "0,1,2,3,4,5,6,7", 679f16c3236SIan Rogers "EventCode": "0x5d", 680f16c3236SIan Rogers "EventName": "TX_EXEC.MISC5", 681f16c3236SIan Rogers "SampleAfterValue": "2000003", 682f16c3236SIan Rogers "UMask": "0x10" 683ede00740SAndi Kleen }, 684ede00740SAndi Kleen { 685f16c3236SIan Rogers "BriefDescription": "Number of times a transactional abort was signaled due to a data capacity limitation for transactional writes.", 686ede00740SAndi Kleen "Counter": "0,1,2,3", 687f16c3236SIan Rogers "CounterHTOff": "0,1,2,3,4,5,6,7", 688f16c3236SIan Rogers "EventCode": "0x54", 689f16c3236SIan Rogers "EventName": "TX_MEM.ABORT_CAPACITY_WRITE", 690f16c3236SIan Rogers "SampleAfterValue": "2000003", 691f16c3236SIan Rogers "UMask": "0x2" 692ede00740SAndi Kleen }, 693ede00740SAndi Kleen { 694f16c3236SIan Rogers "BriefDescription": "Number of times a transactional abort was signaled due to a data conflict on a transactionally accessed address.", 695ede00740SAndi Kleen "Counter": "0,1,2,3", 696f16c3236SIan Rogers "CounterHTOff": "0,1,2,3,4,5,6,7", 697f16c3236SIan Rogers "EventCode": "0x54", 698f16c3236SIan Rogers "EventName": "TX_MEM.ABORT_CONFLICT", 699f16c3236SIan Rogers "SampleAfterValue": "2000003", 700f16c3236SIan Rogers "UMask": "0x1" 701ede00740SAndi Kleen }, 702ede00740SAndi Kleen { 703f16c3236SIan Rogers "BriefDescription": "Number of times an HLE transactional execution aborted due to XRELEASE lock not satisfying the address and value requirements in the elision buffer.", 704ede00740SAndi Kleen "Counter": "0,1,2,3", 705f16c3236SIan Rogers "CounterHTOff": "0,1,2,3,4,5,6,7", 706f16c3236SIan Rogers "EventCode": "0x54", 707f16c3236SIan Rogers "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_MISMATCH", 708f16c3236SIan Rogers "SampleAfterValue": "2000003", 709f16c3236SIan Rogers "UMask": "0x10" 710ede00740SAndi Kleen }, 711ede00740SAndi Kleen { 712f16c3236SIan Rogers "BriefDescription": "Number of times an HLE transactional execution aborted due to NoAllocatedElisionBuffer being non-zero.", 713ede00740SAndi Kleen "Counter": "0,1,2,3", 714f16c3236SIan Rogers "CounterHTOff": "0,1,2,3,4,5,6,7", 715f16c3236SIan Rogers "EventCode": "0x54", 716f16c3236SIan Rogers "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_NOT_EMPTY", 717f16c3236SIan Rogers "SampleAfterValue": "2000003", 718f16c3236SIan Rogers "UMask": "0x8" 719ede00740SAndi Kleen }, 720ede00740SAndi Kleen { 721f16c3236SIan Rogers "BriefDescription": "Number of times an HLE transactional execution aborted due to an unsupported read alignment from the elision buffer.", 722ede00740SAndi Kleen "Counter": "0,1,2,3", 723f16c3236SIan Rogers "CounterHTOff": "0,1,2,3,4,5,6,7", 724f16c3236SIan Rogers "EventCode": "0x54", 725f16c3236SIan Rogers "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_UNSUPPORTED_ALIGNMENT", 726f16c3236SIan Rogers "SampleAfterValue": "2000003", 727f16c3236SIan Rogers "UMask": "0x20" 728ede00740SAndi Kleen }, 729ede00740SAndi Kleen { 730f16c3236SIan Rogers "BriefDescription": "Number of times a HLE transactional region aborted due to a non XRELEASE prefixed instruction writing to an elided lock in the elision buffer.", 731ede00740SAndi Kleen "Counter": "0,1,2,3", 732f16c3236SIan Rogers "CounterHTOff": "0,1,2,3,4,5,6,7", 733f16c3236SIan Rogers "EventCode": "0x54", 734f16c3236SIan Rogers "EventName": "TX_MEM.ABORT_HLE_STORE_TO_ELIDED_LOCK", 735f16c3236SIan Rogers "SampleAfterValue": "2000003", 736f16c3236SIan Rogers "UMask": "0x4" 737ede00740SAndi Kleen }, 738ede00740SAndi Kleen { 739f16c3236SIan Rogers "BriefDescription": "Number of times HLE lock could not be elided due to ElisionBufferAvailable being zero.", 740ede00740SAndi Kleen "Counter": "0,1,2,3", 741f16c3236SIan Rogers "CounterHTOff": "0,1,2,3,4,5,6,7", 742f16c3236SIan Rogers "EventCode": "0x54", 743f16c3236SIan Rogers "EventName": "TX_MEM.HLE_ELISION_BUFFER_FULL", 744f16c3236SIan Rogers "SampleAfterValue": "2000003", 745f16c3236SIan Rogers "UMask": "0x40" 746ede00740SAndi Kleen } 747ede00740SAndi Kleen] 748