1[ 2 { 3 "EventCode": "0x24", 4 "UMask": "0x21", 5 "BriefDescription": "Demand Data Read miss L2, no rejects", 6 "Counter": "0,1,2,3", 7 "EventName": "L2_RQSTS.DEMAND_DATA_RD_MISS", 8 "Errata": "HSD78", 9 "PublicDescription": "Demand data read requests that missed L2, no rejects.", 10 "SampleAfterValue": "200003", 11 "CounterHTOff": "0,1,2,3,4,5,6,7" 12 }, 13 { 14 "EventCode": "0x24", 15 "UMask": "0x22", 16 "BriefDescription": "RFO requests that miss L2 cache", 17 "Counter": "0,1,2,3", 18 "EventName": "L2_RQSTS.RFO_MISS", 19 "PublicDescription": "Counts the number of store RFO requests that miss the L2 cache.", 20 "SampleAfterValue": "200003", 21 "CounterHTOff": "0,1,2,3,4,5,6,7" 22 }, 23 { 24 "EventCode": "0x24", 25 "UMask": "0x24", 26 "BriefDescription": "L2 cache misses when fetching instructions", 27 "Counter": "0,1,2,3", 28 "EventName": "L2_RQSTS.CODE_RD_MISS", 29 "PublicDescription": "Number of instruction fetches that missed the L2 cache.", 30 "SampleAfterValue": "200003", 31 "CounterHTOff": "0,1,2,3,4,5,6,7" 32 }, 33 { 34 "EventCode": "0x24", 35 "UMask": "0x27", 36 "BriefDescription": "Demand requests that miss L2 cache", 37 "Counter": "0,1,2,3", 38 "EventName": "L2_RQSTS.ALL_DEMAND_MISS", 39 "Errata": "HSD78", 40 "PublicDescription": "Demand requests that miss L2 cache.", 41 "SampleAfterValue": "200003", 42 "CounterHTOff": "0,1,2,3,4,5,6,7" 43 }, 44 { 45 "EventCode": "0x24", 46 "UMask": "0x30", 47 "BriefDescription": "L2 prefetch requests that miss L2 cache", 48 "Counter": "0,1,2,3", 49 "EventName": "L2_RQSTS.L2_PF_MISS", 50 "PublicDescription": "Counts all L2 HW prefetcher requests that missed L2.", 51 "SampleAfterValue": "200003", 52 "CounterHTOff": "0,1,2,3,4,5,6,7" 53 }, 54 { 55 "EventCode": "0x24", 56 "UMask": "0x3f", 57 "BriefDescription": "All requests that miss L2 cache", 58 "Counter": "0,1,2,3", 59 "EventName": "L2_RQSTS.MISS", 60 "Errata": "HSD78", 61 "PublicDescription": "All requests that missed L2.", 62 "SampleAfterValue": "200003", 63 "CounterHTOff": "0,1,2,3,4,5,6,7" 64 }, 65 { 66 "EventCode": "0x24", 67 "UMask": "0x41", 68 "BriefDescription": "Demand Data Read requests that hit L2 cache", 69 "Counter": "0,1,2,3", 70 "EventName": "L2_RQSTS.DEMAND_DATA_RD_HIT", 71 "Errata": "HSD78", 72 "PublicDescription": "Demand data read requests that hit L2 cache.", 73 "SampleAfterValue": "200003", 74 "CounterHTOff": "0,1,2,3,4,5,6,7" 75 }, 76 { 77 "EventCode": "0x24", 78 "UMask": "0x42", 79 "BriefDescription": "RFO requests that hit L2 cache", 80 "Counter": "0,1,2,3", 81 "EventName": "L2_RQSTS.RFO_HIT", 82 "PublicDescription": "Counts the number of store RFO requests that hit the L2 cache.", 83 "SampleAfterValue": "200003", 84 "CounterHTOff": "0,1,2,3,4,5,6,7" 85 }, 86 { 87 "EventCode": "0x24", 88 "UMask": "0x44", 89 "BriefDescription": "L2 cache hits when fetching instructions, code reads.", 90 "Counter": "0,1,2,3", 91 "EventName": "L2_RQSTS.CODE_RD_HIT", 92 "PublicDescription": "Number of instruction fetches that hit the L2 cache.", 93 "SampleAfterValue": "200003", 94 "CounterHTOff": "0,1,2,3,4,5,6,7" 95 }, 96 { 97 "EventCode": "0x24", 98 "UMask": "0x50", 99 "BriefDescription": "L2 prefetch requests that hit L2 cache", 100 "Counter": "0,1,2,3", 101 "EventName": "L2_RQSTS.L2_PF_HIT", 102 "PublicDescription": "Counts all L2 HW prefetcher requests that hit L2.", 103 "SampleAfterValue": "200003", 104 "CounterHTOff": "0,1,2,3,4,5,6,7" 105 }, 106 { 107 "EventCode": "0x24", 108 "UMask": "0xe1", 109 "BriefDescription": "Demand Data Read requests", 110 "Counter": "0,1,2,3", 111 "EventName": "L2_RQSTS.ALL_DEMAND_DATA_RD", 112 "Errata": "HSD78", 113 "PublicDescription": "Counts any demand and L1 HW prefetch data load requests to L2.", 114 "SampleAfterValue": "200003", 115 "CounterHTOff": "0,1,2,3,4,5,6,7" 116 }, 117 { 118 "EventCode": "0x24", 119 "UMask": "0xe2", 120 "BriefDescription": "RFO requests to L2 cache", 121 "Counter": "0,1,2,3", 122 "EventName": "L2_RQSTS.ALL_RFO", 123 "PublicDescription": "Counts all L2 store RFO requests.", 124 "SampleAfterValue": "200003", 125 "CounterHTOff": "0,1,2,3,4,5,6,7" 126 }, 127 { 128 "EventCode": "0x24", 129 "UMask": "0xe4", 130 "BriefDescription": "L2 code requests", 131 "Counter": "0,1,2,3", 132 "EventName": "L2_RQSTS.ALL_CODE_RD", 133 "PublicDescription": "Counts all L2 code requests.", 134 "SampleAfterValue": "200003", 135 "CounterHTOff": "0,1,2,3,4,5,6,7" 136 }, 137 { 138 "EventCode": "0x24", 139 "UMask": "0xe7", 140 "BriefDescription": "Demand requests to L2 cache", 141 "Counter": "0,1,2,3", 142 "EventName": "L2_RQSTS.ALL_DEMAND_REFERENCES", 143 "Errata": "HSD78", 144 "PublicDescription": "Demand requests to L2 cache.", 145 "SampleAfterValue": "200003", 146 "CounterHTOff": "0,1,2,3,4,5,6,7" 147 }, 148 { 149 "EventCode": "0x24", 150 "UMask": "0xf8", 151 "BriefDescription": "Requests from L2 hardware prefetchers", 152 "Counter": "0,1,2,3", 153 "EventName": "L2_RQSTS.ALL_PF", 154 "PublicDescription": "Counts all L2 HW prefetcher requests.", 155 "SampleAfterValue": "200003", 156 "CounterHTOff": "0,1,2,3,4,5,6,7" 157 }, 158 { 159 "EventCode": "0x24", 160 "UMask": "0xff", 161 "BriefDescription": "All L2 requests", 162 "Counter": "0,1,2,3", 163 "EventName": "L2_RQSTS.REFERENCES", 164 "Errata": "HSD78", 165 "PublicDescription": "All requests to L2 cache.", 166 "SampleAfterValue": "200003", 167 "CounterHTOff": "0,1,2,3,4,5,6,7" 168 }, 169 { 170 "EventCode": "0x27", 171 "UMask": "0x50", 172 "BriefDescription": "Not rejected writebacks that hit L2 cache", 173 "Counter": "0,1,2,3", 174 "EventName": "L2_DEMAND_RQSTS.WB_HIT", 175 "PublicDescription": "Not rejected writebacks that hit L2 cache.", 176 "SampleAfterValue": "200003", 177 "CounterHTOff": "0,1,2,3,4,5,6,7" 178 }, 179 { 180 "EventCode": "0x2E", 181 "UMask": "0x41", 182 "BriefDescription": "Core-originated cacheable demand requests missed L3", 183 "Counter": "0,1,2,3", 184 "EventName": "LONGEST_LAT_CACHE.MISS", 185 "PublicDescription": "This event counts each cache miss condition for references to the last level cache.", 186 "SampleAfterValue": "100003", 187 "CounterHTOff": "0,1,2,3,4,5,6,7" 188 }, 189 { 190 "EventCode": "0x2E", 191 "UMask": "0x4f", 192 "BriefDescription": "Core-originated cacheable demand requests that refer to L3", 193 "Counter": "0,1,2,3", 194 "EventName": "LONGEST_LAT_CACHE.REFERENCE", 195 "PublicDescription": "This event counts requests originating from the core that reference a cache line in the last level cache.", 196 "SampleAfterValue": "100003", 197 "CounterHTOff": "0,1,2,3,4,5,6,7" 198 }, 199 { 200 "EventCode": "0x48", 201 "UMask": "0x1", 202 "BriefDescription": "L1D miss oustandings duration in cycles", 203 "Counter": "2", 204 "EventName": "L1D_PEND_MISS.PENDING", 205 "PublicDescription": "Increments the number of outstanding L1D misses every cycle. Set Cmask = 1 and Edge =1 to count occurrences.", 206 "SampleAfterValue": "2000003", 207 "CounterHTOff": "2" 208 }, 209 { 210 "EventCode": "0x48", 211 "UMask": "0x1", 212 "BriefDescription": "Cycles with L1D load Misses outstanding.", 213 "Counter": "2", 214 "EventName": "L1D_PEND_MISS.PENDING_CYCLES", 215 "CounterMask": "1", 216 "SampleAfterValue": "2000003", 217 "CounterHTOff": "2" 218 }, 219 { 220 "EventCode": "0x48", 221 "UMask": "0x1", 222 "BriefDescription": "Cycles with L1D load Misses outstanding from any thread on physical core.", 223 "Counter": "2", 224 "EventName": "L1D_PEND_MISS.PENDING_CYCLES_ANY", 225 "AnyThread": "1", 226 "CounterMask": "1", 227 "SampleAfterValue": "2000003", 228 "CounterHTOff": "2" 229 }, 230 { 231 "EventCode": "0x48", 232 "UMask": "0x2", 233 "BriefDescription": "Number of times a request needed a FB entry but there was no entry available for it. That is the FB unavailability was dominant reason for blocking the request. A request includes cacheable/uncacheable demands that is load, store or SW prefetch. HWP are e.", 234 "Counter": "0,1,2,3", 235 "EventName": "L1D_PEND_MISS.REQUEST_FB_FULL", 236 "SampleAfterValue": "2000003", 237 "CounterHTOff": "0,1,2,3,4,5,6,7" 238 }, 239 { 240 "EventCode": "0x48", 241 "UMask": "0x2", 242 "BriefDescription": "Cycles a demand request was blocked due to Fill Buffers inavailability.", 243 "Counter": "0,1,2,3", 244 "EventName": "L1D_PEND_MISS.FB_FULL", 245 "CounterMask": "1", 246 "SampleAfterValue": "2000003", 247 "CounterHTOff": "0,1,2,3,4,5,6,7" 248 }, 249 { 250 "EventCode": "0x51", 251 "UMask": "0x1", 252 "BriefDescription": "L1D data line replacements", 253 "Counter": "0,1,2,3", 254 "EventName": "L1D.REPLACEMENT", 255 "PublicDescription": "This event counts when new data lines are brought into the L1 Data cache, which cause other lines to be evicted from the cache.", 256 "SampleAfterValue": "2000003", 257 "CounterHTOff": "0,1,2,3,4,5,6,7" 258 }, 259 { 260 "EventCode": "0x60", 261 "UMask": "0x1", 262 "BriefDescription": "Offcore outstanding Demand Data Read transactions in uncore queue.", 263 "Counter": "0,1,2,3", 264 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD", 265 "Errata": "HSD78, HSD62, HSD61", 266 "PublicDescription": "Offcore outstanding demand data read transactions in SQ to uncore. Set Cmask=1 to count cycles.", 267 "SampleAfterValue": "2000003", 268 "CounterHTOff": "0,1,2,3,4,5,6,7" 269 }, 270 { 271 "EventCode": "0x60", 272 "UMask": "0x1", 273 "BriefDescription": "Cycles when offcore outstanding Demand Data Read transactions are present in SuperQueue (SQ), queue to uncore.", 274 "Counter": "0,1,2,3", 275 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_DATA_RD", 276 "CounterMask": "1", 277 "Errata": "HSD78, HSD62, HSD61", 278 "SampleAfterValue": "2000003", 279 "CounterHTOff": "0,1,2,3,4,5,6,7" 280 }, 281 { 282 "EventCode": "0x60", 283 "UMask": "0x1", 284 "BriefDescription": "Cycles with at least 6 offcore outstanding Demand Data Read transactions in uncore queue.", 285 "Counter": "0,1,2,3", 286 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD_GE_6", 287 "CounterMask": "6", 288 "Errata": "HSD78, HSD62, HSD61", 289 "SampleAfterValue": "2000003", 290 "CounterHTOff": "0,1,2,3,4,5,6,7" 291 }, 292 { 293 "EventCode": "0x60", 294 "UMask": "0x2", 295 "BriefDescription": "Offcore outstanding code reads transactions in SuperQueue (SQ), queue to uncore, every cycle", 296 "Counter": "0,1,2,3", 297 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_CODE_RD", 298 "Errata": "HSD62, HSD61", 299 "PublicDescription": "Offcore outstanding Demand code Read transactions in SQ to uncore. Set Cmask=1 to count cycles.", 300 "SampleAfterValue": "2000003", 301 "CounterHTOff": "0,1,2,3,4,5,6,7" 302 }, 303 { 304 "EventCode": "0x60", 305 "UMask": "0x4", 306 "BriefDescription": "Offcore outstanding RFO store transactions in SuperQueue (SQ), queue to uncore", 307 "Counter": "0,1,2,3", 308 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_RFO", 309 "Errata": "HSD62, HSD61", 310 "PublicDescription": "Offcore outstanding RFO store transactions in SQ to uncore. Set Cmask=1 to count cycles.", 311 "SampleAfterValue": "2000003", 312 "CounterHTOff": "0,1,2,3,4,5,6,7" 313 }, 314 { 315 "EventCode": "0x60", 316 "UMask": "0x4", 317 "BriefDescription": "Offcore outstanding demand rfo reads transactions in SuperQueue (SQ), queue to uncore, every cycle.", 318 "Counter": "0,1,2,3", 319 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO", 320 "CounterMask": "1", 321 "Errata": "HSD62, HSD61", 322 "SampleAfterValue": "2000003", 323 "CounterHTOff": "0,1,2,3,4,5,6,7" 324 }, 325 { 326 "EventCode": "0x60", 327 "UMask": "0x8", 328 "BriefDescription": "Offcore outstanding cacheable Core Data Read transactions in SuperQueue (SQ), queue to uncore", 329 "Counter": "0,1,2,3", 330 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD", 331 "Errata": "HSD62, HSD61", 332 "PublicDescription": "Offcore outstanding cacheable data read transactions in SQ to uncore. Set Cmask=1 to count cycles.", 333 "SampleAfterValue": "2000003", 334 "CounterHTOff": "0,1,2,3,4,5,6,7" 335 }, 336 { 337 "EventCode": "0x60", 338 "UMask": "0x8", 339 "BriefDescription": "Cycles when offcore outstanding cacheable Core Data Read transactions are present in SuperQueue (SQ), queue to uncore.", 340 "Counter": "0,1,2,3", 341 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD", 342 "CounterMask": "1", 343 "Errata": "HSD62, HSD61", 344 "SampleAfterValue": "2000003", 345 "CounterHTOff": "0,1,2,3,4,5,6,7" 346 }, 347 { 348 "EventCode": "0x63", 349 "UMask": "0x2", 350 "BriefDescription": "Cycles when L1D is locked", 351 "Counter": "0,1,2,3", 352 "EventName": "LOCK_CYCLES.CACHE_LOCK_DURATION", 353 "PublicDescription": "Cycles in which the L1D is locked.", 354 "SampleAfterValue": "2000003", 355 "CounterHTOff": "0,1,2,3,4,5,6,7" 356 }, 357 { 358 "EventCode": "0xB0", 359 "UMask": "0x1", 360 "BriefDescription": "Demand Data Read requests sent to uncore", 361 "Counter": "0,1,2,3", 362 "EventName": "OFFCORE_REQUESTS.DEMAND_DATA_RD", 363 "Errata": "HSD78", 364 "PublicDescription": "Demand data read requests sent to uncore.", 365 "SampleAfterValue": "100003", 366 "CounterHTOff": "0,1,2,3,4,5,6,7" 367 }, 368 { 369 "EventCode": "0xB0", 370 "UMask": "0x2", 371 "BriefDescription": "Cacheable and noncachaeble code read requests", 372 "Counter": "0,1,2,3", 373 "EventName": "OFFCORE_REQUESTS.DEMAND_CODE_RD", 374 "PublicDescription": "Demand code read requests sent to uncore.", 375 "SampleAfterValue": "100003", 376 "CounterHTOff": "0,1,2,3,4,5,6,7" 377 }, 378 { 379 "EventCode": "0xB0", 380 "UMask": "0x4", 381 "BriefDescription": "Demand RFO requests including regular RFOs, locks, ItoM", 382 "Counter": "0,1,2,3", 383 "EventName": "OFFCORE_REQUESTS.DEMAND_RFO", 384 "PublicDescription": "Demand RFO read requests sent to uncore, including regular RFOs, locks, ItoM.", 385 "SampleAfterValue": "100003", 386 "CounterHTOff": "0,1,2,3,4,5,6,7" 387 }, 388 { 389 "EventCode": "0xB0", 390 "UMask": "0x8", 391 "BriefDescription": "Demand and prefetch data reads", 392 "Counter": "0,1,2,3", 393 "EventName": "OFFCORE_REQUESTS.ALL_DATA_RD", 394 "PublicDescription": "Data read requests sent to uncore (demand and prefetch).", 395 "SampleAfterValue": "100003", 396 "CounterHTOff": "0,1,2,3,4,5,6,7" 397 }, 398 { 399 "EventCode": "0xb2", 400 "UMask": "0x1", 401 "BriefDescription": "Offcore requests buffer cannot take more entries for this thread core.", 402 "Counter": "0,1,2,3", 403 "EventName": "OFFCORE_REQUESTS_BUFFER.SQ_FULL", 404 "SampleAfterValue": "2000003", 405 "CounterHTOff": "0,1,2,3,4,5,6,7" 406 }, 407 { 408 "EventCode": "0xB7, 0xBB", 409 "UMask": "0x1", 410 "BriefDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 411 "Counter": "0,1,2,3", 412 "EventName": "OFFCORE_RESPONSE", 413 "SampleAfterValue": "100003", 414 "CounterHTOff": "0,1,2,3" 415 }, 416 { 417 "EventCode": "0xD0", 418 "UMask": "0x11", 419 "BriefDescription": "Retired load uops that miss the STLB. (precise Event)", 420 "Data_LA": "1", 421 "PEBS": "1", 422 "Counter": "0,1,2,3", 423 "EventName": "MEM_UOPS_RETIRED.STLB_MISS_LOADS", 424 "Errata": "HSD29, HSM30", 425 "SampleAfterValue": "100003", 426 "CounterHTOff": "0,1,2,3" 427 }, 428 { 429 "EventCode": "0xD0", 430 "UMask": "0x12", 431 "BriefDescription": "Retired store uops that miss the STLB. (precise Event)", 432 "Data_LA": "1", 433 "PEBS": "1", 434 "Counter": "0,1,2,3", 435 "EventName": "MEM_UOPS_RETIRED.STLB_MISS_STORES", 436 "Errata": "HSD29, HSM30", 437 "L1_Hit_Indication": "1", 438 "SampleAfterValue": "100003", 439 "CounterHTOff": "0,1,2,3" 440 }, 441 { 442 "EventCode": "0xD0", 443 "UMask": "0x21", 444 "BriefDescription": "Retired load uops with locked access. (precise Event)", 445 "Data_LA": "1", 446 "PEBS": "1", 447 "Counter": "0,1,2,3", 448 "EventName": "MEM_UOPS_RETIRED.LOCK_LOADS", 449 "Errata": "HSD76, HSD29, HSM30", 450 "SampleAfterValue": "100003", 451 "CounterHTOff": "0,1,2,3" 452 }, 453 { 454 "EventCode": "0xD0", 455 "UMask": "0x41", 456 "BriefDescription": "Retired load uops that split across a cacheline boundary. (precise Event)", 457 "Data_LA": "1", 458 "PEBS": "1", 459 "Counter": "0,1,2,3", 460 "EventName": "MEM_UOPS_RETIRED.SPLIT_LOADS", 461 "Errata": "HSD29, HSM30", 462 "PublicDescription": "This event counts load uops retired which had memory addresses spilt across 2 cache lines. A line split is across 64B cache-lines which may include a page split (4K). This is a precise event.", 463 "SampleAfterValue": "100003", 464 "CounterHTOff": "0,1,2,3" 465 }, 466 { 467 "EventCode": "0xD0", 468 "UMask": "0x42", 469 "BriefDescription": "Retired store uops that split across a cacheline boundary. (precise Event)", 470 "Data_LA": "1", 471 "PEBS": "1", 472 "Counter": "0,1,2,3", 473 "EventName": "MEM_UOPS_RETIRED.SPLIT_STORES", 474 "Errata": "HSD29, HSM30", 475 "L1_Hit_Indication": "1", 476 "PublicDescription": "This event counts store uops retired which had memory addresses spilt across 2 cache lines. A line split is across 64B cache-lines which may include a page split (4K). This is a precise event.", 477 "SampleAfterValue": "100003", 478 "CounterHTOff": "0,1,2,3" 479 }, 480 { 481 "EventCode": "0xD0", 482 "UMask": "0x81", 483 "BriefDescription": "All retired load uops. (precise Event)", 484 "Data_LA": "1", 485 "PEBS": "1", 486 "Counter": "0,1,2,3", 487 "EventName": "MEM_UOPS_RETIRED.ALL_LOADS", 488 "Errata": "HSD29, HSM30", 489 "SampleAfterValue": "2000003", 490 "CounterHTOff": "0,1,2,3" 491 }, 492 { 493 "EventCode": "0xD0", 494 "UMask": "0x82", 495 "BriefDescription": "All retired store uops. (precise Event)", 496 "Data_LA": "1", 497 "PEBS": "1", 498 "Counter": "0,1,2,3", 499 "EventName": "MEM_UOPS_RETIRED.ALL_STORES", 500 "Errata": "HSD29, HSM30", 501 "L1_Hit_Indication": "1", 502 "PublicDescription": "This event counts all store uops retired. This is a precise event.", 503 "SampleAfterValue": "2000003", 504 "CounterHTOff": "0,1,2,3" 505 }, 506 { 507 "EventCode": "0xD1", 508 "UMask": "0x1", 509 "BriefDescription": "Retired load uops with L1 cache hits as data sources.", 510 "Data_LA": "1", 511 "PEBS": "1", 512 "Counter": "0,1,2,3", 513 "EventName": "MEM_LOAD_UOPS_RETIRED.L1_HIT", 514 "Errata": "HSD29, HSM30", 515 "SampleAfterValue": "2000003", 516 "CounterHTOff": "0,1,2,3" 517 }, 518 { 519 "EventCode": "0xD1", 520 "UMask": "0x2", 521 "BriefDescription": "Retired load uops with L2 cache hits as data sources.", 522 "Data_LA": "1", 523 "PEBS": "1", 524 "Counter": "0,1,2,3", 525 "EventName": "MEM_LOAD_UOPS_RETIRED.L2_HIT", 526 "Errata": "HSD76, HSD29, HSM30", 527 "SampleAfterValue": "100003", 528 "CounterHTOff": "0,1,2,3" 529 }, 530 { 531 "EventCode": "0xD1", 532 "UMask": "0x4", 533 "BriefDescription": "Miss in last-level (L3) cache. Excludes Unknown data-source.", 534 "Data_LA": "1", 535 "PEBS": "1", 536 "Counter": "0,1,2,3", 537 "EventName": "MEM_LOAD_UOPS_RETIRED.L3_HIT", 538 "Errata": "HSD74, HSD29, HSD25, HSM26, HSM30", 539 "PublicDescription": "This event counts retired load uops in which data sources were data hits in the L3 cache without snoops required. This does not include hardware prefetches. This is a precise event.", 540 "SampleAfterValue": "50021", 541 "CounterHTOff": "0,1,2,3" 542 }, 543 { 544 "EventCode": "0xD1", 545 "UMask": "0x8", 546 "BriefDescription": "Retired load uops misses in L1 cache as data sources.", 547 "Data_LA": "1", 548 "PEBS": "1", 549 "Counter": "0,1,2,3", 550 "EventName": "MEM_LOAD_UOPS_RETIRED.L1_MISS", 551 "Errata": "HSM30", 552 "PublicDescription": "This event counts retired load uops in which data sources missed in the L1 cache. This does not include hardware prefetches. This is a precise event.", 553 "SampleAfterValue": "100003", 554 "CounterHTOff": "0,1,2,3" 555 }, 556 { 557 "EventCode": "0xD1", 558 "UMask": "0x10", 559 "BriefDescription": "Retired load uops with L2 cache misses as data sources.", 560 "Data_LA": "1", 561 "PEBS": "1", 562 "Counter": "0,1,2,3", 563 "EventName": "MEM_LOAD_UOPS_RETIRED.L2_MISS", 564 "Errata": "HSD29, HSM30", 565 "SampleAfterValue": "50021", 566 "CounterHTOff": "0,1,2,3" 567 }, 568 { 569 "EventCode": "0xD1", 570 "UMask": "0x20", 571 "BriefDescription": "Miss in last-level (L3) cache. Excludes Unknown data-source.", 572 "Data_LA": "1", 573 "PEBS": "1", 574 "Counter": "0,1,2,3", 575 "EventName": "MEM_LOAD_UOPS_RETIRED.L3_MISS", 576 "Errata": "HSD74, HSD29, HSD25, HSM26, HSM30", 577 "SampleAfterValue": "100003", 578 "CounterHTOff": "0,1,2,3" 579 }, 580 { 581 "EventCode": "0xD1", 582 "UMask": "0x40", 583 "BriefDescription": "Retired load uops which data sources were load uops missed L1 but hit FB due to preceding miss to the same cache line with data not ready.", 584 "Data_LA": "1", 585 "PEBS": "1", 586 "Counter": "0,1,2,3", 587 "EventName": "MEM_LOAD_UOPS_RETIRED.HIT_LFB", 588 "Errata": "HSM30", 589 "SampleAfterValue": "100003", 590 "CounterHTOff": "0,1,2,3" 591 }, 592 { 593 "EventCode": "0xD2", 594 "UMask": "0x1", 595 "BriefDescription": "Retired load uops which data sources were L3 hit and cross-core snoop missed in on-pkg core cache.", 596 "Data_LA": "1", 597 "PEBS": "1", 598 "Counter": "0,1,2,3", 599 "EventName": "MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS", 600 "Errata": "HSD29, HSD25, HSM26, HSM30", 601 "SampleAfterValue": "20011", 602 "CounterHTOff": "0,1,2,3" 603 }, 604 { 605 "EventCode": "0xD2", 606 "UMask": "0x2", 607 "BriefDescription": "Retired load uops which data sources were L3 and cross-core snoop hits in on-pkg core cache. ", 608 "Data_LA": "1", 609 "PEBS": "1", 610 "Counter": "0,1,2,3", 611 "EventName": "MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT", 612 "Errata": "HSD29, HSD25, HSM26, HSM30", 613 "PublicDescription": "This event counts retired load uops that hit in the L3 cache, but required a cross-core snoop which resulted in a HIT in an on-pkg core cache. This does not include hardware prefetches. This is a precise event.", 614 "SampleAfterValue": "20011", 615 "CounterHTOff": "0,1,2,3" 616 }, 617 { 618 "EventCode": "0xD2", 619 "UMask": "0x4", 620 "BriefDescription": "Retired load uops which data sources were HitM responses from shared L3. ", 621 "Data_LA": "1", 622 "PEBS": "1", 623 "Counter": "0,1,2,3", 624 "EventName": "MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM", 625 "Errata": "HSD29, HSD25, HSM26, HSM30", 626 "PublicDescription": "This event counts retired load uops that hit in the L3 cache, but required a cross-core snoop which resulted in a HITM (hit modified) in an on-pkg core cache. This does not include hardware prefetches. This is a precise event.", 627 "SampleAfterValue": "20011", 628 "CounterHTOff": "0,1,2,3" 629 }, 630 { 631 "EventCode": "0xD2", 632 "UMask": "0x8", 633 "BriefDescription": "Retired load uops which data sources were hits in L3 without snoops required.", 634 "Data_LA": "1", 635 "PEBS": "1", 636 "Counter": "0,1,2,3", 637 "EventName": "MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_NONE", 638 "Errata": "HSD74, HSD29, HSD25, HSM26, HSM30", 639 "SampleAfterValue": "100003", 640 "CounterHTOff": "0,1,2,3" 641 }, 642 { 643 "EventCode": "0xD3", 644 "UMask": "0x1", 645 "Data_LA": "1", 646 "PEBS": "1", 647 "Counter": "0,1,2,3", 648 "EventName": "MEM_LOAD_UOPS_L3_MISS_RETIRED.LOCAL_DRAM", 649 "Errata": "HSD74, HSD29, HSD25, HSM30", 650 "PublicDescription": "This event counts retired load uops where the data came from local DRAM. This does not include hardware prefetches. This is a precise event.", 651 "SampleAfterValue": "100003", 652 "CounterHTOff": "0,1,2,3" 653 }, 654 { 655 "EventCode": "0xD3", 656 "UMask": "0x4", 657 "BriefDescription": "Retired load uop whose Data Source was: remote DRAM either Snoop not needed or Snoop Miss (RspI) (Precise Event)", 658 "Data_LA": "1", 659 "PEBS": "1", 660 "Counter": "0,1,2,3", 661 "EventName": "MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_DRAM", 662 "Errata": "HSD29, HSM30", 663 "SampleAfterValue": "100003", 664 "CounterHTOff": "0,1,2,3" 665 }, 666 { 667 "EventCode": "0xD3", 668 "UMask": "0x10", 669 "BriefDescription": "Retired load uop whose Data Source was: Remote cache HITM (Precise Event)", 670 "Data_LA": "1", 671 "PEBS": "1", 672 "Counter": "0,1,2,3", 673 "EventName": "MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_HITM", 674 "Errata": "HSM30", 675 "SampleAfterValue": "100003", 676 "CounterHTOff": "0,1,2,3" 677 }, 678 { 679 "EventCode": "0xD3", 680 "UMask": "0x20", 681 "BriefDescription": "Retired load uop whose Data Source was: forwarded from remote cache (Precise Event)", 682 "Data_LA": "1", 683 "PEBS": "1", 684 "Counter": "0,1,2,3", 685 "EventName": "MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_FWD", 686 "Errata": "HSM30", 687 "SampleAfterValue": "100003", 688 "CounterHTOff": "0,1,2,3" 689 }, 690 { 691 "EventCode": "0xf0", 692 "UMask": "0x1", 693 "BriefDescription": "Demand Data Read requests that access L2 cache", 694 "Counter": "0,1,2,3", 695 "EventName": "L2_TRANS.DEMAND_DATA_RD", 696 "PublicDescription": "Demand data read requests that access L2 cache.", 697 "SampleAfterValue": "200003", 698 "CounterHTOff": "0,1,2,3,4,5,6,7" 699 }, 700 { 701 "EventCode": "0xf0", 702 "UMask": "0x2", 703 "BriefDescription": "RFO requests that access L2 cache", 704 "Counter": "0,1,2,3", 705 "EventName": "L2_TRANS.RFO", 706 "PublicDescription": "RFO requests that access L2 cache.", 707 "SampleAfterValue": "200003", 708 "CounterHTOff": "0,1,2,3,4,5,6,7" 709 }, 710 { 711 "EventCode": "0xf0", 712 "UMask": "0x4", 713 "BriefDescription": "L2 cache accesses when fetching instructions", 714 "Counter": "0,1,2,3", 715 "EventName": "L2_TRANS.CODE_RD", 716 "PublicDescription": "L2 cache accesses when fetching instructions.", 717 "SampleAfterValue": "200003", 718 "CounterHTOff": "0,1,2,3,4,5,6,7" 719 }, 720 { 721 "EventCode": "0xf0", 722 "UMask": "0x8", 723 "BriefDescription": "L2 or L3 HW prefetches that access L2 cache", 724 "Counter": "0,1,2,3", 725 "EventName": "L2_TRANS.ALL_PF", 726 "PublicDescription": "Any MLC or L3 HW prefetch accessing L2, including rejects.", 727 "SampleAfterValue": "200003", 728 "CounterHTOff": "0,1,2,3,4,5,6,7" 729 }, 730 { 731 "EventCode": "0xf0", 732 "UMask": "0x10", 733 "BriefDescription": "L1D writebacks that access L2 cache", 734 "Counter": "0,1,2,3", 735 "EventName": "L2_TRANS.L1D_WB", 736 "PublicDescription": "L1D writebacks that access L2 cache.", 737 "SampleAfterValue": "200003", 738 "CounterHTOff": "0,1,2,3,4,5,6,7" 739 }, 740 { 741 "EventCode": "0xf0", 742 "UMask": "0x20", 743 "BriefDescription": "L2 fill requests that access L2 cache", 744 "Counter": "0,1,2,3", 745 "EventName": "L2_TRANS.L2_FILL", 746 "PublicDescription": "L2 fill requests that access L2 cache.", 747 "SampleAfterValue": "200003", 748 "CounterHTOff": "0,1,2,3,4,5,6,7" 749 }, 750 { 751 "EventCode": "0xf0", 752 "UMask": "0x40", 753 "BriefDescription": "L2 writebacks that access L2 cache", 754 "Counter": "0,1,2,3", 755 "EventName": "L2_TRANS.L2_WB", 756 "PublicDescription": "L2 writebacks that access L2 cache.", 757 "SampleAfterValue": "200003", 758 "CounterHTOff": "0,1,2,3,4,5,6,7" 759 }, 760 { 761 "EventCode": "0xf0", 762 "UMask": "0x80", 763 "BriefDescription": "Transactions accessing L2 pipe", 764 "Counter": "0,1,2,3", 765 "EventName": "L2_TRANS.ALL_REQUESTS", 766 "PublicDescription": "Transactions accessing L2 pipe.", 767 "SampleAfterValue": "200003", 768 "CounterHTOff": "0,1,2,3,4,5,6,7" 769 }, 770 { 771 "EventCode": "0xF1", 772 "UMask": "0x1", 773 "BriefDescription": "L2 cache lines in I state filling L2", 774 "Counter": "0,1,2,3", 775 "EventName": "L2_LINES_IN.I", 776 "PublicDescription": "L2 cache lines in I state filling L2.", 777 "SampleAfterValue": "100003", 778 "CounterHTOff": "0,1,2,3,4,5,6,7" 779 }, 780 { 781 "EventCode": "0xF1", 782 "UMask": "0x2", 783 "BriefDescription": "L2 cache lines in S state filling L2", 784 "Counter": "0,1,2,3", 785 "EventName": "L2_LINES_IN.S", 786 "PublicDescription": "L2 cache lines in S state filling L2.", 787 "SampleAfterValue": "100003", 788 "CounterHTOff": "0,1,2,3,4,5,6,7" 789 }, 790 { 791 "EventCode": "0xF1", 792 "UMask": "0x4", 793 "BriefDescription": "L2 cache lines in E state filling L2", 794 "Counter": "0,1,2,3", 795 "EventName": "L2_LINES_IN.E", 796 "PublicDescription": "L2 cache lines in E state filling L2.", 797 "SampleAfterValue": "100003", 798 "CounterHTOff": "0,1,2,3,4,5,6,7" 799 }, 800 { 801 "EventCode": "0xF1", 802 "UMask": "0x7", 803 "BriefDescription": "L2 cache lines filling L2", 804 "Counter": "0,1,2,3", 805 "EventName": "L2_LINES_IN.ALL", 806 "PublicDescription": "This event counts the number of L2 cache lines brought into the L2 cache. Lines are filled into the L2 cache when there was an L2 miss.", 807 "SampleAfterValue": "100003", 808 "CounterHTOff": "0,1,2,3,4,5,6,7" 809 }, 810 { 811 "EventCode": "0xF2", 812 "UMask": "0x5", 813 "BriefDescription": "Clean L2 cache lines evicted by demand", 814 "Counter": "0,1,2,3", 815 "EventName": "L2_LINES_OUT.DEMAND_CLEAN", 816 "PublicDescription": "Clean L2 cache lines evicted by demand.", 817 "SampleAfterValue": "100003", 818 "CounterHTOff": "0,1,2,3,4,5,6,7" 819 }, 820 { 821 "EventCode": "0xF2", 822 "UMask": "0x6", 823 "BriefDescription": "Dirty L2 cache lines evicted by demand", 824 "Counter": "0,1,2,3", 825 "EventName": "L2_LINES_OUT.DEMAND_DIRTY", 826 "PublicDescription": "Dirty L2 cache lines evicted by demand.", 827 "SampleAfterValue": "100003", 828 "CounterHTOff": "0,1,2,3,4,5,6,7" 829 }, 830 { 831 "EventCode": "0xf4", 832 "UMask": "0x10", 833 "BriefDescription": "Split locks in SQ", 834 "Counter": "0,1,2,3", 835 "EventName": "SQ_MISC.SPLIT_LOCK", 836 "PublicDescription": "", 837 "SampleAfterValue": "100003", 838 "CounterHTOff": "0,1,2,3,4,5,6,7" 839 }, 840 { 841 "Offcore": "1", 842 "EventCode": "0xB7, 0xBB", 843 "UMask": "0x1", 844 "BriefDescription": "Counts demand data reads that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded", 845 "MSRValue": "0x04003c0001", 846 "Counter": "0,1,2,3", 847 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD", 848 "MSRIndex": "0x1a6,0x1a7", 849 "PublicDescription": "Counts demand data reads that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 850 "SampleAfterValue": "100003", 851 "CounterHTOff": "0,1,2,3" 852 }, 853 { 854 "Offcore": "1", 855 "EventCode": "0xB7, 0xBB", 856 "UMask": "0x1", 857 "BriefDescription": "Counts demand data reads that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded", 858 "MSRValue": "0x10003c0001", 859 "Counter": "0,1,2,3", 860 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.HITM_OTHER_CORE", 861 "MSRIndex": "0x1a6,0x1a7", 862 "PublicDescription": "Counts demand data reads that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 863 "SampleAfterValue": "100003", 864 "CounterHTOff": "0,1,2,3" 865 }, 866 { 867 "Offcore": "1", 868 "EventCode": "0xB7, 0xBB", 869 "UMask": "0x1", 870 "BriefDescription": "Counts all demand data writes (RFOs) that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded", 871 "MSRValue": "0x04003c0002", 872 "Counter": "0,1,2,3", 873 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT.HIT_OTHER_CORE_NO_FWD", 874 "MSRIndex": "0x1a6,0x1a7", 875 "PublicDescription": "Counts all demand data writes (RFOs) that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 876 "SampleAfterValue": "100003", 877 "CounterHTOff": "0,1,2,3" 878 }, 879 { 880 "Offcore": "1", 881 "EventCode": "0xB7, 0xBB", 882 "UMask": "0x1", 883 "BriefDescription": "Counts all demand data writes (RFOs) that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded", 884 "MSRValue": "0x10003c0002", 885 "Counter": "0,1,2,3", 886 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT.HITM_OTHER_CORE", 887 "MSRIndex": "0x1a6,0x1a7", 888 "PublicDescription": "Counts all demand data writes (RFOs) that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 889 "SampleAfterValue": "100003", 890 "CounterHTOff": "0,1,2,3" 891 }, 892 { 893 "Offcore": "1", 894 "EventCode": "0xB7, 0xBB", 895 "UMask": "0x1", 896 "BriefDescription": "Counts all demand code reads that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded", 897 "MSRValue": "0x04003c0004", 898 "Counter": "0,1,2,3", 899 "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD", 900 "MSRIndex": "0x1a6,0x1a7", 901 "PublicDescription": "Counts all demand code reads that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 902 "SampleAfterValue": "100003", 903 "CounterHTOff": "0,1,2,3" 904 }, 905 { 906 "Offcore": "1", 907 "EventCode": "0xB7, 0xBB", 908 "UMask": "0x1", 909 "BriefDescription": "Counts all demand code reads that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded", 910 "MSRValue": "0x10003c0004", 911 "Counter": "0,1,2,3", 912 "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_HIT.HITM_OTHER_CORE", 913 "MSRIndex": "0x1a6,0x1a7", 914 "PublicDescription": "Counts all demand code reads that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 915 "SampleAfterValue": "100003", 916 "CounterHTOff": "0,1,2,3" 917 }, 918 { 919 "Offcore": "1", 920 "EventCode": "0xB7, 0xBB", 921 "UMask": "0x1", 922 "BriefDescription": "Counts prefetch (that bring data to L2) data reads that hit in the L3", 923 "MSRValue": "0x3f803c0010", 924 "Counter": "0,1,2,3", 925 "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_HIT.ANY_RESPONSE", 926 "MSRIndex": "0x1a6,0x1a7", 927 "PublicDescription": "Counts prefetch (that bring data to L2) data reads that hit in the L3 Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 928 "SampleAfterValue": "100003", 929 "CounterHTOff": "0,1,2,3" 930 }, 931 { 932 "Offcore": "1", 933 "EventCode": "0xB7, 0xBB", 934 "UMask": "0x1", 935 "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs that hit in the L3", 936 "MSRValue": "0x3f803c0020", 937 "Counter": "0,1,2,3", 938 "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.LLC_HIT.ANY_RESPONSE", 939 "MSRIndex": "0x1a6,0x1a7", 940 "PublicDescription": "Counts all prefetch (that bring data to L2) RFOs that hit in the L3 Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 941 "SampleAfterValue": "100003", 942 "CounterHTOff": "0,1,2,3" 943 }, 944 { 945 "Offcore": "1", 946 "EventCode": "0xB7, 0xBB", 947 "UMask": "0x1", 948 "BriefDescription": "Counts all prefetch (that bring data to LLC only) code reads that hit in the L3", 949 "MSRValue": "0x3f803c0040", 950 "Counter": "0,1,2,3", 951 "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.LLC_HIT.ANY_RESPONSE", 952 "MSRIndex": "0x1a6,0x1a7", 953 "PublicDescription": "Counts all prefetch (that bring data to LLC only) code reads that hit in the L3 Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 954 "SampleAfterValue": "100003", 955 "CounterHTOff": "0,1,2,3" 956 }, 957 { 958 "Offcore": "1", 959 "EventCode": "0xB7, 0xBB", 960 "UMask": "0x1", 961 "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads that hit in the L3", 962 "MSRValue": "0x3f803c0080", 963 "Counter": "0,1,2,3", 964 "EventName": "OFFCORE_RESPONSE.PF_LLC_DATA_RD.LLC_HIT.ANY_RESPONSE", 965 "MSRIndex": "0x1a6,0x1a7", 966 "PublicDescription": "Counts all prefetch (that bring data to LLC only) data reads that hit in the L3 Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 967 "SampleAfterValue": "100003", 968 "CounterHTOff": "0,1,2,3" 969 }, 970 { 971 "Offcore": "1", 972 "EventCode": "0xB7, 0xBB", 973 "UMask": "0x1", 974 "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs that hit in the L3", 975 "MSRValue": "0x3f803c0100", 976 "Counter": "0,1,2,3", 977 "EventName": "OFFCORE_RESPONSE.PF_LLC_RFO.LLC_HIT.ANY_RESPONSE", 978 "MSRIndex": "0x1a6,0x1a7", 979 "PublicDescription": "Counts all prefetch (that bring data to LLC only) RFOs that hit in the L3 Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 980 "SampleAfterValue": "100003", 981 "CounterHTOff": "0,1,2,3" 982 }, 983 { 984 "Offcore": "1", 985 "EventCode": "0xB7, 0xBB", 986 "UMask": "0x1", 987 "BriefDescription": "Counts prefetch (that bring data to LLC only) code reads that hit in the L3", 988 "MSRValue": "0x3f803c0200", 989 "Counter": "0,1,2,3", 990 "EventName": "OFFCORE_RESPONSE.PF_LLC_CODE_RD.LLC_HIT.ANY_RESPONSE", 991 "MSRIndex": "0x1a6,0x1a7", 992 "PublicDescription": "Counts prefetch (that bring data to LLC only) code reads that hit in the L3 Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 993 "SampleAfterValue": "100003", 994 "CounterHTOff": "0,1,2,3" 995 }, 996 { 997 "Offcore": "1", 998 "EventCode": "0xB7, 0xBB", 999 "UMask": "0x1", 1000 "BriefDescription": "Counts all demand & prefetch data reads that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded", 1001 "MSRValue": "0x04003c0091", 1002 "Counter": "0,1,2,3", 1003 "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD", 1004 "MSRIndex": "0x1a6,0x1a7", 1005 "PublicDescription": "Counts all demand & prefetch data reads that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1006 "SampleAfterValue": "100003", 1007 "CounterHTOff": "0,1,2,3" 1008 }, 1009 { 1010 "Offcore": "1", 1011 "EventCode": "0xB7, 0xBB", 1012 "UMask": "0x1", 1013 "BriefDescription": "Counts all demand & prefetch data reads that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded", 1014 "MSRValue": "0x10003c0091", 1015 "Counter": "0,1,2,3", 1016 "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.HITM_OTHER_CORE", 1017 "MSRIndex": "0x1a6,0x1a7", 1018 "PublicDescription": "Counts all demand & prefetch data reads that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1019 "SampleAfterValue": "100003", 1020 "CounterHTOff": "0,1,2,3" 1021 }, 1022 { 1023 "Offcore": "1", 1024 "EventCode": "0xB7, 0xBB", 1025 "UMask": "0x1", 1026 "BriefDescription": "Counts all demand & prefetch RFOs that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded", 1027 "MSRValue": "0x04003c0122", 1028 "Counter": "0,1,2,3", 1029 "EventName": "OFFCORE_RESPONSE.ALL_RFO.LLC_HIT.HIT_OTHER_CORE_NO_FWD", 1030 "MSRIndex": "0x1a6,0x1a7", 1031 "PublicDescription": "Counts all demand & prefetch RFOs that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1032 "SampleAfterValue": "100003", 1033 "CounterHTOff": "0,1,2,3" 1034 }, 1035 { 1036 "Offcore": "1", 1037 "EventCode": "0xB7, 0xBB", 1038 "UMask": "0x1", 1039 "BriefDescription": "Counts all demand & prefetch RFOs that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded", 1040 "MSRValue": "0x10003c0122", 1041 "Counter": "0,1,2,3", 1042 "EventName": "OFFCORE_RESPONSE.ALL_RFO.LLC_HIT.HITM_OTHER_CORE", 1043 "MSRIndex": "0x1a6,0x1a7", 1044 "PublicDescription": "Counts all demand & prefetch RFOs that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1045 "SampleAfterValue": "100003", 1046 "CounterHTOff": "0,1,2,3" 1047 }, 1048 { 1049 "Offcore": "1", 1050 "EventCode": "0xB7, 0xBB", 1051 "UMask": "0x1", 1052 "BriefDescription": "Counts all demand & prefetch code reads that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded", 1053 "MSRValue": "0x04003c0244", 1054 "Counter": "0,1,2,3", 1055 "EventName": "OFFCORE_RESPONSE.ALL_CODE_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD", 1056 "MSRIndex": "0x1a6,0x1a7", 1057 "PublicDescription": "Counts all demand & prefetch code reads that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1058 "SampleAfterValue": "100003", 1059 "CounterHTOff": "0,1,2,3" 1060 }, 1061 { 1062 "Offcore": "1", 1063 "EventCode": "0xB7, 0xBB", 1064 "UMask": "0x1", 1065 "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded", 1066 "MSRValue": "0x04003c07f7", 1067 "Counter": "0,1,2,3", 1068 "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_HIT.HIT_OTHER_CORE_NO_FWD", 1069 "MSRIndex": "0x1a6,0x1a7", 1070 "PublicDescription": "Counts all data/code/rfo reads (demand & prefetch) that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1071 "SampleAfterValue": "100003", 1072 "CounterHTOff": "0,1,2,3" 1073 }, 1074 { 1075 "Offcore": "1", 1076 "EventCode": "0xB7, 0xBB", 1077 "UMask": "0x1", 1078 "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded", 1079 "MSRValue": "0x10003c07f7", 1080 "Counter": "0,1,2,3", 1081 "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_HIT.HITM_OTHER_CORE", 1082 "MSRIndex": "0x1a6,0x1a7", 1083 "PublicDescription": "Counts all data/code/rfo reads (demand & prefetch) that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1084 "SampleAfterValue": "100003", 1085 "CounterHTOff": "0,1,2,3" 1086 }, 1087 { 1088 "Offcore": "1", 1089 "EventCode": "0xB7, 0xBB", 1090 "UMask": "0x1", 1091 "BriefDescription": "Counts all requests that hit in the L3", 1092 "MSRValue": "0x3f803c8fff", 1093 "Counter": "0,1,2,3", 1094 "EventName": "OFFCORE_RESPONSE.ALL_REQUESTS.LLC_HIT.ANY_RESPONSE", 1095 "MSRIndex": "0x1a6,0x1a7", 1096 "PublicDescription": "Counts all requests that hit in the L3 Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1097 "SampleAfterValue": "100003", 1098 "CounterHTOff": "0,1,2,3" 1099 } 1100]