1[
2    {
3        "BriefDescription": "L1D data line replacements",
4        "EventCode": "0x51",
5        "EventName": "L1D.REPLACEMENT",
6        "PublicDescription": "This event counts when new data lines are brought into the L1 Data cache, which cause other lines to be evicted from the cache.",
7        "SampleAfterValue": "2000003",
8        "UMask": "0x1"
9    },
10    {
11        "BriefDescription": "Cycles a demand request was blocked due to Fill Buffers inavailability.",
12        "CounterMask": "1",
13        "EventCode": "0x48",
14        "EventName": "L1D_PEND_MISS.FB_FULL",
15        "SampleAfterValue": "2000003",
16        "UMask": "0x2"
17    },
18    {
19        "BriefDescription": "L1D miss outstanding duration in cycles",
20        "EventCode": "0x48",
21        "EventName": "L1D_PEND_MISS.PENDING",
22        "PublicDescription": "Increments the number of outstanding L1D misses every cycle. Set Cmask = 1 and Edge =1 to count occurrences.",
23        "SampleAfterValue": "2000003",
24        "UMask": "0x1"
25    },
26    {
27        "BriefDescription": "Cycles with L1D load Misses outstanding.",
28        "CounterMask": "1",
29        "EventCode": "0x48",
30        "EventName": "L1D_PEND_MISS.PENDING_CYCLES",
31        "SampleAfterValue": "2000003",
32        "UMask": "0x1"
33    },
34    {
35        "AnyThread": "1",
36        "BriefDescription": "Cycles with L1D load Misses outstanding from any thread on physical core.",
37        "CounterMask": "1",
38        "EventCode": "0x48",
39        "EventName": "L1D_PEND_MISS.PENDING_CYCLES_ANY",
40        "SampleAfterValue": "2000003",
41        "UMask": "0x1"
42    },
43    {
44        "BriefDescription": "Number of times a request needed a FB entry but there was no entry available for it. That is the FB unavailability was dominant reason for blocking the request. A request includes cacheable/uncacheable demands that is load, store or SW prefetch. HWP are e.",
45        "EventCode": "0x48",
46        "EventName": "L1D_PEND_MISS.REQUEST_FB_FULL",
47        "SampleAfterValue": "2000003",
48        "UMask": "0x2"
49    },
50    {
51        "BriefDescription": "Not rejected writebacks that hit L2 cache",
52        "EventCode": "0x27",
53        "EventName": "L2_DEMAND_RQSTS.WB_HIT",
54        "PublicDescription": "Not rejected writebacks that hit L2 cache.",
55        "SampleAfterValue": "200003",
56        "UMask": "0x50"
57    },
58    {
59        "BriefDescription": "L2 cache lines filling L2",
60        "EventCode": "0xF1",
61        "EventName": "L2_LINES_IN.ALL",
62        "PublicDescription": "This event counts the number of L2 cache lines brought into the L2 cache.  Lines are filled into the L2 cache when there was an L2 miss.",
63        "SampleAfterValue": "100003",
64        "UMask": "0x7"
65    },
66    {
67        "BriefDescription": "L2 cache lines in E state filling L2",
68        "EventCode": "0xF1",
69        "EventName": "L2_LINES_IN.E",
70        "PublicDescription": "L2 cache lines in E state filling L2.",
71        "SampleAfterValue": "100003",
72        "UMask": "0x4"
73    },
74    {
75        "BriefDescription": "L2 cache lines in I state filling L2",
76        "EventCode": "0xF1",
77        "EventName": "L2_LINES_IN.I",
78        "PublicDescription": "L2 cache lines in I state filling L2.",
79        "SampleAfterValue": "100003",
80        "UMask": "0x1"
81    },
82    {
83        "BriefDescription": "L2 cache lines in S state filling L2",
84        "EventCode": "0xF1",
85        "EventName": "L2_LINES_IN.S",
86        "PublicDescription": "L2 cache lines in S state filling L2.",
87        "SampleAfterValue": "100003",
88        "UMask": "0x2"
89    },
90    {
91        "BriefDescription": "Clean L2 cache lines evicted by demand",
92        "EventCode": "0xF2",
93        "EventName": "L2_LINES_OUT.DEMAND_CLEAN",
94        "PublicDescription": "Clean L2 cache lines evicted by demand.",
95        "SampleAfterValue": "100003",
96        "UMask": "0x5"
97    },
98    {
99        "BriefDescription": "Dirty L2 cache lines evicted by demand",
100        "EventCode": "0xF2",
101        "EventName": "L2_LINES_OUT.DEMAND_DIRTY",
102        "PublicDescription": "Dirty L2 cache lines evicted by demand.",
103        "SampleAfterValue": "100003",
104        "UMask": "0x6"
105    },
106    {
107        "BriefDescription": "L2 code requests",
108        "EventCode": "0x24",
109        "EventName": "L2_RQSTS.ALL_CODE_RD",
110        "PublicDescription": "Counts all L2 code requests.",
111        "SampleAfterValue": "200003",
112        "UMask": "0xe4"
113    },
114    {
115        "BriefDescription": "Demand Data Read requests",
116        "Errata": "HSD78, HSM80",
117        "EventCode": "0x24",
118        "EventName": "L2_RQSTS.ALL_DEMAND_DATA_RD",
119        "PublicDescription": "Counts any demand and L1 HW prefetch data load requests to L2.",
120        "SampleAfterValue": "200003",
121        "UMask": "0xe1"
122    },
123    {
124        "BriefDescription": "Demand requests that miss L2 cache",
125        "Errata": "HSD78, HSM80",
126        "EventCode": "0x24",
127        "EventName": "L2_RQSTS.ALL_DEMAND_MISS",
128        "PublicDescription": "Demand requests that miss L2 cache.",
129        "SampleAfterValue": "200003",
130        "UMask": "0x27"
131    },
132    {
133        "BriefDescription": "Demand requests to L2 cache",
134        "Errata": "HSD78, HSM80",
135        "EventCode": "0x24",
136        "EventName": "L2_RQSTS.ALL_DEMAND_REFERENCES",
137        "PublicDescription": "Demand requests to L2 cache.",
138        "SampleAfterValue": "200003",
139        "UMask": "0xe7"
140    },
141    {
142        "BriefDescription": "Requests from L2 hardware prefetchers",
143        "EventCode": "0x24",
144        "EventName": "L2_RQSTS.ALL_PF",
145        "PublicDescription": "Counts all L2 HW prefetcher requests.",
146        "SampleAfterValue": "200003",
147        "UMask": "0xf8"
148    },
149    {
150        "BriefDescription": "RFO requests to L2 cache",
151        "EventCode": "0x24",
152        "EventName": "L2_RQSTS.ALL_RFO",
153        "PublicDescription": "Counts all L2 store RFO requests.",
154        "SampleAfterValue": "200003",
155        "UMask": "0xe2"
156    },
157    {
158        "BriefDescription": "L2 cache hits when fetching instructions, code reads.",
159        "EventCode": "0x24",
160        "EventName": "L2_RQSTS.CODE_RD_HIT",
161        "PublicDescription": "Number of instruction fetches that hit the L2 cache.",
162        "SampleAfterValue": "200003",
163        "UMask": "0xc4"
164    },
165    {
166        "BriefDescription": "L2 cache misses when fetching instructions",
167        "EventCode": "0x24",
168        "EventName": "L2_RQSTS.CODE_RD_MISS",
169        "PublicDescription": "Number of instruction fetches that missed the L2 cache.",
170        "SampleAfterValue": "200003",
171        "UMask": "0x24"
172    },
173    {
174        "BriefDescription": "Demand Data Read requests that hit L2 cache",
175        "Errata": "HSD78, HSM80",
176        "EventCode": "0x24",
177        "EventName": "L2_RQSTS.DEMAND_DATA_RD_HIT",
178        "PublicDescription": "Counts the number of demand Data Read requests, initiated by load instructions, that hit L2 cache",
179        "SampleAfterValue": "200003",
180        "UMask": "0xc1"
181    },
182    {
183        "BriefDescription": "Demand Data Read miss L2, no rejects",
184        "Errata": "HSD78, HSM80",
185        "EventCode": "0x24",
186        "EventName": "L2_RQSTS.DEMAND_DATA_RD_MISS",
187        "PublicDescription": "Demand data read requests that missed L2, no rejects.",
188        "SampleAfterValue": "200003",
189        "UMask": "0x21"
190    },
191    {
192        "BriefDescription": "L2 prefetch requests that hit L2 cache",
193        "EventCode": "0x24",
194        "EventName": "L2_RQSTS.L2_PF_HIT",
195        "PublicDescription": "Counts all L2 HW prefetcher requests that hit L2.",
196        "SampleAfterValue": "200003",
197        "UMask": "0xd0"
198    },
199    {
200        "BriefDescription": "L2 prefetch requests that miss L2 cache",
201        "EventCode": "0x24",
202        "EventName": "L2_RQSTS.L2_PF_MISS",
203        "PublicDescription": "Counts all L2 HW prefetcher requests that missed L2.",
204        "SampleAfterValue": "200003",
205        "UMask": "0x30"
206    },
207    {
208        "BriefDescription": "All requests that miss L2 cache",
209        "Errata": "HSD78, HSM80",
210        "EventCode": "0x24",
211        "EventName": "L2_RQSTS.MISS",
212        "PublicDescription": "All requests that missed L2.",
213        "SampleAfterValue": "200003",
214        "UMask": "0x3f"
215    },
216    {
217        "BriefDescription": "All L2 requests",
218        "Errata": "HSD78, HSM80",
219        "EventCode": "0x24",
220        "EventName": "L2_RQSTS.REFERENCES",
221        "PublicDescription": "All requests to L2 cache.",
222        "SampleAfterValue": "200003",
223        "UMask": "0xff"
224    },
225    {
226        "BriefDescription": "RFO requests that hit L2 cache",
227        "EventCode": "0x24",
228        "EventName": "L2_RQSTS.RFO_HIT",
229        "PublicDescription": "Counts the number of store RFO requests that hit the L2 cache.",
230        "SampleAfterValue": "200003",
231        "UMask": "0xc2"
232    },
233    {
234        "BriefDescription": "RFO requests that miss L2 cache",
235        "EventCode": "0x24",
236        "EventName": "L2_RQSTS.RFO_MISS",
237        "PublicDescription": "Counts the number of store RFO requests that miss the L2 cache.",
238        "SampleAfterValue": "200003",
239        "UMask": "0x22"
240    },
241    {
242        "BriefDescription": "L2 or L3 HW prefetches that access L2 cache",
243        "EventCode": "0xf0",
244        "EventName": "L2_TRANS.ALL_PF",
245        "PublicDescription": "Any MLC or L3 HW prefetch accessing L2, including rejects.",
246        "SampleAfterValue": "200003",
247        "UMask": "0x8"
248    },
249    {
250        "BriefDescription": "Transactions accessing L2 pipe",
251        "EventCode": "0xf0",
252        "EventName": "L2_TRANS.ALL_REQUESTS",
253        "PublicDescription": "Transactions accessing L2 pipe.",
254        "SampleAfterValue": "200003",
255        "UMask": "0x80"
256    },
257    {
258        "BriefDescription": "L2 cache accesses when fetching instructions",
259        "EventCode": "0xf0",
260        "EventName": "L2_TRANS.CODE_RD",
261        "PublicDescription": "L2 cache accesses when fetching instructions.",
262        "SampleAfterValue": "200003",
263        "UMask": "0x4"
264    },
265    {
266        "BriefDescription": "Demand Data Read requests that access L2 cache",
267        "EventCode": "0xf0",
268        "EventName": "L2_TRANS.DEMAND_DATA_RD",
269        "PublicDescription": "Demand data read requests that access L2 cache.",
270        "SampleAfterValue": "200003",
271        "UMask": "0x1"
272    },
273    {
274        "BriefDescription": "L1D writebacks that access L2 cache",
275        "EventCode": "0xf0",
276        "EventName": "L2_TRANS.L1D_WB",
277        "PublicDescription": "L1D writebacks that access L2 cache.",
278        "SampleAfterValue": "200003",
279        "UMask": "0x10"
280    },
281    {
282        "BriefDescription": "L2 fill requests that access L2 cache",
283        "EventCode": "0xf0",
284        "EventName": "L2_TRANS.L2_FILL",
285        "PublicDescription": "L2 fill requests that access L2 cache.",
286        "SampleAfterValue": "200003",
287        "UMask": "0x20"
288    },
289    {
290        "BriefDescription": "L2 writebacks that access L2 cache",
291        "EventCode": "0xf0",
292        "EventName": "L2_TRANS.L2_WB",
293        "PublicDescription": "L2 writebacks that access L2 cache.",
294        "SampleAfterValue": "200003",
295        "UMask": "0x40"
296    },
297    {
298        "BriefDescription": "RFO requests that access L2 cache",
299        "EventCode": "0xf0",
300        "EventName": "L2_TRANS.RFO",
301        "PublicDescription": "RFO requests that access L2 cache.",
302        "SampleAfterValue": "200003",
303        "UMask": "0x2"
304    },
305    {
306        "BriefDescription": "Cycles when L1D is locked",
307        "EventCode": "0x63",
308        "EventName": "LOCK_CYCLES.CACHE_LOCK_DURATION",
309        "PublicDescription": "Cycles in which the L1D is locked.",
310        "SampleAfterValue": "2000003",
311        "UMask": "0x2"
312    },
313    {
314        "BriefDescription": "Core-originated cacheable demand requests missed L3",
315        "EventCode": "0x2E",
316        "EventName": "LONGEST_LAT_CACHE.MISS",
317        "PublicDescription": "This event counts each cache miss condition for references to the last level cache.",
318        "SampleAfterValue": "100003",
319        "UMask": "0x41"
320    },
321    {
322        "BriefDescription": "Core-originated cacheable demand requests that refer to L3",
323        "EventCode": "0x2E",
324        "EventName": "LONGEST_LAT_CACHE.REFERENCE",
325        "PublicDescription": "This event counts requests originating from the core that reference a cache line in the last level cache.",
326        "SampleAfterValue": "100003",
327        "UMask": "0x4f"
328    },
329    {
330        "BriefDescription": "Retired load uops which data sources were L3 and cross-core snoop hits in on-pkg core cache.",
331        "Data_LA": "1",
332        "Errata": "HSD29, HSD25, HSM26, HSM30",
333        "EventCode": "0xD2",
334        "EventName": "MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT",
335        "PEBS": "1",
336        "SampleAfterValue": "20011",
337        "UMask": "0x2"
338    },
339    {
340        "BriefDescription": "Retired load uops which data sources were HitM responses from shared L3.",
341        "Data_LA": "1",
342        "Errata": "HSD29, HSD25, HSM26, HSM30",
343        "EventCode": "0xD2",
344        "EventName": "MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM",
345        "PEBS": "1",
346        "SampleAfterValue": "20011",
347        "UMask": "0x4"
348    },
349    {
350        "BriefDescription": "Retired load uops which data sources were L3 hit and cross-core snoop missed in on-pkg core cache.",
351        "Data_LA": "1",
352        "Errata": "HSD29, HSD25, HSM26, HSM30",
353        "EventCode": "0xD2",
354        "EventName": "MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS",
355        "PEBS": "1",
356        "SampleAfterValue": "20011",
357        "UMask": "0x1"
358    },
359    {
360        "BriefDescription": "Retired load uops which data sources were hits in L3 without snoops required.",
361        "Data_LA": "1",
362        "Errata": "HSD74, HSD29, HSD25, HSM26, HSM30",
363        "EventCode": "0xD2",
364        "EventName": "MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_NONE",
365        "PEBS": "1",
366        "SampleAfterValue": "100003",
367        "UMask": "0x8"
368    },
369    {
370        "BriefDescription": "Data from local DRAM either Snoop not needed or Snoop Miss (RspI)",
371        "Data_LA": "1",
372        "Errata": "HSD74, HSD29, HSD25, HSM30",
373        "EventCode": "0xD3",
374        "EventName": "MEM_LOAD_UOPS_L3_MISS_RETIRED.LOCAL_DRAM",
375        "PEBS": "1",
376        "PublicDescription": "This event counts retired load uops where the data came from local DRAM. This does not include hardware prefetches.",
377        "SampleAfterValue": "100003",
378        "UMask": "0x1"
379    },
380    {
381        "BriefDescription": "Retired load uop whose Data Source was: remote DRAM either Snoop not needed or Snoop Miss (RspI)",
382        "Data_LA": "1",
383        "Errata": "HSD29, HSM30",
384        "EventCode": "0xD3",
385        "EventName": "MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_DRAM",
386        "PEBS": "1",
387        "SampleAfterValue": "100003",
388        "UMask": "0x4"
389    },
390    {
391        "BriefDescription": "Retired load uop whose Data Source was: forwarded from remote cache",
392        "Data_LA": "1",
393        "Errata": "HSM30",
394        "EventCode": "0xD3",
395        "EventName": "MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_FWD",
396        "PEBS": "1",
397        "SampleAfterValue": "100003",
398        "UMask": "0x20"
399    },
400    {
401        "BriefDescription": "Retired load uop whose Data Source was: Remote cache HITM",
402        "Data_LA": "1",
403        "Errata": "HSM30",
404        "EventCode": "0xD3",
405        "EventName": "MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_HITM",
406        "PEBS": "1",
407        "SampleAfterValue": "100003",
408        "UMask": "0x10"
409    },
410    {
411        "BriefDescription": "Retired load uops which data sources were load uops missed L1 but hit FB due to preceding miss to the same cache line with data not ready.",
412        "Data_LA": "1",
413        "Errata": "HSM30",
414        "EventCode": "0xD1",
415        "EventName": "MEM_LOAD_UOPS_RETIRED.HIT_LFB",
416        "PEBS": "1",
417        "SampleAfterValue": "100003",
418        "UMask": "0x40"
419    },
420    {
421        "BriefDescription": "Retired load uops with L1 cache hits as data sources.",
422        "Data_LA": "1",
423        "Errata": "HSD29, HSM30",
424        "EventCode": "0xD1",
425        "EventName": "MEM_LOAD_UOPS_RETIRED.L1_HIT",
426        "PEBS": "1",
427        "SampleAfterValue": "2000003",
428        "UMask": "0x1"
429    },
430    {
431        "BriefDescription": "Retired load uops misses in L1 cache as data sources.",
432        "Data_LA": "1",
433        "Errata": "HSM30",
434        "EventCode": "0xD1",
435        "EventName": "MEM_LOAD_UOPS_RETIRED.L1_MISS",
436        "PEBS": "1",
437        "PublicDescription": "Retired load uops missed L1 cache as data sources.",
438        "SampleAfterValue": "100003",
439        "UMask": "0x8"
440    },
441    {
442        "BriefDescription": "Retired load uops with L2 cache hits as data sources.",
443        "Data_LA": "1",
444        "Errata": "HSD76, HSD29, HSM30",
445        "EventCode": "0xD1",
446        "EventName": "MEM_LOAD_UOPS_RETIRED.L2_HIT",
447        "PEBS": "1",
448        "SampleAfterValue": "100003",
449        "UMask": "0x2"
450    },
451    {
452        "BriefDescription": "Miss in mid-level (L2) cache. Excludes Unknown data-source.",
453        "Data_LA": "1",
454        "Errata": "HSD29, HSM30",
455        "EventCode": "0xD1",
456        "EventName": "MEM_LOAD_UOPS_RETIRED.L2_MISS",
457        "PEBS": "1",
458        "PublicDescription": "Retired load uops missed L2. Unknown data source excluded.",
459        "SampleAfterValue": "50021",
460        "UMask": "0x10"
461    },
462    {
463        "BriefDescription": "Retired load uops which data sources were data hits in L3 without snoops required.",
464        "Data_LA": "1",
465        "Errata": "HSD74, HSD29, HSD25, HSM26, HSM30",
466        "EventCode": "0xD1",
467        "EventName": "MEM_LOAD_UOPS_RETIRED.L3_HIT",
468        "PEBS": "1",
469        "PublicDescription": "Retired load uops with L3 cache hits as data sources.",
470        "SampleAfterValue": "50021",
471        "UMask": "0x4"
472    },
473    {
474        "BriefDescription": "Miss in last-level (L3) cache. Excludes Unknown data-source.",
475        "Data_LA": "1",
476        "Errata": "HSD74, HSD29, HSD25, HSM26, HSM30",
477        "EventCode": "0xD1",
478        "EventName": "MEM_LOAD_UOPS_RETIRED.L3_MISS",
479        "PEBS": "1",
480        "PublicDescription": "Retired load uops missed L3. Excludes unknown data source .",
481        "SampleAfterValue": "100003",
482        "UMask": "0x20"
483    },
484    {
485        "BriefDescription": "Retired load uops.",
486        "Data_LA": "1",
487        "Errata": "HSD29, HSM30",
488        "EventCode": "0xD0",
489        "EventName": "MEM_UOPS_RETIRED.ALL_LOADS",
490        "PEBS": "1",
491        "PublicDescription": "Counts all retired load uops. This event accounts for SW prefetch uops of PREFETCHNTA or PREFETCHT0/1/2 or PREFETCHW.",
492        "SampleAfterValue": "2000003",
493        "UMask": "0x81"
494    },
495    {
496        "BriefDescription": "Retired store uops.",
497        "Data_LA": "1",
498        "Errata": "HSD29, HSM30",
499        "EventCode": "0xD0",
500        "EventName": "MEM_UOPS_RETIRED.ALL_STORES",
501        "PEBS": "1",
502        "PublicDescription": "Counts all retired store uops.",
503        "SampleAfterValue": "2000003",
504        "UMask": "0x82"
505    },
506    {
507        "BriefDescription": "Retired load uops with locked access.",
508        "Data_LA": "1",
509        "Errata": "HSD76, HSD29, HSM30",
510        "EventCode": "0xD0",
511        "EventName": "MEM_UOPS_RETIRED.LOCK_LOADS",
512        "PEBS": "1",
513        "SampleAfterValue": "100003",
514        "UMask": "0x21"
515    },
516    {
517        "BriefDescription": "Retired load uops that split across a cacheline boundary.",
518        "Data_LA": "1",
519        "Errata": "HSD29, HSM30",
520        "EventCode": "0xD0",
521        "EventName": "MEM_UOPS_RETIRED.SPLIT_LOADS",
522        "PEBS": "1",
523        "SampleAfterValue": "100003",
524        "UMask": "0x41"
525    },
526    {
527        "BriefDescription": "Retired store uops that split across a cacheline boundary.",
528        "Data_LA": "1",
529        "Errata": "HSD29, HSM30",
530        "EventCode": "0xD0",
531        "EventName": "MEM_UOPS_RETIRED.SPLIT_STORES",
532        "PEBS": "1",
533        "SampleAfterValue": "100003",
534        "UMask": "0x42"
535    },
536    {
537        "BriefDescription": "Retired load uops that miss the STLB.",
538        "Data_LA": "1",
539        "Errata": "HSD29, HSM30",
540        "EventCode": "0xD0",
541        "EventName": "MEM_UOPS_RETIRED.STLB_MISS_LOADS",
542        "PEBS": "1",
543        "SampleAfterValue": "100003",
544        "UMask": "0x11"
545    },
546    {
547        "BriefDescription": "Retired store uops that miss the STLB.",
548        "Data_LA": "1",
549        "Errata": "HSD29, HSM30",
550        "EventCode": "0xD0",
551        "EventName": "MEM_UOPS_RETIRED.STLB_MISS_STORES",
552        "PEBS": "1",
553        "SampleAfterValue": "100003",
554        "UMask": "0x12"
555    },
556    {
557        "BriefDescription": "Demand and prefetch data reads",
558        "EventCode": "0xB0",
559        "EventName": "OFFCORE_REQUESTS.ALL_DATA_RD",
560        "PublicDescription": "Data read requests sent to uncore (demand and prefetch).",
561        "SampleAfterValue": "100003",
562        "UMask": "0x8"
563    },
564    {
565        "BriefDescription": "Cacheable and noncacheable code read requests",
566        "EventCode": "0xB0",
567        "EventName": "OFFCORE_REQUESTS.DEMAND_CODE_RD",
568        "PublicDescription": "Demand code read requests sent to uncore.",
569        "SampleAfterValue": "100003",
570        "UMask": "0x2"
571    },
572    {
573        "BriefDescription": "Demand Data Read requests sent to uncore",
574        "Errata": "HSD78, HSM80",
575        "EventCode": "0xb0",
576        "EventName": "OFFCORE_REQUESTS.DEMAND_DATA_RD",
577        "PublicDescription": "Demand data read requests sent to uncore.",
578        "SampleAfterValue": "100003",
579        "UMask": "0x1"
580    },
581    {
582        "BriefDescription": "Demand RFO requests including regular RFOs, locks, ItoM",
583        "EventCode": "0xB0",
584        "EventName": "OFFCORE_REQUESTS.DEMAND_RFO",
585        "PublicDescription": "Demand RFO read requests sent to uncore, including regular RFOs, locks, ItoM.",
586        "SampleAfterValue": "100003",
587        "UMask": "0x4"
588    },
589    {
590        "BriefDescription": "Offcore requests buffer cannot take more entries for this thread core.",
591        "EventCode": "0xb2",
592        "EventName": "OFFCORE_REQUESTS_BUFFER.SQ_FULL",
593        "SampleAfterValue": "2000003",
594        "UMask": "0x1"
595    },
596    {
597        "BriefDescription": "Offcore outstanding cacheable Core Data Read transactions in SuperQueue (SQ), queue to uncore",
598        "Errata": "HSD62, HSD61, HSM63",
599        "EventCode": "0x60",
600        "EventName": "OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD",
601        "PublicDescription": "Offcore outstanding cacheable data read transactions in SQ to uncore. Set Cmask=1 to count cycles.",
602        "SampleAfterValue": "2000003",
603        "UMask": "0x8"
604    },
605    {
606        "BriefDescription": "Cycles when offcore outstanding cacheable Core Data Read transactions are present in SuperQueue (SQ), queue to uncore.",
607        "CounterMask": "1",
608        "Errata": "HSD62, HSD61, HSM63",
609        "EventCode": "0x60",
610        "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD",
611        "SampleAfterValue": "2000003",
612        "UMask": "0x8"
613    },
614    {
615        "BriefDescription": "Cycles when offcore outstanding Demand Data Read transactions are present in SuperQueue (SQ), queue to uncore.",
616        "CounterMask": "1",
617        "Errata": "HSD78, HSD62, HSD61, HSM63, HSM80",
618        "EventCode": "0x60",
619        "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_DATA_RD",
620        "SampleAfterValue": "2000003",
621        "UMask": "0x1"
622    },
623    {
624        "BriefDescription": "Offcore outstanding demand rfo reads transactions in SuperQueue (SQ), queue to uncore, every cycle.",
625        "CounterMask": "1",
626        "Errata": "HSD62, HSD61, HSM63",
627        "EventCode": "0x60",
628        "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO",
629        "SampleAfterValue": "2000003",
630        "UMask": "0x4"
631    },
632    {
633        "BriefDescription": "Offcore outstanding code reads transactions in SuperQueue (SQ), queue to uncore, every cycle",
634        "Errata": "HSD62, HSD61, HSM63",
635        "EventCode": "0x60",
636        "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_CODE_RD",
637        "PublicDescription": "Offcore outstanding Demand code Read transactions in SQ to uncore. Set Cmask=1 to count cycles.",
638        "SampleAfterValue": "2000003",
639        "UMask": "0x2"
640    },
641    {
642        "BriefDescription": "Offcore outstanding Demand Data Read transactions in uncore queue.",
643        "Errata": "HSD78, HSD62, HSD61, HSM63, HSM80",
644        "EventCode": "0x60",
645        "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD",
646        "PublicDescription": "Offcore outstanding demand data read transactions in SQ to uncore. Set Cmask=1 to count cycles.",
647        "SampleAfterValue": "2000003",
648        "UMask": "0x1"
649    },
650    {
651        "BriefDescription": "Cycles with at least 6 offcore outstanding Demand Data Read transactions in uncore queue.",
652        "CounterMask": "6",
653        "Errata": "HSD78, HSD62, HSD61, HSM63, HSM80",
654        "EventCode": "0x60",
655        "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD_GE_6",
656        "SampleAfterValue": "2000003",
657        "UMask": "0x1"
658    },
659    {
660        "BriefDescription": "Offcore outstanding RFO store transactions in SuperQueue (SQ), queue to uncore",
661        "Errata": "HSD62, HSD61, HSM63",
662        "EventCode": "0x60",
663        "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_RFO",
664        "PublicDescription": "Offcore outstanding RFO store transactions in SQ to uncore. Set Cmask=1 to count cycles.",
665        "SampleAfterValue": "2000003",
666        "UMask": "0x4"
667    },
668    {
669        "BriefDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
670        "EventCode": "0xB7, 0xBB",
671        "EventName": "OFFCORE_RESPONSE",
672        "SampleAfterValue": "100003",
673        "UMask": "0x1"
674    },
675    {
676        "BriefDescription": "Counts all demand & prefetch code reads hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded",
677        "EventCode": "0xB7, 0xBB",
678        "EventName": "OFFCORE_RESPONSE.ALL_CODE_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD",
679        "MSRIndex": "0x1a6,0x1a7",
680        "MSRValue": "0x4003C0244",
681        "SampleAfterValue": "100003",
682        "UMask": "0x1"
683    },
684    {
685        "BriefDescription": "Counts all demand & prefetch data reads hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",
686        "EventCode": "0xB7, 0xBB",
687        "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.HITM_OTHER_CORE",
688        "MSRIndex": "0x1a6,0x1a7",
689        "MSRValue": "0x10003C0091",
690        "SampleAfterValue": "100003",
691        "UMask": "0x1"
692    },
693    {
694        "BriefDescription": "Counts all demand & prefetch data reads hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded",
695        "EventCode": "0xB7, 0xBB",
696        "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD",
697        "MSRIndex": "0x1a6,0x1a7",
698        "MSRValue": "0x4003C0091",
699        "SampleAfterValue": "100003",
700        "UMask": "0x1"
701    },
702    {
703        "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",
704        "EventCode": "0xB7, 0xBB",
705        "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_HIT.HITM_OTHER_CORE",
706        "MSRIndex": "0x1a6,0x1a7",
707        "MSRValue": "0x10003C07F7",
708        "SampleAfterValue": "100003",
709        "UMask": "0x1"
710    },
711    {
712        "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded",
713        "EventCode": "0xB7, 0xBB",
714        "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_HIT.HIT_OTHER_CORE_NO_FWD",
715        "MSRIndex": "0x1a6,0x1a7",
716        "MSRValue": "0x4003C07F7",
717        "SampleAfterValue": "100003",
718        "UMask": "0x1"
719    },
720    {
721        "BriefDescription": "Counts all requests hit in the L3",
722        "EventCode": "0xB7, 0xBB",
723        "EventName": "OFFCORE_RESPONSE.ALL_REQUESTS.LLC_HIT.ANY_RESPONSE",
724        "MSRIndex": "0x1a6,0x1a7",
725        "MSRValue": "0x3F803C8FFF",
726        "SampleAfterValue": "100003",
727        "UMask": "0x1"
728    },
729    {
730        "BriefDescription": "Counts all demand & prefetch RFOs hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",
731        "EventCode": "0xB7, 0xBB",
732        "EventName": "OFFCORE_RESPONSE.ALL_RFO.LLC_HIT.HITM_OTHER_CORE",
733        "MSRIndex": "0x1a6,0x1a7",
734        "MSRValue": "0x10003C0122",
735        "SampleAfterValue": "100003",
736        "UMask": "0x1"
737    },
738    {
739        "BriefDescription": "Counts all demand & prefetch RFOs hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded",
740        "EventCode": "0xB7, 0xBB",
741        "EventName": "OFFCORE_RESPONSE.ALL_RFO.LLC_HIT.HIT_OTHER_CORE_NO_FWD",
742        "MSRIndex": "0x1a6,0x1a7",
743        "MSRValue": "0x4003C0122",
744        "SampleAfterValue": "100003",
745        "UMask": "0x1"
746    },
747    {
748        "BriefDescription": "Counts all demand code reads hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",
749        "EventCode": "0xB7, 0xBB",
750        "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_HIT.HITM_OTHER_CORE",
751        "MSRIndex": "0x1a6,0x1a7",
752        "MSRValue": "0x10003C0004",
753        "SampleAfterValue": "100003",
754        "UMask": "0x1"
755    },
756    {
757        "BriefDescription": "Counts all demand code reads hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded",
758        "EventCode": "0xB7, 0xBB",
759        "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD",
760        "MSRIndex": "0x1a6,0x1a7",
761        "MSRValue": "0x4003C0004",
762        "SampleAfterValue": "100003",
763        "UMask": "0x1"
764    },
765    {
766        "BriefDescription": "Counts demand data reads hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",
767        "EventCode": "0xB7, 0xBB",
768        "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.HITM_OTHER_CORE",
769        "MSRIndex": "0x1a6,0x1a7",
770        "MSRValue": "0x10003C0001",
771        "SampleAfterValue": "100003",
772        "UMask": "0x1"
773    },
774    {
775        "BriefDescription": "Counts demand data reads hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded",
776        "EventCode": "0xB7, 0xBB",
777        "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD",
778        "MSRIndex": "0x1a6,0x1a7",
779        "MSRValue": "0x4003C0001",
780        "SampleAfterValue": "100003",
781        "UMask": "0x1"
782    },
783    {
784        "BriefDescription": "Counts all demand data writes (RFOs) hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",
785        "EventCode": "0xB7, 0xBB",
786        "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT.HITM_OTHER_CORE",
787        "MSRIndex": "0x1a6,0x1a7",
788        "MSRValue": "0x10003C0002",
789        "SampleAfterValue": "100003",
790        "UMask": "0x1"
791    },
792    {
793        "BriefDescription": "Counts all demand data writes (RFOs) hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded",
794        "EventCode": "0xB7, 0xBB",
795        "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT.HIT_OTHER_CORE_NO_FWD",
796        "MSRIndex": "0x1a6,0x1a7",
797        "MSRValue": "0x4003C0002",
798        "SampleAfterValue": "100003",
799        "UMask": "0x1"
800    },
801    {
802        "BriefDescription": "Counts all prefetch (that bring data to LLC only) code reads hit in the L3",
803        "EventCode": "0xB7, 0xBB",
804        "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.LLC_HIT.ANY_RESPONSE",
805        "MSRIndex": "0x1a6,0x1a7",
806        "MSRValue": "0x3F803C0040",
807        "SampleAfterValue": "100003",
808        "UMask": "0x1"
809    },
810    {
811        "BriefDescription": "Counts prefetch (that bring data to L2) data reads hit in the L3",
812        "EventCode": "0xB7, 0xBB",
813        "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_HIT.ANY_RESPONSE",
814        "MSRIndex": "0x1a6,0x1a7",
815        "MSRValue": "0x3F803C0010",
816        "SampleAfterValue": "100003",
817        "UMask": "0x1"
818    },
819    {
820        "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs hit in the L3",
821        "EventCode": "0xB7, 0xBB",
822        "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.LLC_HIT.ANY_RESPONSE",
823        "MSRIndex": "0x1a6,0x1a7",
824        "MSRValue": "0x3F803C0020",
825        "SampleAfterValue": "100003",
826        "UMask": "0x1"
827    },
828    {
829        "BriefDescription": "Counts prefetch (that bring data to LLC only) code reads hit in the L3",
830        "EventCode": "0xB7, 0xBB",
831        "EventName": "OFFCORE_RESPONSE.PF_LLC_CODE_RD.LLC_HIT.ANY_RESPONSE",
832        "MSRIndex": "0x1a6,0x1a7",
833        "MSRValue": "0x3F803C0200",
834        "SampleAfterValue": "100003",
835        "UMask": "0x1"
836    },
837    {
838        "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads hit in the L3",
839        "EventCode": "0xB7, 0xBB",
840        "EventName": "OFFCORE_RESPONSE.PF_LLC_DATA_RD.LLC_HIT.ANY_RESPONSE",
841        "MSRIndex": "0x1a6,0x1a7",
842        "MSRValue": "0x3F803C0080",
843        "SampleAfterValue": "100003",
844        "UMask": "0x1"
845    },
846    {
847        "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs hit in the L3",
848        "EventCode": "0xB7, 0xBB",
849        "EventName": "OFFCORE_RESPONSE.PF_LLC_RFO.LLC_HIT.ANY_RESPONSE",
850        "MSRIndex": "0x1a6,0x1a7",
851        "MSRValue": "0x3F803C0100",
852        "SampleAfterValue": "100003",
853        "UMask": "0x1"
854    },
855    {
856        "BriefDescription": "Split locks in SQ",
857        "EventCode": "0xf4",
858        "EventName": "SQ_MISC.SPLIT_LOCK",
859        "SampleAfterValue": "100003",
860        "UMask": "0x10"
861    }
862]
863