1[ 2 { 3 "BriefDescription": "L1D data line replacements", 4 "Counter": "0,1,2,3", 5 "CounterHTOff": "0,1,2,3,4,5,6,7", 6 "EventCode": "0x51", 7 "EventName": "L1D.REPLACEMENT", 8 "PublicDescription": "This event counts when new data lines are brought into the L1 Data cache, which cause other lines to be evicted from the cache.", 9 "SampleAfterValue": "2000003", 10 "UMask": "0x1" 11 }, 12 { 13 "BriefDescription": "Cycles a demand request was blocked due to Fill Buffers inavailability.", 14 "Counter": "0,1,2,3", 15 "CounterHTOff": "0,1,2,3,4,5,6,7", 16 "CounterMask": "1", 17 "EventCode": "0x48", 18 "EventName": "L1D_PEND_MISS.FB_FULL", 19 "SampleAfterValue": "2000003", 20 "UMask": "0x2" 21 }, 22 { 23 "BriefDescription": "L1D miss outstanding duration in cycles", 24 "Counter": "2", 25 "CounterHTOff": "2", 26 "EventCode": "0x48", 27 "EventName": "L1D_PEND_MISS.PENDING", 28 "PublicDescription": "Increments the number of outstanding L1D misses every cycle. Set Cmask = 1 and Edge =1 to count occurrences.", 29 "SampleAfterValue": "2000003", 30 "UMask": "0x1" 31 }, 32 { 33 "BriefDescription": "Cycles with L1D load Misses outstanding.", 34 "Counter": "2", 35 "CounterHTOff": "2", 36 "CounterMask": "1", 37 "EventCode": "0x48", 38 "EventName": "L1D_PEND_MISS.PENDING_CYCLES", 39 "SampleAfterValue": "2000003", 40 "UMask": "0x1" 41 }, 42 { 43 "AnyThread": "1", 44 "BriefDescription": "Cycles with L1D load Misses outstanding from any thread on physical core.", 45 "Counter": "2", 46 "CounterHTOff": "2", 47 "CounterMask": "1", 48 "EventCode": "0x48", 49 "EventName": "L1D_PEND_MISS.PENDING_CYCLES_ANY", 50 "SampleAfterValue": "2000003", 51 "UMask": "0x1" 52 }, 53 { 54 "BriefDescription": "Number of times a request needed a FB entry but there was no entry available for it. That is the FB unavailability was dominant reason for blocking the request. A request includes cacheable/uncacheable demands that is load, store or SW prefetch. HWP are e.", 55 "Counter": "0,1,2,3", 56 "CounterHTOff": "0,1,2,3,4,5,6,7", 57 "EventCode": "0x48", 58 "EventName": "L1D_PEND_MISS.REQUEST_FB_FULL", 59 "SampleAfterValue": "2000003", 60 "UMask": "0x2" 61 }, 62 { 63 "BriefDescription": "Not rejected writebacks that hit L2 cache", 64 "Counter": "0,1,2,3", 65 "CounterHTOff": "0,1,2,3,4,5,6,7", 66 "EventCode": "0x27", 67 "EventName": "L2_DEMAND_RQSTS.WB_HIT", 68 "PublicDescription": "Not rejected writebacks that hit L2 cache.", 69 "SampleAfterValue": "200003", 70 "UMask": "0x50" 71 }, 72 { 73 "BriefDescription": "L2 cache lines filling L2", 74 "Counter": "0,1,2,3", 75 "CounterHTOff": "0,1,2,3,4,5,6,7", 76 "EventCode": "0xF1", 77 "EventName": "L2_LINES_IN.ALL", 78 "PublicDescription": "This event counts the number of L2 cache lines brought into the L2 cache. Lines are filled into the L2 cache when there was an L2 miss.", 79 "SampleAfterValue": "100003", 80 "UMask": "0x7" 81 }, 82 { 83 "BriefDescription": "L2 cache lines in E state filling L2", 84 "Counter": "0,1,2,3", 85 "CounterHTOff": "0,1,2,3,4,5,6,7", 86 "EventCode": "0xF1", 87 "EventName": "L2_LINES_IN.E", 88 "PublicDescription": "L2 cache lines in E state filling L2.", 89 "SampleAfterValue": "100003", 90 "UMask": "0x4" 91 }, 92 { 93 "BriefDescription": "L2 cache lines in I state filling L2", 94 "Counter": "0,1,2,3", 95 "CounterHTOff": "0,1,2,3,4,5,6,7", 96 "EventCode": "0xF1", 97 "EventName": "L2_LINES_IN.I", 98 "PublicDescription": "L2 cache lines in I state filling L2.", 99 "SampleAfterValue": "100003", 100 "UMask": "0x1" 101 }, 102 { 103 "BriefDescription": "L2 cache lines in S state filling L2", 104 "Counter": "0,1,2,3", 105 "CounterHTOff": "0,1,2,3,4,5,6,7", 106 "EventCode": "0xF1", 107 "EventName": "L2_LINES_IN.S", 108 "PublicDescription": "L2 cache lines in S state filling L2.", 109 "SampleAfterValue": "100003", 110 "UMask": "0x2" 111 }, 112 { 113 "BriefDescription": "Clean L2 cache lines evicted by demand", 114 "Counter": "0,1,2,3", 115 "CounterHTOff": "0,1,2,3,4,5,6,7", 116 "EventCode": "0xF2", 117 "EventName": "L2_LINES_OUT.DEMAND_CLEAN", 118 "PublicDescription": "Clean L2 cache lines evicted by demand.", 119 "SampleAfterValue": "100003", 120 "UMask": "0x5" 121 }, 122 { 123 "BriefDescription": "Dirty L2 cache lines evicted by demand", 124 "Counter": "0,1,2,3", 125 "CounterHTOff": "0,1,2,3,4,5,6,7", 126 "EventCode": "0xF2", 127 "EventName": "L2_LINES_OUT.DEMAND_DIRTY", 128 "PublicDescription": "Dirty L2 cache lines evicted by demand.", 129 "SampleAfterValue": "100003", 130 "UMask": "0x6" 131 }, 132 { 133 "BriefDescription": "L2 code requests", 134 "Counter": "0,1,2,3", 135 "CounterHTOff": "0,1,2,3,4,5,6,7", 136 "EventCode": "0x24", 137 "EventName": "L2_RQSTS.ALL_CODE_RD", 138 "PublicDescription": "Counts all L2 code requests.", 139 "SampleAfterValue": "200003", 140 "UMask": "0xe4" 141 }, 142 { 143 "BriefDescription": "Demand Data Read requests", 144 "Counter": "0,1,2,3", 145 "CounterHTOff": "0,1,2,3,4,5,6,7", 146 "Errata": "HSD78, HSM80", 147 "EventCode": "0x24", 148 "EventName": "L2_RQSTS.ALL_DEMAND_DATA_RD", 149 "PublicDescription": "Counts any demand and L1 HW prefetch data load requests to L2.", 150 "SampleAfterValue": "200003", 151 "UMask": "0xe1" 152 }, 153 { 154 "BriefDescription": "Demand requests that miss L2 cache", 155 "Counter": "0,1,2,3", 156 "CounterHTOff": "0,1,2,3,4,5,6,7", 157 "Errata": "HSD78, HSM80", 158 "EventCode": "0x24", 159 "EventName": "L2_RQSTS.ALL_DEMAND_MISS", 160 "PublicDescription": "Demand requests that miss L2 cache.", 161 "SampleAfterValue": "200003", 162 "UMask": "0x27" 163 }, 164 { 165 "BriefDescription": "Demand requests to L2 cache", 166 "Counter": "0,1,2,3", 167 "CounterHTOff": "0,1,2,3,4,5,6,7", 168 "Errata": "HSD78, HSM80", 169 "EventCode": "0x24", 170 "EventName": "L2_RQSTS.ALL_DEMAND_REFERENCES", 171 "PublicDescription": "Demand requests to L2 cache.", 172 "SampleAfterValue": "200003", 173 "UMask": "0xe7" 174 }, 175 { 176 "BriefDescription": "Requests from L2 hardware prefetchers", 177 "Counter": "0,1,2,3", 178 "CounterHTOff": "0,1,2,3,4,5,6,7", 179 "EventCode": "0x24", 180 "EventName": "L2_RQSTS.ALL_PF", 181 "PublicDescription": "Counts all L2 HW prefetcher requests.", 182 "SampleAfterValue": "200003", 183 "UMask": "0xf8" 184 }, 185 { 186 "BriefDescription": "RFO requests to L2 cache", 187 "Counter": "0,1,2,3", 188 "CounterHTOff": "0,1,2,3,4,5,6,7", 189 "EventCode": "0x24", 190 "EventName": "L2_RQSTS.ALL_RFO", 191 "PublicDescription": "Counts all L2 store RFO requests.", 192 "SampleAfterValue": "200003", 193 "UMask": "0xe2" 194 }, 195 { 196 "BriefDescription": "L2 cache hits when fetching instructions, code reads.", 197 "Counter": "0,1,2,3", 198 "CounterHTOff": "0,1,2,3,4,5,6,7", 199 "EventCode": "0x24", 200 "EventName": "L2_RQSTS.CODE_RD_HIT", 201 "PublicDescription": "Number of instruction fetches that hit the L2 cache.", 202 "SampleAfterValue": "200003", 203 "UMask": "0xc4" 204 }, 205 { 206 "BriefDescription": "L2 cache misses when fetching instructions", 207 "Counter": "0,1,2,3", 208 "CounterHTOff": "0,1,2,3,4,5,6,7", 209 "EventCode": "0x24", 210 "EventName": "L2_RQSTS.CODE_RD_MISS", 211 "PublicDescription": "Number of instruction fetches that missed the L2 cache.", 212 "SampleAfterValue": "200003", 213 "UMask": "0x24" 214 }, 215 { 216 "BriefDescription": "Demand Data Read requests that hit L2 cache", 217 "Counter": "0,1,2,3", 218 "CounterHTOff": "0,1,2,3,4,5,6,7", 219 "Errata": "HSD78, HSM80", 220 "EventCode": "0x24", 221 "EventName": "L2_RQSTS.DEMAND_DATA_RD_HIT", 222 "PublicDescription": "Counts the number of demand Data Read requests, initiated by load instructions, that hit L2 cache", 223 "SampleAfterValue": "200003", 224 "UMask": "0xc1" 225 }, 226 { 227 "BriefDescription": "Demand Data Read miss L2, no rejects", 228 "Counter": "0,1,2,3", 229 "CounterHTOff": "0,1,2,3,4,5,6,7", 230 "Errata": "HSD78, HSM80", 231 "EventCode": "0x24", 232 "EventName": "L2_RQSTS.DEMAND_DATA_RD_MISS", 233 "PublicDescription": "Demand data read requests that missed L2, no rejects.", 234 "SampleAfterValue": "200003", 235 "UMask": "0x21" 236 }, 237 { 238 "BriefDescription": "L2 prefetch requests that hit L2 cache", 239 "Counter": "0,1,2,3", 240 "CounterHTOff": "0,1,2,3,4,5,6,7", 241 "EventCode": "0x24", 242 "EventName": "L2_RQSTS.L2_PF_HIT", 243 "PublicDescription": "Counts all L2 HW prefetcher requests that hit L2.", 244 "SampleAfterValue": "200003", 245 "UMask": "0xd0" 246 }, 247 { 248 "BriefDescription": "L2 prefetch requests that miss L2 cache", 249 "Counter": "0,1,2,3", 250 "CounterHTOff": "0,1,2,3,4,5,6,7", 251 "EventCode": "0x24", 252 "EventName": "L2_RQSTS.L2_PF_MISS", 253 "PublicDescription": "Counts all L2 HW prefetcher requests that missed L2.", 254 "SampleAfterValue": "200003", 255 "UMask": "0x30" 256 }, 257 { 258 "BriefDescription": "All requests that miss L2 cache", 259 "Counter": "0,1,2,3", 260 "CounterHTOff": "0,1,2,3,4,5,6,7", 261 "Errata": "HSD78, HSM80", 262 "EventCode": "0x24", 263 "EventName": "L2_RQSTS.MISS", 264 "PublicDescription": "All requests that missed L2.", 265 "SampleAfterValue": "200003", 266 "UMask": "0x3f" 267 }, 268 { 269 "BriefDescription": "All L2 requests", 270 "Counter": "0,1,2,3", 271 "CounterHTOff": "0,1,2,3,4,5,6,7", 272 "Errata": "HSD78, HSM80", 273 "EventCode": "0x24", 274 "EventName": "L2_RQSTS.REFERENCES", 275 "PublicDescription": "All requests to L2 cache.", 276 "SampleAfterValue": "200003", 277 "UMask": "0xff" 278 }, 279 { 280 "BriefDescription": "RFO requests that hit L2 cache", 281 "Counter": "0,1,2,3", 282 "CounterHTOff": "0,1,2,3,4,5,6,7", 283 "EventCode": "0x24", 284 "EventName": "L2_RQSTS.RFO_HIT", 285 "PublicDescription": "Counts the number of store RFO requests that hit the L2 cache.", 286 "SampleAfterValue": "200003", 287 "UMask": "0xc2" 288 }, 289 { 290 "BriefDescription": "RFO requests that miss L2 cache", 291 "Counter": "0,1,2,3", 292 "CounterHTOff": "0,1,2,3,4,5,6,7", 293 "EventCode": "0x24", 294 "EventName": "L2_RQSTS.RFO_MISS", 295 "PublicDescription": "Counts the number of store RFO requests that miss the L2 cache.", 296 "SampleAfterValue": "200003", 297 "UMask": "0x22" 298 }, 299 { 300 "BriefDescription": "L2 or L3 HW prefetches that access L2 cache", 301 "Counter": "0,1,2,3", 302 "CounterHTOff": "0,1,2,3,4,5,6,7", 303 "EventCode": "0xf0", 304 "EventName": "L2_TRANS.ALL_PF", 305 "PublicDescription": "Any MLC or L3 HW prefetch accessing L2, including rejects.", 306 "SampleAfterValue": "200003", 307 "UMask": "0x8" 308 }, 309 { 310 "BriefDescription": "Transactions accessing L2 pipe", 311 "Counter": "0,1,2,3", 312 "CounterHTOff": "0,1,2,3,4,5,6,7", 313 "EventCode": "0xf0", 314 "EventName": "L2_TRANS.ALL_REQUESTS", 315 "PublicDescription": "Transactions accessing L2 pipe.", 316 "SampleAfterValue": "200003", 317 "UMask": "0x80" 318 }, 319 { 320 "BriefDescription": "L2 cache accesses when fetching instructions", 321 "Counter": "0,1,2,3", 322 "CounterHTOff": "0,1,2,3,4,5,6,7", 323 "EventCode": "0xf0", 324 "EventName": "L2_TRANS.CODE_RD", 325 "PublicDescription": "L2 cache accesses when fetching instructions.", 326 "SampleAfterValue": "200003", 327 "UMask": "0x4" 328 }, 329 { 330 "BriefDescription": "Demand Data Read requests that access L2 cache", 331 "Counter": "0,1,2,3", 332 "CounterHTOff": "0,1,2,3,4,5,6,7", 333 "EventCode": "0xf0", 334 "EventName": "L2_TRANS.DEMAND_DATA_RD", 335 "PublicDescription": "Demand data read requests that access L2 cache.", 336 "SampleAfterValue": "200003", 337 "UMask": "0x1" 338 }, 339 { 340 "BriefDescription": "L1D writebacks that access L2 cache", 341 "Counter": "0,1,2,3", 342 "CounterHTOff": "0,1,2,3,4,5,6,7", 343 "EventCode": "0xf0", 344 "EventName": "L2_TRANS.L1D_WB", 345 "PublicDescription": "L1D writebacks that access L2 cache.", 346 "SampleAfterValue": "200003", 347 "UMask": "0x10" 348 }, 349 { 350 "BriefDescription": "L2 fill requests that access L2 cache", 351 "Counter": "0,1,2,3", 352 "CounterHTOff": "0,1,2,3,4,5,6,7", 353 "EventCode": "0xf0", 354 "EventName": "L2_TRANS.L2_FILL", 355 "PublicDescription": "L2 fill requests that access L2 cache.", 356 "SampleAfterValue": "200003", 357 "UMask": "0x20" 358 }, 359 { 360 "BriefDescription": "L2 writebacks that access L2 cache", 361 "Counter": "0,1,2,3", 362 "CounterHTOff": "0,1,2,3,4,5,6,7", 363 "EventCode": "0xf0", 364 "EventName": "L2_TRANS.L2_WB", 365 "PublicDescription": "L2 writebacks that access L2 cache.", 366 "SampleAfterValue": "200003", 367 "UMask": "0x40" 368 }, 369 { 370 "BriefDescription": "RFO requests that access L2 cache", 371 "Counter": "0,1,2,3", 372 "CounterHTOff": "0,1,2,3,4,5,6,7", 373 "EventCode": "0xf0", 374 "EventName": "L2_TRANS.RFO", 375 "PublicDescription": "RFO requests that access L2 cache.", 376 "SampleAfterValue": "200003", 377 "UMask": "0x2" 378 }, 379 { 380 "BriefDescription": "Cycles when L1D is locked", 381 "Counter": "0,1,2,3", 382 "CounterHTOff": "0,1,2,3,4,5,6,7", 383 "EventCode": "0x63", 384 "EventName": "LOCK_CYCLES.CACHE_LOCK_DURATION", 385 "PublicDescription": "Cycles in which the L1D is locked.", 386 "SampleAfterValue": "2000003", 387 "UMask": "0x2" 388 }, 389 { 390 "BriefDescription": "Core-originated cacheable demand requests missed L3", 391 "Counter": "0,1,2,3", 392 "CounterHTOff": "0,1,2,3,4,5,6,7", 393 "EventCode": "0x2E", 394 "EventName": "LONGEST_LAT_CACHE.MISS", 395 "PublicDescription": "This event counts each cache miss condition for references to the last level cache.", 396 "SampleAfterValue": "100003", 397 "UMask": "0x41" 398 }, 399 { 400 "BriefDescription": "Core-originated cacheable demand requests that refer to L3", 401 "Counter": "0,1,2,3", 402 "CounterHTOff": "0,1,2,3,4,5,6,7", 403 "EventCode": "0x2E", 404 "EventName": "LONGEST_LAT_CACHE.REFERENCE", 405 "PublicDescription": "This event counts requests originating from the core that reference a cache line in the last level cache.", 406 "SampleAfterValue": "100003", 407 "UMask": "0x4f" 408 }, 409 { 410 "BriefDescription": "Retired load uops which data sources were L3 and cross-core snoop hits in on-pkg core cache.", 411 "Counter": "0,1,2,3", 412 "CounterHTOff": "0,1,2,3", 413 "Data_LA": "1", 414 "Errata": "HSD29, HSD25, HSM26, HSM30", 415 "EventCode": "0xD2", 416 "EventName": "MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT", 417 "PEBS": "1", 418 "SampleAfterValue": "20011", 419 "UMask": "0x2" 420 }, 421 { 422 "BriefDescription": "Retired load uops which data sources were HitM responses from shared L3.", 423 "Counter": "0,1,2,3", 424 "CounterHTOff": "0,1,2,3", 425 "Data_LA": "1", 426 "Errata": "HSD29, HSD25, HSM26, HSM30", 427 "EventCode": "0xD2", 428 "EventName": "MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM", 429 "PEBS": "1", 430 "SampleAfterValue": "20011", 431 "UMask": "0x4" 432 }, 433 { 434 "BriefDescription": "Retired load uops which data sources were L3 hit and cross-core snoop missed in on-pkg core cache.", 435 "Counter": "0,1,2,3", 436 "CounterHTOff": "0,1,2,3", 437 "Data_LA": "1", 438 "Errata": "HSD29, HSD25, HSM26, HSM30", 439 "EventCode": "0xD2", 440 "EventName": "MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS", 441 "PEBS": "1", 442 "SampleAfterValue": "20011", 443 "UMask": "0x1" 444 }, 445 { 446 "BriefDescription": "Retired load uops which data sources were hits in L3 without snoops required.", 447 "Counter": "0,1,2,3", 448 "CounterHTOff": "0,1,2,3", 449 "Data_LA": "1", 450 "Errata": "HSD74, HSD29, HSD25, HSM26, HSM30", 451 "EventCode": "0xD2", 452 "EventName": "MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_NONE", 453 "PEBS": "1", 454 "SampleAfterValue": "100003", 455 "UMask": "0x8" 456 }, 457 { 458 "BriefDescription": "Data from local DRAM either Snoop not needed or Snoop Miss (RspI)", 459 "Counter": "0,1,2,3", 460 "CounterHTOff": "0,1,2,3", 461 "Data_LA": "1", 462 "Errata": "HSD74, HSD29, HSD25, HSM30", 463 "EventCode": "0xD3", 464 "EventName": "MEM_LOAD_UOPS_L3_MISS_RETIRED.LOCAL_DRAM", 465 "PEBS": "1", 466 "PublicDescription": "This event counts retired load uops where the data came from local DRAM. This does not include hardware prefetches.", 467 "SampleAfterValue": "100003", 468 "UMask": "0x1" 469 }, 470 { 471 "BriefDescription": "Retired load uop whose Data Source was: remote DRAM either Snoop not needed or Snoop Miss (RspI)", 472 "Counter": "0,1,2,3", 473 "CounterHTOff": "0,1,2,3", 474 "Data_LA": "1", 475 "Errata": "HSD29, HSM30", 476 "EventCode": "0xD3", 477 "EventName": "MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_DRAM", 478 "PEBS": "1", 479 "SampleAfterValue": "100003", 480 "UMask": "0x4" 481 }, 482 { 483 "BriefDescription": "Retired load uop whose Data Source was: forwarded from remote cache", 484 "Counter": "0,1,2,3", 485 "CounterHTOff": "0,1,2,3", 486 "Data_LA": "1", 487 "Errata": "HSM30", 488 "EventCode": "0xD3", 489 "EventName": "MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_FWD", 490 "PEBS": "1", 491 "SampleAfterValue": "100003", 492 "UMask": "0x20" 493 }, 494 { 495 "BriefDescription": "Retired load uop whose Data Source was: Remote cache HITM", 496 "Counter": "0,1,2,3", 497 "CounterHTOff": "0,1,2,3", 498 "Data_LA": "1", 499 "Errata": "HSM30", 500 "EventCode": "0xD3", 501 "EventName": "MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_HITM", 502 "PEBS": "1", 503 "SampleAfterValue": "100003", 504 "UMask": "0x10" 505 }, 506 { 507 "BriefDescription": "Retired load uops which data sources were load uops missed L1 but hit FB due to preceding miss to the same cache line with data not ready.", 508 "Counter": "0,1,2,3", 509 "CounterHTOff": "0,1,2,3", 510 "Data_LA": "1", 511 "Errata": "HSM30", 512 "EventCode": "0xD1", 513 "EventName": "MEM_LOAD_UOPS_RETIRED.HIT_LFB", 514 "PEBS": "1", 515 "SampleAfterValue": "100003", 516 "UMask": "0x40" 517 }, 518 { 519 "BriefDescription": "Retired load uops with L1 cache hits as data sources.", 520 "Counter": "0,1,2,3", 521 "CounterHTOff": "0,1,2,3", 522 "Data_LA": "1", 523 "Errata": "HSD29, HSM30", 524 "EventCode": "0xD1", 525 "EventName": "MEM_LOAD_UOPS_RETIRED.L1_HIT", 526 "PEBS": "1", 527 "SampleAfterValue": "2000003", 528 "UMask": "0x1" 529 }, 530 { 531 "BriefDescription": "Retired load uops misses in L1 cache as data sources.", 532 "Counter": "0,1,2,3", 533 "CounterHTOff": "0,1,2,3", 534 "Data_LA": "1", 535 "Errata": "HSM30", 536 "EventCode": "0xD1", 537 "EventName": "MEM_LOAD_UOPS_RETIRED.L1_MISS", 538 "PEBS": "1", 539 "PublicDescription": "Retired load uops missed L1 cache as data sources.", 540 "SampleAfterValue": "100003", 541 "UMask": "0x8" 542 }, 543 { 544 "BriefDescription": "Retired load uops with L2 cache hits as data sources.", 545 "Counter": "0,1,2,3", 546 "CounterHTOff": "0,1,2,3", 547 "Data_LA": "1", 548 "Errata": "HSD76, HSD29, HSM30", 549 "EventCode": "0xD1", 550 "EventName": "MEM_LOAD_UOPS_RETIRED.L2_HIT", 551 "PEBS": "1", 552 "SampleAfterValue": "100003", 553 "UMask": "0x2" 554 }, 555 { 556 "BriefDescription": "Miss in mid-level (L2) cache. Excludes Unknown data-source.", 557 "Counter": "0,1,2,3", 558 "CounterHTOff": "0,1,2,3", 559 "Data_LA": "1", 560 "Errata": "HSD29, HSM30", 561 "EventCode": "0xD1", 562 "EventName": "MEM_LOAD_UOPS_RETIRED.L2_MISS", 563 "PEBS": "1", 564 "PublicDescription": "Retired load uops missed L2. Unknown data source excluded.", 565 "SampleAfterValue": "50021", 566 "UMask": "0x10" 567 }, 568 { 569 "BriefDescription": "Retired load uops which data sources were data hits in L3 without snoops required.", 570 "Counter": "0,1,2,3", 571 "CounterHTOff": "0,1,2,3", 572 "Data_LA": "1", 573 "Errata": "HSD74, HSD29, HSD25, HSM26, HSM30", 574 "EventCode": "0xD1", 575 "EventName": "MEM_LOAD_UOPS_RETIRED.L3_HIT", 576 "PEBS": "1", 577 "PublicDescription": "Retired load uops with L3 cache hits as data sources.", 578 "SampleAfterValue": "50021", 579 "UMask": "0x4" 580 }, 581 { 582 "BriefDescription": "Miss in last-level (L3) cache. Excludes Unknown data-source.", 583 "Counter": "0,1,2,3", 584 "CounterHTOff": "0,1,2,3", 585 "Data_LA": "1", 586 "Errata": "HSD74, HSD29, HSD25, HSM26, HSM30", 587 "EventCode": "0xD1", 588 "EventName": "MEM_LOAD_UOPS_RETIRED.L3_MISS", 589 "PEBS": "1", 590 "PublicDescription": "Retired load uops missed L3. Excludes unknown data source .", 591 "SampleAfterValue": "100003", 592 "UMask": "0x20" 593 }, 594 { 595 "BriefDescription": "Retired load uops.", 596 "Counter": "0,1,2,3", 597 "CounterHTOff": "0,1,2,3", 598 "Data_LA": "1", 599 "Errata": "HSD29, HSM30", 600 "EventCode": "0xD0", 601 "EventName": "MEM_UOPS_RETIRED.ALL_LOADS", 602 "PEBS": "1", 603 "PublicDescription": "Counts all retired load uops. This event accounts for SW prefetch uops of PREFETCHNTA or PREFETCHT0/1/2 or PREFETCHW.", 604 "SampleAfterValue": "2000003", 605 "UMask": "0x81" 606 }, 607 { 608 "BriefDescription": "Retired store uops.", 609 "Counter": "0,1,2,3", 610 "CounterHTOff": "0,1,2,3", 611 "Data_LA": "1", 612 "Errata": "HSD29, HSM30", 613 "EventCode": "0xD0", 614 "EventName": "MEM_UOPS_RETIRED.ALL_STORES", 615 "L1_Hit_Indication": "1", 616 "PEBS": "1", 617 "PublicDescription": "Counts all retired store uops.", 618 "SampleAfterValue": "2000003", 619 "UMask": "0x82" 620 }, 621 { 622 "BriefDescription": "Retired load uops with locked access.", 623 "Counter": "0,1,2,3", 624 "CounterHTOff": "0,1,2,3", 625 "Data_LA": "1", 626 "Errata": "HSD76, HSD29, HSM30", 627 "EventCode": "0xD0", 628 "EventName": "MEM_UOPS_RETIRED.LOCK_LOADS", 629 "PEBS": "1", 630 "SampleAfterValue": "100003", 631 "UMask": "0x21" 632 }, 633 { 634 "BriefDescription": "Retired load uops that split across a cacheline boundary.", 635 "Counter": "0,1,2,3", 636 "CounterHTOff": "0,1,2,3", 637 "Data_LA": "1", 638 "Errata": "HSD29, HSM30", 639 "EventCode": "0xD0", 640 "EventName": "MEM_UOPS_RETIRED.SPLIT_LOADS", 641 "PEBS": "1", 642 "SampleAfterValue": "100003", 643 "UMask": "0x41" 644 }, 645 { 646 "BriefDescription": "Retired store uops that split across a cacheline boundary.", 647 "Counter": "0,1,2,3", 648 "CounterHTOff": "0,1,2,3", 649 "Data_LA": "1", 650 "Errata": "HSD29, HSM30", 651 "EventCode": "0xD0", 652 "EventName": "MEM_UOPS_RETIRED.SPLIT_STORES", 653 "L1_Hit_Indication": "1", 654 "PEBS": "1", 655 "SampleAfterValue": "100003", 656 "UMask": "0x42" 657 }, 658 { 659 "BriefDescription": "Retired load uops that miss the STLB.", 660 "Counter": "0,1,2,3", 661 "CounterHTOff": "0,1,2,3", 662 "Data_LA": "1", 663 "Errata": "HSD29, HSM30", 664 "EventCode": "0xD0", 665 "EventName": "MEM_UOPS_RETIRED.STLB_MISS_LOADS", 666 "PEBS": "1", 667 "SampleAfterValue": "100003", 668 "UMask": "0x11" 669 }, 670 { 671 "BriefDescription": "Retired store uops that miss the STLB.", 672 "Counter": "0,1,2,3", 673 "CounterHTOff": "0,1,2,3", 674 "Data_LA": "1", 675 "Errata": "HSD29, HSM30", 676 "EventCode": "0xD0", 677 "EventName": "MEM_UOPS_RETIRED.STLB_MISS_STORES", 678 "L1_Hit_Indication": "1", 679 "PEBS": "1", 680 "SampleAfterValue": "100003", 681 "UMask": "0x12" 682 }, 683 { 684 "BriefDescription": "Demand and prefetch data reads", 685 "Counter": "0,1,2,3", 686 "CounterHTOff": "0,1,2,3,4,5,6,7", 687 "EventCode": "0xB0", 688 "EventName": "OFFCORE_REQUESTS.ALL_DATA_RD", 689 "PublicDescription": "Data read requests sent to uncore (demand and prefetch).", 690 "SampleAfterValue": "100003", 691 "UMask": "0x8" 692 }, 693 { 694 "BriefDescription": "Cacheable and noncachaeble code read requests", 695 "Counter": "0,1,2,3", 696 "CounterHTOff": "0,1,2,3,4,5,6,7", 697 "EventCode": "0xB0", 698 "EventName": "OFFCORE_REQUESTS.DEMAND_CODE_RD", 699 "PublicDescription": "Demand code read requests sent to uncore.", 700 "SampleAfterValue": "100003", 701 "UMask": "0x2" 702 }, 703 { 704 "BriefDescription": "Demand Data Read requests sent to uncore", 705 "Counter": "0,1,2,3", 706 "CounterHTOff": "0,1,2,3,4,5,6,7", 707 "Errata": "HSD78, HSM80", 708 "EventCode": "0xb0", 709 "EventName": "OFFCORE_REQUESTS.DEMAND_DATA_RD", 710 "PublicDescription": "Demand data read requests sent to uncore.", 711 "SampleAfterValue": "100003", 712 "UMask": "0x1" 713 }, 714 { 715 "BriefDescription": "Demand RFO requests including regular RFOs, locks, ItoM", 716 "Counter": "0,1,2,3", 717 "CounterHTOff": "0,1,2,3,4,5,6,7", 718 "EventCode": "0xB0", 719 "EventName": "OFFCORE_REQUESTS.DEMAND_RFO", 720 "PublicDescription": "Demand RFO read requests sent to uncore, including regular RFOs, locks, ItoM.", 721 "SampleAfterValue": "100003", 722 "UMask": "0x4" 723 }, 724 { 725 "BriefDescription": "Offcore requests buffer cannot take more entries for this thread core.", 726 "Counter": "0,1,2,3", 727 "CounterHTOff": "0,1,2,3,4,5,6,7", 728 "EventCode": "0xb2", 729 "EventName": "OFFCORE_REQUESTS_BUFFER.SQ_FULL", 730 "SampleAfterValue": "2000003", 731 "UMask": "0x1" 732 }, 733 { 734 "BriefDescription": "Offcore outstanding cacheable Core Data Read transactions in SuperQueue (SQ), queue to uncore", 735 "Counter": "0,1,2,3", 736 "CounterHTOff": "0,1,2,3,4,5,6,7", 737 "Errata": "HSD62, HSD61, HSM63", 738 "EventCode": "0x60", 739 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD", 740 "PublicDescription": "Offcore outstanding cacheable data read transactions in SQ to uncore. Set Cmask=1 to count cycles.", 741 "SampleAfterValue": "2000003", 742 "UMask": "0x8" 743 }, 744 { 745 "BriefDescription": "Cycles when offcore outstanding cacheable Core Data Read transactions are present in SuperQueue (SQ), queue to uncore.", 746 "Counter": "0,1,2,3", 747 "CounterHTOff": "0,1,2,3,4,5,6,7", 748 "CounterMask": "1", 749 "Errata": "HSD62, HSD61, HSM63", 750 "EventCode": "0x60", 751 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD", 752 "SampleAfterValue": "2000003", 753 "UMask": "0x8" 754 }, 755 { 756 "BriefDescription": "Cycles when offcore outstanding Demand Data Read transactions are present in SuperQueue (SQ), queue to uncore.", 757 "Counter": "0,1,2,3", 758 "CounterHTOff": "0,1,2,3,4,5,6,7", 759 "CounterMask": "1", 760 "Errata": "HSD78, HSD62, HSD61, HSM63, HSM80", 761 "EventCode": "0x60", 762 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_DATA_RD", 763 "SampleAfterValue": "2000003", 764 "UMask": "0x1" 765 }, 766 { 767 "BriefDescription": "Offcore outstanding demand rfo reads transactions in SuperQueue (SQ), queue to uncore, every cycle.", 768 "Counter": "0,1,2,3", 769 "CounterHTOff": "0,1,2,3,4,5,6,7", 770 "CounterMask": "1", 771 "Errata": "HSD62, HSD61, HSM63", 772 "EventCode": "0x60", 773 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO", 774 "SampleAfterValue": "2000003", 775 "UMask": "0x4" 776 }, 777 { 778 "BriefDescription": "Offcore outstanding code reads transactions in SuperQueue (SQ), queue to uncore, every cycle", 779 "Counter": "0,1,2,3", 780 "CounterHTOff": "0,1,2,3,4,5,6,7", 781 "Errata": "HSD62, HSD61, HSM63", 782 "EventCode": "0x60", 783 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_CODE_RD", 784 "PublicDescription": "Offcore outstanding Demand code Read transactions in SQ to uncore. Set Cmask=1 to count cycles.", 785 "SampleAfterValue": "2000003", 786 "UMask": "0x2" 787 }, 788 { 789 "BriefDescription": "Offcore outstanding Demand Data Read transactions in uncore queue.", 790 "Counter": "0,1,2,3", 791 "CounterHTOff": "0,1,2,3,4,5,6,7", 792 "Errata": "HSD78, HSD62, HSD61, HSM63, HSM80", 793 "EventCode": "0x60", 794 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD", 795 "PublicDescription": "Offcore outstanding demand data read transactions in SQ to uncore. Set Cmask=1 to count cycles.", 796 "SampleAfterValue": "2000003", 797 "UMask": "0x1" 798 }, 799 { 800 "BriefDescription": "Cycles with at least 6 offcore outstanding Demand Data Read transactions in uncore queue.", 801 "Counter": "0,1,2,3", 802 "CounterHTOff": "0,1,2,3,4,5,6,7", 803 "CounterMask": "6", 804 "Errata": "HSD78, HSD62, HSD61, HSM63, HSM80", 805 "EventCode": "0x60", 806 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD_GE_6", 807 "SampleAfterValue": "2000003", 808 "UMask": "0x1" 809 }, 810 { 811 "BriefDescription": "Offcore outstanding RFO store transactions in SuperQueue (SQ), queue to uncore", 812 "Counter": "0,1,2,3", 813 "CounterHTOff": "0,1,2,3,4,5,6,7", 814 "Errata": "HSD62, HSD61, HSM63", 815 "EventCode": "0x60", 816 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_RFO", 817 "PublicDescription": "Offcore outstanding RFO store transactions in SQ to uncore. Set Cmask=1 to count cycles.", 818 "SampleAfterValue": "2000003", 819 "UMask": "0x4" 820 }, 821 { 822 "BriefDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 823 "Counter": "0,1,2,3", 824 "CounterHTOff": "0,1,2,3", 825 "EventCode": "0xB7, 0xBB", 826 "EventName": "OFFCORE_RESPONSE", 827 "SampleAfterValue": "100003", 828 "UMask": "0x1" 829 }, 830 { 831 "BriefDescription": "Counts all demand & prefetch code reads hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded", 832 "Counter": "0,1,2,3", 833 "CounterHTOff": "0,1,2,3", 834 "EventCode": "0xB7, 0xBB", 835 "EventName": "OFFCORE_RESPONSE.ALL_CODE_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD", 836 "MSRIndex": "0x1a6,0x1a7", 837 "MSRValue": "0x4003C0244", 838 "Offcore": "1", 839 "SampleAfterValue": "100003", 840 "UMask": "0x1" 841 }, 842 { 843 "BriefDescription": "Counts all demand & prefetch data reads hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded", 844 "Counter": "0,1,2,3", 845 "CounterHTOff": "0,1,2,3", 846 "EventCode": "0xB7, 0xBB", 847 "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.HITM_OTHER_CORE", 848 "MSRIndex": "0x1a6,0x1a7", 849 "MSRValue": "0x10003C0091", 850 "Offcore": "1", 851 "SampleAfterValue": "100003", 852 "UMask": "0x1" 853 }, 854 { 855 "BriefDescription": "Counts all demand & prefetch data reads hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded", 856 "Counter": "0,1,2,3", 857 "CounterHTOff": "0,1,2,3", 858 "EventCode": "0xB7, 0xBB", 859 "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD", 860 "MSRIndex": "0x1a6,0x1a7", 861 "MSRValue": "0x4003C0091", 862 "Offcore": "1", 863 "SampleAfterValue": "100003", 864 "UMask": "0x1" 865 }, 866 { 867 "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded", 868 "Counter": "0,1,2,3", 869 "CounterHTOff": "0,1,2,3", 870 "EventCode": "0xB7, 0xBB", 871 "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_HIT.HITM_OTHER_CORE", 872 "MSRIndex": "0x1a6,0x1a7", 873 "MSRValue": "0x10003C07F7", 874 "Offcore": "1", 875 "SampleAfterValue": "100003", 876 "UMask": "0x1" 877 }, 878 { 879 "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded", 880 "Counter": "0,1,2,3", 881 "CounterHTOff": "0,1,2,3", 882 "EventCode": "0xB7, 0xBB", 883 "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_HIT.HIT_OTHER_CORE_NO_FWD", 884 "MSRIndex": "0x1a6,0x1a7", 885 "MSRValue": "0x4003C07F7", 886 "Offcore": "1", 887 "SampleAfterValue": "100003", 888 "UMask": "0x1" 889 }, 890 { 891 "BriefDescription": "Counts all requests hit in the L3", 892 "Counter": "0,1,2,3", 893 "CounterHTOff": "0,1,2,3", 894 "EventCode": "0xB7, 0xBB", 895 "EventName": "OFFCORE_RESPONSE.ALL_REQUESTS.LLC_HIT.ANY_RESPONSE", 896 "MSRIndex": "0x1a6,0x1a7", 897 "MSRValue": "0x3F803C8FFF", 898 "Offcore": "1", 899 "SampleAfterValue": "100003", 900 "UMask": "0x1" 901 }, 902 { 903 "BriefDescription": "Counts all demand & prefetch RFOs hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded", 904 "Counter": "0,1,2,3", 905 "CounterHTOff": "0,1,2,3", 906 "EventCode": "0xB7, 0xBB", 907 "EventName": "OFFCORE_RESPONSE.ALL_RFO.LLC_HIT.HITM_OTHER_CORE", 908 "MSRIndex": "0x1a6,0x1a7", 909 "MSRValue": "0x10003C0122", 910 "Offcore": "1", 911 "SampleAfterValue": "100003", 912 "UMask": "0x1" 913 }, 914 { 915 "BriefDescription": "Counts all demand & prefetch RFOs hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded", 916 "Counter": "0,1,2,3", 917 "CounterHTOff": "0,1,2,3", 918 "EventCode": "0xB7, 0xBB", 919 "EventName": "OFFCORE_RESPONSE.ALL_RFO.LLC_HIT.HIT_OTHER_CORE_NO_FWD", 920 "MSRIndex": "0x1a6,0x1a7", 921 "MSRValue": "0x4003C0122", 922 "Offcore": "1", 923 "SampleAfterValue": "100003", 924 "UMask": "0x1" 925 }, 926 { 927 "BriefDescription": "Counts all demand code reads hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded", 928 "Counter": "0,1,2,3", 929 "CounterHTOff": "0,1,2,3", 930 "EventCode": "0xB7, 0xBB", 931 "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_HIT.HITM_OTHER_CORE", 932 "MSRIndex": "0x1a6,0x1a7", 933 "MSRValue": "0x10003C0004", 934 "Offcore": "1", 935 "SampleAfterValue": "100003", 936 "UMask": "0x1" 937 }, 938 { 939 "BriefDescription": "Counts all demand code reads hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded", 940 "Counter": "0,1,2,3", 941 "CounterHTOff": "0,1,2,3", 942 "EventCode": "0xB7, 0xBB", 943 "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD", 944 "MSRIndex": "0x1a6,0x1a7", 945 "MSRValue": "0x4003C0004", 946 "Offcore": "1", 947 "SampleAfterValue": "100003", 948 "UMask": "0x1" 949 }, 950 { 951 "BriefDescription": "Counts demand data reads hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded", 952 "Counter": "0,1,2,3", 953 "CounterHTOff": "0,1,2,3", 954 "EventCode": "0xB7, 0xBB", 955 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.HITM_OTHER_CORE", 956 "MSRIndex": "0x1a6,0x1a7", 957 "MSRValue": "0x10003C0001", 958 "Offcore": "1", 959 "SampleAfterValue": "100003", 960 "UMask": "0x1" 961 }, 962 { 963 "BriefDescription": "Counts demand data reads hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded", 964 "Counter": "0,1,2,3", 965 "CounterHTOff": "0,1,2,3", 966 "EventCode": "0xB7, 0xBB", 967 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD", 968 "MSRIndex": "0x1a6,0x1a7", 969 "MSRValue": "0x4003C0001", 970 "Offcore": "1", 971 "SampleAfterValue": "100003", 972 "UMask": "0x1" 973 }, 974 { 975 "BriefDescription": "Counts all demand data writes (RFOs) hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded", 976 "Counter": "0,1,2,3", 977 "CounterHTOff": "0,1,2,3", 978 "EventCode": "0xB7, 0xBB", 979 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT.HITM_OTHER_CORE", 980 "MSRIndex": "0x1a6,0x1a7", 981 "MSRValue": "0x10003C0002", 982 "Offcore": "1", 983 "SampleAfterValue": "100003", 984 "UMask": "0x1" 985 }, 986 { 987 "BriefDescription": "Counts all demand data writes (RFOs) hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded", 988 "Counter": "0,1,2,3", 989 "CounterHTOff": "0,1,2,3", 990 "EventCode": "0xB7, 0xBB", 991 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT.HIT_OTHER_CORE_NO_FWD", 992 "MSRIndex": "0x1a6,0x1a7", 993 "MSRValue": "0x4003C0002", 994 "Offcore": "1", 995 "SampleAfterValue": "100003", 996 "UMask": "0x1" 997 }, 998 { 999 "BriefDescription": "Counts all prefetch (that bring data to LLC only) code reads hit in the L3", 1000 "Counter": "0,1,2,3", 1001 "CounterHTOff": "0,1,2,3", 1002 "EventCode": "0xB7, 0xBB", 1003 "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.LLC_HIT.ANY_RESPONSE", 1004 "MSRIndex": "0x1a6,0x1a7", 1005 "MSRValue": "0x3F803C0040", 1006 "Offcore": "1", 1007 "SampleAfterValue": "100003", 1008 "UMask": "0x1" 1009 }, 1010 { 1011 "BriefDescription": "Counts prefetch (that bring data to L2) data reads hit in the L3", 1012 "Counter": "0,1,2,3", 1013 "CounterHTOff": "0,1,2,3", 1014 "EventCode": "0xB7, 0xBB", 1015 "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_HIT.ANY_RESPONSE", 1016 "MSRIndex": "0x1a6,0x1a7", 1017 "MSRValue": "0x3F803C0010", 1018 "Offcore": "1", 1019 "SampleAfterValue": "100003", 1020 "UMask": "0x1" 1021 }, 1022 { 1023 "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs hit in the L3", 1024 "Counter": "0,1,2,3", 1025 "CounterHTOff": "0,1,2,3", 1026 "EventCode": "0xB7, 0xBB", 1027 "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.LLC_HIT.ANY_RESPONSE", 1028 "MSRIndex": "0x1a6,0x1a7", 1029 "MSRValue": "0x3F803C0020", 1030 "Offcore": "1", 1031 "SampleAfterValue": "100003", 1032 "UMask": "0x1" 1033 }, 1034 { 1035 "BriefDescription": "Counts prefetch (that bring data to LLC only) code reads hit in the L3", 1036 "Counter": "0,1,2,3", 1037 "CounterHTOff": "0,1,2,3", 1038 "EventCode": "0xB7, 0xBB", 1039 "EventName": "OFFCORE_RESPONSE.PF_LLC_CODE_RD.LLC_HIT.ANY_RESPONSE", 1040 "MSRIndex": "0x1a6,0x1a7", 1041 "MSRValue": "0x3F803C0200", 1042 "Offcore": "1", 1043 "SampleAfterValue": "100003", 1044 "UMask": "0x1" 1045 }, 1046 { 1047 "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads hit in the L3", 1048 "Counter": "0,1,2,3", 1049 "CounterHTOff": "0,1,2,3", 1050 "EventCode": "0xB7, 0xBB", 1051 "EventName": "OFFCORE_RESPONSE.PF_LLC_DATA_RD.LLC_HIT.ANY_RESPONSE", 1052 "MSRIndex": "0x1a6,0x1a7", 1053 "MSRValue": "0x3F803C0080", 1054 "Offcore": "1", 1055 "SampleAfterValue": "100003", 1056 "UMask": "0x1" 1057 }, 1058 { 1059 "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs hit in the L3", 1060 "Counter": "0,1,2,3", 1061 "CounterHTOff": "0,1,2,3", 1062 "EventCode": "0xB7, 0xBB", 1063 "EventName": "OFFCORE_RESPONSE.PF_LLC_RFO.LLC_HIT.ANY_RESPONSE", 1064 "MSRIndex": "0x1a6,0x1a7", 1065 "MSRValue": "0x3F803C0100", 1066 "Offcore": "1", 1067 "SampleAfterValue": "100003", 1068 "UMask": "0x1" 1069 }, 1070 { 1071 "BriefDescription": "Split locks in SQ", 1072 "Counter": "0,1,2,3", 1073 "CounterHTOff": "0,1,2,3,4,5,6,7", 1074 "EventCode": "0xf4", 1075 "EventName": "SQ_MISC.SPLIT_LOCK", 1076 "SampleAfterValue": "100003", 1077 "UMask": "0x10" 1078 } 1079] 1080