1*6910f7baSIan Rogers[ 2*6910f7baSIan Rogers { 3*6910f7baSIan Rogers "BriefDescription": "Each cycle count number of valid entries in Coherency Tracker queue from allocation till deallocation. Aperture requests (snoops) appear as NC decoded internally and become coherent (snoop L3, access memory)", 4*6910f7baSIan Rogers "EventCode": "0x83", 5*6910f7baSIan Rogers "EventName": "UNC_ARB_COH_TRK_OCCUPANCY.All", 6*6910f7baSIan Rogers "PerPkg": "1", 7*6910f7baSIan Rogers "PublicDescription": "Each cycle count number of valid entries in Coherency Tracker queue from allocation till deallocation. Aperture requests (snoops) appear as NC decoded internally and become coherent (snoop L3, access memory).", 8*6910f7baSIan Rogers "UMask": "0x1", 9*6910f7baSIan Rogers "Unit": "ARB" 10*6910f7baSIan Rogers }, 11*6910f7baSIan Rogers { 12*6910f7baSIan Rogers "BriefDescription": "Number of entries allocated. Account for Any type: e.g. Snoop, Core aperture, etc.", 13*6910f7baSIan Rogers "EventCode": "0x84", 14*6910f7baSIan Rogers "EventName": "UNC_ARB_COH_TRK_REQUESTS.ALL", 15*6910f7baSIan Rogers "PerPkg": "1", 16*6910f7baSIan Rogers "UMask": "0x1", 17*6910f7baSIan Rogers "Unit": "ARB" 18*6910f7baSIan Rogers }, 19*6910f7baSIan Rogers { 20*6910f7baSIan Rogers "BriefDescription": "Each cycle counts number of all Core outgoing valid entries. Such entry is defined as valid from its allocation till first of IDI0 or DRS0 messages is sent out. Accounts for Coherent and non-coherent traffic.", 21*6910f7baSIan Rogers "EventCode": "0x80", 22*6910f7baSIan Rogers "EventName": "UNC_ARB_TRK_OCCUPANCY.ALL", 23*6910f7baSIan Rogers "PerPkg": "1", 24*6910f7baSIan Rogers "UMask": "0x1", 25*6910f7baSIan Rogers "Unit": "ARB" 26*6910f7baSIan Rogers }, 27*6910f7baSIan Rogers { 28*6910f7baSIan Rogers "BriefDescription": "Cycles with at least one request outstanding is waiting for data return from memory controller. Account for coherent and non-coherent requests initiated by IA Cores, Processor Graphics Unit, or LLC.", 29*6910f7baSIan Rogers "CounterMask": "1", 30*6910f7baSIan Rogers "EventCode": "0x80", 31*6910f7baSIan Rogers "EventName": "UNC_ARB_TRK_OCCUPANCY.CYCLES_WITH_ANY_REQUEST", 32*6910f7baSIan Rogers "PerPkg": "1", 33*6910f7baSIan Rogers "UMask": "0x1", 34*6910f7baSIan Rogers "Unit": "ARB" 35*6910f7baSIan Rogers }, 36*6910f7baSIan Rogers { 37*6910f7baSIan Rogers "BriefDescription": "Total number of Core outgoing entries allocated. Accounts for Coherent and non-coherent traffic.", 38*6910f7baSIan Rogers "EventCode": "0x81", 39*6910f7baSIan Rogers "EventName": "UNC_ARB_TRK_REQUESTS.ALL", 40*6910f7baSIan Rogers "PerPkg": "1", 41*6910f7baSIan Rogers "UMask": "0x1", 42*6910f7baSIan Rogers "Unit": "ARB" 43*6910f7baSIan Rogers }, 44*6910f7baSIan Rogers { 45*6910f7baSIan Rogers "BriefDescription": "Number of Writes allocated - any write transactions: full/partials writes and evictions.", 46*6910f7baSIan Rogers "EventCode": "0x81", 47*6910f7baSIan Rogers "EventName": "UNC_ARB_TRK_REQUESTS.WRITES", 48*6910f7baSIan Rogers "PerPkg": "1", 49*6910f7baSIan Rogers "UMask": "0x20", 50*6910f7baSIan Rogers "Unit": "ARB" 51*6910f7baSIan Rogers } 52*6910f7baSIan Rogers] 53