1[
2    {
3        "BriefDescription": "Unhalted core cycles when the thread is in ring 0",
4        "EventCode": "0x5C",
5        "EventName": "CPL_CYCLES.RING0",
6        "PublicDescription": "Unhalted core cycles when the thread is in ring 0.",
7        "SampleAfterValue": "2000003",
8        "UMask": "0x1"
9    },
10    {
11        "BriefDescription": "Number of intervals between processor halts while thread is in ring 0.",
12        "CounterMask": "1",
13        "EdgeDetect": "1",
14        "EventCode": "0x5C",
15        "EventName": "CPL_CYCLES.RING0_TRANS",
16        "SampleAfterValue": "100003",
17        "UMask": "0x1"
18    },
19    {
20        "BriefDescription": "Unhalted core cycles when thread is in rings 1, 2, or 3",
21        "EventCode": "0x5C",
22        "EventName": "CPL_CYCLES.RING123",
23        "PublicDescription": "Unhalted core cycles when the thread is not in ring 0.",
24        "SampleAfterValue": "2000003",
25        "UMask": "0x2"
26    },
27    {
28        "BriefDescription": "Cycles when L1 and L2 are locked due to UC or split lock",
29        "EventCode": "0x63",
30        "EventName": "LOCK_CYCLES.SPLIT_LOCK_UC_LOCK_DURATION",
31        "PublicDescription": "Cycles in which the L1D and L2 are locked, due to a UC lock or split lock.",
32        "SampleAfterValue": "2000003",
33        "UMask": "0x1"
34    }
35]
36