1[
2    {
3        "PublicDescription": "Unhalted core cycles when the thread is in ring 0.",
4        "EventCode": "0x5C",
5        "Counter": "0,1,2,3",
6        "UMask": "0x1",
7        "EventName": "CPL_CYCLES.RING0",
8        "SampleAfterValue": "2000003",
9        "BriefDescription": "Unhalted core cycles when the thread is in ring 0",
10        "CounterHTOff": "0,1,2,3,4,5,6,7"
11    },
12    {
13        "EventCode": "0x5C",
14        "Counter": "0,1,2,3",
15        "UMask": "0x1",
16        "EdgeDetect": "1",
17        "EventName": "CPL_CYCLES.RING0_TRANS",
18        "SampleAfterValue": "100003",
19        "BriefDescription": "Number of intervals between processor halts while thread is in ring 0.",
20        "CounterMask": "1",
21        "CounterHTOff": "0,1,2,3,4,5,6,7"
22    },
23    {
24        "PublicDescription": "Unhalted core cycles when the thread is not in ring 0.",
25        "EventCode": "0x5C",
26        "Counter": "0,1,2,3",
27        "UMask": "0x2",
28        "EventName": "CPL_CYCLES.RING123",
29        "SampleAfterValue": "2000003",
30        "BriefDescription": "Unhalted core cycles when thread is in rings 1, 2, or 3",
31        "CounterHTOff": "0,1,2,3,4,5,6,7"
32    },
33    {
34        "PublicDescription": "Cycles in which the L1D and L2 are locked, due to a UC lock or split lock.",
35        "EventCode": "0x63",
36        "Counter": "0,1,2,3",
37        "UMask": "0x1",
38        "EventName": "LOCK_CYCLES.SPLIT_LOCK_UC_LOCK_DURATION",
39        "SampleAfterValue": "2000003",
40        "BriefDescription": "Cycles when L1 and L2 are locked due to UC or split lock",
41        "CounterHTOff": "0,1,2,3,4,5,6,7"
42    }
43]