1[
2    {
3        "BriefDescription": "Unhalted core cycles when the thread is in ring 0",
4        "Counter": "0,1,2,3",
5        "CounterHTOff": "0,1,2,3,4,5,6,7",
6        "EventCode": "0x5C",
7        "EventName": "CPL_CYCLES.RING0",
8        "PublicDescription": "Unhalted core cycles when the thread is in ring 0.",
9        "SampleAfterValue": "2000003",
10        "UMask": "0x1"
11    },
12    {
13        "BriefDescription": "Number of intervals between processor halts while thread is in ring 0.",
14        "Counter": "0,1,2,3",
15        "CounterHTOff": "0,1,2,3,4,5,6,7",
16        "CounterMask": "1",
17        "EdgeDetect": "1",
18        "EventCode": "0x5C",
19        "EventName": "CPL_CYCLES.RING0_TRANS",
20        "SampleAfterValue": "100003",
21        "UMask": "0x1"
22    },
23    {
24        "BriefDescription": "Unhalted core cycles when thread is in rings 1, 2, or 3",
25        "Counter": "0,1,2,3",
26        "CounterHTOff": "0,1,2,3,4,5,6,7",
27        "EventCode": "0x5C",
28        "EventName": "CPL_CYCLES.RING123",
29        "PublicDescription": "Unhalted core cycles when the thread is not in ring 0.",
30        "SampleAfterValue": "2000003",
31        "UMask": "0x2"
32    },
33    {
34        "BriefDescription": "Cycles when L1 and L2 are locked due to UC or split lock",
35        "Counter": "0,1,2,3",
36        "CounterHTOff": "0,1,2,3,4,5,6,7",
37        "EventCode": "0x63",
38        "EventName": "LOCK_CYCLES.SPLIT_LOCK_UC_LOCK_DURATION",
39        "PublicDescription": "Cycles in which the L1D and L2 are locked, due to a UC lock or split lock.",
40        "SampleAfterValue": "2000003",
41        "UMask": "0x1"
42    }
43]