1dcfbad10SAndi Kleen[ 2dcfbad10SAndi Kleen { 3dcfbad10SAndi Kleen "BriefDescription": "Unhalted core cycles when the thread is in ring 0", 4*4dd25272SIan Rogers "Counter": "0,1,2,3", 5*4dd25272SIan Rogers "CounterHTOff": "0,1,2,3,4,5,6,7", 6*4dd25272SIan Rogers "EventCode": "0x5C", 7*4dd25272SIan Rogers "EventName": "CPL_CYCLES.RING0", 8*4dd25272SIan Rogers "PublicDescription": "Unhalted core cycles when the thread is in ring 0.", 9*4dd25272SIan Rogers "SampleAfterValue": "2000003", 10*4dd25272SIan Rogers "UMask": "0x1" 11dcfbad10SAndi Kleen }, 12dcfbad10SAndi Kleen { 13*4dd25272SIan Rogers "BriefDescription": "Number of intervals between processor halts while thread is in ring 0.", 14dcfbad10SAndi Kleen "Counter": "0,1,2,3", 15*4dd25272SIan Rogers "CounterHTOff": "0,1,2,3,4,5,6,7", 16*4dd25272SIan Rogers "CounterMask": "1", 17dcfbad10SAndi Kleen "EdgeDetect": "1", 18*4dd25272SIan Rogers "EventCode": "0x5C", 19dcfbad10SAndi Kleen "EventName": "CPL_CYCLES.RING0_TRANS", 20dcfbad10SAndi Kleen "SampleAfterValue": "100003", 21*4dd25272SIan Rogers "UMask": "0x1" 22dcfbad10SAndi Kleen }, 23dcfbad10SAndi Kleen { 24ca3a2d05SAndi Kleen "BriefDescription": "Unhalted core cycles when thread is in rings 1, 2, or 3", 25*4dd25272SIan Rogers "Counter": "0,1,2,3", 26*4dd25272SIan Rogers "CounterHTOff": "0,1,2,3,4,5,6,7", 27*4dd25272SIan Rogers "EventCode": "0x5C", 28*4dd25272SIan Rogers "EventName": "CPL_CYCLES.RING123", 29*4dd25272SIan Rogers "PublicDescription": "Unhalted core cycles when the thread is not in ring 0.", 30*4dd25272SIan Rogers "SampleAfterValue": "2000003", 31*4dd25272SIan Rogers "UMask": "0x2" 32ca3a2d05SAndi Kleen }, 33ca3a2d05SAndi Kleen { 34dcfbad10SAndi Kleen "BriefDescription": "Cycles when L1 and L2 are locked due to UC or split lock", 35*4dd25272SIan Rogers "Counter": "0,1,2,3", 36*4dd25272SIan Rogers "CounterHTOff": "0,1,2,3,4,5,6,7", 37*4dd25272SIan Rogers "EventCode": "0x63", 38*4dd25272SIan Rogers "EventName": "LOCK_CYCLES.SPLIT_LOCK_UC_LOCK_DURATION", 39*4dd25272SIan Rogers "PublicDescription": "Cycles in which the L1D and L2 are locked, due to a UC lock or split lock.", 40*4dd25272SIan Rogers "SampleAfterValue": "2000003", 41*4dd25272SIan Rogers "UMask": "0x1" 42dcfbad10SAndi Kleen } 43dcfbad10SAndi Kleen]