1dcfbad10SAndi Kleen[ 2dcfbad10SAndi Kleen { 3dcfbad10SAndi Kleen "EventCode": "0xC1", 4dcfbad10SAndi Kleen "Counter": "0,1,2,3", 5dcfbad10SAndi Kleen "UMask": "0x8", 6dcfbad10SAndi Kleen "Errata": "HSD56, HSM57", 7dcfbad10SAndi Kleen "EventName": "OTHER_ASSISTS.AVX_TO_SSE", 8dcfbad10SAndi Kleen "SampleAfterValue": "100003", 9dcfbad10SAndi Kleen "BriefDescription": "Number of transitions from AVX-256 to legacy SSE when penalty applicable.", 10dcfbad10SAndi Kleen "CounterHTOff": "0,1,2,3,4,5,6,7" 11dcfbad10SAndi Kleen }, 12dcfbad10SAndi Kleen { 13dcfbad10SAndi Kleen "EventCode": "0xC1", 14dcfbad10SAndi Kleen "Counter": "0,1,2,3", 15dcfbad10SAndi Kleen "UMask": "0x10", 16dcfbad10SAndi Kleen "Errata": "HSD56, HSM57", 17dcfbad10SAndi Kleen "EventName": "OTHER_ASSISTS.SSE_TO_AVX", 18dcfbad10SAndi Kleen "SampleAfterValue": "100003", 19dcfbad10SAndi Kleen "BriefDescription": "Number of transitions from SSE to AVX-256 when penalty applicable.", 20dcfbad10SAndi Kleen "CounterHTOff": "0,1,2,3,4,5,6,7" 21dcfbad10SAndi Kleen }, 22dcfbad10SAndi Kleen { 23dcfbad10SAndi Kleen "PublicDescription": "Number of X87 FP assists due to output values.", 24dcfbad10SAndi Kleen "EventCode": "0xCA", 25dcfbad10SAndi Kleen "Counter": "0,1,2,3", 26dcfbad10SAndi Kleen "UMask": "0x2", 27dcfbad10SAndi Kleen "EventName": "FP_ASSIST.X87_OUTPUT", 28dcfbad10SAndi Kleen "SampleAfterValue": "100003", 29dcfbad10SAndi Kleen "BriefDescription": "Number of X87 assists due to output value.", 30dcfbad10SAndi Kleen "CounterHTOff": "0,1,2,3,4,5,6,7" 31dcfbad10SAndi Kleen }, 32dcfbad10SAndi Kleen { 33dcfbad10SAndi Kleen "PublicDescription": "Number of X87 FP assists due to input values.", 34dcfbad10SAndi Kleen "EventCode": "0xCA", 35dcfbad10SAndi Kleen "Counter": "0,1,2,3", 36dcfbad10SAndi Kleen "UMask": "0x4", 37dcfbad10SAndi Kleen "EventName": "FP_ASSIST.X87_INPUT", 38dcfbad10SAndi Kleen "SampleAfterValue": "100003", 39dcfbad10SAndi Kleen "BriefDescription": "Number of X87 assists due to input value.", 40dcfbad10SAndi Kleen "CounterHTOff": "0,1,2,3,4,5,6,7" 41dcfbad10SAndi Kleen }, 42dcfbad10SAndi Kleen { 43dcfbad10SAndi Kleen "PublicDescription": "Number of SIMD FP assists due to output values.", 44dcfbad10SAndi Kleen "EventCode": "0xCA", 45dcfbad10SAndi Kleen "Counter": "0,1,2,3", 46dcfbad10SAndi Kleen "UMask": "0x8", 47dcfbad10SAndi Kleen "EventName": "FP_ASSIST.SIMD_OUTPUT", 48dcfbad10SAndi Kleen "SampleAfterValue": "100003", 49dcfbad10SAndi Kleen "BriefDescription": "Number of SIMD FP assists due to Output values", 50dcfbad10SAndi Kleen "CounterHTOff": "0,1,2,3,4,5,6,7" 51dcfbad10SAndi Kleen }, 52dcfbad10SAndi Kleen { 53dcfbad10SAndi Kleen "PublicDescription": "Number of SIMD FP assists due to input values.", 54dcfbad10SAndi Kleen "EventCode": "0xCA", 55dcfbad10SAndi Kleen "Counter": "0,1,2,3", 56dcfbad10SAndi Kleen "UMask": "0x10", 57dcfbad10SAndi Kleen "EventName": "FP_ASSIST.SIMD_INPUT", 58dcfbad10SAndi Kleen "SampleAfterValue": "100003", 59dcfbad10SAndi Kleen "BriefDescription": "Number of SIMD FP assists due to input values", 60dcfbad10SAndi Kleen "CounterHTOff": "0,1,2,3,4,5,6,7" 61dcfbad10SAndi Kleen }, 62dcfbad10SAndi Kleen { 63dcfbad10SAndi Kleen "PublicDescription": "Cycles with any input/output SSE* or FP assists.", 64dcfbad10SAndi Kleen "EventCode": "0xCA", 65dcfbad10SAndi Kleen "Counter": "0,1,2,3", 66dcfbad10SAndi Kleen "UMask": "0x1e", 67dcfbad10SAndi Kleen "EventName": "FP_ASSIST.ANY", 68dcfbad10SAndi Kleen "SampleAfterValue": "100003", 69dcfbad10SAndi Kleen "BriefDescription": "Cycles with any input/output SSE or FP assist", 70dcfbad10SAndi Kleen "CounterMask": "1", 71dcfbad10SAndi Kleen "CounterHTOff": "0,1,2,3" 72dcfbad10SAndi Kleen }, 73dcfbad10SAndi Kleen { 74dcfbad10SAndi Kleen "PublicDescription": "Note that a whole rep string only counts AVX_INST.ALL once.", 75dcfbad10SAndi Kleen "EventCode": "0xC6", 76dcfbad10SAndi Kleen "Counter": "0,1,2,3", 77dcfbad10SAndi Kleen "UMask": "0x7", 78dcfbad10SAndi Kleen "EventName": "AVX_INSTS.ALL", 79dcfbad10SAndi Kleen "SampleAfterValue": "2000003", 80dcfbad10SAndi Kleen "BriefDescription": "Approximate counts of AVX & AVX2 256-bit instructions, including non-arithmetic instructions, loads, and stores. May count non-AVX instructions that employ 256-bit operations, including (but not necessarily limited to) rep string instructions that use 256-bit loads and stores for optimized performance, XSAVE* and XRSTOR*, and operations that transition the x87 FPU data registers between x87 and MMX.", 81dcfbad10SAndi Kleen "CounterHTOff": "0,1,2,3,4,5,6,7" 82dcfbad10SAndi Kleen } 83dcfbad10SAndi Kleen]