1[ 2 { 3 "BriefDescription": "L1D data line replacements", 4 "EventCode": "0x51", 5 "EventName": "L1D.REPLACEMENT", 6 "PublicDescription": "This event counts when new data lines are brought into the L1 Data cache, which cause other lines to be evicted from the cache.", 7 "SampleAfterValue": "2000003", 8 "UMask": "0x1" 9 }, 10 { 11 "BriefDescription": "Cycles a demand request was blocked due to Fill Buffers unavailability.", 12 "CounterMask": "1", 13 "EventCode": "0x48", 14 "EventName": "L1D_PEND_MISS.FB_FULL", 15 "SampleAfterValue": "2000003", 16 "UMask": "0x2" 17 }, 18 { 19 "BriefDescription": "L1D miss outstanding duration in cycles", 20 "EventCode": "0x48", 21 "EventName": "L1D_PEND_MISS.PENDING", 22 "PublicDescription": "Increments the number of outstanding L1D misses every cycle. Set Cmask = 1 and Edge =1 to count occurrences.", 23 "SampleAfterValue": "2000003", 24 "UMask": "0x1" 25 }, 26 { 27 "BriefDescription": "Cycles with L1D load Misses outstanding.", 28 "CounterMask": "1", 29 "EventCode": "0x48", 30 "EventName": "L1D_PEND_MISS.PENDING_CYCLES", 31 "SampleAfterValue": "2000003", 32 "UMask": "0x1" 33 }, 34 { 35 "AnyThread": "1", 36 "BriefDescription": "Cycles with L1D load Misses outstanding from any thread on physical core.", 37 "CounterMask": "1", 38 "EventCode": "0x48", 39 "EventName": "L1D_PEND_MISS.PENDING_CYCLES_ANY", 40 "SampleAfterValue": "2000003", 41 "UMask": "0x1" 42 }, 43 { 44 "BriefDescription": "Number of times a request needed a FB entry but there was no entry available for it. That is the FB unavailability was dominant reason for blocking the request. A request includes cacheable/uncacheable demands that is load, store or SW prefetch. HWP are e.", 45 "EventCode": "0x48", 46 "EventName": "L1D_PEND_MISS.REQUEST_FB_FULL", 47 "SampleAfterValue": "2000003", 48 "UMask": "0x2" 49 }, 50 { 51 "BriefDescription": "Not rejected writebacks that hit L2 cache", 52 "EventCode": "0x27", 53 "EventName": "L2_DEMAND_RQSTS.WB_HIT", 54 "PublicDescription": "Not rejected writebacks that hit L2 cache.", 55 "SampleAfterValue": "200003", 56 "UMask": "0x50" 57 }, 58 { 59 "BriefDescription": "L2 cache lines filling L2", 60 "EventCode": "0xF1", 61 "EventName": "L2_LINES_IN.ALL", 62 "PublicDescription": "This event counts the number of L2 cache lines brought into the L2 cache. Lines are filled into the L2 cache when there was an L2 miss.", 63 "SampleAfterValue": "100003", 64 "UMask": "0x7" 65 }, 66 { 67 "BriefDescription": "L2 cache lines in E state filling L2", 68 "EventCode": "0xF1", 69 "EventName": "L2_LINES_IN.E", 70 "PublicDescription": "L2 cache lines in E state filling L2.", 71 "SampleAfterValue": "100003", 72 "UMask": "0x4" 73 }, 74 { 75 "BriefDescription": "L2 cache lines in I state filling L2", 76 "EventCode": "0xF1", 77 "EventName": "L2_LINES_IN.I", 78 "PublicDescription": "L2 cache lines in I state filling L2.", 79 "SampleAfterValue": "100003", 80 "UMask": "0x1" 81 }, 82 { 83 "BriefDescription": "L2 cache lines in S state filling L2", 84 "EventCode": "0xF1", 85 "EventName": "L2_LINES_IN.S", 86 "PublicDescription": "L2 cache lines in S state filling L2.", 87 "SampleAfterValue": "100003", 88 "UMask": "0x2" 89 }, 90 { 91 "BriefDescription": "Clean L2 cache lines evicted by demand", 92 "EventCode": "0xF2", 93 "EventName": "L2_LINES_OUT.DEMAND_CLEAN", 94 "PublicDescription": "Clean L2 cache lines evicted by demand.", 95 "SampleAfterValue": "100003", 96 "UMask": "0x5" 97 }, 98 { 99 "BriefDescription": "Dirty L2 cache lines evicted by demand", 100 "EventCode": "0xF2", 101 "EventName": "L2_LINES_OUT.DEMAND_DIRTY", 102 "PublicDescription": "Dirty L2 cache lines evicted by demand.", 103 "SampleAfterValue": "100003", 104 "UMask": "0x6" 105 }, 106 { 107 "BriefDescription": "L2 code requests", 108 "EventCode": "0x24", 109 "EventName": "L2_RQSTS.ALL_CODE_RD", 110 "PublicDescription": "Counts all L2 code requests.", 111 "SampleAfterValue": "200003", 112 "UMask": "0xe4" 113 }, 114 { 115 "BriefDescription": "Demand Data Read requests", 116 "Errata": "HSD78, HSM80", 117 "EventCode": "0x24", 118 "EventName": "L2_RQSTS.ALL_DEMAND_DATA_RD", 119 "PublicDescription": "Counts any demand and L1 HW prefetch data load requests to L2.", 120 "SampleAfterValue": "200003", 121 "UMask": "0xe1" 122 }, 123 { 124 "BriefDescription": "Demand requests that miss L2 cache", 125 "Errata": "HSD78, HSM80", 126 "EventCode": "0x24", 127 "EventName": "L2_RQSTS.ALL_DEMAND_MISS", 128 "PublicDescription": "Demand requests that miss L2 cache.", 129 "SampleAfterValue": "200003", 130 "UMask": "0x27" 131 }, 132 { 133 "BriefDescription": "Demand requests to L2 cache", 134 "Errata": "HSD78, HSM80", 135 "EventCode": "0x24", 136 "EventName": "L2_RQSTS.ALL_DEMAND_REFERENCES", 137 "PublicDescription": "Demand requests to L2 cache.", 138 "SampleAfterValue": "200003", 139 "UMask": "0xe7" 140 }, 141 { 142 "BriefDescription": "Requests from L2 hardware prefetchers", 143 "EventCode": "0x24", 144 "EventName": "L2_RQSTS.ALL_PF", 145 "PublicDescription": "Counts all L2 HW prefetcher requests.", 146 "SampleAfterValue": "200003", 147 "UMask": "0xf8" 148 }, 149 { 150 "BriefDescription": "RFO requests to L2 cache", 151 "EventCode": "0x24", 152 "EventName": "L2_RQSTS.ALL_RFO", 153 "PublicDescription": "Counts all L2 store RFO requests.", 154 "SampleAfterValue": "200003", 155 "UMask": "0xe2" 156 }, 157 { 158 "BriefDescription": "L2 cache hits when fetching instructions, code reads.", 159 "EventCode": "0x24", 160 "EventName": "L2_RQSTS.CODE_RD_HIT", 161 "PublicDescription": "Number of instruction fetches that hit the L2 cache.", 162 "SampleAfterValue": "200003", 163 "UMask": "0xc4" 164 }, 165 { 166 "BriefDescription": "L2 cache misses when fetching instructions", 167 "EventCode": "0x24", 168 "EventName": "L2_RQSTS.CODE_RD_MISS", 169 "PublicDescription": "Number of instruction fetches that missed the L2 cache.", 170 "SampleAfterValue": "200003", 171 "UMask": "0x24" 172 }, 173 { 174 "BriefDescription": "Demand Data Read requests that hit L2 cache", 175 "Errata": "HSD78, HSM80", 176 "EventCode": "0x24", 177 "EventName": "L2_RQSTS.DEMAND_DATA_RD_HIT", 178 "PublicDescription": "Counts the number of demand Data Read requests, initiated by load instructions, that hit L2 cache", 179 "SampleAfterValue": "200003", 180 "UMask": "0xc1" 181 }, 182 { 183 "BriefDescription": "Demand Data Read miss L2, no rejects", 184 "Errata": "HSD78, HSM80", 185 "EventCode": "0x24", 186 "EventName": "L2_RQSTS.DEMAND_DATA_RD_MISS", 187 "PublicDescription": "Demand data read requests that missed L2, no rejects.", 188 "SampleAfterValue": "200003", 189 "UMask": "0x21" 190 }, 191 { 192 "BriefDescription": "L2 prefetch requests that hit L2 cache", 193 "EventCode": "0x24", 194 "EventName": "L2_RQSTS.L2_PF_HIT", 195 "PublicDescription": "Counts all L2 HW prefetcher requests that hit L2.", 196 "SampleAfterValue": "200003", 197 "UMask": "0xd0" 198 }, 199 { 200 "BriefDescription": "L2 prefetch requests that miss L2 cache", 201 "EventCode": "0x24", 202 "EventName": "L2_RQSTS.L2_PF_MISS", 203 "PublicDescription": "Counts all L2 HW prefetcher requests that missed L2.", 204 "SampleAfterValue": "200003", 205 "UMask": "0x30" 206 }, 207 { 208 "BriefDescription": "All requests that miss L2 cache", 209 "Errata": "HSD78, HSM80", 210 "EventCode": "0x24", 211 "EventName": "L2_RQSTS.MISS", 212 "PublicDescription": "All requests that missed L2.", 213 "SampleAfterValue": "200003", 214 "UMask": "0x3f" 215 }, 216 { 217 "BriefDescription": "All L2 requests", 218 "Errata": "HSD78, HSM80", 219 "EventCode": "0x24", 220 "EventName": "L2_RQSTS.REFERENCES", 221 "PublicDescription": "All requests to L2 cache.", 222 "SampleAfterValue": "200003", 223 "UMask": "0xff" 224 }, 225 { 226 "BriefDescription": "RFO requests that hit L2 cache", 227 "EventCode": "0x24", 228 "EventName": "L2_RQSTS.RFO_HIT", 229 "PublicDescription": "Counts the number of store RFO requests that hit the L2 cache.", 230 "SampleAfterValue": "200003", 231 "UMask": "0xc2" 232 }, 233 { 234 "BriefDescription": "RFO requests that miss L2 cache", 235 "EventCode": "0x24", 236 "EventName": "L2_RQSTS.RFO_MISS", 237 "PublicDescription": "Counts the number of store RFO requests that miss the L2 cache.", 238 "SampleAfterValue": "200003", 239 "UMask": "0x22" 240 }, 241 { 242 "BriefDescription": "L2 or L3 HW prefetches that access L2 cache", 243 "EventCode": "0xf0", 244 "EventName": "L2_TRANS.ALL_PF", 245 "PublicDescription": "Any MLC or L3 HW prefetch accessing L2, including rejects.", 246 "SampleAfterValue": "200003", 247 "UMask": "0x8" 248 }, 249 { 250 "BriefDescription": "Transactions accessing L2 pipe", 251 "EventCode": "0xf0", 252 "EventName": "L2_TRANS.ALL_REQUESTS", 253 "PublicDescription": "Transactions accessing L2 pipe.", 254 "SampleAfterValue": "200003", 255 "UMask": "0x80" 256 }, 257 { 258 "BriefDescription": "L2 cache accesses when fetching instructions", 259 "EventCode": "0xf0", 260 "EventName": "L2_TRANS.CODE_RD", 261 "PublicDescription": "L2 cache accesses when fetching instructions.", 262 "SampleAfterValue": "200003", 263 "UMask": "0x4" 264 }, 265 { 266 "BriefDescription": "Demand Data Read requests that access L2 cache", 267 "EventCode": "0xf0", 268 "EventName": "L2_TRANS.DEMAND_DATA_RD", 269 "PublicDescription": "Demand data read requests that access L2 cache.", 270 "SampleAfterValue": "200003", 271 "UMask": "0x1" 272 }, 273 { 274 "BriefDescription": "L1D writebacks that access L2 cache", 275 "EventCode": "0xf0", 276 "EventName": "L2_TRANS.L1D_WB", 277 "PublicDescription": "L1D writebacks that access L2 cache.", 278 "SampleAfterValue": "200003", 279 "UMask": "0x10" 280 }, 281 { 282 "BriefDescription": "L2 fill requests that access L2 cache", 283 "EventCode": "0xf0", 284 "EventName": "L2_TRANS.L2_FILL", 285 "PublicDescription": "L2 fill requests that access L2 cache.", 286 "SampleAfterValue": "200003", 287 "UMask": "0x20" 288 }, 289 { 290 "BriefDescription": "L2 writebacks that access L2 cache", 291 "EventCode": "0xf0", 292 "EventName": "L2_TRANS.L2_WB", 293 "PublicDescription": "L2 writebacks that access L2 cache.", 294 "SampleAfterValue": "200003", 295 "UMask": "0x40" 296 }, 297 { 298 "BriefDescription": "RFO requests that access L2 cache", 299 "EventCode": "0xf0", 300 "EventName": "L2_TRANS.RFO", 301 "PublicDescription": "RFO requests that access L2 cache.", 302 "SampleAfterValue": "200003", 303 "UMask": "0x2" 304 }, 305 { 306 "BriefDescription": "Cycles when L1D is locked", 307 "EventCode": "0x63", 308 "EventName": "LOCK_CYCLES.CACHE_LOCK_DURATION", 309 "PublicDescription": "Cycles in which the L1D is locked.", 310 "SampleAfterValue": "2000003", 311 "UMask": "0x2" 312 }, 313 { 314 "BriefDescription": "Core-originated cacheable demand requests missed L3", 315 "EventCode": "0x2E", 316 "EventName": "LONGEST_LAT_CACHE.MISS", 317 "PublicDescription": "This event counts each cache miss condition for references to the last level cache.", 318 "SampleAfterValue": "100003", 319 "UMask": "0x41" 320 }, 321 { 322 "BriefDescription": "Core-originated cacheable demand requests that refer to L3", 323 "EventCode": "0x2E", 324 "EventName": "LONGEST_LAT_CACHE.REFERENCE", 325 "PublicDescription": "This event counts requests originating from the core that reference a cache line in the last level cache.", 326 "SampleAfterValue": "100003", 327 "UMask": "0x4f" 328 }, 329 { 330 "BriefDescription": "Retired load uops which data sources were L3 and cross-core snoop hits in on-pkg core cache.", 331 "Data_LA": "1", 332 "Errata": "HSD29, HSD25, HSM26, HSM30", 333 "EventCode": "0xD2", 334 "EventName": "MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT", 335 "PEBS": "1", 336 "SampleAfterValue": "20011", 337 "UMask": "0x2" 338 }, 339 { 340 "BriefDescription": "Retired load uops which data sources were HitM responses from shared L3.", 341 "Data_LA": "1", 342 "Errata": "HSD29, HSD25, HSM26, HSM30", 343 "EventCode": "0xD2", 344 "EventName": "MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM", 345 "PEBS": "1", 346 "SampleAfterValue": "20011", 347 "UMask": "0x4" 348 }, 349 { 350 "BriefDescription": "Retired load uops which data sources were L3 hit and cross-core snoop missed in on-pkg core cache.", 351 "Data_LA": "1", 352 "Errata": "HSD29, HSD25, HSM26, HSM30", 353 "EventCode": "0xD2", 354 "EventName": "MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS", 355 "PEBS": "1", 356 "SampleAfterValue": "20011", 357 "UMask": "0x1" 358 }, 359 { 360 "BriefDescription": "Retired load uops which data sources were hits in L3 without snoops required.", 361 "Data_LA": "1", 362 "Errata": "HSD74, HSD29, HSD25, HSM26, HSM30", 363 "EventCode": "0xD2", 364 "EventName": "MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_NONE", 365 "PEBS": "1", 366 "SampleAfterValue": "100003", 367 "UMask": "0x8" 368 }, 369 { 370 "BriefDescription": "Data from local DRAM either Snoop not needed or Snoop Miss (RspI)", 371 "Data_LA": "1", 372 "Errata": "HSD74, HSD29, HSD25, HSM30", 373 "EventCode": "0xD3", 374 "EventName": "MEM_LOAD_UOPS_L3_MISS_RETIRED.LOCAL_DRAM", 375 "PEBS": "1", 376 "PublicDescription": "This event counts retired load uops where the data came from local DRAM. This does not include hardware prefetches.", 377 "SampleAfterValue": "100003", 378 "UMask": "0x1" 379 }, 380 { 381 "BriefDescription": "Retired load uops which data sources were load uops missed L1 but hit FB due to preceding miss to the same cache line with data not ready.", 382 "Data_LA": "1", 383 "Errata": "HSM30", 384 "EventCode": "0xD1", 385 "EventName": "MEM_LOAD_UOPS_RETIRED.HIT_LFB", 386 "PEBS": "1", 387 "SampleAfterValue": "100003", 388 "UMask": "0x40" 389 }, 390 { 391 "BriefDescription": "Retired load uops with L1 cache hits as data sources.", 392 "Data_LA": "1", 393 "Errata": "HSD29, HSM30", 394 "EventCode": "0xD1", 395 "EventName": "MEM_LOAD_UOPS_RETIRED.L1_HIT", 396 "PEBS": "1", 397 "SampleAfterValue": "2000003", 398 "UMask": "0x1" 399 }, 400 { 401 "BriefDescription": "Retired load uops misses in L1 cache as data sources.", 402 "Data_LA": "1", 403 "Errata": "HSM30", 404 "EventCode": "0xD1", 405 "EventName": "MEM_LOAD_UOPS_RETIRED.L1_MISS", 406 "PEBS": "1", 407 "PublicDescription": "Retired load uops missed L1 cache as data sources.", 408 "SampleAfterValue": "100003", 409 "UMask": "0x8" 410 }, 411 { 412 "BriefDescription": "Retired load uops with L2 cache hits as data sources.", 413 "Data_LA": "1", 414 "Errata": "HSD76, HSD29, HSM30", 415 "EventCode": "0xD1", 416 "EventName": "MEM_LOAD_UOPS_RETIRED.L2_HIT", 417 "PEBS": "1", 418 "SampleAfterValue": "100003", 419 "UMask": "0x2" 420 }, 421 { 422 "BriefDescription": "Miss in mid-level (L2) cache. Excludes Unknown data-source.", 423 "Data_LA": "1", 424 "Errata": "HSD29, HSM30", 425 "EventCode": "0xD1", 426 "EventName": "MEM_LOAD_UOPS_RETIRED.L2_MISS", 427 "PEBS": "1", 428 "PublicDescription": "Retired load uops missed L2. Unknown data source excluded.", 429 "SampleAfterValue": "50021", 430 "UMask": "0x10" 431 }, 432 { 433 "BriefDescription": "Retired load uops which data sources were data hits in L3 without snoops required.", 434 "Data_LA": "1", 435 "Errata": "HSD74, HSD29, HSD25, HSM26, HSM30", 436 "EventCode": "0xD1", 437 "EventName": "MEM_LOAD_UOPS_RETIRED.L3_HIT", 438 "PEBS": "1", 439 "PublicDescription": "Retired load uops with L3 cache hits as data sources.", 440 "SampleAfterValue": "50021", 441 "UMask": "0x4" 442 }, 443 { 444 "BriefDescription": "Miss in last-level (L3) cache. Excludes Unknown data-source.", 445 "Data_LA": "1", 446 "Errata": "HSD74, HSD29, HSD25, HSM26, HSM30", 447 "EventCode": "0xD1", 448 "EventName": "MEM_LOAD_UOPS_RETIRED.L3_MISS", 449 "PEBS": "1", 450 "PublicDescription": "Retired load uops missed L3. Excludes unknown data source .", 451 "SampleAfterValue": "100003", 452 "UMask": "0x20" 453 }, 454 { 455 "BriefDescription": "Retired load uops.", 456 "Data_LA": "1", 457 "Errata": "HSD29, HSM30", 458 "EventCode": "0xD0", 459 "EventName": "MEM_UOPS_RETIRED.ALL_LOADS", 460 "PEBS": "1", 461 "PublicDescription": "Counts all retired load uops. This event accounts for SW prefetch uops of PREFETCHNTA or PREFETCHT0/1/2 or PREFETCHW.", 462 "SampleAfterValue": "2000003", 463 "UMask": "0x81" 464 }, 465 { 466 "BriefDescription": "Retired store uops.", 467 "Data_LA": "1", 468 "Errata": "HSD29, HSM30", 469 "EventCode": "0xD0", 470 "EventName": "MEM_UOPS_RETIRED.ALL_STORES", 471 "PEBS": "1", 472 "PublicDescription": "Counts all retired store uops.", 473 "SampleAfterValue": "2000003", 474 "UMask": "0x82" 475 }, 476 { 477 "BriefDescription": "Retired load uops with locked access.", 478 "Data_LA": "1", 479 "Errata": "HSD76, HSD29, HSM30", 480 "EventCode": "0xD0", 481 "EventName": "MEM_UOPS_RETIRED.LOCK_LOADS", 482 "PEBS": "1", 483 "SampleAfterValue": "100003", 484 "UMask": "0x21" 485 }, 486 { 487 "BriefDescription": "Retired load uops that split across a cacheline boundary.", 488 "Data_LA": "1", 489 "Errata": "HSD29, HSM30", 490 "EventCode": "0xD0", 491 "EventName": "MEM_UOPS_RETIRED.SPLIT_LOADS", 492 "PEBS": "1", 493 "SampleAfterValue": "100003", 494 "UMask": "0x41" 495 }, 496 { 497 "BriefDescription": "Retired store uops that split across a cacheline boundary.", 498 "Data_LA": "1", 499 "Errata": "HSD29, HSM30", 500 "EventCode": "0xD0", 501 "EventName": "MEM_UOPS_RETIRED.SPLIT_STORES", 502 "PEBS": "1", 503 "SampleAfterValue": "100003", 504 "UMask": "0x42" 505 }, 506 { 507 "BriefDescription": "Retired load uops that miss the STLB.", 508 "Data_LA": "1", 509 "Errata": "HSD29, HSM30", 510 "EventCode": "0xD0", 511 "EventName": "MEM_UOPS_RETIRED.STLB_MISS_LOADS", 512 "PEBS": "1", 513 "SampleAfterValue": "100003", 514 "UMask": "0x11" 515 }, 516 { 517 "BriefDescription": "Retired store uops that miss the STLB.", 518 "Data_LA": "1", 519 "Errata": "HSD29, HSM30", 520 "EventCode": "0xD0", 521 "EventName": "MEM_UOPS_RETIRED.STLB_MISS_STORES", 522 "PEBS": "1", 523 "SampleAfterValue": "100003", 524 "UMask": "0x12" 525 }, 526 { 527 "BriefDescription": "Demand and prefetch data reads", 528 "EventCode": "0xB0", 529 "EventName": "OFFCORE_REQUESTS.ALL_DATA_RD", 530 "PublicDescription": "Data read requests sent to uncore (demand and prefetch).", 531 "SampleAfterValue": "100003", 532 "UMask": "0x8" 533 }, 534 { 535 "BriefDescription": "Cacheable and noncacheable code read requests", 536 "EventCode": "0xB0", 537 "EventName": "OFFCORE_REQUESTS.DEMAND_CODE_RD", 538 "PublicDescription": "Demand code read requests sent to uncore.", 539 "SampleAfterValue": "100003", 540 "UMask": "0x2" 541 }, 542 { 543 "BriefDescription": "Demand Data Read requests sent to uncore", 544 "Errata": "HSD78, HSM80", 545 "EventCode": "0xb0", 546 "EventName": "OFFCORE_REQUESTS.DEMAND_DATA_RD", 547 "PublicDescription": "Demand data read requests sent to uncore.", 548 "SampleAfterValue": "100003", 549 "UMask": "0x1" 550 }, 551 { 552 "BriefDescription": "Demand RFO requests including regular RFOs, locks, ItoM", 553 "EventCode": "0xB0", 554 "EventName": "OFFCORE_REQUESTS.DEMAND_RFO", 555 "PublicDescription": "Demand RFO read requests sent to uncore, including regular RFOs, locks, ItoM.", 556 "SampleAfterValue": "100003", 557 "UMask": "0x4" 558 }, 559 { 560 "BriefDescription": "Offcore requests buffer cannot take more entries for this thread core.", 561 "EventCode": "0xb2", 562 "EventName": "OFFCORE_REQUESTS_BUFFER.SQ_FULL", 563 "SampleAfterValue": "2000003", 564 "UMask": "0x1" 565 }, 566 { 567 "BriefDescription": "Offcore outstanding cacheable Core Data Read transactions in SuperQueue (SQ), queue to uncore", 568 "Errata": "HSD62, HSD61, HSM63", 569 "EventCode": "0x60", 570 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD", 571 "PublicDescription": "Offcore outstanding cacheable data read transactions in SQ to uncore. Set Cmask=1 to count cycles.", 572 "SampleAfterValue": "2000003", 573 "UMask": "0x8" 574 }, 575 { 576 "BriefDescription": "Cycles when offcore outstanding cacheable Core Data Read transactions are present in SuperQueue (SQ), queue to uncore.", 577 "CounterMask": "1", 578 "Errata": "HSD62, HSD61, HSM63", 579 "EventCode": "0x60", 580 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD", 581 "SampleAfterValue": "2000003", 582 "UMask": "0x8" 583 }, 584 { 585 "BriefDescription": "Cycles when offcore outstanding Demand Data Read transactions are present in SuperQueue (SQ), queue to uncore.", 586 "CounterMask": "1", 587 "Errata": "HSD78, HSD62, HSD61, HSM63, HSM80", 588 "EventCode": "0x60", 589 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_DATA_RD", 590 "SampleAfterValue": "2000003", 591 "UMask": "0x1" 592 }, 593 { 594 "BriefDescription": "Offcore outstanding demand rfo reads transactions in SuperQueue (SQ), queue to uncore, every cycle.", 595 "CounterMask": "1", 596 "Errata": "HSD62, HSD61, HSM63", 597 "EventCode": "0x60", 598 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO", 599 "SampleAfterValue": "2000003", 600 "UMask": "0x4" 601 }, 602 { 603 "BriefDescription": "Offcore outstanding code reads transactions in SuperQueue (SQ), queue to uncore, every cycle", 604 "Errata": "HSD62, HSD61, HSM63", 605 "EventCode": "0x60", 606 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_CODE_RD", 607 "PublicDescription": "Offcore outstanding Demand code Read transactions in SQ to uncore. Set Cmask=1 to count cycles.", 608 "SampleAfterValue": "2000003", 609 "UMask": "0x2" 610 }, 611 { 612 "BriefDescription": "Offcore outstanding Demand Data Read transactions in uncore queue.", 613 "Errata": "HSD78, HSD62, HSD61, HSM63, HSM80", 614 "EventCode": "0x60", 615 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD", 616 "PublicDescription": "Offcore outstanding demand data read transactions in SQ to uncore. Set Cmask=1 to count cycles.", 617 "SampleAfterValue": "2000003", 618 "UMask": "0x1" 619 }, 620 { 621 "BriefDescription": "Cycles with at least 6 offcore outstanding Demand Data Read transactions in uncore queue.", 622 "CounterMask": "6", 623 "Errata": "HSD78, HSD62, HSD61, HSM63, HSM80", 624 "EventCode": "0x60", 625 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD_GE_6", 626 "SampleAfterValue": "2000003", 627 "UMask": "0x1" 628 }, 629 { 630 "BriefDescription": "Offcore outstanding RFO store transactions in SuperQueue (SQ), queue to uncore", 631 "Errata": "HSD62, HSD61, HSM63", 632 "EventCode": "0x60", 633 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_RFO", 634 "PublicDescription": "Offcore outstanding RFO store transactions in SQ to uncore. Set Cmask=1 to count cycles.", 635 "SampleAfterValue": "2000003", 636 "UMask": "0x4" 637 }, 638 { 639 "BriefDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 640 "EventCode": "0xB7, 0xBB", 641 "EventName": "OFFCORE_RESPONSE", 642 "SampleAfterValue": "100003", 643 "UMask": "0x1" 644 }, 645 { 646 "BriefDescription": "Counts all demand & prefetch code reads hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded", 647 "EventCode": "0xB7, 0xBB", 648 "EventName": "OFFCORE_RESPONSE.ALL_CODE_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD", 649 "MSRIndex": "0x1a6,0x1a7", 650 "MSRValue": "0x4003C0244", 651 "SampleAfterValue": "100003", 652 "UMask": "0x1" 653 }, 654 { 655 "BriefDescription": "Counts all demand & prefetch data reads hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded", 656 "EventCode": "0xB7, 0xBB", 657 "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT.HITM_OTHER_CORE", 658 "MSRIndex": "0x1a6,0x1a7", 659 "MSRValue": "0x10003C0091", 660 "SampleAfterValue": "100003", 661 "UMask": "0x1" 662 }, 663 { 664 "BriefDescription": "Counts all demand & prefetch data reads hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded", 665 "EventCode": "0xB7, 0xBB", 666 "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD", 667 "MSRIndex": "0x1a6,0x1a7", 668 "MSRValue": "0x4003C0091", 669 "SampleAfterValue": "100003", 670 "UMask": "0x1" 671 }, 672 { 673 "BriefDescription": "hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded", 674 "EventCode": "0xB7, 0xBB", 675 "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_HIT.HITM_OTHER_CORE", 676 "MSRIndex": "0x1a6,0x1a7", 677 "MSRValue": "0x10003C07F7", 678 "SampleAfterValue": "100003", 679 "UMask": "0x1" 680 }, 681 { 682 "BriefDescription": "hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded", 683 "EventCode": "0xB7, 0xBB", 684 "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_HIT.HIT_OTHER_CORE_NO_FWD", 685 "MSRIndex": "0x1a6,0x1a7", 686 "MSRValue": "0x4003C07F7", 687 "SampleAfterValue": "100003", 688 "UMask": "0x1" 689 }, 690 { 691 "BriefDescription": "Counts all requests hit in the L3", 692 "EventCode": "0xB7, 0xBB", 693 "EventName": "OFFCORE_RESPONSE.ALL_REQUESTS.L3_HIT.ANY_RESPONSE", 694 "MSRIndex": "0x1a6,0x1a7", 695 "MSRValue": "0x3F803C8FFF", 696 "SampleAfterValue": "100003", 697 "UMask": "0x1" 698 }, 699 { 700 "BriefDescription": "Counts all demand & prefetch RFOs hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded", 701 "EventCode": "0xB7, 0xBB", 702 "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT.HITM_OTHER_CORE", 703 "MSRIndex": "0x1a6,0x1a7", 704 "MSRValue": "0x10003C0122", 705 "SampleAfterValue": "100003", 706 "UMask": "0x1" 707 }, 708 { 709 "BriefDescription": "Counts all demand & prefetch RFOs hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded", 710 "EventCode": "0xB7, 0xBB", 711 "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD", 712 "MSRIndex": "0x1a6,0x1a7", 713 "MSRValue": "0x4003C0122", 714 "SampleAfterValue": "100003", 715 "UMask": "0x1" 716 }, 717 { 718 "BriefDescription": "Counts all demand code reads hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded", 719 "EventCode": "0xB7, 0xBB", 720 "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT.HITM_OTHER_CORE", 721 "MSRIndex": "0x1a6,0x1a7", 722 "MSRValue": "0x10003C0004", 723 "SampleAfterValue": "100003", 724 "UMask": "0x1" 725 }, 726 { 727 "BriefDescription": "Counts all demand code reads hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded", 728 "EventCode": "0xB7, 0xBB", 729 "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD", 730 "MSRIndex": "0x1a6,0x1a7", 731 "MSRValue": "0x4003C0004", 732 "SampleAfterValue": "100003", 733 "UMask": "0x1" 734 }, 735 { 736 "BriefDescription": "Counts demand data reads hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded", 737 "EventCode": "0xB7, 0xBB", 738 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.HITM_OTHER_CORE", 739 "MSRIndex": "0x1a6,0x1a7", 740 "MSRValue": "0x10003C0001", 741 "SampleAfterValue": "100003", 742 "UMask": "0x1" 743 }, 744 { 745 "BriefDescription": "Counts demand data reads hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded", 746 "EventCode": "0xB7, 0xBB", 747 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD", 748 "MSRIndex": "0x1a6,0x1a7", 749 "MSRValue": "0x4003C0001", 750 "SampleAfterValue": "100003", 751 "UMask": "0x1" 752 }, 753 { 754 "BriefDescription": "Counts all demand data writes (RFOs) hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded", 755 "EventCode": "0xB7, 0xBB", 756 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.HITM_OTHER_CORE", 757 "MSRIndex": "0x1a6,0x1a7", 758 "MSRValue": "0x10003C0002", 759 "SampleAfterValue": "100003", 760 "UMask": "0x1" 761 }, 762 { 763 "BriefDescription": "Counts all demand data writes (RFOs) hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded", 764 "EventCode": "0xB7, 0xBB", 765 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD", 766 "MSRIndex": "0x1a6,0x1a7", 767 "MSRValue": "0x4003C0002", 768 "SampleAfterValue": "100003", 769 "UMask": "0x1" 770 }, 771 { 772 "BriefDescription": "Counts all prefetch (that bring data to LLC only) code reads hit in the L3", 773 "EventCode": "0xB7, 0xBB", 774 "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.L3_HIT.ANY_RESPONSE", 775 "MSRIndex": "0x1a6,0x1a7", 776 "MSRValue": "0x3F803C0040", 777 "SampleAfterValue": "100003", 778 "UMask": "0x1" 779 }, 780 { 781 "BriefDescription": "Counts prefetch (that bring data to L2) data reads hit in the L3", 782 "EventCode": "0xB7, 0xBB", 783 "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_HIT.ANY_RESPONSE", 784 "MSRIndex": "0x1a6,0x1a7", 785 "MSRValue": "0x3F803C0010", 786 "SampleAfterValue": "100003", 787 "UMask": "0x1" 788 }, 789 { 790 "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs hit in the L3", 791 "EventCode": "0xB7, 0xBB", 792 "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT.ANY_RESPONSE", 793 "MSRIndex": "0x1a6,0x1a7", 794 "MSRValue": "0x3F803C0020", 795 "SampleAfterValue": "100003", 796 "UMask": "0x1" 797 }, 798 { 799 "BriefDescription": "Counts prefetch (that bring data to LLC only) code reads hit in the L3", 800 "EventCode": "0xB7, 0xBB", 801 "EventName": "OFFCORE_RESPONSE.PF_L3_CODE_RD.L3_HIT.ANY_RESPONSE", 802 "MSRIndex": "0x1a6,0x1a7", 803 "MSRValue": "0x3F803C0200", 804 "SampleAfterValue": "100003", 805 "UMask": "0x1" 806 }, 807 { 808 "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads hit in the L3", 809 "EventCode": "0xB7, 0xBB", 810 "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT.ANY_RESPONSE", 811 "MSRIndex": "0x1a6,0x1a7", 812 "MSRValue": "0x3F803C0080", 813 "SampleAfterValue": "100003", 814 "UMask": "0x1" 815 }, 816 { 817 "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs hit in the L3", 818 "EventCode": "0xB7, 0xBB", 819 "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT.ANY_RESPONSE", 820 "MSRIndex": "0x1a6,0x1a7", 821 "MSRValue": "0x3F803C0100", 822 "SampleAfterValue": "100003", 823 "UMask": "0x1" 824 }, 825 { 826 "BriefDescription": "Split locks in SQ", 827 "EventCode": "0xf4", 828 "EventName": "SQ_MISC.SPLIT_LOCK", 829 "SampleAfterValue": "100003", 830 "UMask": "0x10" 831 } 832] 833