1*1e8ad07eSIan Rogers[
2*1e8ad07eSIan Rogers    {
3*1e8ad07eSIan Rogers        "BriefDescription": "Load miss in all TLB levels causes a page walk that completes. (All page sizes)",
4*1e8ad07eSIan Rogers        "EventCode": "0x12",
5*1e8ad07eSIan Rogers        "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED",
6*1e8ad07eSIan Rogers        "PublicDescription": "Counts completed page walks  (all page sizes) caused by demand data loads. This implies it missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.",
7*1e8ad07eSIan Rogers        "SampleAfterValue": "100003",
8*1e8ad07eSIan Rogers        "UMask": "0xe"
9*1e8ad07eSIan Rogers    },
10*1e8ad07eSIan Rogers    {
11*1e8ad07eSIan Rogers        "BriefDescription": "Store misses in all TLB levels causes a page walk that completes. (All page sizes)",
12*1e8ad07eSIan Rogers        "EventCode": "0x13",
13*1e8ad07eSIan Rogers        "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED",
14*1e8ad07eSIan Rogers        "PublicDescription": "Counts completed page walks  (all page sizes) caused by demand data stores. This implies it missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.",
15*1e8ad07eSIan Rogers        "SampleAfterValue": "100003",
16*1e8ad07eSIan Rogers        "UMask": "0xe"
17*1e8ad07eSIan Rogers    },
18*1e8ad07eSIan Rogers    {
19*1e8ad07eSIan Rogers        "BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (All page sizes)",
20*1e8ad07eSIan Rogers        "EventCode": "0x11",
21*1e8ad07eSIan Rogers        "EventName": "ITLB_MISSES.WALK_COMPLETED",
22*1e8ad07eSIan Rogers        "PublicDescription": "Counts completed page walks (all page sizes) caused by a code fetch. This implies it missed in the ITLB (Instruction TLB) and further levels of TLB. The page walk can end with or without a fault.",
23*1e8ad07eSIan Rogers        "SampleAfterValue": "100003",
24*1e8ad07eSIan Rogers        "UMask": "0xe"
25*1e8ad07eSIan Rogers    }
26*1e8ad07eSIan Rogers]
27