1[
2    {
3        "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 128 cycles.",
4        "Data_LA": "1",
5        "EventCode": "0xcd",
6        "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_128",
7        "MSRIndex": "0x3F6",
8        "MSRValue": "0x80",
9        "PEBS": "2",
10        "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 128 cycles.  Reported latency may be longer than just the memory latency.",
11        "SampleAfterValue": "1009",
12        "UMask": "0x1"
13    },
14    {
15        "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 16 cycles.",
16        "Data_LA": "1",
17        "EventCode": "0xcd",
18        "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_16",
19        "MSRIndex": "0x3F6",
20        "MSRValue": "0x10",
21        "PEBS": "2",
22        "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 16 cycles.  Reported latency may be longer than just the memory latency.",
23        "SampleAfterValue": "20011",
24        "UMask": "0x1"
25    },
26    {
27        "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 256 cycles.",
28        "Data_LA": "1",
29        "EventCode": "0xcd",
30        "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_256",
31        "MSRIndex": "0x3F6",
32        "MSRValue": "0x100",
33        "PEBS": "2",
34        "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 256 cycles.  Reported latency may be longer than just the memory latency.",
35        "SampleAfterValue": "503",
36        "UMask": "0x1"
37    },
38    {
39        "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 32 cycles.",
40        "Data_LA": "1",
41        "EventCode": "0xcd",
42        "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_32",
43        "MSRIndex": "0x3F6",
44        "MSRValue": "0x20",
45        "PEBS": "2",
46        "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 32 cycles.  Reported latency may be longer than just the memory latency.",
47        "SampleAfterValue": "100007",
48        "UMask": "0x1"
49    },
50    {
51        "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 4 cycles.",
52        "Data_LA": "1",
53        "EventCode": "0xcd",
54        "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_4",
55        "MSRIndex": "0x3F6",
56        "MSRValue": "0x4",
57        "PEBS": "2",
58        "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 4 cycles.  Reported latency may be longer than just the memory latency.",
59        "SampleAfterValue": "100003",
60        "UMask": "0x1"
61    },
62    {
63        "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 512 cycles.",
64        "Data_LA": "1",
65        "EventCode": "0xcd",
66        "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_512",
67        "MSRIndex": "0x3F6",
68        "MSRValue": "0x200",
69        "PEBS": "2",
70        "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 512 cycles.  Reported latency may be longer than just the memory latency.",
71        "SampleAfterValue": "101",
72        "UMask": "0x1"
73    },
74    {
75        "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 64 cycles.",
76        "Data_LA": "1",
77        "EventCode": "0xcd",
78        "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_64",
79        "MSRIndex": "0x3F6",
80        "MSRValue": "0x40",
81        "PEBS": "2",
82        "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 64 cycles.  Reported latency may be longer than just the memory latency.",
83        "SampleAfterValue": "2003",
84        "UMask": "0x1"
85    },
86    {
87        "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 8 cycles.",
88        "Data_LA": "1",
89        "EventCode": "0xcd",
90        "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_8",
91        "MSRIndex": "0x3F6",
92        "MSRValue": "0x8",
93        "PEBS": "2",
94        "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 8 cycles.  Reported latency may be longer than just the memory latency.",
95        "SampleAfterValue": "50021",
96        "UMask": "0x1"
97    },
98    {
99        "BriefDescription": "Retired memory store access operations. A PDist event for PEBS Store Latency Facility.",
100        "Data_LA": "1",
101        "EventCode": "0xcd",
102        "EventName": "MEM_TRANS_RETIRED.STORE_SAMPLE",
103        "PEBS": "2",
104        "PublicDescription": "Counts Retired memory accesses with at least 1 store operation. This PEBS event is the precisely-distributed (PDist) trigger covering all stores uops for sampling by the PEBS Store Latency Facility. The facility is described in Intel SDM Volume 3 section 19.9.8",
105        "SampleAfterValue": "1000003",
106        "UMask": "0x2"
107    },
108    {
109        "BriefDescription": "Counts demand data reads that were not supplied by the local socket's L1, L2, or L3 caches.",
110        "EventCode": "0x2A,0x2B",
111        "EventName": "OCR.DEMAND_DATA_RD.L3_MISS",
112        "MSRIndex": "0x1a6,0x1a7",
113        "MSRValue": "0x3FBFC00001",
114        "SampleAfterValue": "100003",
115        "UMask": "0x1"
116    },
117    {
118        "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that were not supplied by the local socket's L1, L2, or L3 caches.",
119        "EventCode": "0x2A,0x2B",
120        "EventName": "OCR.DEMAND_RFO.L3_MISS",
121        "MSRIndex": "0x1a6,0x1a7",
122        "MSRValue": "0x3F3FC00002",
123        "SampleAfterValue": "100003",
124        "UMask": "0x1"
125    },
126    {
127        "BriefDescription": "Number of times an RTM execution aborted.",
128        "EventCode": "0xc9",
129        "EventName": "RTM_RETIRED.ABORTED",
130        "PublicDescription": "Counts the number of times RTM abort was triggered.",
131        "SampleAfterValue": "100003",
132        "UMask": "0x4"
133    },
134    {
135        "BriefDescription": "Number of times an RTM execution successfully committed",
136        "EventCode": "0xc9",
137        "EventName": "RTM_RETIRED.COMMIT",
138        "PublicDescription": "Counts the number of times RTM commit succeeded.",
139        "SampleAfterValue": "100003",
140        "UMask": "0x2"
141    },
142    {
143        "BriefDescription": "Number of times an RTM execution started.",
144        "EventCode": "0xc9",
145        "EventName": "RTM_RETIRED.START",
146        "PublicDescription": "Counts the number of times we entered an RTM region. Does not count nested transactions.",
147        "SampleAfterValue": "100003",
148        "UMask": "0x1"
149    },
150    {
151        "BriefDescription": "Speculatively counts the number of TSX aborts due to a data capacity limitation for transactional reads",
152        "EventCode": "0x54",
153        "EventName": "TX_MEM.ABORT_CAPACITY_READ",
154        "PublicDescription": "Speculatively counts the number of Transactional Synchronization Extensions (TSX) aborts due to a data capacity limitation for transactional reads",
155        "SampleAfterValue": "100003",
156        "UMask": "0x80"
157    },
158    {
159        "BriefDescription": "Speculatively counts the number of TSX aborts due to a data capacity limitation for transactional writes.",
160        "EventCode": "0x54",
161        "EventName": "TX_MEM.ABORT_CAPACITY_WRITE",
162        "PublicDescription": "Speculatively counts the number of Transactional Synchronization Extensions (TSX) aborts due to a data capacity limitation for transactional writes.",
163        "SampleAfterValue": "100003",
164        "UMask": "0x2"
165    },
166    {
167        "BriefDescription": "Number of times a transactional abort was signaled due to a data conflict on a transactionally accessed address",
168        "EventCode": "0x54",
169        "EventName": "TX_MEM.ABORT_CONFLICT",
170        "PublicDescription": "Counts the number of times a TSX line had a cache conflict.",
171        "SampleAfterValue": "100003",
172        "UMask": "0x1"
173    }
174]
175