165db92e0SKan Liang[
265db92e0SKan Liang    {
3*45957c1eSIan Rogers        "BriefDescription": "Cycles code-fetch stalled due to any reason.",
4*45957c1eSIan Rogers        "EventCode": "0x86",
565db92e0SKan Liang        "EventName": "FETCH_STALL.ALL",
6*45957c1eSIan Rogers        "PublicDescription": "Counts cycles that fetch is stalled due to any reason. That is, the decoder queue is able to accept bytes, but the fetch unit is unable to provide bytes.  This will include cycles due to an ITLB miss, ICache miss and other events.",
7*45957c1eSIan Rogers        "SampleAfterValue": "200003"
865db92e0SKan Liang    },
965db92e0SKan Liang    {
10*45957c1eSIan Rogers        "BriefDescription": "Cycles the code-fetch stalls and an ITLB miss is outstanding.",
11*45957c1eSIan Rogers        "EventCode": "0x86",
1265db92e0SKan Liang        "EventName": "FETCH_STALL.ITLB_FILL_PENDING_CYCLES",
13*45957c1eSIan Rogers        "PublicDescription": "Counts cycles that fetch is stalled due to an outstanding ITLB miss. That is, the decoder queue is able to accept bytes, but the fetch unit is unable to provide bytes due to an ITLB miss.  Note: this event is not the same as page walk cycles to retrieve an instruction translation.",
1465db92e0SKan Liang        "SampleAfterValue": "200003",
15*45957c1eSIan Rogers        "UMask": "0x1"
1665db92e0SKan Liang    },
1765db92e0SKan Liang    {
18*45957c1eSIan Rogers        "BriefDescription": "Cycles hardware interrupts are masked",
1965db92e0SKan Liang        "EventCode": "0xCB",
2065db92e0SKan Liang        "EventName": "HW_INTERRUPTS.MASKED",
21*45957c1eSIan Rogers        "PublicDescription": "Counts the number of core cycles during which interrupts are masked (disabled). Increments by 1 each core cycle that EFLAGS.IF is 0, regardless of whether interrupts are pending or not.",
2265db92e0SKan Liang        "SampleAfterValue": "200003",
23*45957c1eSIan Rogers        "UMask": "0x2"
2465db92e0SKan Liang    },
2565db92e0SKan Liang    {
26*45957c1eSIan Rogers        "BriefDescription": "Cycles pending interrupts are masked",
27*45957c1eSIan Rogers        "EventCode": "0xCB",
2865db92e0SKan Liang        "EventName": "HW_INTERRUPTS.PENDING_AND_MASKED",
29*45957c1eSIan Rogers        "PublicDescription": "Counts core cycles during which there are pending interrupts, but interrupts are masked (EFLAGS.IF = 0).",
3065db92e0SKan Liang        "SampleAfterValue": "200003",
31*45957c1eSIan Rogers        "UMask": "0x4"
32*45957c1eSIan Rogers    },
33*45957c1eSIan Rogers    {
34*45957c1eSIan Rogers        "BriefDescription": "Hardware interrupts received",
35*45957c1eSIan Rogers        "EventCode": "0xCB",
36*45957c1eSIan Rogers        "EventName": "HW_INTERRUPTS.RECEIVED",
37*45957c1eSIan Rogers        "PublicDescription": "Counts hardware interrupts received by the processor.",
38*45957c1eSIan Rogers        "SampleAfterValue": "203",
39*45957c1eSIan Rogers        "UMask": "0x1"
4065db92e0SKan Liang    }
4165db92e0SKan Liang]
42