14a00680bSAndi Kleen[
24a00680bSAndi Kleen    {
3*4ee19e31SIan Rogers        "BriefDescription": "Cycles code-fetch stalled due to any reason.",
4*4ee19e31SIan Rogers        "EventCode": "0x86",
503da89c5SAndi Kleen        "EventName": "FETCH_STALL.ALL",
6*4ee19e31SIan Rogers        "PublicDescription": "Counts cycles that fetch is stalled due to any reason. That is, the decoder queue is able to accept bytes, but the fetch unit is unable to provide bytes.  This will include cycles due to an ITLB miss, ICache miss and other events.",
7*4ee19e31SIan Rogers        "SampleAfterValue": "200003"
803da89c5SAndi Kleen    },
903da89c5SAndi Kleen    {
10*4ee19e31SIan Rogers        "BriefDescription": "Cycles code-fetch stalled due to an outstanding ITLB miss.",
1103da89c5SAndi Kleen        "EventCode": "0x86",
1203da89c5SAndi Kleen        "EventName": "FETCH_STALL.ITLB_FILL_PENDING_CYCLES",
13*4ee19e31SIan Rogers        "PublicDescription": "Counts cycles that fetch is stalled due to an outstanding ITLB miss. That is, the decoder queue is able to accept bytes, but the fetch unit is unable to provide bytes due to an ITLB miss.  Note: this event is not the same as page walk cycles to retrieve an instruction translation.",
1403da89c5SAndi Kleen        "SampleAfterValue": "200003",
15*4ee19e31SIan Rogers        "UMask": "0x1"
1603da89c5SAndi Kleen    },
1703da89c5SAndi Kleen    {
18*4ee19e31SIan Rogers        "BriefDescription": "Cycles hardware interrupts are masked",
1903da89c5SAndi Kleen        "EventCode": "0xCB",
2003da89c5SAndi Kleen        "EventName": "HW_INTERRUPTS.MASKED",
21*4ee19e31SIan Rogers        "PublicDescription": "Counts the number of core cycles during which interrupts are masked (disabled). Increments by 1 each core cycle that EFLAGS.IF is 0, regardless of whether interrupts are pending or not.",
224a00680bSAndi Kleen        "SampleAfterValue": "200003",
23*4ee19e31SIan Rogers        "UMask": "0x2"
244a00680bSAndi Kleen    },
254a00680bSAndi Kleen    {
26*4ee19e31SIan Rogers        "BriefDescription": "Cycles pending interrupts are masked",
27*4ee19e31SIan Rogers        "EventCode": "0xCB",
284a00680bSAndi Kleen        "EventName": "HW_INTERRUPTS.PENDING_AND_MASKED",
29*4ee19e31SIan Rogers        "PublicDescription": "Counts core cycles during which there are pending interrupts, but interrupts are masked (EFLAGS.IF = 0).",
304a00680bSAndi Kleen        "SampleAfterValue": "200003",
31*4ee19e31SIan Rogers        "UMask": "0x4"
32*4ee19e31SIan Rogers    },
33*4ee19e31SIan Rogers    {
34*4ee19e31SIan Rogers        "BriefDescription": "Hardware interrupts received",
35*4ee19e31SIan Rogers        "EventCode": "0xCB",
36*4ee19e31SIan Rogers        "EventName": "HW_INTERRUPTS.RECEIVED",
37*4ee19e31SIan Rogers        "PublicDescription": "Counts hardware interrupts received by the processor.",
38*4ee19e31SIan Rogers        "SampleAfterValue": "203",
39*4ee19e31SIan Rogers        "UMask": "0x1"
404a00680bSAndi Kleen    }
414a00680bSAndi Kleen]
42