1[
2    {
3        "BriefDescription": "Counts the number of machine clears due to memory ordering caused by a snoop from an external agent. Does not count internally generated machine clears such as those due to memory disambiguation.",
4        "EventCode": "0xc3",
5        "EventName": "MACHINE_CLEARS.MEMORY_ORDERING",
6        "SampleAfterValue": "20003",
7        "UMask": "0x2"
8    },
9    {
10        "BriefDescription": "Counts the number of misaligned load uops that are 4K page splits.",
11        "EventCode": "0x13",
12        "EventName": "MISALIGN_MEM_REF.LOAD_PAGE_SPLIT",
13        "PEBS": "1",
14        "SampleAfterValue": "200003",
15        "UMask": "0x2"
16    },
17    {
18        "BriefDescription": "Counts the number of misaligned store uops that are 4K page splits.",
19        "EventCode": "0x13",
20        "EventName": "MISALIGN_MEM_REF.STORE_PAGE_SPLIT",
21        "PEBS": "1",
22        "SampleAfterValue": "200003",
23        "UMask": "0x4"
24    },
25    {
26        "BriefDescription": "Counts all code reads that were not supplied by the L3 cache.",
27        "EventCode": "0XB7",
28        "EventName": "OCR.ALL_CODE_RD.L3_MISS",
29        "MSRIndex": "0x1a6,0x1a7",
30        "MSRValue": "0x2184000044",
31        "SampleAfterValue": "100003",
32        "UMask": "0x1"
33    },
34    {
35        "BriefDescription": "Counts all code reads that were not supplied by the L3 cache.",
36        "EventCode": "0XB7",
37        "EventName": "OCR.ALL_CODE_RD.L3_MISS_LOCAL",
38        "MSRIndex": "0x1a6,0x1a7",
39        "MSRValue": "0x2184000044",
40        "SampleAfterValue": "100003",
41        "UMask": "0x1"
42    },
43    {
44        "BriefDescription": "Counts modified writebacks from L1 cache and L2 cache that were not supplied by the L3 cache.",
45        "EventCode": "0XB7",
46        "EventName": "OCR.COREWB_M.L3_MISS",
47        "MSRIndex": "0x1a6,0x1a7",
48        "MSRValue": "0x3002184000000",
49        "SampleAfterValue": "100003",
50        "UMask": "0x1"
51    },
52    {
53        "BriefDescription": "Counts modified writebacks from L1 cache and L2 cache that were not supplied by the L3 cache.",
54        "EventCode": "0XB7",
55        "EventName": "OCR.COREWB_M.L3_MISS_LOCAL",
56        "MSRIndex": "0x1a6,0x1a7",
57        "MSRValue": "0x3002184000000",
58        "SampleAfterValue": "100003",
59        "UMask": "0x1"
60    },
61    {
62        "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that were not supplied by the L3 cache.",
63        "EventCode": "0XB7",
64        "EventName": "OCR.DEMAND_CODE_RD.L3_MISS",
65        "MSRIndex": "0x1a6,0x1a7",
66        "MSRValue": "0x2184000004",
67        "SampleAfterValue": "100003",
68        "UMask": "0x1"
69    },
70    {
71        "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that were not supplied by the L3 cache.",
72        "EventCode": "0XB7",
73        "EventName": "OCR.DEMAND_CODE_RD.L3_MISS_LOCAL",
74        "MSRIndex": "0x1a6,0x1a7",
75        "MSRValue": "0x2184000004",
76        "SampleAfterValue": "100003",
77        "UMask": "0x1"
78    },
79    {
80        "BriefDescription": "Counts cacheable demand data reads, L1 data cache hardware prefetches and software prefetches (except PREFETCHW) that were not supplied by the L3 cache.",
81        "EventCode": "0XB7",
82        "EventName": "OCR.DEMAND_DATA_AND_L1PF_RD.L3_MISS",
83        "MSRIndex": "0x1a6,0x1a7",
84        "MSRValue": "0x2184000001",
85        "SampleAfterValue": "100003",
86        "UMask": "0x1"
87    },
88    {
89        "BriefDescription": "Counts cacheable demand data reads, L1 data cache hardware prefetches and software prefetches (except PREFETCHW) that were not supplied by the L3 cache.",
90        "EventCode": "0XB7",
91        "EventName": "OCR.DEMAND_DATA_AND_L1PF_RD.L3_MISS_LOCAL",
92        "MSRIndex": "0x1a6,0x1a7",
93        "MSRValue": "0x2184000001",
94        "SampleAfterValue": "100003",
95        "UMask": "0x1"
96    },
97    {
98        "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_AND_L1PF_RD.L3_MISS",
99        "EventCode": "0XB7",
100        "EventName": "OCR.DEMAND_DATA_RD.L3_MISS",
101        "MSRIndex": "0x1a6,0x1a7",
102        "MSRValue": "0x2184000001",
103        "SampleAfterValue": "100003",
104        "UMask": "0x1"
105    },
106    {
107        "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_AND_L1PF_RD.L3_MISS_LOCAL",
108        "EventCode": "0XB7",
109        "EventName": "OCR.DEMAND_DATA_RD.L3_MISS_LOCAL",
110        "MSRIndex": "0x1a6,0x1a7",
111        "MSRValue": "0x2184000001",
112        "SampleAfterValue": "100003",
113        "UMask": "0x1"
114    },
115    {
116        "BriefDescription": "Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were not supplied by the L3 cache.",
117        "EventCode": "0XB7",
118        "EventName": "OCR.DEMAND_RFO.L3_MISS",
119        "MSRIndex": "0x1a6,0x1a7",
120        "MSRValue": "0x2184000002",
121        "SampleAfterValue": "100003",
122        "UMask": "0x1"
123    },
124    {
125        "BriefDescription": "Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were not supplied by the L3 cache.",
126        "EventCode": "0XB7",
127        "EventName": "OCR.DEMAND_RFO.L3_MISS_LOCAL",
128        "MSRIndex": "0x1a6,0x1a7",
129        "MSRValue": "0x2184000002",
130        "SampleAfterValue": "100003",
131        "UMask": "0x1"
132    },
133    {
134        "BriefDescription": "Counts streaming stores which modify a full 64 byte cacheline that were not supplied by the L3 cache.",
135        "EventCode": "0XB7",
136        "EventName": "OCR.FULL_STREAMING_WR.L3_MISS",
137        "MSRIndex": "0x1a6,0x1a7",
138        "MSRValue": "0x802184000000",
139        "SampleAfterValue": "100003",
140        "UMask": "0x1"
141    },
142    {
143        "BriefDescription": "Counts streaming stores which modify a full 64 byte cacheline that were not supplied by the L3 cache.",
144        "EventCode": "0XB7",
145        "EventName": "OCR.FULL_STREAMING_WR.L3_MISS_LOCAL",
146        "MSRIndex": "0x1a6,0x1a7",
147        "MSRValue": "0x802184000000",
148        "SampleAfterValue": "100003",
149        "UMask": "0x1"
150    },
151    {
152        "BriefDescription": "Counts L2 cache hardware prefetch code reads (written to the L2 cache only) that were not supplied by the L3 cache.",
153        "EventCode": "0XB7",
154        "EventName": "OCR.HWPF_L2_CODE_RD.L3_MISS",
155        "MSRIndex": "0x1a6,0x1a7",
156        "MSRValue": "0x2184000040",
157        "SampleAfterValue": "100003",
158        "UMask": "0x1"
159    },
160    {
161        "BriefDescription": "Counts L2 cache hardware prefetch code reads (written to the L2 cache only) that were not supplied by the L3 cache.",
162        "EventCode": "0XB7",
163        "EventName": "OCR.HWPF_L2_CODE_RD.L3_MISS_LOCAL",
164        "MSRIndex": "0x1a6,0x1a7",
165        "MSRValue": "0x2184000040",
166        "SampleAfterValue": "100003",
167        "UMask": "0x1"
168    },
169    {
170        "BriefDescription": "Counts L2 cache hardware prefetch data reads (written to the L2 cache only) that were not supplied by the L3 cache.",
171        "EventCode": "0XB7",
172        "EventName": "OCR.HWPF_L2_DATA_RD.L3_MISS",
173        "MSRIndex": "0x1a6,0x1a7",
174        "MSRValue": "0x2184000010",
175        "SampleAfterValue": "100003",
176        "UMask": "0x1"
177    },
178    {
179        "BriefDescription": "Counts L2 cache hardware prefetch data reads (written to the L2 cache only) that were not supplied by the L3 cache.",
180        "EventCode": "0XB7",
181        "EventName": "OCR.HWPF_L2_DATA_RD.L3_MISS_LOCAL",
182        "MSRIndex": "0x1a6,0x1a7",
183        "MSRValue": "0x2184000010",
184        "SampleAfterValue": "100003",
185        "UMask": "0x1"
186    },
187    {
188        "BriefDescription": "Counts L2 cache hardware prefetch RFOs (written to the L2 cache only) that were not supplied by the L3 cache.",
189        "EventCode": "0XB7",
190        "EventName": "OCR.HWPF_L2_RFO.L3_MISS",
191        "MSRIndex": "0x1a6,0x1a7",
192        "MSRValue": "0x2184000020",
193        "SampleAfterValue": "100003",
194        "UMask": "0x1"
195    },
196    {
197        "BriefDescription": "Counts L2 cache hardware prefetch RFOs (written to the L2 cache only) that were not supplied by the L3 cache.",
198        "EventCode": "0XB7",
199        "EventName": "OCR.HWPF_L2_RFO.L3_MISS_LOCAL",
200        "MSRIndex": "0x1a6,0x1a7",
201        "MSRValue": "0x2184000020",
202        "SampleAfterValue": "100003",
203        "UMask": "0x1"
204    },
205    {
206        "BriefDescription": "Counts modified writebacks from L1 cache that miss the L2 cache that were not supplied by the L3 cache.",
207        "EventCode": "0XB7",
208        "EventName": "OCR.L1WB_M.L3_MISS",
209        "MSRIndex": "0x1a6,0x1a7",
210        "MSRValue": "0x1002184000000",
211        "SampleAfterValue": "100003",
212        "UMask": "0x1"
213    },
214    {
215        "BriefDescription": "Counts modified writebacks from L1 cache that miss the L2 cache that were not supplied by the L3 cache.",
216        "EventCode": "0XB7",
217        "EventName": "OCR.L1WB_M.L3_MISS_LOCAL",
218        "MSRIndex": "0x1a6,0x1a7",
219        "MSRValue": "0x1002184000000",
220        "SampleAfterValue": "100003",
221        "UMask": "0x1"
222    },
223    {
224        "BriefDescription": "Counts modified writeBacks from L2 cache that miss the L3 cache that were not supplied by the L3 cache.",
225        "EventCode": "0XB7",
226        "EventName": "OCR.L2WB_M.L3_MISS",
227        "MSRIndex": "0x1a6,0x1a7",
228        "MSRValue": "0x2002184000000",
229        "SampleAfterValue": "100003",
230        "UMask": "0x1"
231    },
232    {
233        "BriefDescription": "Counts modified writeBacks from L2 cache that miss the L3 cache that were not supplied by the L3 cache.",
234        "EventCode": "0XB7",
235        "EventName": "OCR.L2WB_M.L3_MISS_LOCAL",
236        "MSRIndex": "0x1a6,0x1a7",
237        "MSRValue": "0x2002184000000",
238        "SampleAfterValue": "100003",
239        "UMask": "0x1"
240    },
241    {
242        "BriefDescription": "Counts miscellaneous requests, such as I/O accesses, that were not supplied by the L3 cache.",
243        "EventCode": "0XB7",
244        "EventName": "OCR.OTHER.L3_MISS",
245        "MSRIndex": "0x1a6,0x1a7",
246        "MSRValue": "0x2184008000",
247        "SampleAfterValue": "100003",
248        "UMask": "0x1"
249    },
250    {
251        "BriefDescription": "Counts miscellaneous requests, such as I/O accesses, that were not supplied by the L3 cache.",
252        "EventCode": "0XB7",
253        "EventName": "OCR.OTHER.L3_MISS_LOCAL",
254        "MSRIndex": "0x1a6,0x1a7",
255        "MSRValue": "0x2184008000",
256        "SampleAfterValue": "100003",
257        "UMask": "0x1"
258    },
259    {
260        "BriefDescription": "Counts streaming stores which modify only part of a 64 byte cacheline that were not supplied by the L3 cache.",
261        "EventCode": "0XB7",
262        "EventName": "OCR.PARTIAL_STREAMING_WR.L3_MISS",
263        "MSRIndex": "0x1a6,0x1a7",
264        "MSRValue": "0x402184000000",
265        "SampleAfterValue": "100003",
266        "UMask": "0x1"
267    },
268    {
269        "BriefDescription": "Counts streaming stores which modify only part of a 64 byte cacheline that were not supplied by the L3 cache.",
270        "EventCode": "0XB7",
271        "EventName": "OCR.PARTIAL_STREAMING_WR.L3_MISS_LOCAL",
272        "MSRIndex": "0x1a6,0x1a7",
273        "MSRValue": "0x402184000000",
274        "SampleAfterValue": "100003",
275        "UMask": "0x1"
276    },
277    {
278        "BriefDescription": "Counts all hardware and software prefetches that were not supplied by the L3 cache.",
279        "EventCode": "0XB7",
280        "EventName": "OCR.PREFETCHES.L3_MISS",
281        "MSRIndex": "0x1a6,0x1a7",
282        "MSRValue": "0x2184000470",
283        "SampleAfterValue": "100003",
284        "UMask": "0x1"
285    },
286    {
287        "BriefDescription": "Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were not supplied by the L3 cache.",
288        "EventCode": "0XB7",
289        "EventName": "OCR.READS_TO_CORE.L3_MISS",
290        "MSRIndex": "0x1a6,0x1a7",
291        "MSRValue": "0x2184000477",
292        "SampleAfterValue": "100003",
293        "UMask": "0x1"
294    },
295    {
296        "BriefDescription": "Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were not supplied by the L3 cache.",
297        "EventCode": "0XB7",
298        "EventName": "OCR.READS_TO_CORE.L3_MISS_LOCAL",
299        "MSRIndex": "0x1a6,0x1a7",
300        "MSRValue": "0x2184000477",
301        "SampleAfterValue": "100003",
302        "UMask": "0x1"
303    },
304    {
305        "BriefDescription": "Counts streaming stores that were not supplied by the L3 cache.",
306        "EventCode": "0XB7",
307        "EventName": "OCR.STREAMING_WR.L3_MISS",
308        "MSRIndex": "0x1a6,0x1a7",
309        "MSRValue": "0x2184000800",
310        "SampleAfterValue": "100003",
311        "UMask": "0x1"
312    },
313    {
314        "BriefDescription": "Counts streaming stores that were not supplied by the L3 cache.",
315        "EventCode": "0XB7",
316        "EventName": "OCR.STREAMING_WR.L3_MISS_LOCAL",
317        "MSRIndex": "0x1a6,0x1a7",
318        "MSRValue": "0x2184000800",
319        "SampleAfterValue": "100003",
320        "UMask": "0x1"
321    },
322    {
323        "BriefDescription": "Counts uncached memory reads that were not supplied by the L3 cache.",
324        "EventCode": "0XB7",
325        "EventName": "OCR.UC_RD.L3_MISS",
326        "MSRIndex": "0x1a6,0x1a7",
327        "MSRValue": "0x102184000000",
328        "SampleAfterValue": "100003",
329        "UMask": "0x1"
330    },
331    {
332        "BriefDescription": "Counts uncached memory reads that were not supplied by the L3 cache.",
333        "EventCode": "0XB7",
334        "EventName": "OCR.UC_RD.L3_MISS_LOCAL",
335        "MSRIndex": "0x1a6,0x1a7",
336        "MSRValue": "0x102184000000",
337        "SampleAfterValue": "100003",
338        "UMask": "0x1"
339    },
340    {
341        "BriefDescription": "Counts uncached memory writes that were not supplied by the L3 cache.",
342        "EventCode": "0XB7",
343        "EventName": "OCR.UC_WR.L3_MISS",
344        "MSRIndex": "0x1a6,0x1a7",
345        "MSRValue": "0x202184000000",
346        "SampleAfterValue": "100003",
347        "UMask": "0x1"
348    },
349    {
350        "BriefDescription": "Counts uncached memory writes that were not supplied by the L3 cache.",
351        "EventCode": "0XB7",
352        "EventName": "OCR.UC_WR.L3_MISS_LOCAL",
353        "MSRIndex": "0x1a6,0x1a7",
354        "MSRValue": "0x202184000000",
355        "SampleAfterValue": "100003",
356        "UMask": "0x1"
357    }
358]
359