1*aa1bd892SJin Yao[ 2*aa1bd892SJin Yao { 3*aa1bd892SJin Yao "BriefDescription": "Counts the number of memory ordering machine clears triggered by a snoop from an external agent.", 4*aa1bd892SJin Yao "CollectPEBSRecord": "2", 5*aa1bd892SJin Yao "Counter": "0,1,2,3", 6*aa1bd892SJin Yao "EventCode": "0xc3", 7*aa1bd892SJin Yao "EventName": "MACHINE_CLEARS.MEMORY_ORDERING", 8*aa1bd892SJin Yao "PDIR_COUNTER": "na", 9*aa1bd892SJin Yao "PEBScounters": "0,1,2,3", 10*aa1bd892SJin Yao "PublicDescription": "Counts the number of memory ordering machine clears triggered by a snoop from an external agent. Does not count internally generated machine clears such as those due to disambiguations.", 11*aa1bd892SJin Yao "SampleAfterValue": "20003", 12*aa1bd892SJin Yao "UMask": "0x2" 13*aa1bd892SJin Yao }, 14*aa1bd892SJin Yao { 15*aa1bd892SJin Yao "BriefDescription": "Counts cacheable demand data reads, L1 data cache hardware prefetches and software prefetches (except PREFETCHW) that were not supplied by the L3 cache.", 16*aa1bd892SJin Yao "Counter": "0,1,2,3", 17*aa1bd892SJin Yao "EventCode": "0XB7", 18*aa1bd892SJin Yao "EventName": "OCR.DEMAND_DATA_AND_L1PF_RD.L3_MISS", 19*aa1bd892SJin Yao "MSRIndex": "0x1a6,0x1a7", 20*aa1bd892SJin Yao "MSRValue": "0x2104000001", 21*aa1bd892SJin Yao "Offcore": "1", 22*aa1bd892SJin Yao "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 23*aa1bd892SJin Yao "SampleAfterValue": "100003", 24*aa1bd892SJin Yao "UMask": "0x1" 25*aa1bd892SJin Yao }, 26*aa1bd892SJin Yao { 27*aa1bd892SJin Yao "BriefDescription": "Counts cacheable demand data reads, L1 data cache hardware prefetches and software prefetches (except PREFETCHW) that were not supplied by the L3 cache.", 28*aa1bd892SJin Yao "Counter": "0,1,2,3", 29*aa1bd892SJin Yao "EventCode": "0XB7", 30*aa1bd892SJin Yao "EventName": "OCR.DEMAND_DATA_AND_L1PF_RD.L3_MISS_LOCAL", 31*aa1bd892SJin Yao "MSRIndex": "0x1a6,0x1a7", 32*aa1bd892SJin Yao "MSRValue": "0x2104000001", 33*aa1bd892SJin Yao "Offcore": "1", 34*aa1bd892SJin Yao "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 35*aa1bd892SJin Yao "SampleAfterValue": "100003", 36*aa1bd892SJin Yao "UMask": "0x1" 37*aa1bd892SJin Yao }, 38*aa1bd892SJin Yao { 39*aa1bd892SJin Yao "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_AND_L1PF_RD.L3_MISS", 40*aa1bd892SJin Yao "Counter": "0,1,2,3", 41*aa1bd892SJin Yao "EventCode": "0XB7", 42*aa1bd892SJin Yao "EventName": "OCR.DEMAND_DATA_RD.L3_MISS", 43*aa1bd892SJin Yao "MSRIndex": "0x1a6,0x1a7", 44*aa1bd892SJin Yao "MSRValue": "0x2104000001", 45*aa1bd892SJin Yao "Offcore": "1", 46*aa1bd892SJin Yao "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 47*aa1bd892SJin Yao "SampleAfterValue": "100003", 48*aa1bd892SJin Yao "UMask": "0x1" 49*aa1bd892SJin Yao }, 50*aa1bd892SJin Yao { 51*aa1bd892SJin Yao "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_AND_L1PF_RD.L3_MISS_LOCAL", 52*aa1bd892SJin Yao "Counter": "0,1,2,3", 53*aa1bd892SJin Yao "EventCode": "0XB7", 54*aa1bd892SJin Yao "EventName": "OCR.DEMAND_DATA_RD.L3_MISS_LOCAL", 55*aa1bd892SJin Yao "MSRIndex": "0x1a6,0x1a7", 56*aa1bd892SJin Yao "MSRValue": "0x2104000001", 57*aa1bd892SJin Yao "Offcore": "1", 58*aa1bd892SJin Yao "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 59*aa1bd892SJin Yao "SampleAfterValue": "100003", 60*aa1bd892SJin Yao "UMask": "0x1" 61*aa1bd892SJin Yao }, 62*aa1bd892SJin Yao { 63*aa1bd892SJin Yao "BriefDescription": "Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were not supplied by the L3 cache.", 64*aa1bd892SJin Yao "Counter": "0,1,2,3", 65*aa1bd892SJin Yao "EventCode": "0XB7", 66*aa1bd892SJin Yao "EventName": "OCR.DEMAND_RFO.L3_MISS", 67*aa1bd892SJin Yao "MSRIndex": "0x1a6,0x1a7", 68*aa1bd892SJin Yao "MSRValue": "0x2104000002", 69*aa1bd892SJin Yao "Offcore": "1", 70*aa1bd892SJin Yao "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 71*aa1bd892SJin Yao "SampleAfterValue": "100003", 72*aa1bd892SJin Yao "UMask": "0x1" 73*aa1bd892SJin Yao }, 74*aa1bd892SJin Yao { 75*aa1bd892SJin Yao "BriefDescription": "Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were not supplied by the L3 cache.", 76*aa1bd892SJin Yao "Counter": "0,1,2,3", 77*aa1bd892SJin Yao "EventCode": "0XB7", 78*aa1bd892SJin Yao "EventName": "OCR.DEMAND_RFO.L3_MISS_LOCAL", 79*aa1bd892SJin Yao "MSRIndex": "0x1a6,0x1a7", 80*aa1bd892SJin Yao "MSRValue": "0x2104000002", 81*aa1bd892SJin Yao "Offcore": "1", 82*aa1bd892SJin Yao "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 83*aa1bd892SJin Yao "SampleAfterValue": "100003", 84*aa1bd892SJin Yao "UMask": "0x1" 85*aa1bd892SJin Yao } 86*aa1bd892SJin Yao]