1[
2    {
3        "EventCode": "0x08",
4        "UMask": "0x1",
5        "BriefDescription": "Load misses in all DTLB levels that cause page walks",
6        "Counter": "0,1,2,3",
7        "EventName": "DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK",
8        "PublicDescription": "Counts demand data loads that caused a page walk of any page size (4K/2M/4M/1G). This implies it missed in all TLB levels, but the walk need not have completed.",
9        "SampleAfterValue": "100003",
10        "CounterHTOff": "0,1,2,3,4,5,6,7"
11    },
12    {
13        "EventCode": "0x08",
14        "UMask": "0x2",
15        "BriefDescription": "Page walk completed due to a demand data load to a 4K page",
16        "Counter": "0,1,2,3",
17        "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_4K",
18        "PublicDescription": "Counts page walks completed due to demand data loads whose address translations missed in the TLB and were mapped to 4K pages.  The page walks can end with or without a page fault.",
19        "SampleAfterValue": "2000003",
20        "CounterHTOff": "0,1,2,3,4,5,6,7"
21    },
22    {
23        "EventCode": "0x08",
24        "UMask": "0x4",
25        "BriefDescription": "Page walk completed due to a demand data load to a 2M/4M page",
26        "Counter": "0,1,2,3",
27        "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M",
28        "PublicDescription": "Counts page walks completed due to demand data loads whose address translations missed in the TLB and were mapped to 2M/4M pages.  The page walks can end with or without a page fault.",
29        "SampleAfterValue": "2000003",
30        "CounterHTOff": "0,1,2,3,4,5,6,7"
31    },
32    {
33        "EventCode": "0x08",
34        "UMask": "0x8",
35        "BriefDescription": "Page walk completed due to a demand data load to a 1G page",
36        "Counter": "0,1,2,3",
37        "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_1G",
38        "PublicDescription": "Counts page walks completed due to demand data loads whose address translations missed in the TLB and were mapped to 4K pages.  The page walks can end with or without a page fault.",
39        "SampleAfterValue": "2000003",
40        "CounterHTOff": "0,1,2,3,4,5,6,7"
41    },
42    {
43        "EventCode": "0x08",
44        "UMask": "0xe",
45        "BriefDescription": "Load miss in all TLB levels causes a page walk that completes. (All page sizes)",
46        "Counter": "0,1,2,3",
47        "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED",
48        "PublicDescription": "Counts demand data loads that caused a completed page walk of any page size (4K/2M/4M/1G). This implies it missed in all TLB levels. The page walk can end with or without a fault.",
49        "SampleAfterValue": "100003",
50        "CounterHTOff": "0,1,2,3,4,5,6,7"
51    },
52    {
53        "EventCode": "0x08",
54        "UMask": "0x10",
55        "BriefDescription": "Counts 1 per cycle for each PMH that is busy with a page walk for a load. EPT page walk duration are excluded in Skylake.",
56        "Counter": "0,1,2,3",
57        "EventName": "DTLB_LOAD_MISSES.WALK_PENDING",
58        "PublicDescription": "Counts 1 per cycle for each PMH that is busy with a page walk for a load. EPT page walk duration are excluded in Skylake microarchitecture.",
59        "SampleAfterValue": "2000003",
60        "CounterHTOff": "0,1,2,3,4,5,6,7"
61    },
62    {
63        "EventCode": "0x08",
64        "UMask": "0x10",
65        "BriefDescription": "Cycles when at least one PMH is busy with a page walk for a load. EPT page walk duration are excluded in Skylake.",
66        "Counter": "0,1,2,3",
67        "EventName": "DTLB_LOAD_MISSES.WALK_ACTIVE",
68        "CounterMask": "1",
69        "PublicDescription": "Counts cycles when at least one PMH (Page Miss Handler) is busy with a page walk for a load.",
70        "SampleAfterValue": "100003",
71        "CounterHTOff": "0,1,2,3,4,5,6,7"
72    },
73    {
74        "EventCode": "0x08",
75        "UMask": "0x20",
76        "BriefDescription": "Loads that miss the DTLB and hit the STLB.",
77        "Counter": "0,1,2,3",
78        "EventName": "DTLB_LOAD_MISSES.STLB_HIT",
79        "PublicDescription": "Counts loads that miss the DTLB (Data TLB) and hit the STLB (Second level TLB).",
80        "SampleAfterValue": "2000003",
81        "CounterHTOff": "0,1,2,3,4,5,6,7"
82    },
83    {
84        "EventCode": "0x49",
85        "UMask": "0x1",
86        "BriefDescription": "Store misses in all DTLB levels that cause page walks",
87        "Counter": "0,1,2,3",
88        "EventName": "DTLB_STORE_MISSES.MISS_CAUSES_A_WALK",
89        "PublicDescription": "Counts demand data stores that caused a page walk of any page size (4K/2M/4M/1G). This implies it missed in all TLB levels, but the walk need not have completed.",
90        "SampleAfterValue": "100003",
91        "CounterHTOff": "0,1,2,3,4,5,6,7"
92    },
93    {
94        "EventCode": "0x49",
95        "UMask": "0x2",
96        "BriefDescription": "Page walk completed due to a demand data store to a 4K page",
97        "Counter": "0,1,2,3",
98        "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_4K",
99        "PublicDescription": "Counts page walks completed due to demand data stores whose address translations missed in the TLB and were mapped to 4K pages.  The page walks can end with or without a page fault.",
100        "SampleAfterValue": "100003",
101        "CounterHTOff": "0,1,2,3,4,5,6,7"
102    },
103    {
104        "EventCode": "0x49",
105        "UMask": "0x4",
106        "BriefDescription": "Page walk completed due to a demand data store to a 2M/4M page",
107        "Counter": "0,1,2,3",
108        "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_2M_4M",
109        "PublicDescription": "Counts page walks completed due to demand data stores whose address translations missed in the TLB and were mapped to 2M/4M pages.  The page walks can end with or without a page fault.",
110        "SampleAfterValue": "100003",
111        "CounterHTOff": "0,1,2,3,4,5,6,7"
112    },
113    {
114        "EventCode": "0x49",
115        "UMask": "0x8",
116        "BriefDescription": "Page walk completed due to a demand data store to a 1G page",
117        "Counter": "0,1,2,3",
118        "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_1G",
119        "PublicDescription": "Counts page walks completed due to demand data stores whose address translations missed in the TLB and were mapped to 1G pages.  The page walks can end with or without a page fault.",
120        "SampleAfterValue": "100003",
121        "CounterHTOff": "0,1,2,3,4,5,6,7"
122    },
123    {
124        "EventCode": "0x49",
125        "UMask": "0xe",
126        "BriefDescription": "Store misses in all TLB levels causes a page walk that completes. (All page sizes)",
127        "Counter": "0,1,2,3",
128        "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED",
129        "PublicDescription": "Counts demand data stores that caused a completed page walk of any page size (4K/2M/4M/1G). This implies it missed in all TLB levels. The page walk can end with or without a fault.",
130        "SampleAfterValue": "100003",
131        "CounterHTOff": "0,1,2,3,4,5,6,7"
132    },
133    {
134        "EventCode": "0x49",
135        "UMask": "0x10",
136        "BriefDescription": "Counts 1 per cycle for each PMH that is busy with a page walk for a store. EPT page walk duration are excluded in Skylake.",
137        "Counter": "0,1,2,3",
138        "EventName": "DTLB_STORE_MISSES.WALK_PENDING",
139        "PublicDescription": "Counts 1 per cycle for each PMH that is busy with a page walk for a store. EPT page walk duration are excluded in Skylake microarchitecture.",
140        "SampleAfterValue": "2000003",
141        "CounterHTOff": "0,1,2,3,4,5,6,7"
142    },
143    {
144        "EventCode": "0x49",
145        "UMask": "0x10",
146        "BriefDescription": "Cycles when at least one PMH is busy with a page walk for a store. EPT page walk duration are excluded in Skylake.",
147        "Counter": "0,1,2,3",
148        "EventName": "DTLB_STORE_MISSES.WALK_ACTIVE",
149        "CounterMask": "1",
150        "PublicDescription": "Counts cycles when at least one PMH (Page Miss Handler) is busy with a page walk for a store.",
151        "SampleAfterValue": "100003",
152        "CounterHTOff": "0,1,2,3,4,5,6,7"
153    },
154    {
155        "EventCode": "0x49",
156        "UMask": "0x20",
157        "BriefDescription": "Stores that miss the DTLB and hit the STLB.",
158        "Counter": "0,1,2,3",
159        "EventName": "DTLB_STORE_MISSES.STLB_HIT",
160        "PublicDescription": "Stores that miss the DTLB (Data TLB) and hit the STLB (2nd Level TLB).",
161        "SampleAfterValue": "100003",
162        "CounterHTOff": "0,1,2,3,4,5,6,7"
163    },
164    {
165        "EventCode": "0x4F",
166        "UMask": "0x10",
167        "BriefDescription": "Counts 1 per cycle for each PMH that is busy with a EPT (Extended Page Table) walk for any request type.",
168        "Counter": "0,1,2,3",
169        "EventName": "EPT.WALK_PENDING",
170        "PublicDescription": "Counts cycles for each PMH (Page Miss Handler) that is busy with an EPT (Extended Page Table) walk for any request type.",
171        "SampleAfterValue": "2000003",
172        "CounterHTOff": "0,1,2,3,4,5,6,7"
173    },
174    {
175        "EventCode": "0x85",
176        "UMask": "0x1",
177        "BriefDescription": "Misses at all ITLB levels that cause page walks",
178        "Counter": "0,1,2,3",
179        "EventName": "ITLB_MISSES.MISS_CAUSES_A_WALK",
180        "PublicDescription": "Counts page walks of any page size (4K/2M/4M/1G) caused by a code fetch. This implies it missed in the ITLB and further levels of TLB, but the walk need not have completed.",
181        "SampleAfterValue": "100003",
182        "CounterHTOff": "0,1,2,3,4,5,6,7"
183    },
184    {
185        "EventCode": "0x85",
186        "UMask": "0x2",
187        "BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (4K)",
188        "Counter": "0,1,2,3",
189        "EventName": "ITLB_MISSES.WALK_COMPLETED_4K",
190        "PublicDescription": "Counts completed page walks (4K page size) caused by a code fetch. This implies it missed in the ITLB and further levels of TLB. The page walk can end with or without a fault.",
191        "SampleAfterValue": "100003",
192        "CounterHTOff": "0,1,2,3,4,5,6,7"
193    },
194    {
195        "EventCode": "0x85",
196        "UMask": "0x4",
197        "BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (2M/4M)",
198        "Counter": "0,1,2,3",
199        "EventName": "ITLB_MISSES.WALK_COMPLETED_2M_4M",
200        "PublicDescription": "Counts code misses in all ITLB levels that caused a completed page walk (2M and 4M page sizes). The page walk can end with or without a fault.",
201        "SampleAfterValue": "100003",
202        "CounterHTOff": "0,1,2,3,4,5,6,7"
203    },
204    {
205        "EventCode": "0x85",
206        "UMask": "0x8",
207        "BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (1G)",
208        "Counter": "0,1,2,3",
209        "EventName": "ITLB_MISSES.WALK_COMPLETED_1G",
210        "PublicDescription": "Counts store misses in all DTLB levels that cause a completed page walk (1G page size). The page walk can end with or without a fault.",
211        "SampleAfterValue": "100003",
212        "CounterHTOff": "0,1,2,3,4,5,6,7"
213    },
214    {
215        "EventCode": "0x85",
216        "UMask": "0xe",
217        "BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (All page sizes)",
218        "Counter": "0,1,2,3",
219        "EventName": "ITLB_MISSES.WALK_COMPLETED",
220        "PublicDescription": "Counts completed page walks (2M and 4M page sizes) caused by a code fetch. This implies it missed in the ITLB and further levels of TLB. The page walk can end with or without a fault.",
221        "SampleAfterValue": "100003",
222        "CounterHTOff": "0,1,2,3,4,5,6,7"
223    },
224    {
225        "EventCode": "0x85",
226        "UMask": "0x10",
227        "BriefDescription": "Counts 1 per cycle for each PMH that is busy with a page walk for an instruction fetch request. EPT page walk duration are excluded in Skylake.",
228        "Counter": "0,1,2,3",
229        "EventName": "ITLB_MISSES.WALK_PENDING",
230        "PublicDescription": "Counts 1 per cycle for each PMH (Page Miss Handler) that is busy with a page walk for an instruction fetch request. EPT page walk duration are excluded in Skylake michroarchitecture.",
231        "SampleAfterValue": "100003",
232        "CounterHTOff": "0,1,2,3,4,5,6,7"
233    },
234    {
235        "EventCode": "0x85",
236        "UMask": "0x10",
237        "BriefDescription": "Cycles when at least one PMH is busy with a page walk for code (instruction fetch) request. EPT page walk duration are excluded in Skylake.",
238        "MSRValue": "0x00",
239        "Counter": "0,1,2,3",
240        "EventName": "ITLB_MISSES.WALK_ACTIVE",
241        "CounterMask": "1",
242        "PublicDescription": "Cycles when at least one PMH is busy with a page walk for code (instruction fetch) request. EPT page walk duration are excluded in Skylake microarchitecture.",
243        "SampleAfterValue": "100003",
244        "CounterHTOff": "0,1,2,3,4,5,6,7"
245    },
246    {
247        "EventCode": "0x85",
248        "UMask": "0x20",
249        "BriefDescription": "Instruction fetch requests that miss the ITLB and hit the STLB.",
250        "Counter": "0,1,2,3",
251        "EventName": "ITLB_MISSES.STLB_HIT",
252        "SampleAfterValue": "100003",
253        "CounterHTOff": "0,1,2,3,4,5,6,7"
254    },
255    {
256        "EventCode": "0xAE",
257        "UMask": "0x1",
258        "BriefDescription": "Flushing of the Instruction TLB (ITLB) pages, includes 4k/2M/4M pages.",
259        "Counter": "0,1,2,3",
260        "EventName": "ITLB.ITLB_FLUSH",
261        "PublicDescription": "Counts the number of flushes of the big or small ITLB pages. Counting include both TLB Flush (covering all sets) and TLB Set Clear (set-specific).",
262        "SampleAfterValue": "100007",
263        "CounterHTOff": "0,1,2,3,4,5,6,7"
264    },
265    {
266        "EventCode": "0xBD",
267        "UMask": "0x1",
268        "BriefDescription": "DTLB flush attempts of the thread-specific entries",
269        "Counter": "0,1,2,3",
270        "EventName": "TLB_FLUSH.DTLB_THREAD",
271        "PublicDescription": "Counts the number of DTLB flush attempts of the thread-specific entries.",
272        "SampleAfterValue": "100007",
273        "CounterHTOff": "0,1,2,3,4,5,6,7"
274    },
275    {
276        "EventCode": "0xBD",
277        "UMask": "0x20",
278        "BriefDescription": "STLB flush attempts",
279        "Counter": "0,1,2,3",
280        "EventName": "TLB_FLUSH.STLB_ANY",
281        "PublicDescription": "Counts the number of any STLB flush attempts (such as entire, VPID, PCID, InvPage, CR3 write, etc.).",
282        "SampleAfterValue": "100007",
283        "CounterHTOff": "0,1,2,3,4,5,6,7"
284    }
285]