1[ 2 { 3 "BriefDescription": "DRAM Page Activate commands sent due to a write request", 4 "Counter": "0,1,2,3", 5 "EventCode": "0x1", 6 "EventName": "UNC_M_ACT_COUNT.WR", 7 "PerPkg": "1", 8 "UMask": "0x2", 9 "Unit": "iMC" 10 }, 11 { 12 "BriefDescription": "All DRAM Read CAS Commands issued (does not include underfills)", 13 "Counter": "0,1,2,3", 14 "EventCode": "0x4", 15 "EventName": "UNC_M_CAS_COUNT.RD_REG", 16 "PerPkg": "1", 17 "UMask": "0x1", 18 "Unit": "iMC" 19 }, 20 { 21 "BriefDescription": "DRAM Underfill Read CAS Commands issued", 22 "Counter": "0,1,2,3", 23 "EventCode": "0x4", 24 "EventName": "UNC_M_CAS_COUNT.RD_UNDERFILL", 25 "PerPkg": "1", 26 "UMask": "0x2", 27 "Unit": "iMC" 28 }, 29 { 30 "BriefDescription": "read requests to memory controller. Derived from unc_m_cas_count.rd", 31 "Counter": "0,1,2,3", 32 "EventCode": "0x4", 33 "EventName": "LLC_MISSES.MEM_READ", 34 "PerPkg": "1", 35 "ScaleUnit": "64Bytes", 36 "UMask": "0x3", 37 "Unit": "iMC" 38 }, 39 { 40 "BriefDescription": "read requests to memory controller", 41 "Counter": "0,1,2,3", 42 "EventCode": "0x4", 43 "EventName": "UNC_M_CAS_COUNT.RD", 44 "PerPkg": "1", 45 "ScaleUnit": "64Bytes", 46 "UMask": "0x3", 47 "Unit": "iMC" 48 }, 49 { 50 "BriefDescription": "DRAM CAS (Column Address Strobe) Commands.; DRAM WR_CAS (w/ and w/out auto-pre) in Write Major Mode", 51 "Counter": "0,1,2,3", 52 "EventCode": "0x4", 53 "EventName": "UNC_M_CAS_COUNT.WR_WMM", 54 "PerPkg": "1", 55 "UMask": "0x4", 56 "Unit": "iMC" 57 }, 58 { 59 "BriefDescription": "write requests to memory controller. Derived from unc_m_cas_count.wr", 60 "Counter": "0,1,2,3", 61 "EventCode": "0x4", 62 "EventName": "LLC_MISSES.MEM_WRITE", 63 "PerPkg": "1", 64 "ScaleUnit": "64Bytes", 65 "UMask": "0xC", 66 "Unit": "iMC" 67 }, 68 { 69 "BriefDescription": "write requests to memory controller", 70 "Counter": "0,1,2,3", 71 "EventCode": "0x4", 72 "EventName": "UNC_M_CAS_COUNT.WR", 73 "PerPkg": "1", 74 "ScaleUnit": "64Bytes", 75 "UMask": "0xC", 76 "Unit": "iMC" 77 }, 78 { 79 "BriefDescription": "All DRAM CAS Commands issued", 80 "Counter": "0,1,2,3", 81 "EventCode": "0x4", 82 "EventName": "UNC_M_CAS_COUNT.ALL", 83 "PerPkg": "1", 84 "UMask": "0xF", 85 "Unit": "iMC" 86 }, 87 { 88 "BriefDescription": "Memory controller clock ticks", 89 "Counter": "0,1,2,3", 90 "EventName": "UNC_M_CLOCKTICKS", 91 "PerPkg": "1", 92 "Unit": "iMC" 93 }, 94 { 95 "BriefDescription": "Cycles where DRAM ranks are in power down (CKE) mode+C37", 96 "Counter": "0,1,2,3", 97 "EventCode": "0x85", 98 "EventName": "UNC_M_POWER_CHANNEL_PPD", 99 "MetricExpr": "(UNC_M_POWER_CHANNEL_PPD / UNC_M_CLOCKTICKS) * 100.", 100 "MetricName": "power_channel_ppd %", 101 "PerPkg": "1", 102 "Unit": "iMC" 103 }, 104 { 105 "BriefDescription": "Cycles Memory is in self refresh power mode", 106 "Counter": "0,1,2,3", 107 "EventCode": "0x43", 108 "EventName": "UNC_M_POWER_SELF_REFRESH", 109 "MetricExpr": "(UNC_M_POWER_SELF_REFRESH / UNC_M_CLOCKTICKS) * 100.", 110 "MetricName": "power_self_refresh %", 111 "PerPkg": "1", 112 "Unit": "iMC" 113 }, 114 { 115 "BriefDescription": "Pre-charges due to page misses", 116 "Counter": "0,1,2,3", 117 "EventCode": "0x2", 118 "EventName": "UNC_M_PRE_COUNT.PAGE_MISS", 119 "PerPkg": "1", 120 "UMask": "0x1", 121 "Unit": "iMC" 122 }, 123 { 124 "BriefDescription": "Pre-charge for reads", 125 "Counter": "0,1,2,3", 126 "EventCode": "0x2", 127 "EventName": "UNC_M_PRE_COUNT.RD", 128 "PerPkg": "1", 129 "UMask": "0x4", 130 "Unit": "iMC" 131 }, 132 { 133 "BriefDescription": "Read Pending Queue Allocations", 134 "Counter": "0,1,2,3", 135 "EventCode": "0x10", 136 "EventName": "UNC_M_RPQ_INSERTS", 137 "PerPkg": "1", 138 "Unit": "iMC" 139 }, 140 { 141 "BriefDescription": "Read Pending Queue Occupancy", 142 "Counter": "0,1,2,3", 143 "EventCode": "0x80", 144 "EventName": "UNC_M_RPQ_OCCUPANCY", 145 "PerPkg": "1", 146 "Unit": "iMC" 147 }, 148 { 149 "BriefDescription": "All hits to Near Memory(DRAM cache) in Memory Mode", 150 "Counter": "0,1,2,3", 151 "EventCode": "0xD3", 152 "EventName": "UNC_M_TAGCHK.HIT", 153 "PerPkg": "1", 154 "UMask": "0x1", 155 "Unit": "iMC" 156 }, 157 { 158 "BriefDescription": "All Clean line misses to Near Memory(DRAM cache) in Memory Mode", 159 "Counter": "0,1,2,3", 160 "EventCode": "0xD3", 161 "EventName": "UNC_M_TAGCHK.MISS_CLEAN", 162 "PerPkg": "1", 163 "UMask": "0x2", 164 "Unit": "iMC" 165 }, 166 { 167 "BriefDescription": "All dirty line misses to Near Memory(DRAM cache) in Memory Mode", 168 "Counter": "0,1,2,3", 169 "EventCode": "0xD3", 170 "EventName": "UNC_M_TAGCHK.MISS_DIRTY", 171 "PerPkg": "1", 172 "UMask": "0x4", 173 "Unit": "iMC" 174 }, 175 { 176 "BriefDescription": "Write Pending Queue Allocations", 177 "Counter": "0,1,2,3", 178 "EventCode": "0x20", 179 "EventName": "UNC_M_WPQ_INSERTS", 180 "PerPkg": "1", 181 "Unit": "iMC" 182 }, 183 { 184 "BriefDescription": "Write Pending Queue Occupancy", 185 "Counter": "0,1,2,3", 186 "EventCode": "0x81", 187 "EventName": "UNC_M_WPQ_OCCUPANCY", 188 "PerPkg": "1", 189 "Unit": "iMC" 190 }, 191 { 192 "BriefDescription": "Read Pending Queue Occupancy of all read requests for Intel Optane DC persistent memory", 193 "Counter": "0,1,2,3", 194 "EventCode": "0xE0", 195 "EventName": "UNC_M_PMM_RPQ_OCCUPANCY.ALL", 196 "PerPkg": "1", 197 "UMask": "0x1", 198 "Unit": "iMC" 199 }, 200 { 201 "BriefDescription": "Intel Optane DC persistent memory read latency (ns). Derived from unc_m_pmm_rpq_occupancy.all", 202 "Counter": "0,1,2,3", 203 "EventCode": "0xE0", 204 "EventName": "UNC_M_PMM_READ_LATENCY", 205 "MetricExpr": "UNC_M_PMM_RPQ_OCCUPANCY.ALL / UNC_M_PMM_RPQ_INSERTS / UNC_M_CLOCKTICKS", 206 "MetricName": "UNC_M_PMM_READ_LATENCY", 207 "PerPkg": "1", 208 "ScaleUnit": "6000000000ns", 209 "UMask": "0x1", 210 "Unit": "iMC" 211 }, 212 { 213 "BriefDescription": "Write requests allocated in the PMM Write Pending Queue for Intel Optane DC persistent memory", 214 "Counter": "0,1,2,3", 215 "EventCode": "0xE3", 216 "EventName": "UNC_M_PMM_RPQ_INSERTS", 217 "PerPkg": "1", 218 "Unit": "iMC" 219 }, 220 { 221 "BriefDescription": "Intel Optane DC persistent memory bandwidth read (MB/sec). Derived from unc_m_pmm_rpq_inserts", 222 "Counter": "0,1,2,3", 223 "EventCode": "0xE3", 224 "EventName": "UNC_M_PMM_BANDWIDTH.READ", 225 "PerPkg": "1", 226 "ScaleUnit": "6.103515625E-5MB/sec", 227 "Unit": "iMC" 228 }, 229 { 230 "BriefDescription": "Intel Optane DC persistent memory bandwidth total (MB/sec). Derived from unc_m_pmm_rpq_inserts", 231 "Counter": "0,1,2,3", 232 "EventCode": "0xE3", 233 "EventName": "UNC_M_PMM_BANDWIDTH.TOTAL", 234 "MetricExpr": "UNC_M_PMM_RPQ_INSERTS + UNC_M_PMM_WPQ_INSERTS", 235 "MetricName": "UNC_M_PMM_BANDWIDTH.TOTAL", 236 "PerPkg": "1", 237 "ScaleUnit": "6.103515625E-5MB/sec", 238 "Unit": "iMC" 239 }, 240 { 241 "BriefDescription": "All commands for Intel Optane DC persistent memory", 242 "Counter": "0,1,2,3", 243 "EventCode": "0xEA", 244 "EventName": "UNC_M_PMM_CMD1.ALL", 245 "PerPkg": "1", 246 "UMask": "0x1", 247 "Unit": "iMC" 248 }, 249 { 250 "BriefDescription": "Regular reads(RPQ) commands for Intel Optane DC persistent memory", 251 "Counter": "0,1,2,3", 252 "EventCode": "0xEA", 253 "EventName": "UNC_M_PMM_CMD1.RD", 254 "PerPkg": "1", 255 "UMask": "0x2", 256 "Unit": "iMC" 257 }, 258 { 259 "BriefDescription": "Write commands for Intel Optane DC persistent memory", 260 "Counter": "0,1,2,3", 261 "EventCode": "0xEA", 262 "EventName": "UNC_M_PMM_CMD1.WR", 263 "PerPkg": "1", 264 "UMask": "0x4", 265 "Unit": "iMC" 266 }, 267 { 268 "BriefDescription": "Underfill read commands for Intel Optane DC persistent memory", 269 "Counter": "0,1,2,3", 270 "EventCode": "0xEA", 271 "EventName": "UNC_M_PMM_CMD1.UFILL_RD", 272 "PerPkg": "1", 273 "UMask": "0x8", 274 "Unit": "iMC" 275 }, 276 { 277 "BriefDescription": "Write requests allocated in the PMM Write Pending Queue for Intel Optane DC persistent memory", 278 "Counter": "0,1,2,3", 279 "EventCode": "0xE7", 280 "EventName": "UNC_M_PMM_WPQ_INSERTS", 281 "PerPkg": "1", 282 "Unit": "iMC" 283 }, 284 { 285 "BriefDescription": "Intel Optane DC persistent memory bandwidth write (MB/sec). Derived from unc_m_pmm_wpq_inserts", 286 "Counter": "0,1,2,3", 287 "EventCode": "0xE7", 288 "EventName": "UNC_M_PMM_BANDWIDTH.WRITE", 289 "PerPkg": "1", 290 "ScaleUnit": "6.103515625E-5MB/sec", 291 "Unit": "iMC" 292 }, 293 { 294 "BriefDescription": "Write Pending Queue Occupancy of all write requests for Intel Optane DC persistent memory", 295 "Counter": "0,1,2,3", 296 "EventCode": "0xE4", 297 "EventName": "UNC_M_PMM_WPQ_OCCUPANCY.ALL", 298 "PerPkg": "1", 299 "UMask": "0x1", 300 "Unit": "iMC" 301 }, 302 { 303 "BriefDescription": "DRAM Activate Count; Activate due to Read", 304 "Counter": "0,1,2,3", 305 "EventCode": "0x1", 306 "EventName": "UNC_M_ACT_COUNT.RD", 307 "PerPkg": "1", 308 "UMask": "0x1", 309 "Unit": "iMC" 310 }, 311 { 312 "BriefDescription": "DRAM Activate Count; Activate due to Bypass", 313 "Counter": "0,1,2,3", 314 "EventCode": "0x1", 315 "EventName": "UNC_M_ACT_COUNT.BYP", 316 "PerPkg": "1", 317 "UMask": "0x8", 318 "Unit": "iMC" 319 }, 320 { 321 "BriefDescription": "ACT command issued by 2 cycle bypass", 322 "Counter": "0,1,2,3", 323 "EventCode": "0xA1", 324 "EventName": "UNC_M_BYP_CMDS.ACT", 325 "PerPkg": "1", 326 "UMask": "0x1", 327 "Unit": "iMC" 328 }, 329 { 330 "BriefDescription": "CAS command issued by 2 cycle bypass", 331 "Counter": "0,1,2,3", 332 "EventCode": "0xA1", 333 "EventName": "UNC_M_BYP_CMDS.CAS", 334 "PerPkg": "1", 335 "UMask": "0x2", 336 "Unit": "iMC" 337 }, 338 { 339 "BriefDescription": "PRE command issued by 2 cycle bypass", 340 "Counter": "0,1,2,3", 341 "EventCode": "0xA1", 342 "EventName": "UNC_M_BYP_CMDS.PRE", 343 "PerPkg": "1", 344 "UMask": "0x4", 345 "Unit": "iMC" 346 }, 347 { 348 "BriefDescription": "DRAM CAS (Column Address Strobe) Commands.; DRAM WR_CAS (w/ and w/out auto-pre) in Read Major Mode", 349 "Counter": "0,1,2,3", 350 "EventCode": "0x4", 351 "EventName": "UNC_M_CAS_COUNT.WR_RMM", 352 "PerPkg": "1", 353 "UMask": "0x8", 354 "Unit": "iMC" 355 }, 356 { 357 "BriefDescription": "DRAM CAS (Column Address Strobe) Commands.; Read CAS issued in WMM", 358 "Counter": "0,1,2,3", 359 "EventCode": "0x4", 360 "EventName": "UNC_M_CAS_COUNT.RD_WMM", 361 "PerPkg": "1", 362 "UMask": "0x10", 363 "Unit": "iMC" 364 }, 365 { 366 "BriefDescription": "DRAM CAS (Column Address Strobe) Commands.; Read CAS issued in RMM", 367 "Counter": "0,1,2,3", 368 "EventCode": "0x4", 369 "EventName": "UNC_M_CAS_COUNT.RD_RMM", 370 "PerPkg": "1", 371 "UMask": "0x20", 372 "Unit": "iMC" 373 }, 374 { 375 "BriefDescription": "DRAM CAS (Column Address Strobe) Commands.; Read CAS issued in Read ISOCH Mode", 376 "Counter": "0,1,2,3", 377 "EventCode": "0x4", 378 "EventName": "UNC_M_CAS_COUNT.RD_ISOCH", 379 "PerPkg": "1", 380 "UMask": "0x40", 381 "Unit": "iMC" 382 }, 383 { 384 "BriefDescription": "DRAM CAS (Column Address Strobe) Commands.; Read CAS issued in Write ISOCH Mode", 385 "Counter": "0,1,2,3", 386 "EventCode": "0x4", 387 "EventName": "UNC_M_CAS_COUNT.WR_ISOCH", 388 "PerPkg": "1", 389 "UMask": "0x80", 390 "Unit": "iMC" 391 }, 392 { 393 "BriefDescription": "DRAM Precharge All Commands", 394 "Counter": "0,1,2,3", 395 "EventCode": "0x6", 396 "EventName": "UNC_M_DRAM_PRE_ALL", 397 "PerPkg": "1", 398 "Unit": "iMC" 399 }, 400 { 401 "BriefDescription": "ECC Correctable Errors", 402 "Counter": "0,1,2,3", 403 "EventCode": "0x9", 404 "EventName": "UNC_M_ECC_CORRECTABLE_ERRORS", 405 "PerPkg": "1", 406 "Unit": "iMC" 407 }, 408 { 409 "BriefDescription": "Cycles in a Major Mode; Read Major Mode", 410 "Counter": "0,1,2,3", 411 "EventCode": "0x7", 412 "EventName": "UNC_M_MAJOR_MODES.READ", 413 "PerPkg": "1", 414 "UMask": "0x1", 415 "Unit": "iMC" 416 }, 417 { 418 "BriefDescription": "Cycles in a Major Mode; Write Major Mode", 419 "Counter": "0,1,2,3", 420 "EventCode": "0x7", 421 "EventName": "UNC_M_MAJOR_MODES.WRITE", 422 "PerPkg": "1", 423 "UMask": "0x2", 424 "Unit": "iMC" 425 }, 426 { 427 "BriefDescription": "Cycles in a Major Mode; Partial Major Mode", 428 "Counter": "0,1,2,3", 429 "EventCode": "0x7", 430 "EventName": "UNC_M_MAJOR_MODES.PARTIAL", 431 "PerPkg": "1", 432 "UMask": "0x4", 433 "Unit": "iMC" 434 }, 435 { 436 "BriefDescription": "Cycles in a Major Mode; Isoch Major Mode", 437 "Counter": "0,1,2,3", 438 "EventCode": "0x7", 439 "EventName": "UNC_M_MAJOR_MODES.ISOCH", 440 "PerPkg": "1", 441 "UMask": "0x8", 442 "Unit": "iMC" 443 }, 444 { 445 "BriefDescription": "Channel DLLOFF Cycles", 446 "Counter": "0,1,2,3", 447 "EventCode": "0x84", 448 "EventName": "UNC_M_POWER_CHANNEL_DLLOFF", 449 "PerPkg": "1", 450 "Unit": "iMC" 451 }, 452 { 453 "BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID", 454 "Counter": "0,1,2,3", 455 "EventCode": "0x83", 456 "EventName": "UNC_M_POWER_CKE_CYCLES.RANK0", 457 "PerPkg": "1", 458 "UMask": "0x1", 459 "Unit": "iMC" 460 }, 461 { 462 "BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID", 463 "Counter": "0,1,2,3", 464 "EventCode": "0x83", 465 "EventName": "UNC_M_POWER_CKE_CYCLES.RANK1", 466 "PerPkg": "1", 467 "UMask": "0x2", 468 "Unit": "iMC" 469 }, 470 { 471 "BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID", 472 "Counter": "0,1,2,3", 473 "EventCode": "0x83", 474 "EventName": "UNC_M_POWER_CKE_CYCLES.RANK2", 475 "PerPkg": "1", 476 "UMask": "0x4", 477 "Unit": "iMC" 478 }, 479 { 480 "BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID", 481 "Counter": "0,1,2,3", 482 "EventCode": "0x83", 483 "EventName": "UNC_M_POWER_CKE_CYCLES.RANK3", 484 "PerPkg": "1", 485 "UMask": "0x8", 486 "Unit": "iMC" 487 }, 488 { 489 "BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID", 490 "Counter": "0,1,2,3", 491 "EventCode": "0x83", 492 "EventName": "UNC_M_POWER_CKE_CYCLES.RANK4", 493 "PerPkg": "1", 494 "UMask": "0x10", 495 "Unit": "iMC" 496 }, 497 { 498 "BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID", 499 "Counter": "0,1,2,3", 500 "EventCode": "0x83", 501 "EventName": "UNC_M_POWER_CKE_CYCLES.RANK5", 502 "PerPkg": "1", 503 "UMask": "0x20", 504 "Unit": "iMC" 505 }, 506 { 507 "BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID", 508 "Counter": "0,1,2,3", 509 "EventCode": "0x83", 510 "EventName": "UNC_M_POWER_CKE_CYCLES.RANK6", 511 "PerPkg": "1", 512 "UMask": "0x40", 513 "Unit": "iMC" 514 }, 515 { 516 "BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID", 517 "Counter": "0,1,2,3", 518 "EventCode": "0x83", 519 "EventName": "UNC_M_POWER_CKE_CYCLES.RANK7", 520 "PerPkg": "1", 521 "UMask": "0x80", 522 "Unit": "iMC" 523 }, 524 { 525 "BriefDescription": "Critical Throttle Cycles", 526 "Counter": "0,1,2,3", 527 "EventCode": "0x86", 528 "EventName": "UNC_M_POWER_CRITICAL_THROTTLE_CYCLES", 529 "PerPkg": "1", 530 "Unit": "iMC" 531 }, 532 { 533 "BriefDescription": "UNC_M_POWER_PCU_THROTTLING", 534 "Counter": "0,1,2,3", 535 "EventCode": "0x42", 536 "EventName": "UNC_M_POWER_PCU_THROTTLING", 537 "PerPkg": "1", 538 "Unit": "iMC" 539 }, 540 { 541 "BriefDescription": "Throttle Cycles for Rank 0; DIMM ID", 542 "Counter": "0,1,2,3", 543 "EventCode": "0x41", 544 "EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK0", 545 "PerPkg": "1", 546 "UMask": "0x1", 547 "Unit": "iMC" 548 }, 549 { 550 "BriefDescription": "Throttle Cycles for Rank 0; DIMM ID", 551 "Counter": "0,1,2,3", 552 "EventCode": "0x41", 553 "EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK1", 554 "PerPkg": "1", 555 "UMask": "0x2", 556 "Unit": "iMC" 557 }, 558 { 559 "BriefDescription": "Throttle Cycles for Rank 0; DIMM ID", 560 "Counter": "0,1,2,3", 561 "EventCode": "0x41", 562 "EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK2", 563 "PerPkg": "1", 564 "UMask": "0x4", 565 "Unit": "iMC" 566 }, 567 { 568 "BriefDescription": "Throttle Cycles for Rank 0; DIMM ID", 569 "Counter": "0,1,2,3", 570 "EventCode": "0x41", 571 "EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK3", 572 "PerPkg": "1", 573 "UMask": "0x8", 574 "Unit": "iMC" 575 }, 576 { 577 "BriefDescription": "Throttle Cycles for Rank 0; DIMM ID", 578 "Counter": "0,1,2,3", 579 "EventCode": "0x41", 580 "EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK4", 581 "PerPkg": "1", 582 "UMask": "0x10", 583 "Unit": "iMC" 584 }, 585 { 586 "BriefDescription": "Throttle Cycles for Rank 0; DIMM ID", 587 "Counter": "0,1,2,3", 588 "EventCode": "0x41", 589 "EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK5", 590 "PerPkg": "1", 591 "UMask": "0x20", 592 "Unit": "iMC" 593 }, 594 { 595 "BriefDescription": "Throttle Cycles for Rank 0; DIMM ID", 596 "Counter": "0,1,2,3", 597 "EventCode": "0x41", 598 "EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK6", 599 "PerPkg": "1", 600 "UMask": "0x40", 601 "Unit": "iMC" 602 }, 603 { 604 "BriefDescription": "Throttle Cycles for Rank 0; DIMM ID", 605 "Counter": "0,1,2,3", 606 "EventCode": "0x41", 607 "EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK7", 608 "PerPkg": "1", 609 "UMask": "0x80", 610 "Unit": "iMC" 611 }, 612 { 613 "BriefDescription": "Read Preemption Count; Read over Read Preemption", 614 "Counter": "0,1,2,3", 615 "EventCode": "0x8", 616 "EventName": "UNC_M_PREEMPTION.RD_PREEMPT_RD", 617 "PerPkg": "1", 618 "UMask": "0x1", 619 "Unit": "iMC" 620 }, 621 { 622 "BriefDescription": "Read Preemption Count; Read over Write Preemption", 623 "Counter": "0,1,2,3", 624 "EventCode": "0x8", 625 "EventName": "UNC_M_PREEMPTION.RD_PREEMPT_WR", 626 "PerPkg": "1", 627 "UMask": "0x2", 628 "Unit": "iMC" 629 }, 630 { 631 "BriefDescription": "DRAM Precharge commands.; Precharge due to timer expiration", 632 "Counter": "0,1,2,3", 633 "EventCode": "0x2", 634 "EventName": "UNC_M_PRE_COUNT.PAGE_CLOSE", 635 "PerPkg": "1", 636 "UMask": "0x2", 637 "Unit": "iMC" 638 }, 639 { 640 "BriefDescription": "Pre-charge for writes", 641 "Counter": "0,1,2,3", 642 "EventCode": "0x2", 643 "EventName": "UNC_M_PRE_COUNT.WR", 644 "PerPkg": "1", 645 "UMask": "0x8", 646 "Unit": "iMC" 647 }, 648 { 649 "BriefDescription": "DRAM Precharge commands.; Precharge due to bypass", 650 "Counter": "0,1,2,3", 651 "EventCode": "0x2", 652 "EventName": "UNC_M_PRE_COUNT.BYP", 653 "PerPkg": "1", 654 "UMask": "0x10", 655 "Unit": "iMC" 656 }, 657 { 658 "BriefDescription": "Read CAS issued with LOW priority", 659 "Counter": "0,1,2,3", 660 "EventCode": "0xA0", 661 "EventName": "UNC_M_RD_CAS_PRIO.LOW", 662 "PerPkg": "1", 663 "UMask": "0x1", 664 "Unit": "iMC" 665 }, 666 { 667 "BriefDescription": "Read CAS issued with MEDIUM priority", 668 "Counter": "0,1,2,3", 669 "EventCode": "0xA0", 670 "EventName": "UNC_M_RD_CAS_PRIO.MED", 671 "PerPkg": "1", 672 "UMask": "0x2", 673 "Unit": "iMC" 674 }, 675 { 676 "BriefDescription": "Read CAS issued with HIGH priority", 677 "Counter": "0,1,2,3", 678 "EventCode": "0xA0", 679 "EventName": "UNC_M_RD_CAS_PRIO.HIGH", 680 "PerPkg": "1", 681 "UMask": "0x4", 682 "Unit": "iMC" 683 }, 684 { 685 "BriefDescription": "Read CAS issued with PANIC NON ISOCH priority (starved)", 686 "Counter": "0,1,2,3", 687 "EventCode": "0xA0", 688 "EventName": "UNC_M_RD_CAS_PRIO.PANIC", 689 "PerPkg": "1", 690 "UMask": "0x8", 691 "Unit": "iMC" 692 }, 693 { 694 "BriefDescription": "RD_CAS Access to Rank 0; Bank 0", 695 "Counter": "0,1,2,3", 696 "EventCode": "0xB0", 697 "EventName": "UNC_M_RD_CAS_RANK0.BANK0", 698 "PerPkg": "1", 699 "Unit": "iMC" 700 }, 701 { 702 "BriefDescription": "RD_CAS Access to Rank 0; Bank 1", 703 "Counter": "0,1,2,3", 704 "EventCode": "0xB0", 705 "EventName": "UNC_M_RD_CAS_RANK0.BANK1", 706 "PerPkg": "1", 707 "UMask": "0x1", 708 "Unit": "iMC" 709 }, 710 { 711 "BriefDescription": "RD_CAS Access to Rank 0; Bank 2", 712 "Counter": "0,1,2,3", 713 "EventCode": "0xB0", 714 "EventName": "UNC_M_RD_CAS_RANK0.BANK2", 715 "PerPkg": "1", 716 "UMask": "0x2", 717 "Unit": "iMC" 718 }, 719 { 720 "BriefDescription": "RD_CAS Access to Rank 0; Bank 3", 721 "Counter": "0,1,2,3", 722 "EventCode": "0xB0", 723 "EventName": "UNC_M_RD_CAS_RANK0.BANK3", 724 "PerPkg": "1", 725 "UMask": "0x3", 726 "Unit": "iMC" 727 }, 728 { 729 "BriefDescription": "RD_CAS Access to Rank 0; Bank 4", 730 "Counter": "0,1,2,3", 731 "EventCode": "0xB0", 732 "EventName": "UNC_M_RD_CAS_RANK0.BANK4", 733 "PerPkg": "1", 734 "UMask": "0x4", 735 "Unit": "iMC" 736 }, 737 { 738 "BriefDescription": "RD_CAS Access to Rank 0; Bank 5", 739 "Counter": "0,1,2,3", 740 "EventCode": "0xB0", 741 "EventName": "UNC_M_RD_CAS_RANK0.BANK5", 742 "PerPkg": "1", 743 "UMask": "0x5", 744 "Unit": "iMC" 745 }, 746 { 747 "BriefDescription": "RD_CAS Access to Rank 0; Bank 6", 748 "Counter": "0,1,2,3", 749 "EventCode": "0xB0", 750 "EventName": "UNC_M_RD_CAS_RANK0.BANK6", 751 "PerPkg": "1", 752 "UMask": "0x6", 753 "Unit": "iMC" 754 }, 755 { 756 "BriefDescription": "RD_CAS Access to Rank 0; Bank 7", 757 "Counter": "0,1,2,3", 758 "EventCode": "0xB0", 759 "EventName": "UNC_M_RD_CAS_RANK0.BANK7", 760 "PerPkg": "1", 761 "UMask": "0x7", 762 "Unit": "iMC" 763 }, 764 { 765 "BriefDescription": "RD_CAS Access to Rank 0; Bank 8", 766 "Counter": "0,1,2,3", 767 "EventCode": "0xB0", 768 "EventName": "UNC_M_RD_CAS_RANK0.BANK8", 769 "PerPkg": "1", 770 "UMask": "0x8", 771 "Unit": "iMC" 772 }, 773 { 774 "BriefDescription": "RD_CAS Access to Rank 0; Bank 9", 775 "Counter": "0,1,2,3", 776 "EventCode": "0xB0", 777 "EventName": "UNC_M_RD_CAS_RANK0.BANK9", 778 "PerPkg": "1", 779 "UMask": "0x9", 780 "Unit": "iMC" 781 }, 782 { 783 "BriefDescription": "RD_CAS Access to Rank 0; Bank 10", 784 "Counter": "0,1,2,3", 785 "EventCode": "0xB0", 786 "EventName": "UNC_M_RD_CAS_RANK0.BANK10", 787 "PerPkg": "1", 788 "UMask": "0xA", 789 "Unit": "iMC" 790 }, 791 { 792 "BriefDescription": "RD_CAS Access to Rank 0; Bank 11", 793 "Counter": "0,1,2,3", 794 "EventCode": "0xB0", 795 "EventName": "UNC_M_RD_CAS_RANK0.BANK11", 796 "PerPkg": "1", 797 "UMask": "0xB", 798 "Unit": "iMC" 799 }, 800 { 801 "BriefDescription": "RD_CAS Access to Rank 0; Bank 12", 802 "Counter": "0,1,2,3", 803 "EventCode": "0xB0", 804 "EventName": "UNC_M_RD_CAS_RANK0.BANK12", 805 "PerPkg": "1", 806 "UMask": "0xC", 807 "Unit": "iMC" 808 }, 809 { 810 "BriefDescription": "RD_CAS Access to Rank 0; Bank 13", 811 "Counter": "0,1,2,3", 812 "EventCode": "0xB0", 813 "EventName": "UNC_M_RD_CAS_RANK0.BANK13", 814 "PerPkg": "1", 815 "UMask": "0xD", 816 "Unit": "iMC" 817 }, 818 { 819 "BriefDescription": "RD_CAS Access to Rank 0; Bank 14", 820 "Counter": "0,1,2,3", 821 "EventCode": "0xB0", 822 "EventName": "UNC_M_RD_CAS_RANK0.BANK14", 823 "PerPkg": "1", 824 "UMask": "0xE", 825 "Unit": "iMC" 826 }, 827 { 828 "BriefDescription": "RD_CAS Access to Rank 0; Bank 15", 829 "Counter": "0,1,2,3", 830 "EventCode": "0xB0", 831 "EventName": "UNC_M_RD_CAS_RANK0.BANK15", 832 "PerPkg": "1", 833 "UMask": "0xF", 834 "Unit": "iMC" 835 }, 836 { 837 "BriefDescription": "RD_CAS Access to Rank 0; All Banks", 838 "Counter": "0,1,2,3", 839 "EventCode": "0xB0", 840 "EventName": "UNC_M_RD_CAS_RANK0.ALLBANKS", 841 "PerPkg": "1", 842 "UMask": "0x10", 843 "Unit": "iMC" 844 }, 845 { 846 "BriefDescription": "RD_CAS Access to Rank 0; Bank Group 0 (Banks 0-3)", 847 "Counter": "0,1,2,3", 848 "EventCode": "0xB0", 849 "EventName": "UNC_M_RD_CAS_RANK0.BANKG0", 850 "PerPkg": "1", 851 "UMask": "0x11", 852 "Unit": "iMC" 853 }, 854 { 855 "BriefDescription": "RD_CAS Access to Rank 0; Bank Group 1 (Banks 4-7)", 856 "Counter": "0,1,2,3", 857 "EventCode": "0xB0", 858 "EventName": "UNC_M_RD_CAS_RANK0.BANKG1", 859 "PerPkg": "1", 860 "UMask": "0x12", 861 "Unit": "iMC" 862 }, 863 { 864 "BriefDescription": "RD_CAS Access to Rank 0; Bank Group 2 (Banks 8-11)", 865 "Counter": "0,1,2,3", 866 "EventCode": "0xB0", 867 "EventName": "UNC_M_RD_CAS_RANK0.BANKG2", 868 "PerPkg": "1", 869 "UMask": "0x13", 870 "Unit": "iMC" 871 }, 872 { 873 "BriefDescription": "RD_CAS Access to Rank 0; Bank Group 3 (Banks 12-15)", 874 "Counter": "0,1,2,3", 875 "EventCode": "0xB0", 876 "EventName": "UNC_M_RD_CAS_RANK0.BANKG3", 877 "PerPkg": "1", 878 "UMask": "0x14", 879 "Unit": "iMC" 880 }, 881 { 882 "BriefDescription": "RD_CAS Access to Rank 1; Bank 0", 883 "Counter": "0,1,2,3", 884 "EventCode": "0xB1", 885 "EventName": "UNC_M_RD_CAS_RANK1.BANK0", 886 "PerPkg": "1", 887 "Unit": "iMC" 888 }, 889 { 890 "BriefDescription": "RD_CAS Access to Rank 1; Bank 1", 891 "Counter": "0,1,2,3", 892 "EventCode": "0xB1", 893 "EventName": "UNC_M_RD_CAS_RANK1.BANK1", 894 "PerPkg": "1", 895 "UMask": "0x1", 896 "Unit": "iMC" 897 }, 898 { 899 "BriefDescription": "RD_CAS Access to Rank 1; Bank 2", 900 "Counter": "0,1,2,3", 901 "EventCode": "0xB1", 902 "EventName": "UNC_M_RD_CAS_RANK1.BANK2", 903 "PerPkg": "1", 904 "UMask": "0x2", 905 "Unit": "iMC" 906 }, 907 { 908 "BriefDescription": "RD_CAS Access to Rank 1; Bank 3", 909 "Counter": "0,1,2,3", 910 "EventCode": "0xB1", 911 "EventName": "UNC_M_RD_CAS_RANK1.BANK3", 912 "PerPkg": "1", 913 "UMask": "0x3", 914 "Unit": "iMC" 915 }, 916 { 917 "BriefDescription": "RD_CAS Access to Rank 1; Bank 4", 918 "Counter": "0,1,2,3", 919 "EventCode": "0xB1", 920 "EventName": "UNC_M_RD_CAS_RANK1.BANK4", 921 "PerPkg": "1", 922 "UMask": "0x4", 923 "Unit": "iMC" 924 }, 925 { 926 "BriefDescription": "RD_CAS Access to Rank 1; Bank 5", 927 "Counter": "0,1,2,3", 928 "EventCode": "0xB1", 929 "EventName": "UNC_M_RD_CAS_RANK1.BANK5", 930 "PerPkg": "1", 931 "UMask": "0x5", 932 "Unit": "iMC" 933 }, 934 { 935 "BriefDescription": "RD_CAS Access to Rank 1; Bank 6", 936 "Counter": "0,1,2,3", 937 "EventCode": "0xB1", 938 "EventName": "UNC_M_RD_CAS_RANK1.BANK6", 939 "PerPkg": "1", 940 "UMask": "0x6", 941 "Unit": "iMC" 942 }, 943 { 944 "BriefDescription": "RD_CAS Access to Rank 1; Bank 7", 945 "Counter": "0,1,2,3", 946 "EventCode": "0xB1", 947 "EventName": "UNC_M_RD_CAS_RANK1.BANK7", 948 "PerPkg": "1", 949 "UMask": "0x7", 950 "Unit": "iMC" 951 }, 952 { 953 "BriefDescription": "RD_CAS Access to Rank 1; Bank 8", 954 "Counter": "0,1,2,3", 955 "EventCode": "0xB1", 956 "EventName": "UNC_M_RD_CAS_RANK1.BANK8", 957 "PerPkg": "1", 958 "UMask": "0x8", 959 "Unit": "iMC" 960 }, 961 { 962 "BriefDescription": "RD_CAS Access to Rank 1; Bank 9", 963 "Counter": "0,1,2,3", 964 "EventCode": "0xB1", 965 "EventName": "UNC_M_RD_CAS_RANK1.BANK9", 966 "PerPkg": "1", 967 "UMask": "0x9", 968 "Unit": "iMC" 969 }, 970 { 971 "BriefDescription": "RD_CAS Access to Rank 1; Bank 10", 972 "Counter": "0,1,2,3", 973 "EventCode": "0xB1", 974 "EventName": "UNC_M_RD_CAS_RANK1.BANK10", 975 "PerPkg": "1", 976 "UMask": "0xA", 977 "Unit": "iMC" 978 }, 979 { 980 "BriefDescription": "RD_CAS Access to Rank 1; Bank 11", 981 "Counter": "0,1,2,3", 982 "EventCode": "0xB1", 983 "EventName": "UNC_M_RD_CAS_RANK1.BANK11", 984 "PerPkg": "1", 985 "UMask": "0xB", 986 "Unit": "iMC" 987 }, 988 { 989 "BriefDescription": "RD_CAS Access to Rank 1; Bank 12", 990 "Counter": "0,1,2,3", 991 "EventCode": "0xB1", 992 "EventName": "UNC_M_RD_CAS_RANK1.BANK12", 993 "PerPkg": "1", 994 "UMask": "0xC", 995 "Unit": "iMC" 996 }, 997 { 998 "BriefDescription": "RD_CAS Access to Rank 1; Bank 13", 999 "Counter": "0,1,2,3", 1000 "EventCode": "0xB1", 1001 "EventName": "UNC_M_RD_CAS_RANK1.BANK13", 1002 "PerPkg": "1", 1003 "UMask": "0xD", 1004 "Unit": "iMC" 1005 }, 1006 { 1007 "BriefDescription": "RD_CAS Access to Rank 1; Bank 14", 1008 "Counter": "0,1,2,3", 1009 "EventCode": "0xB1", 1010 "EventName": "UNC_M_RD_CAS_RANK1.BANK14", 1011 "PerPkg": "1", 1012 "UMask": "0xE", 1013 "Unit": "iMC" 1014 }, 1015 { 1016 "BriefDescription": "RD_CAS Access to Rank 1; Bank 15", 1017 "Counter": "0,1,2,3", 1018 "EventCode": "0xB1", 1019 "EventName": "UNC_M_RD_CAS_RANK1.BANK15", 1020 "PerPkg": "1", 1021 "UMask": "0xF", 1022 "Unit": "iMC" 1023 }, 1024 { 1025 "BriefDescription": "RD_CAS Access to Rank 1; All Banks", 1026 "Counter": "0,1,2,3", 1027 "EventCode": "0xB1", 1028 "EventName": "UNC_M_RD_CAS_RANK1.ALLBANKS", 1029 "PerPkg": "1", 1030 "UMask": "0x10", 1031 "Unit": "iMC" 1032 }, 1033 { 1034 "BriefDescription": "RD_CAS Access to Rank 1; Bank Group 0 (Banks 0-3)", 1035 "Counter": "0,1,2,3", 1036 "EventCode": "0xB1", 1037 "EventName": "UNC_M_RD_CAS_RANK1.BANKG0", 1038 "PerPkg": "1", 1039 "UMask": "0x11", 1040 "Unit": "iMC" 1041 }, 1042 { 1043 "BriefDescription": "RD_CAS Access to Rank 1; Bank Group 1 (Banks 4-7)", 1044 "Counter": "0,1,2,3", 1045 "EventCode": "0xB1", 1046 "EventName": "UNC_M_RD_CAS_RANK1.BANKG1", 1047 "PerPkg": "1", 1048 "UMask": "0x12", 1049 "Unit": "iMC" 1050 }, 1051 { 1052 "BriefDescription": "RD_CAS Access to Rank 1; Bank Group 2 (Banks 8-11)", 1053 "Counter": "0,1,2,3", 1054 "EventCode": "0xB1", 1055 "EventName": "UNC_M_RD_CAS_RANK1.BANKG2", 1056 "PerPkg": "1", 1057 "UMask": "0x13", 1058 "Unit": "iMC" 1059 }, 1060 { 1061 "BriefDescription": "RD_CAS Access to Rank 1; Bank Group 3 (Banks 12-15)", 1062 "Counter": "0,1,2,3", 1063 "EventCode": "0xB1", 1064 "EventName": "UNC_M_RD_CAS_RANK1.BANKG3", 1065 "PerPkg": "1", 1066 "UMask": "0x14", 1067 "Unit": "iMC" 1068 }, 1069 { 1070 "BriefDescription": "RD_CAS Access to Rank 2; Bank 0", 1071 "Counter": "0,1,2,3", 1072 "EventCode": "0xB2", 1073 "EventName": "UNC_M_RD_CAS_RANK2.BANK0", 1074 "PerPkg": "1", 1075 "Unit": "iMC" 1076 }, 1077 { 1078 "BriefDescription": "RD_CAS Access to Rank 2; Bank 1", 1079 "Counter": "0,1,2,3", 1080 "EventCode": "0xB2", 1081 "EventName": "UNC_M_RD_CAS_RANK2.BANK1", 1082 "PerPkg": "1", 1083 "UMask": "0x1", 1084 "Unit": "iMC" 1085 }, 1086 { 1087 "BriefDescription": "RD_CAS Access to Rank 2; Bank 2", 1088 "Counter": "0,1,2,3", 1089 "EventCode": "0xB2", 1090 "EventName": "UNC_M_RD_CAS_RANK2.BANK2", 1091 "PerPkg": "1", 1092 "UMask": "0x2", 1093 "Unit": "iMC" 1094 }, 1095 { 1096 "BriefDescription": "RD_CAS Access to Rank 2; Bank 3", 1097 "Counter": "0,1,2,3", 1098 "EventCode": "0xB2", 1099 "EventName": "UNC_M_RD_CAS_RANK2.BANK3", 1100 "PerPkg": "1", 1101 "UMask": "0x3", 1102 "Unit": "iMC" 1103 }, 1104 { 1105 "BriefDescription": "RD_CAS Access to Rank 2; Bank 4", 1106 "Counter": "0,1,2,3", 1107 "EventCode": "0xB2", 1108 "EventName": "UNC_M_RD_CAS_RANK2.BANK4", 1109 "PerPkg": "1", 1110 "UMask": "0x4", 1111 "Unit": "iMC" 1112 }, 1113 { 1114 "BriefDescription": "RD_CAS Access to Rank 2; Bank 5", 1115 "Counter": "0,1,2,3", 1116 "EventCode": "0xB2", 1117 "EventName": "UNC_M_RD_CAS_RANK2.BANK5", 1118 "PerPkg": "1", 1119 "UMask": "0x5", 1120 "Unit": "iMC" 1121 }, 1122 { 1123 "BriefDescription": "RD_CAS Access to Rank 2; Bank 6", 1124 "Counter": "0,1,2,3", 1125 "EventCode": "0xB2", 1126 "EventName": "UNC_M_RD_CAS_RANK2.BANK6", 1127 "PerPkg": "1", 1128 "UMask": "0x6", 1129 "Unit": "iMC" 1130 }, 1131 { 1132 "BriefDescription": "RD_CAS Access to Rank 2; Bank 7", 1133 "Counter": "0,1,2,3", 1134 "EventCode": "0xB2", 1135 "EventName": "UNC_M_RD_CAS_RANK2.BANK7", 1136 "PerPkg": "1", 1137 "UMask": "0x7", 1138 "Unit": "iMC" 1139 }, 1140 { 1141 "BriefDescription": "RD_CAS Access to Rank 2; Bank 8", 1142 "Counter": "0,1,2,3", 1143 "EventCode": "0xB2", 1144 "EventName": "UNC_M_RD_CAS_RANK2.BANK8", 1145 "PerPkg": "1", 1146 "UMask": "0x8", 1147 "Unit": "iMC" 1148 }, 1149 { 1150 "BriefDescription": "RD_CAS Access to Rank 2; Bank 9", 1151 "Counter": "0,1,2,3", 1152 "EventCode": "0xB2", 1153 "EventName": "UNC_M_RD_CAS_RANK2.BANK9", 1154 "PerPkg": "1", 1155 "UMask": "0x9", 1156 "Unit": "iMC" 1157 }, 1158 { 1159 "BriefDescription": "RD_CAS Access to Rank 2; Bank 10", 1160 "Counter": "0,1,2,3", 1161 "EventCode": "0xB2", 1162 "EventName": "UNC_M_RD_CAS_RANK2.BANK10", 1163 "PerPkg": "1", 1164 "UMask": "0xA", 1165 "Unit": "iMC" 1166 }, 1167 { 1168 "BriefDescription": "RD_CAS Access to Rank 2; Bank 11", 1169 "Counter": "0,1,2,3", 1170 "EventCode": "0xB2", 1171 "EventName": "UNC_M_RD_CAS_RANK2.BANK11", 1172 "PerPkg": "1", 1173 "UMask": "0xB", 1174 "Unit": "iMC" 1175 }, 1176 { 1177 "BriefDescription": "RD_CAS Access to Rank 2; Bank 12", 1178 "Counter": "0,1,2,3", 1179 "EventCode": "0xB2", 1180 "EventName": "UNC_M_RD_CAS_RANK2.BANK12", 1181 "PerPkg": "1", 1182 "UMask": "0xC", 1183 "Unit": "iMC" 1184 }, 1185 { 1186 "BriefDescription": "RD_CAS Access to Rank 2; Bank 13", 1187 "Counter": "0,1,2,3", 1188 "EventCode": "0xB2", 1189 "EventName": "UNC_M_RD_CAS_RANK2.BANK13", 1190 "PerPkg": "1", 1191 "UMask": "0xD", 1192 "Unit": "iMC" 1193 }, 1194 { 1195 "BriefDescription": "RD_CAS Access to Rank 2; Bank 14", 1196 "Counter": "0,1,2,3", 1197 "EventCode": "0xB2", 1198 "EventName": "UNC_M_RD_CAS_RANK2.BANK14", 1199 "PerPkg": "1", 1200 "UMask": "0xE", 1201 "Unit": "iMC" 1202 }, 1203 { 1204 "BriefDescription": "RD_CAS Access to Rank 2; Bank 15", 1205 "Counter": "0,1,2,3", 1206 "EventCode": "0xB2", 1207 "EventName": "UNC_M_RD_CAS_RANK2.BANK15", 1208 "PerPkg": "1", 1209 "UMask": "0xF", 1210 "Unit": "iMC" 1211 }, 1212 { 1213 "BriefDescription": "RD_CAS Access to Rank 2; All Banks", 1214 "Counter": "0,1,2,3", 1215 "EventCode": "0xB2", 1216 "EventName": "UNC_M_RD_CAS_RANK2.ALLBANKS", 1217 "PerPkg": "1", 1218 "UMask": "0x10", 1219 "Unit": "iMC" 1220 }, 1221 { 1222 "BriefDescription": "RD_CAS Access to Rank 2; Bank Group 0 (Banks 0-3)", 1223 "Counter": "0,1,2,3", 1224 "EventCode": "0xB2", 1225 "EventName": "UNC_M_RD_CAS_RANK2.BANKG0", 1226 "PerPkg": "1", 1227 "UMask": "0x11", 1228 "Unit": "iMC" 1229 }, 1230 { 1231 "BriefDescription": "RD_CAS Access to Rank 2; Bank Group 1 (Banks 4-7)", 1232 "Counter": "0,1,2,3", 1233 "EventCode": "0xB2", 1234 "EventName": "UNC_M_RD_CAS_RANK2.BANKG1", 1235 "PerPkg": "1", 1236 "UMask": "0x12", 1237 "Unit": "iMC" 1238 }, 1239 { 1240 "BriefDescription": "RD_CAS Access to Rank 2; Bank Group 2 (Banks 8-11)", 1241 "Counter": "0,1,2,3", 1242 "EventCode": "0xB2", 1243 "EventName": "UNC_M_RD_CAS_RANK2.BANKG2", 1244 "PerPkg": "1", 1245 "UMask": "0x13", 1246 "Unit": "iMC" 1247 }, 1248 { 1249 "BriefDescription": "RD_CAS Access to Rank 2; Bank Group 3 (Banks 12-15)", 1250 "Counter": "0,1,2,3", 1251 "EventCode": "0xB2", 1252 "EventName": "UNC_M_RD_CAS_RANK2.BANKG3", 1253 "PerPkg": "1", 1254 "UMask": "0x14", 1255 "Unit": "iMC" 1256 }, 1257 { 1258 "BriefDescription": "RD_CAS Access to Rank 3; Bank 0", 1259 "Counter": "0,1,2,3", 1260 "EventCode": "0xB3", 1261 "EventName": "UNC_M_RD_CAS_RANK3.BANK0", 1262 "PerPkg": "1", 1263 "Unit": "iMC" 1264 }, 1265 { 1266 "BriefDescription": "RD_CAS Access to Rank 3; Bank 1", 1267 "Counter": "0,1,2,3", 1268 "EventCode": "0xB3", 1269 "EventName": "UNC_M_RD_CAS_RANK3.BANK1", 1270 "PerPkg": "1", 1271 "UMask": "0x1", 1272 "Unit": "iMC" 1273 }, 1274 { 1275 "BriefDescription": "RD_CAS Access to Rank 3; Bank 2", 1276 "Counter": "0,1,2,3", 1277 "EventCode": "0xB3", 1278 "EventName": "UNC_M_RD_CAS_RANK3.BANK2", 1279 "PerPkg": "1", 1280 "UMask": "0x2", 1281 "Unit": "iMC" 1282 }, 1283 { 1284 "BriefDescription": "RD_CAS Access to Rank 3; Bank 3", 1285 "Counter": "0,1,2,3", 1286 "EventCode": "0xB3", 1287 "EventName": "UNC_M_RD_CAS_RANK3.BANK3", 1288 "PerPkg": "1", 1289 "UMask": "0x3", 1290 "Unit": "iMC" 1291 }, 1292 { 1293 "BriefDescription": "RD_CAS Access to Rank 3; Bank 4", 1294 "Counter": "0,1,2,3", 1295 "EventCode": "0xB3", 1296 "EventName": "UNC_M_RD_CAS_RANK3.BANK4", 1297 "PerPkg": "1", 1298 "UMask": "0x4", 1299 "Unit": "iMC" 1300 }, 1301 { 1302 "BriefDescription": "RD_CAS Access to Rank 3; Bank 5", 1303 "Counter": "0,1,2,3", 1304 "EventCode": "0xB3", 1305 "EventName": "UNC_M_RD_CAS_RANK3.BANK5", 1306 "PerPkg": "1", 1307 "UMask": "0x5", 1308 "Unit": "iMC" 1309 }, 1310 { 1311 "BriefDescription": "RD_CAS Access to Rank 3; Bank 6", 1312 "Counter": "0,1,2,3", 1313 "EventCode": "0xB3", 1314 "EventName": "UNC_M_RD_CAS_RANK3.BANK6", 1315 "PerPkg": "1", 1316 "UMask": "0x6", 1317 "Unit": "iMC" 1318 }, 1319 { 1320 "BriefDescription": "RD_CAS Access to Rank 3; Bank 7", 1321 "Counter": "0,1,2,3", 1322 "EventCode": "0xB3", 1323 "EventName": "UNC_M_RD_CAS_RANK3.BANK7", 1324 "PerPkg": "1", 1325 "UMask": "0x7", 1326 "Unit": "iMC" 1327 }, 1328 { 1329 "BriefDescription": "RD_CAS Access to Rank 3; Bank 8", 1330 "Counter": "0,1,2,3", 1331 "EventCode": "0xB3", 1332 "EventName": "UNC_M_RD_CAS_RANK3.BANK8", 1333 "PerPkg": "1", 1334 "UMask": "0x8", 1335 "Unit": "iMC" 1336 }, 1337 { 1338 "BriefDescription": "RD_CAS Access to Rank 3; Bank 9", 1339 "Counter": "0,1,2,3", 1340 "EventCode": "0xB3", 1341 "EventName": "UNC_M_RD_CAS_RANK3.BANK9", 1342 "PerPkg": "1", 1343 "UMask": "0x9", 1344 "Unit": "iMC" 1345 }, 1346 { 1347 "BriefDescription": "RD_CAS Access to Rank 3; Bank 10", 1348 "Counter": "0,1,2,3", 1349 "EventCode": "0xB3", 1350 "EventName": "UNC_M_RD_CAS_RANK3.BANK10", 1351 "PerPkg": "1", 1352 "UMask": "0xA", 1353 "Unit": "iMC" 1354 }, 1355 { 1356 "BriefDescription": "RD_CAS Access to Rank 3; Bank 11", 1357 "Counter": "0,1,2,3", 1358 "EventCode": "0xB3", 1359 "EventName": "UNC_M_RD_CAS_RANK3.BANK11", 1360 "PerPkg": "1", 1361 "UMask": "0xB", 1362 "Unit": "iMC" 1363 }, 1364 { 1365 "BriefDescription": "RD_CAS Access to Rank 3; Bank 12", 1366 "Counter": "0,1,2,3", 1367 "EventCode": "0xB3", 1368 "EventName": "UNC_M_RD_CAS_RANK3.BANK12", 1369 "PerPkg": "1", 1370 "UMask": "0xC", 1371 "Unit": "iMC" 1372 }, 1373 { 1374 "BriefDescription": "RD_CAS Access to Rank 3; Bank 13", 1375 "Counter": "0,1,2,3", 1376 "EventCode": "0xB3", 1377 "EventName": "UNC_M_RD_CAS_RANK3.BANK13", 1378 "PerPkg": "1", 1379 "UMask": "0xD", 1380 "Unit": "iMC" 1381 }, 1382 { 1383 "BriefDescription": "RD_CAS Access to Rank 3; Bank 14", 1384 "Counter": "0,1,2,3", 1385 "EventCode": "0xB3", 1386 "EventName": "UNC_M_RD_CAS_RANK3.BANK14", 1387 "PerPkg": "1", 1388 "UMask": "0xE", 1389 "Unit": "iMC" 1390 }, 1391 { 1392 "BriefDescription": "RD_CAS Access to Rank 3; Bank 15", 1393 "Counter": "0,1,2,3", 1394 "EventCode": "0xB3", 1395 "EventName": "UNC_M_RD_CAS_RANK3.BANK15", 1396 "PerPkg": "1", 1397 "UMask": "0xF", 1398 "Unit": "iMC" 1399 }, 1400 { 1401 "BriefDescription": "RD_CAS Access to Rank 3; All Banks", 1402 "Counter": "0,1,2,3", 1403 "EventCode": "0xB3", 1404 "EventName": "UNC_M_RD_CAS_RANK3.ALLBANKS", 1405 "PerPkg": "1", 1406 "UMask": "0x10", 1407 "Unit": "iMC" 1408 }, 1409 { 1410 "BriefDescription": "RD_CAS Access to Rank 3; Bank Group 0 (Banks 0-3)", 1411 "Counter": "0,1,2,3", 1412 "EventCode": "0xB3", 1413 "EventName": "UNC_M_RD_CAS_RANK3.BANKG0", 1414 "PerPkg": "1", 1415 "UMask": "0x11", 1416 "Unit": "iMC" 1417 }, 1418 { 1419 "BriefDescription": "RD_CAS Access to Rank 3; Bank Group 1 (Banks 4-7)", 1420 "Counter": "0,1,2,3", 1421 "EventCode": "0xB3", 1422 "EventName": "UNC_M_RD_CAS_RANK3.BANKG1", 1423 "PerPkg": "1", 1424 "UMask": "0x12", 1425 "Unit": "iMC" 1426 }, 1427 { 1428 "BriefDescription": "RD_CAS Access to Rank 3; Bank Group 2 (Banks 8-11)", 1429 "Counter": "0,1,2,3", 1430 "EventCode": "0xB3", 1431 "EventName": "UNC_M_RD_CAS_RANK3.BANKG2", 1432 "PerPkg": "1", 1433 "UMask": "0x13", 1434 "Unit": "iMC" 1435 }, 1436 { 1437 "BriefDescription": "RD_CAS Access to Rank 3; Bank Group 3 (Banks 12-15)", 1438 "Counter": "0,1,2,3", 1439 "EventCode": "0xB3", 1440 "EventName": "UNC_M_RD_CAS_RANK3.BANKG3", 1441 "PerPkg": "1", 1442 "UMask": "0x14", 1443 "Unit": "iMC" 1444 }, 1445 { 1446 "BriefDescription": "RD_CAS Access to Rank 4; Bank 0", 1447 "Counter": "0,1,2,3", 1448 "EventCode": "0xB4", 1449 "EventName": "UNC_M_RD_CAS_RANK4.BANK0", 1450 "PerPkg": "1", 1451 "Unit": "iMC" 1452 }, 1453 { 1454 "BriefDescription": "RD_CAS Access to Rank 4; Bank 1", 1455 "Counter": "0,1,2,3", 1456 "EventCode": "0xB4", 1457 "EventName": "UNC_M_RD_CAS_RANK4.BANK1", 1458 "PerPkg": "1", 1459 "UMask": "0x1", 1460 "Unit": "iMC" 1461 }, 1462 { 1463 "BriefDescription": "RD_CAS Access to Rank 4; Bank 2", 1464 "Counter": "0,1,2,3", 1465 "EventCode": "0xB4", 1466 "EventName": "UNC_M_RD_CAS_RANK4.BANK2", 1467 "PerPkg": "1", 1468 "UMask": "0x2", 1469 "Unit": "iMC" 1470 }, 1471 { 1472 "BriefDescription": "RD_CAS Access to Rank 4; Bank 3", 1473 "Counter": "0,1,2,3", 1474 "EventCode": "0xB4", 1475 "EventName": "UNC_M_RD_CAS_RANK4.BANK3", 1476 "PerPkg": "1", 1477 "UMask": "0x3", 1478 "Unit": "iMC" 1479 }, 1480 { 1481 "BriefDescription": "RD_CAS Access to Rank 4; Bank 4", 1482 "Counter": "0,1,2,3", 1483 "EventCode": "0xB4", 1484 "EventName": "UNC_M_RD_CAS_RANK4.BANK4", 1485 "PerPkg": "1", 1486 "UMask": "0x4", 1487 "Unit": "iMC" 1488 }, 1489 { 1490 "BriefDescription": "RD_CAS Access to Rank 4; Bank 5", 1491 "Counter": "0,1,2,3", 1492 "EventCode": "0xB4", 1493 "EventName": "UNC_M_RD_CAS_RANK4.BANK5", 1494 "PerPkg": "1", 1495 "UMask": "0x5", 1496 "Unit": "iMC" 1497 }, 1498 { 1499 "BriefDescription": "RD_CAS Access to Rank 4; Bank 6", 1500 "Counter": "0,1,2,3", 1501 "EventCode": "0xB4", 1502 "EventName": "UNC_M_RD_CAS_RANK4.BANK6", 1503 "PerPkg": "1", 1504 "UMask": "0x6", 1505 "Unit": "iMC" 1506 }, 1507 { 1508 "BriefDescription": "RD_CAS Access to Rank 4; Bank 7", 1509 "Counter": "0,1,2,3", 1510 "EventCode": "0xB4", 1511 "EventName": "UNC_M_RD_CAS_RANK4.BANK7", 1512 "PerPkg": "1", 1513 "UMask": "0x7", 1514 "Unit": "iMC" 1515 }, 1516 { 1517 "BriefDescription": "RD_CAS Access to Rank 4; Bank 8", 1518 "Counter": "0,1,2,3", 1519 "EventCode": "0xB4", 1520 "EventName": "UNC_M_RD_CAS_RANK4.BANK8", 1521 "PerPkg": "1", 1522 "UMask": "0x8", 1523 "Unit": "iMC" 1524 }, 1525 { 1526 "BriefDescription": "RD_CAS Access to Rank 4; Bank 9", 1527 "Counter": "0,1,2,3", 1528 "EventCode": "0xB4", 1529 "EventName": "UNC_M_RD_CAS_RANK4.BANK9", 1530 "PerPkg": "1", 1531 "UMask": "0x9", 1532 "Unit": "iMC" 1533 }, 1534 { 1535 "BriefDescription": "RD_CAS Access to Rank 4; Bank 10", 1536 "Counter": "0,1,2,3", 1537 "EventCode": "0xB4", 1538 "EventName": "UNC_M_RD_CAS_RANK4.BANK10", 1539 "PerPkg": "1", 1540 "UMask": "0xA", 1541 "Unit": "iMC" 1542 }, 1543 { 1544 "BriefDescription": "RD_CAS Access to Rank 4; Bank 11", 1545 "Counter": "0,1,2,3", 1546 "EventCode": "0xB4", 1547 "EventName": "UNC_M_RD_CAS_RANK4.BANK11", 1548 "PerPkg": "1", 1549 "UMask": "0xB", 1550 "Unit": "iMC" 1551 }, 1552 { 1553 "BriefDescription": "RD_CAS Access to Rank 4; Bank 12", 1554 "Counter": "0,1,2,3", 1555 "EventCode": "0xB4", 1556 "EventName": "UNC_M_RD_CAS_RANK4.BANK12", 1557 "PerPkg": "1", 1558 "UMask": "0xC", 1559 "Unit": "iMC" 1560 }, 1561 { 1562 "BriefDescription": "RD_CAS Access to Rank 4; Bank 13", 1563 "Counter": "0,1,2,3", 1564 "EventCode": "0xB4", 1565 "EventName": "UNC_M_RD_CAS_RANK4.BANK13", 1566 "PerPkg": "1", 1567 "UMask": "0xD", 1568 "Unit": "iMC" 1569 }, 1570 { 1571 "BriefDescription": "RD_CAS Access to Rank 4; Bank 14", 1572 "Counter": "0,1,2,3", 1573 "EventCode": "0xB4", 1574 "EventName": "UNC_M_RD_CAS_RANK4.BANK14", 1575 "PerPkg": "1", 1576 "UMask": "0xE", 1577 "Unit": "iMC" 1578 }, 1579 { 1580 "BriefDescription": "RD_CAS Access to Rank 4; Bank 15", 1581 "Counter": "0,1,2,3", 1582 "EventCode": "0xB4", 1583 "EventName": "UNC_M_RD_CAS_RANK4.BANK15", 1584 "PerPkg": "1", 1585 "UMask": "0xF", 1586 "Unit": "iMC" 1587 }, 1588 { 1589 "BriefDescription": "RD_CAS Access to Rank 4; All Banks", 1590 "Counter": "0,1,2,3", 1591 "EventCode": "0xB4", 1592 "EventName": "UNC_M_RD_CAS_RANK4.ALLBANKS", 1593 "PerPkg": "1", 1594 "UMask": "0x10", 1595 "Unit": "iMC" 1596 }, 1597 { 1598 "BriefDescription": "RD_CAS Access to Rank 4; Bank Group 0 (Banks 0-3)", 1599 "Counter": "0,1,2,3", 1600 "EventCode": "0xB4", 1601 "EventName": "UNC_M_RD_CAS_RANK4.BANKG0", 1602 "PerPkg": "1", 1603 "UMask": "0x11", 1604 "Unit": "iMC" 1605 }, 1606 { 1607 "BriefDescription": "RD_CAS Access to Rank 4; Bank Group 1 (Banks 4-7)", 1608 "Counter": "0,1,2,3", 1609 "EventCode": "0xB4", 1610 "EventName": "UNC_M_RD_CAS_RANK4.BANKG1", 1611 "PerPkg": "1", 1612 "UMask": "0x12", 1613 "Unit": "iMC" 1614 }, 1615 { 1616 "BriefDescription": "RD_CAS Access to Rank 4; Bank Group 2 (Banks 8-11)", 1617 "Counter": "0,1,2,3", 1618 "EventCode": "0xB4", 1619 "EventName": "UNC_M_RD_CAS_RANK4.BANKG2", 1620 "PerPkg": "1", 1621 "UMask": "0x13", 1622 "Unit": "iMC" 1623 }, 1624 { 1625 "BriefDescription": "RD_CAS Access to Rank 4; Bank Group 3 (Banks 12-15)", 1626 "Counter": "0,1,2,3", 1627 "EventCode": "0xB4", 1628 "EventName": "UNC_M_RD_CAS_RANK4.BANKG3", 1629 "PerPkg": "1", 1630 "UMask": "0x14", 1631 "Unit": "iMC" 1632 }, 1633 { 1634 "BriefDescription": "RD_CAS Access to Rank 5; Bank 0", 1635 "Counter": "0,1,2,3", 1636 "EventCode": "0xB5", 1637 "EventName": "UNC_M_RD_CAS_RANK5.BANK0", 1638 "PerPkg": "1", 1639 "Unit": "iMC" 1640 }, 1641 { 1642 "BriefDescription": "RD_CAS Access to Rank 5; Bank 1", 1643 "Counter": "0,1,2,3", 1644 "EventCode": "0xB5", 1645 "EventName": "UNC_M_RD_CAS_RANK5.BANK1", 1646 "PerPkg": "1", 1647 "UMask": "0x1", 1648 "Unit": "iMC" 1649 }, 1650 { 1651 "BriefDescription": "RD_CAS Access to Rank 5; Bank 2", 1652 "Counter": "0,1,2,3", 1653 "EventCode": "0xB5", 1654 "EventName": "UNC_M_RD_CAS_RANK5.BANK2", 1655 "PerPkg": "1", 1656 "UMask": "0x2", 1657 "Unit": "iMC" 1658 }, 1659 { 1660 "BriefDescription": "RD_CAS Access to Rank 5; Bank 3", 1661 "Counter": "0,1,2,3", 1662 "EventCode": "0xB5", 1663 "EventName": "UNC_M_RD_CAS_RANK5.BANK3", 1664 "PerPkg": "1", 1665 "UMask": "0x3", 1666 "Unit": "iMC" 1667 }, 1668 { 1669 "BriefDescription": "RD_CAS Access to Rank 5; Bank 4", 1670 "Counter": "0,1,2,3", 1671 "EventCode": "0xB5", 1672 "EventName": "UNC_M_RD_CAS_RANK5.BANK4", 1673 "PerPkg": "1", 1674 "UMask": "0x4", 1675 "Unit": "iMC" 1676 }, 1677 { 1678 "BriefDescription": "RD_CAS Access to Rank 5; Bank 5", 1679 "Counter": "0,1,2,3", 1680 "EventCode": "0xB5", 1681 "EventName": "UNC_M_RD_CAS_RANK5.BANK5", 1682 "PerPkg": "1", 1683 "UMask": "0x5", 1684 "Unit": "iMC" 1685 }, 1686 { 1687 "BriefDescription": "RD_CAS Access to Rank 5; Bank 6", 1688 "Counter": "0,1,2,3", 1689 "EventCode": "0xB5", 1690 "EventName": "UNC_M_RD_CAS_RANK5.BANK6", 1691 "PerPkg": "1", 1692 "UMask": "0x6", 1693 "Unit": "iMC" 1694 }, 1695 { 1696 "BriefDescription": "RD_CAS Access to Rank 5; Bank 7", 1697 "Counter": "0,1,2,3", 1698 "EventCode": "0xB5", 1699 "EventName": "UNC_M_RD_CAS_RANK5.BANK7", 1700 "PerPkg": "1", 1701 "UMask": "0x7", 1702 "Unit": "iMC" 1703 }, 1704 { 1705 "BriefDescription": "RD_CAS Access to Rank 5; Bank 8", 1706 "Counter": "0,1,2,3", 1707 "EventCode": "0xB5", 1708 "EventName": "UNC_M_RD_CAS_RANK5.BANK8", 1709 "PerPkg": "1", 1710 "UMask": "0x8", 1711 "Unit": "iMC" 1712 }, 1713 { 1714 "BriefDescription": "RD_CAS Access to Rank 5; Bank 9", 1715 "Counter": "0,1,2,3", 1716 "EventCode": "0xB5", 1717 "EventName": "UNC_M_RD_CAS_RANK5.BANK9", 1718 "PerPkg": "1", 1719 "UMask": "0x9", 1720 "Unit": "iMC" 1721 }, 1722 { 1723 "BriefDescription": "RD_CAS Access to Rank 5; Bank 10", 1724 "Counter": "0,1,2,3", 1725 "EventCode": "0xB5", 1726 "EventName": "UNC_M_RD_CAS_RANK5.BANK10", 1727 "PerPkg": "1", 1728 "UMask": "0xA", 1729 "Unit": "iMC" 1730 }, 1731 { 1732 "BriefDescription": "RD_CAS Access to Rank 5; Bank 11", 1733 "Counter": "0,1,2,3", 1734 "EventCode": "0xB5", 1735 "EventName": "UNC_M_RD_CAS_RANK5.BANK11", 1736 "PerPkg": "1", 1737 "UMask": "0xB", 1738 "Unit": "iMC" 1739 }, 1740 { 1741 "BriefDescription": "RD_CAS Access to Rank 5; Bank 12", 1742 "Counter": "0,1,2,3", 1743 "EventCode": "0xB5", 1744 "EventName": "UNC_M_RD_CAS_RANK5.BANK12", 1745 "PerPkg": "1", 1746 "UMask": "0xC", 1747 "Unit": "iMC" 1748 }, 1749 { 1750 "BriefDescription": "RD_CAS Access to Rank 5; Bank 13", 1751 "Counter": "0,1,2,3", 1752 "EventCode": "0xB5", 1753 "EventName": "UNC_M_RD_CAS_RANK5.BANK13", 1754 "PerPkg": "1", 1755 "UMask": "0xD", 1756 "Unit": "iMC" 1757 }, 1758 { 1759 "BriefDescription": "RD_CAS Access to Rank 5; Bank 14", 1760 "Counter": "0,1,2,3", 1761 "EventCode": "0xB5", 1762 "EventName": "UNC_M_RD_CAS_RANK5.BANK14", 1763 "PerPkg": "1", 1764 "UMask": "0xE", 1765 "Unit": "iMC" 1766 }, 1767 { 1768 "BriefDescription": "RD_CAS Access to Rank 5; Bank 15", 1769 "Counter": "0,1,2,3", 1770 "EventCode": "0xB5", 1771 "EventName": "UNC_M_RD_CAS_RANK5.BANK15", 1772 "PerPkg": "1", 1773 "UMask": "0xF", 1774 "Unit": "iMC" 1775 }, 1776 { 1777 "BriefDescription": "RD_CAS Access to Rank 5; All Banks", 1778 "Counter": "0,1,2,3", 1779 "EventCode": "0xB5", 1780 "EventName": "UNC_M_RD_CAS_RANK5.ALLBANKS", 1781 "PerPkg": "1", 1782 "UMask": "0x10", 1783 "Unit": "iMC" 1784 }, 1785 { 1786 "BriefDescription": "RD_CAS Access to Rank 5; Bank Group 0 (Banks 0-3)", 1787 "Counter": "0,1,2,3", 1788 "EventCode": "0xB5", 1789 "EventName": "UNC_M_RD_CAS_RANK5.BANKG0", 1790 "PerPkg": "1", 1791 "UMask": "0x11", 1792 "Unit": "iMC" 1793 }, 1794 { 1795 "BriefDescription": "RD_CAS Access to Rank 5; Bank Group 1 (Banks 4-7)", 1796 "Counter": "0,1,2,3", 1797 "EventCode": "0xB5", 1798 "EventName": "UNC_M_RD_CAS_RANK5.BANKG1", 1799 "PerPkg": "1", 1800 "UMask": "0x12", 1801 "Unit": "iMC" 1802 }, 1803 { 1804 "BriefDescription": "RD_CAS Access to Rank 5; Bank Group 2 (Banks 8-11)", 1805 "Counter": "0,1,2,3", 1806 "EventCode": "0xB5", 1807 "EventName": "UNC_M_RD_CAS_RANK5.BANKG2", 1808 "PerPkg": "1", 1809 "UMask": "0x13", 1810 "Unit": "iMC" 1811 }, 1812 { 1813 "BriefDescription": "RD_CAS Access to Rank 5; Bank Group 3 (Banks 12-15)", 1814 "Counter": "0,1,2,3", 1815 "EventCode": "0xB5", 1816 "EventName": "UNC_M_RD_CAS_RANK5.BANKG3", 1817 "PerPkg": "1", 1818 "UMask": "0x14", 1819 "Unit": "iMC" 1820 }, 1821 { 1822 "BriefDescription": "RD_CAS Access to Rank 6; Bank 0", 1823 "Counter": "0,1,2,3", 1824 "EventCode": "0xB6", 1825 "EventName": "UNC_M_RD_CAS_RANK6.BANK0", 1826 "PerPkg": "1", 1827 "Unit": "iMC" 1828 }, 1829 { 1830 "BriefDescription": "RD_CAS Access to Rank 6; Bank 1", 1831 "Counter": "0,1,2,3", 1832 "EventCode": "0xB6", 1833 "EventName": "UNC_M_RD_CAS_RANK6.BANK1", 1834 "PerPkg": "1", 1835 "UMask": "0x1", 1836 "Unit": "iMC" 1837 }, 1838 { 1839 "BriefDescription": "RD_CAS Access to Rank 6; Bank 2", 1840 "Counter": "0,1,2,3", 1841 "EventCode": "0xB6", 1842 "EventName": "UNC_M_RD_CAS_RANK6.BANK2", 1843 "PerPkg": "1", 1844 "UMask": "0x2", 1845 "Unit": "iMC" 1846 }, 1847 { 1848 "BriefDescription": "RD_CAS Access to Rank 6; Bank 3", 1849 "Counter": "0,1,2,3", 1850 "EventCode": "0xB6", 1851 "EventName": "UNC_M_RD_CAS_RANK6.BANK3", 1852 "PerPkg": "1", 1853 "UMask": "0x3", 1854 "Unit": "iMC" 1855 }, 1856 { 1857 "BriefDescription": "RD_CAS Access to Rank 6; Bank 4", 1858 "Counter": "0,1,2,3", 1859 "EventCode": "0xB6", 1860 "EventName": "UNC_M_RD_CAS_RANK6.BANK4", 1861 "PerPkg": "1", 1862 "UMask": "0x4", 1863 "Unit": "iMC" 1864 }, 1865 { 1866 "BriefDescription": "RD_CAS Access to Rank 6; Bank 5", 1867 "Counter": "0,1,2,3", 1868 "EventCode": "0xB6", 1869 "EventName": "UNC_M_RD_CAS_RANK6.BANK5", 1870 "PerPkg": "1", 1871 "UMask": "0x5", 1872 "Unit": "iMC" 1873 }, 1874 { 1875 "BriefDescription": "RD_CAS Access to Rank 6; Bank 6", 1876 "Counter": "0,1,2,3", 1877 "EventCode": "0xB6", 1878 "EventName": "UNC_M_RD_CAS_RANK6.BANK6", 1879 "PerPkg": "1", 1880 "UMask": "0x6", 1881 "Unit": "iMC" 1882 }, 1883 { 1884 "BriefDescription": "RD_CAS Access to Rank 6; Bank 7", 1885 "Counter": "0,1,2,3", 1886 "EventCode": "0xB6", 1887 "EventName": "UNC_M_RD_CAS_RANK6.BANK7", 1888 "PerPkg": "1", 1889 "UMask": "0x7", 1890 "Unit": "iMC" 1891 }, 1892 { 1893 "BriefDescription": "RD_CAS Access to Rank 6; Bank 8", 1894 "Counter": "0,1,2,3", 1895 "EventCode": "0xB6", 1896 "EventName": "UNC_M_RD_CAS_RANK6.BANK8", 1897 "PerPkg": "1", 1898 "UMask": "0x8", 1899 "Unit": "iMC" 1900 }, 1901 { 1902 "BriefDescription": "RD_CAS Access to Rank 6; Bank 9", 1903 "Counter": "0,1,2,3", 1904 "EventCode": "0xB6", 1905 "EventName": "UNC_M_RD_CAS_RANK6.BANK9", 1906 "PerPkg": "1", 1907 "UMask": "0x9", 1908 "Unit": "iMC" 1909 }, 1910 { 1911 "BriefDescription": "RD_CAS Access to Rank 6; Bank 10", 1912 "Counter": "0,1,2,3", 1913 "EventCode": "0xB6", 1914 "EventName": "UNC_M_RD_CAS_RANK6.BANK10", 1915 "PerPkg": "1", 1916 "UMask": "0xA", 1917 "Unit": "iMC" 1918 }, 1919 { 1920 "BriefDescription": "RD_CAS Access to Rank 6; Bank 11", 1921 "Counter": "0,1,2,3", 1922 "EventCode": "0xB6", 1923 "EventName": "UNC_M_RD_CAS_RANK6.BANK11", 1924 "PerPkg": "1", 1925 "UMask": "0xB", 1926 "Unit": "iMC" 1927 }, 1928 { 1929 "BriefDescription": "RD_CAS Access to Rank 6; Bank 12", 1930 "Counter": "0,1,2,3", 1931 "EventCode": "0xB6", 1932 "EventName": "UNC_M_RD_CAS_RANK6.BANK12", 1933 "PerPkg": "1", 1934 "UMask": "0xC", 1935 "Unit": "iMC" 1936 }, 1937 { 1938 "BriefDescription": "RD_CAS Access to Rank 6; Bank 13", 1939 "Counter": "0,1,2,3", 1940 "EventCode": "0xB6", 1941 "EventName": "UNC_M_RD_CAS_RANK6.BANK13", 1942 "PerPkg": "1", 1943 "UMask": "0xD", 1944 "Unit": "iMC" 1945 }, 1946 { 1947 "BriefDescription": "RD_CAS Access to Rank 6; Bank 14", 1948 "Counter": "0,1,2,3", 1949 "EventCode": "0xB6", 1950 "EventName": "UNC_M_RD_CAS_RANK6.BANK14", 1951 "PerPkg": "1", 1952 "UMask": "0xE", 1953 "Unit": "iMC" 1954 }, 1955 { 1956 "BriefDescription": "RD_CAS Access to Rank 6; Bank 15", 1957 "Counter": "0,1,2,3", 1958 "EventCode": "0xB6", 1959 "EventName": "UNC_M_RD_CAS_RANK6.BANK15", 1960 "PerPkg": "1", 1961 "UMask": "0xF", 1962 "Unit": "iMC" 1963 }, 1964 { 1965 "BriefDescription": "RD_CAS Access to Rank 6; All Banks", 1966 "Counter": "0,1,2,3", 1967 "EventCode": "0xB6", 1968 "EventName": "UNC_M_RD_CAS_RANK6.ALLBANKS", 1969 "PerPkg": "1", 1970 "UMask": "0x10", 1971 "Unit": "iMC" 1972 }, 1973 { 1974 "BriefDescription": "RD_CAS Access to Rank 6; Bank Group 0 (Banks 0-3)", 1975 "Counter": "0,1,2,3", 1976 "EventCode": "0xB6", 1977 "EventName": "UNC_M_RD_CAS_RANK6.BANKG0", 1978 "PerPkg": "1", 1979 "UMask": "0x11", 1980 "Unit": "iMC" 1981 }, 1982 { 1983 "BriefDescription": "RD_CAS Access to Rank 6; Bank Group 1 (Banks 4-7)", 1984 "Counter": "0,1,2,3", 1985 "EventCode": "0xB6", 1986 "EventName": "UNC_M_RD_CAS_RANK6.BANKG1", 1987 "PerPkg": "1", 1988 "UMask": "0x12", 1989 "Unit": "iMC" 1990 }, 1991 { 1992 "BriefDescription": "RD_CAS Access to Rank 6; Bank Group 2 (Banks 8-11)", 1993 "Counter": "0,1,2,3", 1994 "EventCode": "0xB6", 1995 "EventName": "UNC_M_RD_CAS_RANK6.BANKG2", 1996 "PerPkg": "1", 1997 "UMask": "0x13", 1998 "Unit": "iMC" 1999 }, 2000 { 2001 "BriefDescription": "RD_CAS Access to Rank 6; Bank Group 3 (Banks 12-15)", 2002 "Counter": "0,1,2,3", 2003 "EventCode": "0xB6", 2004 "EventName": "UNC_M_RD_CAS_RANK6.BANKG3", 2005 "PerPkg": "1", 2006 "UMask": "0x14", 2007 "Unit": "iMC" 2008 }, 2009 { 2010 "BriefDescription": "RD_CAS Access to Rank 7; Bank 0", 2011 "Counter": "0,1,2,3", 2012 "EventCode": "0xB7", 2013 "EventName": "UNC_M_RD_CAS_RANK7.BANK0", 2014 "PerPkg": "1", 2015 "Unit": "iMC" 2016 }, 2017 { 2018 "BriefDescription": "RD_CAS Access to Rank 7; Bank 1", 2019 "Counter": "0,1,2,3", 2020 "EventCode": "0xB7", 2021 "EventName": "UNC_M_RD_CAS_RANK7.BANK1", 2022 "PerPkg": "1", 2023 "UMask": "0x1", 2024 "Unit": "iMC" 2025 }, 2026 { 2027 "BriefDescription": "RD_CAS Access to Rank 7; Bank 2", 2028 "Counter": "0,1,2,3", 2029 "EventCode": "0xB7", 2030 "EventName": "UNC_M_RD_CAS_RANK7.BANK2", 2031 "PerPkg": "1", 2032 "UMask": "0x2", 2033 "Unit": "iMC" 2034 }, 2035 { 2036 "BriefDescription": "RD_CAS Access to Rank 7; Bank 3", 2037 "Counter": "0,1,2,3", 2038 "EventCode": "0xB7", 2039 "EventName": "UNC_M_RD_CAS_RANK7.BANK3", 2040 "PerPkg": "1", 2041 "UMask": "0x3", 2042 "Unit": "iMC" 2043 }, 2044 { 2045 "BriefDescription": "RD_CAS Access to Rank 7; Bank 4", 2046 "Counter": "0,1,2,3", 2047 "EventCode": "0xB7", 2048 "EventName": "UNC_M_RD_CAS_RANK7.BANK4", 2049 "PerPkg": "1", 2050 "UMask": "0x4", 2051 "Unit": "iMC" 2052 }, 2053 { 2054 "BriefDescription": "RD_CAS Access to Rank 7; Bank 5", 2055 "Counter": "0,1,2,3", 2056 "EventCode": "0xB7", 2057 "EventName": "UNC_M_RD_CAS_RANK7.BANK5", 2058 "PerPkg": "1", 2059 "UMask": "0x5", 2060 "Unit": "iMC" 2061 }, 2062 { 2063 "BriefDescription": "RD_CAS Access to Rank 7; Bank 6", 2064 "Counter": "0,1,2,3", 2065 "EventCode": "0xB7", 2066 "EventName": "UNC_M_RD_CAS_RANK7.BANK6", 2067 "PerPkg": "1", 2068 "UMask": "0x6", 2069 "Unit": "iMC" 2070 }, 2071 { 2072 "BriefDescription": "RD_CAS Access to Rank 7; Bank 7", 2073 "Counter": "0,1,2,3", 2074 "EventCode": "0xB7", 2075 "EventName": "UNC_M_RD_CAS_RANK7.BANK7", 2076 "PerPkg": "1", 2077 "UMask": "0x7", 2078 "Unit": "iMC" 2079 }, 2080 { 2081 "BriefDescription": "RD_CAS Access to Rank 7; Bank 8", 2082 "Counter": "0,1,2,3", 2083 "EventCode": "0xB7", 2084 "EventName": "UNC_M_RD_CAS_RANK7.BANK8", 2085 "PerPkg": "1", 2086 "UMask": "0x8", 2087 "Unit": "iMC" 2088 }, 2089 { 2090 "BriefDescription": "RD_CAS Access to Rank 7; Bank 9", 2091 "Counter": "0,1,2,3", 2092 "EventCode": "0xB7", 2093 "EventName": "UNC_M_RD_CAS_RANK7.BANK9", 2094 "PerPkg": "1", 2095 "UMask": "0x9", 2096 "Unit": "iMC" 2097 }, 2098 { 2099 "BriefDescription": "RD_CAS Access to Rank 7; Bank 10", 2100 "Counter": "0,1,2,3", 2101 "EventCode": "0xB7", 2102 "EventName": "UNC_M_RD_CAS_RANK7.BANK10", 2103 "PerPkg": "1", 2104 "UMask": "0xA", 2105 "Unit": "iMC" 2106 }, 2107 { 2108 "BriefDescription": "RD_CAS Access to Rank 7; Bank 11", 2109 "Counter": "0,1,2,3", 2110 "EventCode": "0xB7", 2111 "EventName": "UNC_M_RD_CAS_RANK7.BANK11", 2112 "PerPkg": "1", 2113 "UMask": "0xB", 2114 "Unit": "iMC" 2115 }, 2116 { 2117 "BriefDescription": "RD_CAS Access to Rank 7; Bank 12", 2118 "Counter": "0,1,2,3", 2119 "EventCode": "0xB7", 2120 "EventName": "UNC_M_RD_CAS_RANK7.BANK12", 2121 "PerPkg": "1", 2122 "UMask": "0xC", 2123 "Unit": "iMC" 2124 }, 2125 { 2126 "BriefDescription": "RD_CAS Access to Rank 7; Bank 13", 2127 "Counter": "0,1,2,3", 2128 "EventCode": "0xB7", 2129 "EventName": "UNC_M_RD_CAS_RANK7.BANK13", 2130 "PerPkg": "1", 2131 "UMask": "0xD", 2132 "Unit": "iMC" 2133 }, 2134 { 2135 "BriefDescription": "RD_CAS Access to Rank 7; Bank 14", 2136 "Counter": "0,1,2,3", 2137 "EventCode": "0xB7", 2138 "EventName": "UNC_M_RD_CAS_RANK7.BANK14", 2139 "PerPkg": "1", 2140 "UMask": "0xE", 2141 "Unit": "iMC" 2142 }, 2143 { 2144 "BriefDescription": "RD_CAS Access to Rank 7; Bank 15", 2145 "Counter": "0,1,2,3", 2146 "EventCode": "0xB7", 2147 "EventName": "UNC_M_RD_CAS_RANK7.BANK15", 2148 "PerPkg": "1", 2149 "UMask": "0xF", 2150 "Unit": "iMC" 2151 }, 2152 { 2153 "BriefDescription": "RD_CAS Access to Rank 7; All Banks", 2154 "Counter": "0,1,2,3", 2155 "EventCode": "0xB7", 2156 "EventName": "UNC_M_RD_CAS_RANK7.ALLBANKS", 2157 "PerPkg": "1", 2158 "UMask": "0x10", 2159 "Unit": "iMC" 2160 }, 2161 { 2162 "BriefDescription": "RD_CAS Access to Rank 7; Bank Group 0 (Banks 0-3)", 2163 "Counter": "0,1,2,3", 2164 "EventCode": "0xB7", 2165 "EventName": "UNC_M_RD_CAS_RANK7.BANKG0", 2166 "PerPkg": "1", 2167 "UMask": "0x11", 2168 "Unit": "iMC" 2169 }, 2170 { 2171 "BriefDescription": "RD_CAS Access to Rank 7; Bank Group 1 (Banks 4-7)", 2172 "Counter": "0,1,2,3", 2173 "EventCode": "0xB7", 2174 "EventName": "UNC_M_RD_CAS_RANK7.BANKG1", 2175 "PerPkg": "1", 2176 "UMask": "0x12", 2177 "Unit": "iMC" 2178 }, 2179 { 2180 "BriefDescription": "RD_CAS Access to Rank 7; Bank Group 2 (Banks 8-11)", 2181 "Counter": "0,1,2,3", 2182 "EventCode": "0xB7", 2183 "EventName": "UNC_M_RD_CAS_RANK7.BANKG2", 2184 "PerPkg": "1", 2185 "UMask": "0x13", 2186 "Unit": "iMC" 2187 }, 2188 { 2189 "BriefDescription": "RD_CAS Access to Rank 7; Bank Group 3 (Banks 12-15)", 2190 "Counter": "0,1,2,3", 2191 "EventCode": "0xB7", 2192 "EventName": "UNC_M_RD_CAS_RANK7.BANKG3", 2193 "PerPkg": "1", 2194 "UMask": "0x14", 2195 "Unit": "iMC" 2196 }, 2197 { 2198 "BriefDescription": "Read Pending Queue Full Cycles", 2199 "Counter": "0,1,2,3", 2200 "EventCode": "0x12", 2201 "EventName": "UNC_M_RPQ_CYCLES_FULL", 2202 "PerPkg": "1", 2203 "Unit": "iMC" 2204 }, 2205 { 2206 "BriefDescription": "Read Pending Queue Not Empty", 2207 "Counter": "0,1,2,3", 2208 "EventCode": "0x11", 2209 "EventName": "UNC_M_RPQ_CYCLES_NE", 2210 "PerPkg": "1", 2211 "Unit": "iMC" 2212 }, 2213 { 2214 "BriefDescription": "Scoreboard Accesses; Read Accepts", 2215 "Counter": "0,1,2,3", 2216 "EventCode": "0xD2", 2217 "EventName": "UNC_M_SB_ACCESSES.RD_ACCEPTS", 2218 "PerPkg": "1", 2219 "UMask": "0x1", 2220 "Unit": "iMC" 2221 }, 2222 { 2223 "BriefDescription": "Scoreboard Accesses; Read Rejects", 2224 "Counter": "0,1,2,3", 2225 "EventCode": "0xD2", 2226 "EventName": "UNC_M_SB_ACCESSES.RD_REJECTS", 2227 "PerPkg": "1", 2228 "UMask": "0x2", 2229 "Unit": "iMC" 2230 }, 2231 { 2232 "BriefDescription": "Scoreboard Accesses; NM read completions", 2233 "Counter": "0,1,2,3", 2234 "EventCode": "0xD2", 2235 "EventName": "UNC_M_SB_ACCESSES.WR_ACCEPTS", 2236 "PerPkg": "1", 2237 "UMask": "0x4", 2238 "Unit": "iMC" 2239 }, 2240 { 2241 "BriefDescription": "Scoreboard Accesses; NM write completions", 2242 "Counter": "0,1,2,3", 2243 "EventCode": "0xD2", 2244 "EventName": "UNC_M_SB_ACCESSES.WR_REJECTS", 2245 "PerPkg": "1", 2246 "UMask": "0x8", 2247 "Unit": "iMC" 2248 }, 2249 { 2250 "BriefDescription": "Scoreboard Accesses; FM read completions", 2251 "Counter": "0,1,2,3", 2252 "EventCode": "0xD2", 2253 "EventName": "UNC_M_SB_ACCESSES.NM_RD_CMPS", 2254 "PerPkg": "1", 2255 "UMask": "0x10", 2256 "Unit": "iMC" 2257 }, 2258 { 2259 "BriefDescription": "Scoreboard Accesses; FM write completions", 2260 "Counter": "0,1,2,3", 2261 "EventCode": "0xD2", 2262 "EventName": "UNC_M_SB_ACCESSES.NM_WR_CMPS", 2263 "PerPkg": "1", 2264 "UMask": "0x20", 2265 "Unit": "iMC" 2266 }, 2267 { 2268 "BriefDescription": "Scoreboard Accesses; Write Accepts", 2269 "Counter": "0,1,2,3", 2270 "EventCode": "0xD2", 2271 "EventName": "UNC_M_SB_ACCESSES.FM_RD_CMPS", 2272 "PerPkg": "1", 2273 "UMask": "0x40", 2274 "Unit": "iMC" 2275 }, 2276 { 2277 "BriefDescription": "Scoreboard Accesses; Write Rejects", 2278 "Counter": "0,1,2,3", 2279 "EventCode": "0xD2", 2280 "EventName": "UNC_M_SB_ACCESSES.FM_WR_CMPS", 2281 "PerPkg": "1", 2282 "UMask": "0x80", 2283 "Unit": "iMC" 2284 }, 2285 { 2286 "BriefDescription": "Alloc", 2287 "Counter": "0,1,2,3", 2288 "EventCode": "0xD9", 2289 "EventName": "UNC_M_SB_CANARY.ALLOC", 2290 "PerPkg": "1", 2291 "UMask": "0x1", 2292 "Unit": "iMC" 2293 }, 2294 { 2295 "BriefDescription": "Dealloc", 2296 "Counter": "0,1,2,3", 2297 "EventCode": "0xD9", 2298 "EventName": "UNC_M_SB_CANARY.DEALLOC", 2299 "PerPkg": "1", 2300 "UMask": "0x2", 2301 "Unit": "iMC" 2302 }, 2303 { 2304 "BriefDescription": "Reject", 2305 "Counter": "0,1,2,3", 2306 "EventCode": "0xD9", 2307 "EventName": "UNC_M_SB_CANARY.REJ", 2308 "PerPkg": "1", 2309 "UMask": "0x4", 2310 "Unit": "iMC" 2311 }, 2312 { 2313 "BriefDescription": "Valid", 2314 "Counter": "0,1,2,3", 2315 "EventCode": "0xD9", 2316 "EventName": "UNC_M_SB_CANARY.VLD", 2317 "PerPkg": "1", 2318 "UMask": "0x8", 2319 "Unit": "iMC" 2320 }, 2321 { 2322 "BriefDescription": "Near Mem Read Starved", 2323 "Counter": "0,1,2,3", 2324 "EventCode": "0xD9", 2325 "EventName": "UNC_M_SB_CANARY.NMRD_STARVED", 2326 "PerPkg": "1", 2327 "UMask": "0x10", 2328 "Unit": "iMC" 2329 }, 2330 { 2331 "BriefDescription": "Near Mem Write Starved", 2332 "Counter": "0,1,2,3", 2333 "EventCode": "0xD9", 2334 "EventName": "UNC_M_SB_CANARY.NMWR_STARVED", 2335 "PerPkg": "1", 2336 "UMask": "0x20", 2337 "Unit": "iMC" 2338 }, 2339 { 2340 "BriefDescription": "Far Mem Read Starved", 2341 "Counter": "0,1,2,3", 2342 "EventCode": "0xD9", 2343 "EventName": "UNC_M_SB_CANARY.FMRD_STARVED", 2344 "PerPkg": "1", 2345 "UMask": "0x40", 2346 "Unit": "iMC" 2347 }, 2348 { 2349 "BriefDescription": "Far Mem Write Starved", 2350 "Counter": "0,1,2,3", 2351 "EventCode": "0xD9", 2352 "EventName": "UNC_M_SB_CANARY.FMWR_STARVED", 2353 "PerPkg": "1", 2354 "UMask": "0x80", 2355 "Unit": "iMC" 2356 }, 2357 { 2358 "BriefDescription": "Scoreboard Cycles Full", 2359 "Counter": "0,1,2,3", 2360 "EventCode": "0xD1", 2361 "EventName": "UNC_M_SB_CYCLES_FULL", 2362 "PerPkg": "1", 2363 "Unit": "iMC" 2364 }, 2365 { 2366 "BriefDescription": "Scoreboard Cycles Not-Empty", 2367 "Counter": "0,1,2,3", 2368 "EventCode": "0xD0", 2369 "EventName": "UNC_M_SB_CYCLES_NE", 2370 "PerPkg": "1", 2371 "Unit": "iMC" 2372 }, 2373 { 2374 "BriefDescription": "Scoreboard Inserts; Reads", 2375 "Counter": "0,1,2,3", 2376 "EventCode": "0xD6", 2377 "EventName": "UNC_M_SB_INSERTS.RDS", 2378 "PerPkg": "1", 2379 "UMask": "0x1", 2380 "Unit": "iMC" 2381 }, 2382 { 2383 "BriefDescription": "Scoreboard Inserts; Writes", 2384 "Counter": "0,1,2,3", 2385 "EventCode": "0xD6", 2386 "EventName": "UNC_M_SB_INSERTS.WRS", 2387 "PerPkg": "1", 2388 "UMask": "0x2", 2389 "Unit": "iMC" 2390 }, 2391 { 2392 "BriefDescription": "Scoreboard Inserts; Block region reads", 2393 "Counter": "0,1,2,3", 2394 "EventCode": "0xD6", 2395 "EventName": "UNC_M_SB_INSERTS.BLOCK_RDS", 2396 "PerPkg": "1", 2397 "UMask": "0x10", 2398 "Unit": "iMC" 2399 }, 2400 { 2401 "BriefDescription": "Scoreboard Inserts; Block region writes", 2402 "Counter": "0,1,2,3", 2403 "EventCode": "0xD6", 2404 "EventName": "UNC_M_SB_INSERTS.BLOCK_WRS", 2405 "PerPkg": "1", 2406 "UMask": "0x20", 2407 "Unit": "iMC" 2408 }, 2409 { 2410 "BriefDescription": "Scoreboard Inserts; Dealloc all commands (for error flows)", 2411 "Counter": "0,1,2,3", 2412 "EventCode": "0xD6", 2413 "EventName": "UNC_M_SB_INSERTS.DEALLOC", 2414 "PerPkg": "1", 2415 "UMask": "0x40", 2416 "Unit": "iMC" 2417 }, 2418 { 2419 "BriefDescription": "Scoreboard Inserts; Patrol inserts", 2420 "Counter": "0,1,2,3", 2421 "EventCode": "0xD6", 2422 "EventName": "UNC_M_SB_INSERTS.PATROL", 2423 "PerPkg": "1", 2424 "UMask": "0x80", 2425 "Unit": "iMC" 2426 }, 2427 { 2428 "BriefDescription": "Scoreboard Occupancy; Reads", 2429 "Counter": "0,1,2,3", 2430 "EventCode": "0xD5", 2431 "EventName": "UNC_M_SB_OCCUPANCY.RDS", 2432 "PerPkg": "1", 2433 "UMask": "0x1", 2434 "Unit": "iMC" 2435 }, 2436 { 2437 "BriefDescription": "Scoreboard Occupancy; Writes", 2438 "Counter": "0,1,2,3", 2439 "EventCode": "0xD5", 2440 "EventName": "UNC_M_SB_OCCUPANCY.WRS", 2441 "PerPkg": "1", 2442 "UMask": "0x2", 2443 "Unit": "iMC" 2444 }, 2445 { 2446 "BriefDescription": "Scoreboard Occupancy; Block region reads", 2447 "Counter": "0,1,2,3", 2448 "EventCode": "0xD5", 2449 "EventName": "UNC_M_SB_OCCUPANCY.BLOCK_RDS", 2450 "PerPkg": "1", 2451 "UMask": "0x20", 2452 "Unit": "iMC" 2453 }, 2454 { 2455 "BriefDescription": "Scoreboard Occupancy; Block region writes", 2456 "Counter": "0,1,2,3", 2457 "EventCode": "0xD5", 2458 "EventName": "UNC_M_SB_OCCUPANCY.BLOCK_WRS", 2459 "PerPkg": "1", 2460 "UMask": "0x40", 2461 "Unit": "iMC" 2462 }, 2463 { 2464 "BriefDescription": "Scoreboard Occupancy; Patrol", 2465 "Counter": "0,1,2,3", 2466 "EventCode": "0xD5", 2467 "EventName": "UNC_M_SB_OCCUPANCY.PATROL", 2468 "PerPkg": "1", 2469 "UMask": "0x80", 2470 "Unit": "iMC" 2471 }, 2472 { 2473 "BriefDescription": "Number of Scoreboard Requests Rejected; NM requests rejected due to set conflict", 2474 "Counter": "0,1,2,3", 2475 "EventCode": "0xD4", 2476 "EventName": "UNC_M_SB_REJECT.NM_SET_CNFLT", 2477 "PerPkg": "1", 2478 "UMask": "0x1", 2479 "Unit": "iMC" 2480 }, 2481 { 2482 "BriefDescription": "Number of Scoreboard Requests Rejected; FM requests rejected due to full address conflict", 2483 "Counter": "0,1,2,3", 2484 "EventCode": "0xD4", 2485 "EventName": "UNC_M_SB_REJECT.FM_ADDR_CNFLT", 2486 "PerPkg": "1", 2487 "UMask": "0x2", 2488 "Unit": "iMC" 2489 }, 2490 { 2491 "BriefDescription": "Number of Scoreboard Requests Rejected; Patrol requests rejected due to set conflict", 2492 "Counter": "0,1,2,3", 2493 "EventCode": "0xD4", 2494 "EventName": "UNC_M_SB_REJECT.PATROL_SET_CNFLT", 2495 "PerPkg": "1", 2496 "UMask": "0x4", 2497 "Unit": "iMC" 2498 }, 2499 { 2500 "BriefDescription": "Near Mem Read - Set", 2501 "Counter": "0,1,2,3", 2502 "EventCode": "0xD7", 2503 "EventName": "UNC_M_SB_STRV_ALLOC.NMRD_SET", 2504 "PerPkg": "1", 2505 "UMask": "0x1", 2506 "Unit": "iMC" 2507 }, 2508 { 2509 "BriefDescription": "Far Mem Read - Set", 2510 "Counter": "0,1,2,3", 2511 "EventCode": "0xD7", 2512 "EventName": "UNC_M_SB_STRV_ALLOC.FMRD_SET", 2513 "PerPkg": "1", 2514 "UMask": "0x2", 2515 "Unit": "iMC" 2516 }, 2517 { 2518 "BriefDescription": "Near Mem Write - Set", 2519 "Counter": "0,1,2,3", 2520 "EventCode": "0xD7", 2521 "EventName": "UNC_M_SB_STRV_ALLOC.NMWR_SET", 2522 "PerPkg": "1", 2523 "UMask": "0x4", 2524 "Unit": "iMC" 2525 }, 2526 { 2527 "BriefDescription": "Far Mem Write - Set", 2528 "Counter": "0,1,2,3", 2529 "EventCode": "0xD7", 2530 "EventName": "UNC_M_SB_STRV_ALLOC.FMWR_SET", 2531 "PerPkg": "1", 2532 "UMask": "0x8", 2533 "Unit": "iMC" 2534 }, 2535 { 2536 "BriefDescription": "Near Mem Read - Clear", 2537 "Counter": "0,1,2,3", 2538 "EventCode": "0xD7", 2539 "EventName": "UNC_M_SB_STRV_ALLOC.NMRD_CLR", 2540 "PerPkg": "1", 2541 "UMask": "0x10", 2542 "Unit": "iMC" 2543 }, 2544 { 2545 "BriefDescription": "Far Mem Read - Clear", 2546 "Counter": "0,1,2,3", 2547 "EventCode": "0xD7", 2548 "EventName": "UNC_M_SB_STRV_ALLOC.FMRD_CLR", 2549 "PerPkg": "1", 2550 "UMask": "0x20", 2551 "Unit": "iMC" 2552 }, 2553 { 2554 "BriefDescription": "Near Mem Write - Clear", 2555 "Counter": "0,1,2,3", 2556 "EventCode": "0xD7", 2557 "EventName": "UNC_M_SB_STRV_ALLOC.NMWR_CLR", 2558 "PerPkg": "1", 2559 "UMask": "0x40", 2560 "Unit": "iMC" 2561 }, 2562 { 2563 "BriefDescription": "Far Mem Write - Clear", 2564 "Counter": "0,1,2,3", 2565 "EventCode": "0xD7", 2566 "EventName": "UNC_M_SB_STRV_ALLOC.FMWR_CLR", 2567 "PerPkg": "1", 2568 "UMask": "0x80", 2569 "Unit": "iMC" 2570 }, 2571 { 2572 "BriefDescription": "Near Mem Read", 2573 "Counter": "0,1,2,3", 2574 "EventCode": "0xD8", 2575 "EventName": "UNC_M_SB_STRV_OCC.NMRD", 2576 "PerPkg": "1", 2577 "UMask": "0x1", 2578 "Unit": "iMC" 2579 }, 2580 { 2581 "BriefDescription": "Far Mem Read", 2582 "Counter": "0,1,2,3", 2583 "EventCode": "0xD8", 2584 "EventName": "UNC_M_SB_STRV_OCC.FMRD", 2585 "PerPkg": "1", 2586 "UMask": "0x2", 2587 "Unit": "iMC" 2588 }, 2589 { 2590 "BriefDescription": "Near Mem Write", 2591 "Counter": "0,1,2,3", 2592 "EventCode": "0xD8", 2593 "EventName": "UNC_M_SB_STRV_OCC.NMWR", 2594 "PerPkg": "1", 2595 "UMask": "0x4", 2596 "Unit": "iMC" 2597 }, 2598 { 2599 "BriefDescription": "Far Mem Write", 2600 "Counter": "0,1,2,3", 2601 "EventCode": "0xD8", 2602 "EventName": "UNC_M_SB_STRV_OCC.FMWR", 2603 "PerPkg": "1", 2604 "UMask": "0x8", 2605 "Unit": "iMC" 2606 }, 2607 { 2608 "BriefDescription": "UNC_M_SB_TAGGED.NEW", 2609 "Counter": "0,1,2,3", 2610 "EventCode": "0xDD", 2611 "EventName": "UNC_M_SB_TAGGED.NEW", 2612 "PerPkg": "1", 2613 "UMask": "0x1", 2614 "Unit": "iMC" 2615 }, 2616 { 2617 "BriefDescription": "UNC_M_SB_TAGGED.RD_HIT", 2618 "Counter": "0,1,2,3", 2619 "EventCode": "0xDD", 2620 "EventName": "UNC_M_SB_TAGGED.RD_HIT", 2621 "PerPkg": "1", 2622 "UMask": "0x2", 2623 "Unit": "iMC" 2624 }, 2625 { 2626 "BriefDescription": "UNC_M_SB_TAGGED.RD_MISS", 2627 "Counter": "0,1,2,3", 2628 "EventCode": "0xDD", 2629 "EventName": "UNC_M_SB_TAGGED.RD_MISS", 2630 "PerPkg": "1", 2631 "UMask": "0x4", 2632 "Unit": "iMC" 2633 }, 2634 { 2635 "BriefDescription": "UNC_M_SB_TAGGED.DDR4_CMP", 2636 "Counter": "0,1,2,3", 2637 "EventCode": "0xDD", 2638 "EventName": "UNC_M_SB_TAGGED.DDR4_CMP", 2639 "PerPkg": "1", 2640 "UMask": "0x8", 2641 "Unit": "iMC" 2642 }, 2643 { 2644 "BriefDescription": "UNC_M_SB_TAGGED.OCC", 2645 "Counter": "0,1,2,3", 2646 "EventCode": "0xDD", 2647 "EventName": "UNC_M_SB_TAGGED.OCC", 2648 "PerPkg": "1", 2649 "UMask": "0x80", 2650 "Unit": "iMC" 2651 }, 2652 { 2653 "BriefDescription": "Transition from WMM to RMM because of low threshold; Transition from WMM to RMM because of starve counter", 2654 "Counter": "0,1,2,3", 2655 "EventCode": "0xC0", 2656 "EventName": "UNC_M_WMM_TO_RMM.LOW_THRESH", 2657 "PerPkg": "1", 2658 "UMask": "0x1", 2659 "Unit": "iMC" 2660 }, 2661 { 2662 "BriefDescription": "Transition from WMM to RMM because of low threshold", 2663 "Counter": "0,1,2,3", 2664 "EventCode": "0xC0", 2665 "EventName": "UNC_M_WMM_TO_RMM.STARVE", 2666 "PerPkg": "1", 2667 "UMask": "0x2", 2668 "Unit": "iMC" 2669 }, 2670 { 2671 "BriefDescription": "Transition from WMM to RMM because of low threshold", 2672 "Counter": "0,1,2,3", 2673 "EventCode": "0xC0", 2674 "EventName": "UNC_M_WMM_TO_RMM.VMSE_RETRY", 2675 "PerPkg": "1", 2676 "UMask": "0x4", 2677 "Unit": "iMC" 2678 }, 2679 { 2680 "BriefDescription": "Write Pending Queue Full Cycles", 2681 "Counter": "0,1,2,3", 2682 "EventCode": "0x22", 2683 "EventName": "UNC_M_WPQ_CYCLES_FULL", 2684 "PerPkg": "1", 2685 "Unit": "iMC" 2686 }, 2687 { 2688 "BriefDescription": "Write Pending Queue Not Empty", 2689 "Counter": "0,1,2,3", 2690 "EventCode": "0x21", 2691 "EventName": "UNC_M_WPQ_CYCLES_NE", 2692 "PerPkg": "1", 2693 "Unit": "iMC" 2694 }, 2695 { 2696 "BriefDescription": "Write Pending Queue CAM Match", 2697 "Counter": "0,1,2,3", 2698 "EventCode": "0x23", 2699 "EventName": "UNC_M_WPQ_READ_HIT", 2700 "PerPkg": "1", 2701 "Unit": "iMC" 2702 }, 2703 { 2704 "BriefDescription": "Write Pending Queue CAM Match", 2705 "Counter": "0,1,2,3", 2706 "EventCode": "0x24", 2707 "EventName": "UNC_M_WPQ_WRITE_HIT", 2708 "PerPkg": "1", 2709 "Unit": "iMC" 2710 }, 2711 { 2712 "BriefDescription": "Not getting the requested Major Mode", 2713 "Counter": "0,1,2,3", 2714 "EventCode": "0xC1", 2715 "EventName": "UNC_M_WRONG_MM", 2716 "PerPkg": "1", 2717 "Unit": "iMC" 2718 }, 2719 { 2720 "BriefDescription": "WR_CAS Access to Rank 0; Bank 0", 2721 "Counter": "0,1,2,3", 2722 "EventCode": "0xB8", 2723 "EventName": "UNC_M_WR_CAS_RANK0.BANK0", 2724 "PerPkg": "1", 2725 "Unit": "iMC" 2726 }, 2727 { 2728 "BriefDescription": "WR_CAS Access to Rank 0; Bank 1", 2729 "Counter": "0,1,2,3", 2730 "EventCode": "0xB8", 2731 "EventName": "UNC_M_WR_CAS_RANK0.BANK1", 2732 "PerPkg": "1", 2733 "UMask": "0x1", 2734 "Unit": "iMC" 2735 }, 2736 { 2737 "BriefDescription": "WR_CAS Access to Rank 0; Bank 2", 2738 "Counter": "0,1,2,3", 2739 "EventCode": "0xB8", 2740 "EventName": "UNC_M_WR_CAS_RANK0.BANK2", 2741 "PerPkg": "1", 2742 "UMask": "0x2", 2743 "Unit": "iMC" 2744 }, 2745 { 2746 "BriefDescription": "WR_CAS Access to Rank 0; Bank 3", 2747 "Counter": "0,1,2,3", 2748 "EventCode": "0xB8", 2749 "EventName": "UNC_M_WR_CAS_RANK0.BANK3", 2750 "PerPkg": "1", 2751 "UMask": "0x3", 2752 "Unit": "iMC" 2753 }, 2754 { 2755 "BriefDescription": "WR_CAS Access to Rank 0; Bank 4", 2756 "Counter": "0,1,2,3", 2757 "EventCode": "0xB8", 2758 "EventName": "UNC_M_WR_CAS_RANK0.BANK4", 2759 "PerPkg": "1", 2760 "UMask": "0x4", 2761 "Unit": "iMC" 2762 }, 2763 { 2764 "BriefDescription": "WR_CAS Access to Rank 0; Bank 5", 2765 "Counter": "0,1,2,3", 2766 "EventCode": "0xB8", 2767 "EventName": "UNC_M_WR_CAS_RANK0.BANK5", 2768 "PerPkg": "1", 2769 "UMask": "0x5", 2770 "Unit": "iMC" 2771 }, 2772 { 2773 "BriefDescription": "WR_CAS Access to Rank 0; Bank 6", 2774 "Counter": "0,1,2,3", 2775 "EventCode": "0xB8", 2776 "EventName": "UNC_M_WR_CAS_RANK0.BANK6", 2777 "PerPkg": "1", 2778 "UMask": "0x6", 2779 "Unit": "iMC" 2780 }, 2781 { 2782 "BriefDescription": "WR_CAS Access to Rank 0; Bank 7", 2783 "Counter": "0,1,2,3", 2784 "EventCode": "0xB8", 2785 "EventName": "UNC_M_WR_CAS_RANK0.BANK7", 2786 "PerPkg": "1", 2787 "UMask": "0x7", 2788 "Unit": "iMC" 2789 }, 2790 { 2791 "BriefDescription": "WR_CAS Access to Rank 0; Bank 8", 2792 "Counter": "0,1,2,3", 2793 "EventCode": "0xB8", 2794 "EventName": "UNC_M_WR_CAS_RANK0.BANK8", 2795 "PerPkg": "1", 2796 "UMask": "0x8", 2797 "Unit": "iMC" 2798 }, 2799 { 2800 "BriefDescription": "WR_CAS Access to Rank 0; Bank 9", 2801 "Counter": "0,1,2,3", 2802 "EventCode": "0xB8", 2803 "EventName": "UNC_M_WR_CAS_RANK0.BANK9", 2804 "PerPkg": "1", 2805 "UMask": "0x9", 2806 "Unit": "iMC" 2807 }, 2808 { 2809 "BriefDescription": "WR_CAS Access to Rank 0; Bank 10", 2810 "Counter": "0,1,2,3", 2811 "EventCode": "0xB8", 2812 "EventName": "UNC_M_WR_CAS_RANK0.BANK10", 2813 "PerPkg": "1", 2814 "UMask": "0xA", 2815 "Unit": "iMC" 2816 }, 2817 { 2818 "BriefDescription": "WR_CAS Access to Rank 0; Bank 11", 2819 "Counter": "0,1,2,3", 2820 "EventCode": "0xB8", 2821 "EventName": "UNC_M_WR_CAS_RANK0.BANK11", 2822 "PerPkg": "1", 2823 "UMask": "0xB", 2824 "Unit": "iMC" 2825 }, 2826 { 2827 "BriefDescription": "WR_CAS Access to Rank 0; Bank 12", 2828 "Counter": "0,1,2,3", 2829 "EventCode": "0xB8", 2830 "EventName": "UNC_M_WR_CAS_RANK0.BANK12", 2831 "PerPkg": "1", 2832 "UMask": "0xC", 2833 "Unit": "iMC" 2834 }, 2835 { 2836 "BriefDescription": "WR_CAS Access to Rank 0; Bank 13", 2837 "Counter": "0,1,2,3", 2838 "EventCode": "0xB8", 2839 "EventName": "UNC_M_WR_CAS_RANK0.BANK13", 2840 "PerPkg": "1", 2841 "UMask": "0xD", 2842 "Unit": "iMC" 2843 }, 2844 { 2845 "BriefDescription": "WR_CAS Access to Rank 0; Bank 14", 2846 "Counter": "0,1,2,3", 2847 "EventCode": "0xB8", 2848 "EventName": "UNC_M_WR_CAS_RANK0.BANK14", 2849 "PerPkg": "1", 2850 "UMask": "0xE", 2851 "Unit": "iMC" 2852 }, 2853 { 2854 "BriefDescription": "WR_CAS Access to Rank 0; Bank 15", 2855 "Counter": "0,1,2,3", 2856 "EventCode": "0xB8", 2857 "EventName": "UNC_M_WR_CAS_RANK0.BANK15", 2858 "PerPkg": "1", 2859 "UMask": "0xF", 2860 "Unit": "iMC" 2861 }, 2862 { 2863 "BriefDescription": "WR_CAS Access to Rank 0; All Banks", 2864 "Counter": "0,1,2,3", 2865 "EventCode": "0xB8", 2866 "EventName": "UNC_M_WR_CAS_RANK0.ALLBANKS", 2867 "PerPkg": "1", 2868 "UMask": "0x10", 2869 "Unit": "iMC" 2870 }, 2871 { 2872 "BriefDescription": "WR_CAS Access to Rank 0; Bank Group 0 (Banks 0-3)", 2873 "Counter": "0,1,2,3", 2874 "EventCode": "0xB8", 2875 "EventName": "UNC_M_WR_CAS_RANK0.BANKG0", 2876 "PerPkg": "1", 2877 "UMask": "0x11", 2878 "Unit": "iMC" 2879 }, 2880 { 2881 "BriefDescription": "WR_CAS Access to Rank 0; Bank Group 1 (Banks 4-7)", 2882 "Counter": "0,1,2,3", 2883 "EventCode": "0xB8", 2884 "EventName": "UNC_M_WR_CAS_RANK0.BANKG1", 2885 "PerPkg": "1", 2886 "UMask": "0x12", 2887 "Unit": "iMC" 2888 }, 2889 { 2890 "BriefDescription": "WR_CAS Access to Rank 0; Bank Group 2 (Banks 8-11)", 2891 "Counter": "0,1,2,3", 2892 "EventCode": "0xB8", 2893 "EventName": "UNC_M_WR_CAS_RANK0.BANKG2", 2894 "PerPkg": "1", 2895 "UMask": "0x13", 2896 "Unit": "iMC" 2897 }, 2898 { 2899 "BriefDescription": "WR_CAS Access to Rank 0; Bank Group 3 (Banks 12-15)", 2900 "Counter": "0,1,2,3", 2901 "EventCode": "0xB8", 2902 "EventName": "UNC_M_WR_CAS_RANK0.BANKG3", 2903 "PerPkg": "1", 2904 "UMask": "0x14", 2905 "Unit": "iMC" 2906 }, 2907 { 2908 "BriefDescription": "WR_CAS Access to Rank 1; Bank 0", 2909 "Counter": "0,1,2,3", 2910 "EventCode": "0xB9", 2911 "EventName": "UNC_M_WR_CAS_RANK1.BANK0", 2912 "PerPkg": "1", 2913 "Unit": "iMC" 2914 }, 2915 { 2916 "BriefDescription": "WR_CAS Access to Rank 1; Bank 1", 2917 "Counter": "0,1,2,3", 2918 "EventCode": "0xB9", 2919 "EventName": "UNC_M_WR_CAS_RANK1.BANK1", 2920 "PerPkg": "1", 2921 "UMask": "0x1", 2922 "Unit": "iMC" 2923 }, 2924 { 2925 "BriefDescription": "WR_CAS Access to Rank 1; Bank 2", 2926 "Counter": "0,1,2,3", 2927 "EventCode": "0xB9", 2928 "EventName": "UNC_M_WR_CAS_RANK1.BANK2", 2929 "PerPkg": "1", 2930 "UMask": "0x2", 2931 "Unit": "iMC" 2932 }, 2933 { 2934 "BriefDescription": "WR_CAS Access to Rank 1; Bank 3", 2935 "Counter": "0,1,2,3", 2936 "EventCode": "0xB9", 2937 "EventName": "UNC_M_WR_CAS_RANK1.BANK3", 2938 "PerPkg": "1", 2939 "UMask": "0x3", 2940 "Unit": "iMC" 2941 }, 2942 { 2943 "BriefDescription": "WR_CAS Access to Rank 1; Bank 4", 2944 "Counter": "0,1,2,3", 2945 "EventCode": "0xB9", 2946 "EventName": "UNC_M_WR_CAS_RANK1.BANK4", 2947 "PerPkg": "1", 2948 "UMask": "0x4", 2949 "Unit": "iMC" 2950 }, 2951 { 2952 "BriefDescription": "WR_CAS Access to Rank 1; Bank 5", 2953 "Counter": "0,1,2,3", 2954 "EventCode": "0xB9", 2955 "EventName": "UNC_M_WR_CAS_RANK1.BANK5", 2956 "PerPkg": "1", 2957 "UMask": "0x5", 2958 "Unit": "iMC" 2959 }, 2960 { 2961 "BriefDescription": "WR_CAS Access to Rank 1; Bank 6", 2962 "Counter": "0,1,2,3", 2963 "EventCode": "0xB9", 2964 "EventName": "UNC_M_WR_CAS_RANK1.BANK6", 2965 "PerPkg": "1", 2966 "UMask": "0x6", 2967 "Unit": "iMC" 2968 }, 2969 { 2970 "BriefDescription": "WR_CAS Access to Rank 1; Bank 7", 2971 "Counter": "0,1,2,3", 2972 "EventCode": "0xB9", 2973 "EventName": "UNC_M_WR_CAS_RANK1.BANK7", 2974 "PerPkg": "1", 2975 "UMask": "0x7", 2976 "Unit": "iMC" 2977 }, 2978 { 2979 "BriefDescription": "WR_CAS Access to Rank 1; Bank 8", 2980 "Counter": "0,1,2,3", 2981 "EventCode": "0xB9", 2982 "EventName": "UNC_M_WR_CAS_RANK1.BANK8", 2983 "PerPkg": "1", 2984 "UMask": "0x8", 2985 "Unit": "iMC" 2986 }, 2987 { 2988 "BriefDescription": "WR_CAS Access to Rank 1; Bank 9", 2989 "Counter": "0,1,2,3", 2990 "EventCode": "0xB9", 2991 "EventName": "UNC_M_WR_CAS_RANK1.BANK9", 2992 "PerPkg": "1", 2993 "UMask": "0x9", 2994 "Unit": "iMC" 2995 }, 2996 { 2997 "BriefDescription": "WR_CAS Access to Rank 1; Bank 10", 2998 "Counter": "0,1,2,3", 2999 "EventCode": "0xB9", 3000 "EventName": "UNC_M_WR_CAS_RANK1.BANK10", 3001 "PerPkg": "1", 3002 "UMask": "0xA", 3003 "Unit": "iMC" 3004 }, 3005 { 3006 "BriefDescription": "WR_CAS Access to Rank 1; Bank 11", 3007 "Counter": "0,1,2,3", 3008 "EventCode": "0xB9", 3009 "EventName": "UNC_M_WR_CAS_RANK1.BANK11", 3010 "PerPkg": "1", 3011 "UMask": "0xB", 3012 "Unit": "iMC" 3013 }, 3014 { 3015 "BriefDescription": "WR_CAS Access to Rank 1; Bank 12", 3016 "Counter": "0,1,2,3", 3017 "EventCode": "0xB9", 3018 "EventName": "UNC_M_WR_CAS_RANK1.BANK12", 3019 "PerPkg": "1", 3020 "UMask": "0xC", 3021 "Unit": "iMC" 3022 }, 3023 { 3024 "BriefDescription": "WR_CAS Access to Rank 1; Bank 13", 3025 "Counter": "0,1,2,3", 3026 "EventCode": "0xB9", 3027 "EventName": "UNC_M_WR_CAS_RANK1.BANK13", 3028 "PerPkg": "1", 3029 "UMask": "0xD", 3030 "Unit": "iMC" 3031 }, 3032 { 3033 "BriefDescription": "WR_CAS Access to Rank 1; Bank 14", 3034 "Counter": "0,1,2,3", 3035 "EventCode": "0xB9", 3036 "EventName": "UNC_M_WR_CAS_RANK1.BANK14", 3037 "PerPkg": "1", 3038 "UMask": "0xE", 3039 "Unit": "iMC" 3040 }, 3041 { 3042 "BriefDescription": "WR_CAS Access to Rank 1; Bank 15", 3043 "Counter": "0,1,2,3", 3044 "EventCode": "0xB9", 3045 "EventName": "UNC_M_WR_CAS_RANK1.BANK15", 3046 "PerPkg": "1", 3047 "UMask": "0xF", 3048 "Unit": "iMC" 3049 }, 3050 { 3051 "BriefDescription": "WR_CAS Access to Rank 1; All Banks", 3052 "Counter": "0,1,2,3", 3053 "EventCode": "0xB9", 3054 "EventName": "UNC_M_WR_CAS_RANK1.ALLBANKS", 3055 "PerPkg": "1", 3056 "UMask": "0x10", 3057 "Unit": "iMC" 3058 }, 3059 { 3060 "BriefDescription": "WR_CAS Access to Rank 1; Bank Group 0 (Banks 0-3)", 3061 "Counter": "0,1,2,3", 3062 "EventCode": "0xB9", 3063 "EventName": "UNC_M_WR_CAS_RANK1.BANKG0", 3064 "PerPkg": "1", 3065 "UMask": "0x11", 3066 "Unit": "iMC" 3067 }, 3068 { 3069 "BriefDescription": "WR_CAS Access to Rank 1; Bank Group 1 (Banks 4-7)", 3070 "Counter": "0,1,2,3", 3071 "EventCode": "0xB9", 3072 "EventName": "UNC_M_WR_CAS_RANK1.BANKG1", 3073 "PerPkg": "1", 3074 "UMask": "0x12", 3075 "Unit": "iMC" 3076 }, 3077 { 3078 "BriefDescription": "WR_CAS Access to Rank 1; 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Bank 7", 4099 "Counter": "0,1,2,3", 4100 "EventCode": "0xBF", 4101 "EventName": "UNC_M_WR_CAS_RANK7.BANK7", 4102 "PerPkg": "1", 4103 "UMask": "0x7", 4104 "Unit": "iMC" 4105 }, 4106 { 4107 "BriefDescription": "WR_CAS Access to Rank 7; Bank 8", 4108 "Counter": "0,1,2,3", 4109 "EventCode": "0xBF", 4110 "EventName": "UNC_M_WR_CAS_RANK7.BANK8", 4111 "PerPkg": "1", 4112 "UMask": "0x8", 4113 "Unit": "iMC" 4114 }, 4115 { 4116 "BriefDescription": "WR_CAS Access to Rank 7; Bank 9", 4117 "Counter": "0,1,2,3", 4118 "EventCode": "0xBF", 4119 "EventName": "UNC_M_WR_CAS_RANK7.BANK9", 4120 "PerPkg": "1", 4121 "UMask": "0x9", 4122 "Unit": "iMC" 4123 }, 4124 { 4125 "BriefDescription": "WR_CAS Access to Rank 7; Bank 10", 4126 "Counter": "0,1,2,3", 4127 "EventCode": "0xBF", 4128 "EventName": "UNC_M_WR_CAS_RANK7.BANK10", 4129 "PerPkg": "1", 4130 "UMask": "0xA", 4131 "Unit": "iMC" 4132 }, 4133 { 4134 "BriefDescription": "WR_CAS Access to Rank 7; Bank 11", 4135 "Counter": "0,1,2,3", 4136 "EventCode": "0xBF", 4137 "EventName": "UNC_M_WR_CAS_RANK7.BANK11", 4138 "PerPkg": "1", 4139 "UMask": "0xB", 4140 "Unit": "iMC" 4141 }, 4142 { 4143 "BriefDescription": "WR_CAS Access to Rank 7; Bank 12", 4144 "Counter": "0,1,2,3", 4145 "EventCode": "0xBF", 4146 "EventName": "UNC_M_WR_CAS_RANK7.BANK12", 4147 "PerPkg": "1", 4148 "UMask": "0xC", 4149 "Unit": "iMC" 4150 }, 4151 { 4152 "BriefDescription": "WR_CAS Access to Rank 7; Bank 13", 4153 "Counter": "0,1,2,3", 4154 "EventCode": "0xBF", 4155 "EventName": "UNC_M_WR_CAS_RANK7.BANK13", 4156 "PerPkg": "1", 4157 "UMask": "0xD", 4158 "Unit": "iMC" 4159 }, 4160 { 4161 "BriefDescription": "WR_CAS Access to Rank 7; Bank 14", 4162 "Counter": "0,1,2,3", 4163 "EventCode": "0xBF", 4164 "EventName": "UNC_M_WR_CAS_RANK7.BANK14", 4165 "PerPkg": "1", 4166 "UMask": "0xE", 4167 "Unit": "iMC" 4168 }, 4169 { 4170 "BriefDescription": "WR_CAS Access to Rank 7; Bank 15", 4171 "Counter": "0,1,2,3", 4172 "EventCode": "0xBF", 4173 "EventName": "UNC_M_WR_CAS_RANK7.BANK15", 4174 "PerPkg": "1", 4175 "UMask": "0xF", 4176 "Unit": "iMC" 4177 }, 4178 { 4179 "BriefDescription": "WR_CAS Access to Rank 7; All Banks", 4180 "Counter": "0,1,2,3", 4181 "EventCode": "0xBF", 4182 "EventName": "UNC_M_WR_CAS_RANK7.ALLBANKS", 4183 "PerPkg": "1", 4184 "UMask": "0x10", 4185 "Unit": "iMC" 4186 }, 4187 { 4188 "BriefDescription": "WR_CAS Access to Rank 7; Bank Group 0 (Banks 0-3)", 4189 "Counter": "0,1,2,3", 4190 "EventCode": "0xBF", 4191 "EventName": "UNC_M_WR_CAS_RANK7.BANKG0", 4192 "PerPkg": "1", 4193 "UMask": "0x11", 4194 "Unit": "iMC" 4195 }, 4196 { 4197 "BriefDescription": "WR_CAS Access to Rank 7; Bank Group 1 (Banks 4-7)", 4198 "Counter": "0,1,2,3", 4199 "EventCode": "0xBF", 4200 "EventName": "UNC_M_WR_CAS_RANK7.BANKG1", 4201 "PerPkg": "1", 4202 "UMask": "0x12", 4203 "Unit": "iMC" 4204 }, 4205 { 4206 "BriefDescription": "WR_CAS Access to Rank 7; Bank Group 2 (Banks 8-11)", 4207 "Counter": "0,1,2,3", 4208 "EventCode": "0xBF", 4209 "EventName": "UNC_M_WR_CAS_RANK7.BANKG2", 4210 "PerPkg": "1", 4211 "UMask": "0x13", 4212 "Unit": "iMC" 4213 }, 4214 { 4215 "BriefDescription": "WR_CAS Access to Rank 7; Bank Group 3 (Banks 12-15)", 4216 "Counter": "0,1,2,3", 4217 "EventCode": "0xBF", 4218 "EventName": "UNC_M_WR_CAS_RANK7.BANKG3", 4219 "PerPkg": "1", 4220 "UMask": "0x14", 4221 "Unit": "iMC" 4222 }, 4223 { 4224 "BriefDescription": "Clockticks in the Memory Controller using a dedicated 48-bit Fixed Counter", 4225 "Counter": "FIXED", 4226 "EventCode": "0xff", 4227 "EventName": "UNC_M_CLOCKTICKS_F", 4228 "PerPkg": "1", 4229 "Unit": "iMC" 4230 }, 4231 { 4232 "BriefDescription": "PMM Occupancy", 4233 "Counter": "0,1,2,3", 4234 "EventCode": "0xE0", 4235 "EventName": "UNC_M_PMM_RPQ_OCCUPANCY.GNT_WAIT", 4236 "PerPkg": "1", 4237 "UMask": "0x4", 4238 "Unit": "iMC" 4239 }, 4240 { 4241 "BriefDescription": "PMM Read Queue Cycles Not Empty", 4242 "Counter": "0,1,2,3", 4243 "EventCode": "0xE1", 4244 "EventName": "UNC_M_PMM_RPQ_CYCLES_NE", 4245 "PerPkg": "1", 4246 "Unit": "iMC" 4247 }, 4248 { 4249 "BriefDescription": "PMM Read Queue Cycles Full", 4250 "Counter": "0,1,2,3", 4251 "EventCode": "0xE2", 4252 "EventName": "UNC_M_PMM_RPQ_CYCLES_FULL", 4253 "PerPkg": "1", 4254 "Unit": "iMC" 4255 }, 4256 { 4257 "BriefDescription": "RPQ GNTs", 4258 "Counter": "0,1,2,3", 4259 "EventCode": "0xEA", 4260 "EventName": "UNC_M_PMM_CMD1.RPQ_GNTS", 4261 "PerPkg": "1", 4262 "UMask": "0x10", 4263 "Unit": "iMC" 4264 }, 4265 { 4266 "BriefDescription": "Underfill GNTs", 4267 "Counter": "0,1,2,3", 4268 "EventCode": "0xEA", 4269 "EventName": "UNC_M_PMM_CMD1.WPQ_GNTS", 4270 "PerPkg": "1", 4271 "UMask": "0x20", 4272 "Unit": "iMC" 4273 }, 4274 { 4275 "BriefDescription": "Misc GNTs", 4276 "Counter": "0,1,2,3", 4277 "EventCode": "0xEA", 4278 "EventName": "UNC_M_PMM_CMD1.MISC_GNT", 4279 "PerPkg": "1", 4280 "UMask": "0x40", 4281 "Unit": "iMC" 4282 }, 4283 { 4284 "BriefDescription": "Misc Commands (error, flow ACKs)", 4285 "Counter": "0,1,2,3", 4286 "EventCode": "0xEA", 4287 "EventName": "UNC_M_PMM_CMD1.MISC", 4288 "PerPkg": "1", 4289 "UMask": "0x80", 4290 "Unit": "iMC" 4291 }, 4292 { 4293 "BriefDescription": "Opportunistic Reads", 4294 "Counter": "0,1,2,3", 4295 "EventCode": "0xEB", 4296 "EventName": "UNC_M_PMM_CMD2.OPP_RD", 4297 "PerPkg": "1", 4298 "UMask": "0x1", 4299 "Unit": "iMC" 4300 }, 4301 { 4302 "BriefDescription": "Expected No data packet (ERID matched NDP encoding)", 4303 "Counter": "0,1,2,3", 4304 "EventCode": "0xEB", 4305 "EventName": "UNC_M_PMM_CMD2.NODATA_EXP", 4306 "PerPkg": "1", 4307 "UMask": "0x2", 4308 "Unit": "iMC" 4309 }, 4310 { 4311 "BriefDescription": "Unexpected No data packet (ERID matched a Read, but data was a NDP)", 4312 "Counter": "0,1,2,3", 4313 "EventCode": "0xEB", 4314 "EventName": "UNC_M_PMM_CMD2.NODATA_UNEXP", 4315 "PerPkg": "1", 4316 "UMask": "0x4", 4317 "Unit": "iMC" 4318 }, 4319 { 4320 "BriefDescription": "Read Requests - Slot 0", 4321 "Counter": "0,1,2,3", 4322 "EventCode": "0xEB", 4323 "EventName": "UNC_M_PMM_CMD2.REQS_SLOT0", 4324 "PerPkg": "1", 4325 "UMask": "0x8", 4326 "Unit": "iMC" 4327 }, 4328 { 4329 "BriefDescription": "Read Requests - Slot 1", 4330 "Counter": "0,1,2,3", 4331 "EventCode": "0xEB", 4332 "EventName": "UNC_M_PMM_CMD2.REQS_SLOT1", 4333 "PerPkg": "1", 4334 "UMask": "0x10", 4335 "Unit": "iMC" 4336 }, 4337 { 4338 "BriefDescription": "PMM ECC Errors", 4339 "Counter": "0,1,2,3", 4340 "EventCode": "0xEB", 4341 "EventName": "UNC_M_PMM_CMD2.PMM_ECC_ERROR", 4342 "PerPkg": "1", 4343 "UMask": "0x20", 4344 "Unit": "iMC" 4345 }, 4346 { 4347 "BriefDescription": "PMM ERID detectable parity error", 4348 "Counter": "0,1,2,3", 4349 "EventCode": "0xEB", 4350 "EventName": "UNC_M_PMM_CMD2.PMM_ERID_ERROR", 4351 "PerPkg": "1", 4352 "UMask": "0x40", 4353 "Unit": "iMC" 4354 }, 4355 { 4356 "BriefDescription": "PMM Major Mode; Cycles PMM is in Read Major Mode", 4357 "Counter": "0,1,2,3", 4358 "EventCode": "0xEC", 4359 "EventName": "UNC_M_PMM_MAJMODE1.RD_CYC", 4360 "PerPkg": "1", 4361 "UMask": "0x1", 4362 "Unit": "iMC" 4363 }, 4364 { 4365 "BriefDescription": "PMM Major Mode; Cycles PMM is in Partial Write Major Mode", 4366 "Counter": "0,1,2,3", 4367 "EventCode": "0xEC", 4368 "EventName": "UNC_M_PMM_MAJMODE1.PARTIAL_WR_CYC", 4369 "PerPkg": "1", 4370 "UMask": "0x4", 4371 "Unit": "iMC" 4372 }, 4373 { 4374 "BriefDescription": "PMM Major Mode", 4375 "Counter": "0,1,2,3", 4376 "EventCode": "0xEC", 4377 "EventName": "UNC_M_PMM_MAJMODE1.PARTIAL_WR_ENTER", 4378 "PerPkg": "1", 4379 "UMask": "0x20", 4380 "Unit": "iMC" 4381 }, 4382 { 4383 "BriefDescription": "PMM Major Mode", 4384 "Counter": "0,1,2,3", 4385 "EventCode": "0xEC", 4386 "EventName": "UNC_M_PMM_MAJMODE1.PARTIAL_WR_EXIT", 4387 "PerPkg": "1", 4388 "UMask": "0x40", 4389 "Unit": "iMC" 4390 }, 4391 { 4392 "BriefDescription": "UNC_M_MAJMODE2.DRAM_CYC", 4393 "Counter": "0,1,2,3", 4394 "EventCode": "0xED", 4395 "EventName": "UNC_M_MAJMODE2.DRAM_CYC", 4396 "PerPkg": "1", 4397 "UMask": "0x2", 4398 "Unit": "iMC" 4399 }, 4400 { 4401 "BriefDescription": "UNC_M_MAJMODE2.DRAM_ENTER", 4402 "Counter": "0,1,2,3", 4403 "EventCode": "0xED", 4404 "EventName": "UNC_M_MAJMODE2.DRAM_ENTER", 4405 "PerPkg": "1", 4406 "UMask": "0x8", 4407 "Unit": "iMC" 4408 }, 4409 { 4410 "BriefDescription": "UNC_M_MAJMODE2.PMM_ENTER", 4411 "Counter": "0,1,2,3", 4412 "EventCode": "0xED", 4413 "EventName": "UNC_M_MAJMODE2.PMM_ENTER", 4414 "PerPkg": "1", 4415 "UMask": "0x4", 4416 "Unit": "iMC" 4417 }, 4418 { 4419 "BriefDescription": "PMM Write Queue Cycles Full", 4420 "Counter": "0,1,2,3", 4421 "EventCode": "0xE6", 4422 "EventName": "UNC_M_PMM_WPQ_CYCLES_FULL", 4423 "PerPkg": "1", 4424 "Unit": "iMC" 4425 }, 4426 { 4427 "BriefDescription": "PMM Write Queue Cycles Not Empty", 4428 "Counter": "0,1,2,3", 4429 "EventCode": "0xE5", 4430 "EventName": "UNC_M_PMM_WPQ_CYCLES_NE", 4431 "PerPkg": "1", 4432 "Unit": "iMC" 4433 }, 4434 { 4435 "BriefDescription": "PMM Occupancy", 4436 "Counter": "0,1,2,3", 4437 "EventCode": "0xE4", 4438 "EventName": "UNC_M_PMM_WPQ_OCCUPANCY.CAS", 4439 "PerPkg": "1", 4440 "UMask": "0x2", 4441 "Unit": "iMC" 4442 }, 4443 { 4444 "BriefDescription": "PMM Occupancy", 4445 "Counter": "0,1,2,3", 4446 "EventCode": "0xE4", 4447 "EventName": "UNC_M_PMM_WPQ_OCCUPANCY.PWR", 4448 "PerPkg": "1", 4449 "UMask": "0x4", 4450 "Unit": "iMC" 4451 }, 4452 { 4453 "BriefDescription": "UNC_M_PMM_WPQ_PCOMMIT", 4454 "Counter": "0,1,2,3", 4455 "EventCode": "0xE8", 4456 "EventName": "UNC_M_PMM_WPQ_PCOMMIT", 4457 "PerPkg": "1", 4458 "Unit": "iMC" 4459 }, 4460 { 4461 "BriefDescription": "UNC_M_PMM_WPQ_PCOMMIT_CYC", 4462 "Counter": "0,1,2,3", 4463 "EventCode": "0xE9", 4464 "EventName": "UNC_M_PMM_WPQ_PCOMMIT_CYC", 4465 "PerPkg": "1", 4466 "Unit": "iMC" 4467 }, 4468 { 4469 "BriefDescription": "PMM Major Mode; Cycles PMM is in Write Major Mode", 4470 "Counter": "0,1,2,3", 4471 "EventCode": "0xEC", 4472 "EventName": "UNC_M_PMM_MAJMODE1.WR_CYC", 4473 "PerPkg": "1", 4474 "UMask": "0x2", 4475 "Unit": "iMC" 4476 }, 4477 { 4478 "BriefDescription": "UNC_M_MAJMODE2.PMM_CYC", 4479 "Counter": "0,1,2,3", 4480 "EventCode": "0xED", 4481 "EventName": "UNC_M_MAJMODE2.PMM_CYC", 4482 "PerPkg": "1", 4483 "UMask": "0x1", 4484 "Unit": "iMC" 4485 }, 4486 { 4487 "BriefDescription": "UNC_M_SB_TAGGED.PMM0_CMP", 4488 "Counter": "0,1,2,3", 4489 "EventCode": "0xDD", 4490 "EventName": "UNC_M_SB_TAGGED.PMM0_CMP", 4491 "PerPkg": "1", 4492 "UMask": "0x10", 4493 "Unit": "iMC" 4494 }, 4495 { 4496 "BriefDescription": "UNC_M_SB_TAGGED.PMM1_CMP", 4497 "Counter": "0,1,2,3", 4498 "EventCode": "0xDD", 4499 "EventName": "UNC_M_SB_TAGGED.PMM1_CMP", 4500 "PerPkg": "1", 4501 "UMask": "0x20", 4502 "Unit": "iMC" 4503 }, 4504 { 4505 "BriefDescription": "UNC_M_SB_TAGGED.PMM2_CMP", 4506 "Counter": "0,1,2,3", 4507 "EventCode": "0xDD", 4508 "EventName": "UNC_M_SB_TAGGED.PMM2_CMP", 4509 "PerPkg": "1", 4510 "UMask": "0x40", 4511 "Unit": "iMC" 4512 }, 4513 { 4514 "BriefDescription": "Scoreboard Inserts; Persistent Mem writes", 4515 "Counter": "0,1,2,3", 4516 "EventCode": "0xD6", 4517 "EventName": "UNC_M_SB_INSERTS.PMM_WRS", 4518 "PerPkg": "1", 4519 "UMask": "0x08", 4520 "Unit": "iMC" 4521 }, 4522 { 4523 "BriefDescription": "Scoreboard Occupancy; Persistent Mem writes", 4524 "Counter": "0,1,2,3", 4525 "EventCode": "0xD5", 4526 "EventName": "UNC_M_SB_OCCUPANCY.PMM_WRS", 4527 "PerPkg": "1", 4528 "UMask": "0x08", 4529 "Unit": "iMC" 4530 }, 4531 { 4532 "BriefDescription": "Scoreboard Occupancy; Persistent Mem reads", 4533 "Counter": "0,1,2,3", 4534 "EventCode": "0xD5", 4535 "EventName": "UNC_M_SB_OCCUPANCY.PMM_RDS", 4536 "PerPkg": "1", 4537 "UMask": "0x04", 4538 "Unit": "iMC" 4539 }, 4540 { 4541 "BriefDescription": "Scoreboard Inserts; Persistent Mem reads", 4542 "Counter": "0,1,2,3", 4543 "EventCode": "0xD6", 4544 "EventName": "UNC_M_SB_INSERTS.PMM_RDS", 4545 "PerPkg": "1", 4546 "UMask": "0x04", 4547 "Unit": "iMC" 4548 } 4549] 4550