1ecd94f1bSKan Liang[
2ecd94f1bSKan Liang    {
37fcf1b89SHaiyan Song        "BriefDescription": "Cycles when divide unit is busy executing divide or square root operations. Accounts for integer and floating-point operations.",
4ecd94f1bSKan Liang        "Counter": "0,1,2,3",
57fcf1b89SHaiyan Song        "CounterHTOff": "0,1,2,3,4,5,6,7",
67fcf1b89SHaiyan Song        "CounterMask": "1",
77fcf1b89SHaiyan Song        "EventCode": "0x14",
87fcf1b89SHaiyan Song        "EventName": "ARITH.DIVIDER_ACTIVE",
97fcf1b89SHaiyan Song        "SampleAfterValue": "2000003",
107fcf1b89SHaiyan Song        "UMask": "0x1"
11ecd94f1bSKan Liang    },
12ecd94f1bSKan Liang    {
13e0ddfd8dSJin Yao        "BriefDescription": "All (macro) branch instructions retired.",
14ecd94f1bSKan Liang        "Counter": "0,1,2,3",
157fcf1b89SHaiyan Song        "CounterHTOff": "0,1,2,3,4,5,6,7",
16e0ddfd8dSJin Yao        "Errata": "SKL091",
17e0ddfd8dSJin Yao        "EventCode": "0xC4",
18e0ddfd8dSJin Yao        "EventName": "BR_INST_RETIRED.ALL_BRANCHES",
19e0ddfd8dSJin Yao        "PublicDescription": "Counts all (macro) branch instructions retired.",
20e0ddfd8dSJin Yao        "SampleAfterValue": "400009"
21ecd94f1bSKan Liang    },
22ecd94f1bSKan Liang    {
23e0ddfd8dSJin Yao        "BriefDescription": "All (macro) branch instructions retired.",
24ecd94f1bSKan Liang        "Counter": "0,1,2,3",
25e0ddfd8dSJin Yao        "CounterHTOff": "0,1,2,3",
26e0ddfd8dSJin Yao        "Errata": "SKL091",
27e0ddfd8dSJin Yao        "EventCode": "0xC4",
28e0ddfd8dSJin Yao        "EventName": "BR_INST_RETIRED.ALL_BRANCHES_PEBS",
29e0ddfd8dSJin Yao        "PEBS": "2",
30e0ddfd8dSJin Yao        "PublicDescription": "This is a precise version of BR_INST_RETIRED.ALL_BRANCHES that counts all (macro) branch instructions retired.",
31ecd94f1bSKan Liang        "SampleAfterValue": "400009",
32e0ddfd8dSJin Yao        "UMask": "0x4"
337fcf1b89SHaiyan Song    },
347fcf1b89SHaiyan Song    {
357fcf1b89SHaiyan Song        "BriefDescription": "Conditional branch instructions retired.",
367fcf1b89SHaiyan Song        "Counter": "0,1,2,3",
377fcf1b89SHaiyan Song        "CounterHTOff": "0,1,2,3,4,5,6,7",
387fcf1b89SHaiyan Song        "Errata": "SKL091",
397fcf1b89SHaiyan Song        "EventCode": "0xC4",
407fcf1b89SHaiyan Song        "EventName": "BR_INST_RETIRED.CONDITIONAL",
417fcf1b89SHaiyan Song        "PEBS": "1",
427fcf1b89SHaiyan Song        "PublicDescription": "This event counts conditional branch instructions retired.",
437fcf1b89SHaiyan Song        "SampleAfterValue": "400009",
447fcf1b89SHaiyan Song        "UMask": "0x1"
457fcf1b89SHaiyan Song    },
467fcf1b89SHaiyan Song    {
47e0ddfd8dSJin Yao        "BriefDescription": "Not taken branch instructions retired.",
487fcf1b89SHaiyan Song        "Counter": "0,1,2,3",
497fcf1b89SHaiyan Song        "CounterHTOff": "0,1,2,3,4,5,6,7",
50e0ddfd8dSJin Yao        "Errata": "SKL091",
51e0ddfd8dSJin Yao        "EventCode": "0xc4",
52e0ddfd8dSJin Yao        "EventName": "BR_INST_RETIRED.COND_NTAKEN",
53e0ddfd8dSJin Yao        "PublicDescription": "This event counts not taken branch instructions retired.",
54e0ddfd8dSJin Yao        "SampleAfterValue": "400009",
557fcf1b89SHaiyan Song        "UMask": "0x10"
567fcf1b89SHaiyan Song    },
577fcf1b89SHaiyan Song    {
58e0ddfd8dSJin Yao        "BriefDescription": "Far branch instructions retired.",
597fcf1b89SHaiyan Song        "Counter": "0,1,2,3",
607fcf1b89SHaiyan Song        "CounterHTOff": "0,1,2,3,4,5,6,7",
61e0ddfd8dSJin Yao        "Errata": "SKL091",
62e0ddfd8dSJin Yao        "EventCode": "0xC4",
63e0ddfd8dSJin Yao        "EventName": "BR_INST_RETIRED.FAR_BRANCH",
64e0ddfd8dSJin Yao        "PEBS": "1",
65e0ddfd8dSJin Yao        "PublicDescription": "This event counts far branch instructions retired.",
66e0ddfd8dSJin Yao        "SampleAfterValue": "100007",
67e0ddfd8dSJin Yao        "UMask": "0x40"
68e0ddfd8dSJin Yao    },
69e0ddfd8dSJin Yao    {
70e0ddfd8dSJin Yao        "BriefDescription": "Direct and indirect near call instructions retired.",
71e0ddfd8dSJin Yao        "Counter": "0,1,2,3",
72e0ddfd8dSJin Yao        "CounterHTOff": "0,1,2,3,4,5,6,7",
73e0ddfd8dSJin Yao        "Errata": "SKL091",
74e0ddfd8dSJin Yao        "EventCode": "0xC4",
75e0ddfd8dSJin Yao        "EventName": "BR_INST_RETIRED.NEAR_CALL",
76e0ddfd8dSJin Yao        "PEBS": "1",
77e0ddfd8dSJin Yao        "PublicDescription": "This event counts both direct and indirect near call instructions retired.",
78e0ddfd8dSJin Yao        "SampleAfterValue": "100007",
79e0ddfd8dSJin Yao        "UMask": "0x2"
80e0ddfd8dSJin Yao    },
81e0ddfd8dSJin Yao    {
82e0ddfd8dSJin Yao        "BriefDescription": "Return instructions retired.",
83e0ddfd8dSJin Yao        "Counter": "0,1,2,3",
84e0ddfd8dSJin Yao        "CounterHTOff": "0,1,2,3,4,5,6,7",
85e0ddfd8dSJin Yao        "Errata": "SKL091",
86e0ddfd8dSJin Yao        "EventCode": "0xC4",
87e0ddfd8dSJin Yao        "EventName": "BR_INST_RETIRED.NEAR_RETURN",
88e0ddfd8dSJin Yao        "PEBS": "1",
89e0ddfd8dSJin Yao        "PublicDescription": "This event counts return instructions retired.",
90e0ddfd8dSJin Yao        "SampleAfterValue": "100007",
91e0ddfd8dSJin Yao        "UMask": "0x8"
92e0ddfd8dSJin Yao    },
93e0ddfd8dSJin Yao    {
94e0ddfd8dSJin Yao        "BriefDescription": "Taken branch instructions retired.",
95e0ddfd8dSJin Yao        "Counter": "0,1,2,3",
96e0ddfd8dSJin Yao        "CounterHTOff": "0,1,2,3,4,5,6,7",
97e0ddfd8dSJin Yao        "Errata": "SKL091",
98e0ddfd8dSJin Yao        "EventCode": "0xC4",
99e0ddfd8dSJin Yao        "EventName": "BR_INST_RETIRED.NEAR_TAKEN",
100e0ddfd8dSJin Yao        "PEBS": "1",
101e0ddfd8dSJin Yao        "PublicDescription": "This event counts taken branch instructions retired.",
102e0ddfd8dSJin Yao        "SampleAfterValue": "400009",
103e0ddfd8dSJin Yao        "UMask": "0x20"
104e0ddfd8dSJin Yao    },
105e0ddfd8dSJin Yao    {
106e0ddfd8dSJin Yao        "BriefDescription": "Not taken branch instructions retired.",
107e0ddfd8dSJin Yao        "Counter": "0,1,2,3",
108e0ddfd8dSJin Yao        "CounterHTOff": "0,1,2,3,4,5,6,7",
109e0ddfd8dSJin Yao        "Errata": "SKL091",
110e0ddfd8dSJin Yao        "EventCode": "0xC4",
111e0ddfd8dSJin Yao        "EventName": "BR_INST_RETIRED.NOT_TAKEN",
112e0ddfd8dSJin Yao        "PublicDescription": "This event counts not taken branch instructions retired.",
113e0ddfd8dSJin Yao        "SampleAfterValue": "400009",
114e0ddfd8dSJin Yao        "UMask": "0x10"
115e0ddfd8dSJin Yao    },
116e0ddfd8dSJin Yao    {
117e0ddfd8dSJin Yao        "BriefDescription": "All mispredicted macro branch instructions retired.",
118e0ddfd8dSJin Yao        "Counter": "0,1,2,3",
119e0ddfd8dSJin Yao        "CounterHTOff": "0,1,2,3,4,5,6,7",
120e0ddfd8dSJin Yao        "EventCode": "0xC5",
121e0ddfd8dSJin Yao        "EventName": "BR_MISP_RETIRED.ALL_BRANCHES",
122e0ddfd8dSJin Yao        "PublicDescription": "Counts all the retired branch instructions that were mispredicted by the processor. A branch misprediction occurs when the processor incorrectly predicts the destination of the branch.  When the misprediction is discovered at execution, all the instructions executed in the wrong (speculative) path must be discarded, and the processor must start fetching from the correct path.",
123e0ddfd8dSJin Yao        "SampleAfterValue": "400009"
1247fcf1b89SHaiyan Song    },
1257fcf1b89SHaiyan Song    {
1267fcf1b89SHaiyan Song        "BriefDescription": "Mispredicted macro branch instructions retired.",
1277fcf1b89SHaiyan Song        "Counter": "0,1,2,3",
1287fcf1b89SHaiyan Song        "CounterHTOff": "0,1,2,3",
1297fcf1b89SHaiyan Song        "EventCode": "0xC5",
1307fcf1b89SHaiyan Song        "EventName": "BR_MISP_RETIRED.ALL_BRANCHES_PEBS",
1317fcf1b89SHaiyan Song        "PEBS": "2",
1327fcf1b89SHaiyan Song        "PublicDescription": "This is a precise version of BR_MISP_RETIRED.ALL_BRANCHES that counts all mispredicted macro branch instructions retired.",
1337fcf1b89SHaiyan Song        "SampleAfterValue": "400009",
1347fcf1b89SHaiyan Song        "UMask": "0x4"
1357fcf1b89SHaiyan Song    },
1367fcf1b89SHaiyan Song    {
137e0ddfd8dSJin Yao        "BriefDescription": "Mispredicted conditional branch instructions retired.",
1387fcf1b89SHaiyan Song        "Counter": "0,1,2,3",
1397fcf1b89SHaiyan Song        "CounterHTOff": "0,1,2,3,4,5,6,7",
140e0ddfd8dSJin Yao        "EventCode": "0xC5",
141e0ddfd8dSJin Yao        "EventName": "BR_MISP_RETIRED.CONDITIONAL",
142e0ddfd8dSJin Yao        "PEBS": "1",
143e0ddfd8dSJin Yao        "PublicDescription": "This event counts mispredicted conditional branch instructions retired.",
144e0ddfd8dSJin Yao        "SampleAfterValue": "400009",
1457fcf1b89SHaiyan Song        "UMask": "0x1"
1467fcf1b89SHaiyan Song    },
1477fcf1b89SHaiyan Song    {
148e0ddfd8dSJin Yao        "BriefDescription": "Mispredicted direct and indirect near call instructions retired.",
1497fcf1b89SHaiyan Song        "Counter": "0,1,2,3",
1507fcf1b89SHaiyan Song        "CounterHTOff": "0,1,2,3,4,5,6,7",
151e0ddfd8dSJin Yao        "EventCode": "0xC5",
152e0ddfd8dSJin Yao        "EventName": "BR_MISP_RETIRED.NEAR_CALL",
153e0ddfd8dSJin Yao        "PEBS": "1",
154e0ddfd8dSJin Yao        "PublicDescription": "Counts both taken and not taken retired mispredicted direct and indirect near calls, including both register and memory indirect.",
155e0ddfd8dSJin Yao        "SampleAfterValue": "400009",
156e0ddfd8dSJin Yao        "UMask": "0x2"
157e0ddfd8dSJin Yao    },
158e0ddfd8dSJin Yao    {
159e0ddfd8dSJin Yao        "BriefDescription": "Number of near branch instructions retired that were mispredicted and taken.",
160e0ddfd8dSJin Yao        "Counter": "0,1,2,3",
161e0ddfd8dSJin Yao        "CounterHTOff": "0,1,2,3,4,5,6,7",
162e0ddfd8dSJin Yao        "EventCode": "0xC5",
163e0ddfd8dSJin Yao        "EventName": "BR_MISP_RETIRED.NEAR_TAKEN",
164e0ddfd8dSJin Yao        "PEBS": "1",
165e0ddfd8dSJin Yao        "SampleAfterValue": "400009",
166e0ddfd8dSJin Yao        "UMask": "0x20"
1677fcf1b89SHaiyan Song    },
1687fcf1b89SHaiyan Song    {
1697fcf1b89SHaiyan Song        "BriefDescription": "Core crystal clock cycles when this thread is unhalted and the other thread is halted.",
1707fcf1b89SHaiyan Song        "Counter": "0,1,2,3",
1717fcf1b89SHaiyan Song        "CounterHTOff": "0,1,2,3,4,5,6,7",
1727fcf1b89SHaiyan Song        "EventCode": "0x3C",
1737fcf1b89SHaiyan Song        "EventName": "CPU_CLK_THREAD_UNHALTED.ONE_THREAD_ACTIVE",
1747fcf1b89SHaiyan Song        "SampleAfterValue": "25003",
1757fcf1b89SHaiyan Song        "UMask": "0x2"
1767fcf1b89SHaiyan Song    },
1777fcf1b89SHaiyan Song    {
178e0ddfd8dSJin Yao        "BriefDescription": "Core crystal clock cycles when the thread is unhalted.",
1797fcf1b89SHaiyan Song        "Counter": "0,1,2,3",
1807fcf1b89SHaiyan Song        "CounterHTOff": "0,1,2,3,4,5,6,7",
181e0ddfd8dSJin Yao        "EventCode": "0x3C",
182e0ddfd8dSJin Yao        "EventName": "CPU_CLK_THREAD_UNHALTED.REF_XCLK",
183e0ddfd8dSJin Yao        "SampleAfterValue": "25003",
184e0ddfd8dSJin Yao        "UMask": "0x1"
185e0ddfd8dSJin Yao    },
186e0ddfd8dSJin Yao    {
187e0ddfd8dSJin Yao        "AnyThread": "1",
188e0ddfd8dSJin Yao        "BriefDescription": "Core crystal clock cycles when at least one thread on the physical core is unhalted.",
189e0ddfd8dSJin Yao        "Counter": "0,1,2,3",
190e0ddfd8dSJin Yao        "CounterHTOff": "0,1,2,3,4,5,6,7",
191e0ddfd8dSJin Yao        "EventCode": "0x3C",
192e0ddfd8dSJin Yao        "EventName": "CPU_CLK_THREAD_UNHALTED.REF_XCLK_ANY",
193e0ddfd8dSJin Yao        "SampleAfterValue": "25003",
194e0ddfd8dSJin Yao        "UMask": "0x1"
195e0ddfd8dSJin Yao    },
196e0ddfd8dSJin Yao    {
197e0ddfd8dSJin Yao        "BriefDescription": "Core crystal clock cycles when this thread is unhalted and the other thread is halted.",
198e0ddfd8dSJin Yao        "Counter": "0,1,2,3",
199e0ddfd8dSJin Yao        "CounterHTOff": "0,1,2,3,4,5,6,7",
200e0ddfd8dSJin Yao        "EventCode": "0x3C",
201e0ddfd8dSJin Yao        "EventName": "CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE",
202e0ddfd8dSJin Yao        "SampleAfterValue": "25003",
203e0ddfd8dSJin Yao        "UMask": "0x2"
204e0ddfd8dSJin Yao    },
205e0ddfd8dSJin Yao    {
206e0ddfd8dSJin Yao        "BriefDescription": "Reference cycles when the core is not in halt state.",
207e0ddfd8dSJin Yao        "Counter": "Fixed counter 2",
208e0ddfd8dSJin Yao        "CounterHTOff": "Fixed counter 2",
209e0ddfd8dSJin Yao        "EventName": "CPU_CLK_UNHALTED.REF_TSC",
210e0ddfd8dSJin Yao        "PublicDescription": "Counts the number of reference cycles when the core is not in a halt state. The core enters the halt state when it is running the HLT instruction or the MWAIT instruction. This event is not affected by core frequency changes (for example, P states, TM2 transitions) but has the same incrementing frequency as the time stamp counter. This event can approximate elapsed time while the core was not in a halt state. This event has a constant ratio with the CPU_CLK_UNHALTED.REF_XCLK event. It is counted on a dedicated fixed counter, leaving the four (eight when Hyperthreading is disabled) programmable counters available for other events. Note: On all current platforms this event stops counting during 'throttling (TM)' states duty off periods the processor is 'halted'.  The counter update is done at a lower clock rate then the core clock the overflow status bit for this counter may appear 'sticky'.  After the counter has overflowed and software clears the overflow status bit and resets the counter to less than MAX. The reset value to the counter is not clocked immediately so the overflow status bit will flip 'high (1)' and generate another PMI (if enabled) after which the reset value gets clocked into the counter. Therefore, software will get the interrupt, read the overflow status bit '1 for bit 34 while the counter value is less than MAX. Software should ignore this case.",
211e0ddfd8dSJin Yao        "SampleAfterValue": "2000003",
212e0ddfd8dSJin Yao        "UMask": "0x3"
213e0ddfd8dSJin Yao    },
214e0ddfd8dSJin Yao    {
215e0ddfd8dSJin Yao        "BriefDescription": "Core crystal clock cycles when the thread is unhalted.",
216e0ddfd8dSJin Yao        "Counter": "0,1,2,3",
217e0ddfd8dSJin Yao        "CounterHTOff": "0,1,2,3,4,5,6,7",
218e0ddfd8dSJin Yao        "EventCode": "0x3C",
219e0ddfd8dSJin Yao        "EventName": "CPU_CLK_UNHALTED.REF_XCLK",
220e0ddfd8dSJin Yao        "SampleAfterValue": "25003",
221e0ddfd8dSJin Yao        "UMask": "0x1"
222e0ddfd8dSJin Yao    },
223e0ddfd8dSJin Yao    {
224e0ddfd8dSJin Yao        "AnyThread": "1",
225e0ddfd8dSJin Yao        "BriefDescription": "Core crystal clock cycles when at least one thread on the physical core is unhalted.",
226e0ddfd8dSJin Yao        "Counter": "0,1,2,3",
227e0ddfd8dSJin Yao        "CounterHTOff": "0,1,2,3,4,5,6,7",
228e0ddfd8dSJin Yao        "EventCode": "0x3C",
229e0ddfd8dSJin Yao        "EventName": "CPU_CLK_UNHALTED.REF_XCLK_ANY",
230e0ddfd8dSJin Yao        "SampleAfterValue": "25003",
231e0ddfd8dSJin Yao        "UMask": "0x1"
232e0ddfd8dSJin Yao    },
233e0ddfd8dSJin Yao    {
234e0ddfd8dSJin Yao        "BriefDescription": "Counts when there is a transition from ring 1, 2 or 3 to ring 0.",
235e0ddfd8dSJin Yao        "Counter": "0,1,2,3",
236e0ddfd8dSJin Yao        "CounterHTOff": "0,1,2,3,4,5,6,7",
237e0ddfd8dSJin Yao        "CounterMask": "1",
238e0ddfd8dSJin Yao        "EdgeDetect": "1",
239e0ddfd8dSJin Yao        "EventCode": "0x3C",
240e0ddfd8dSJin Yao        "EventName": "CPU_CLK_UNHALTED.RING0_TRANS",
241e0ddfd8dSJin Yao        "PublicDescription": "Counts when the Current Privilege Level (CPL) transitions from ring 1, 2 or 3 to ring 0 (Kernel).",
242e0ddfd8dSJin Yao        "SampleAfterValue": "100007"
243e0ddfd8dSJin Yao    },
244e0ddfd8dSJin Yao    {
245e0ddfd8dSJin Yao        "BriefDescription": "Core cycles when the thread is not in halt state",
246e0ddfd8dSJin Yao        "Counter": "Fixed counter 1",
247e0ddfd8dSJin Yao        "CounterHTOff": "Fixed counter 1",
248e0ddfd8dSJin Yao        "EventName": "CPU_CLK_UNHALTED.THREAD",
249e0ddfd8dSJin Yao        "PublicDescription": "Counts the number of core cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. This event is a component in many key event ratios. The core frequency may change from time to time due to transitions associated with Enhanced Intel SpeedStep Technology or TM2. For this reason this event may have a changing ratio with regards to time. When the core frequency is constant, this event can approximate elapsed time while the core was not in the halt state. It is counted on a dedicated fixed counter, leaving the four (eight when Hyperthreading is disabled) programmable counters available for other events.",
250e0ddfd8dSJin Yao        "SampleAfterValue": "2000003",
251e0ddfd8dSJin Yao        "UMask": "0x2"
252e0ddfd8dSJin Yao    },
253e0ddfd8dSJin Yao    {
254e0ddfd8dSJin Yao        "AnyThread": "1",
255e0ddfd8dSJin Yao        "BriefDescription": "Core cycles when at least one thread on the physical core is not in halt state.",
256e0ddfd8dSJin Yao        "Counter": "Fixed counter 1",
257e0ddfd8dSJin Yao        "CounterHTOff": "Fixed counter 1",
258e0ddfd8dSJin Yao        "EventName": "CPU_CLK_UNHALTED.THREAD_ANY",
259e0ddfd8dSJin Yao        "SampleAfterValue": "2000003",
260e0ddfd8dSJin Yao        "UMask": "0x2"
261e0ddfd8dSJin Yao    },
262e0ddfd8dSJin Yao    {
263e0ddfd8dSJin Yao        "BriefDescription": "Thread cycles when thread is not in halt state",
264e0ddfd8dSJin Yao        "Counter": "0,1,2,3",
265e0ddfd8dSJin Yao        "CounterHTOff": "0,1,2,3,4,5,6,7",
266e0ddfd8dSJin Yao        "EventCode": "0x3C",
267e0ddfd8dSJin Yao        "EventName": "CPU_CLK_UNHALTED.THREAD_P",
268e0ddfd8dSJin Yao        "PublicDescription": "This is an architectural event that counts the number of thread cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. The core frequency may change from time to time due to power or thermal throttling. For this reason, this event may have a changing ratio with regards to wall clock time.",
269e0ddfd8dSJin Yao        "SampleAfterValue": "2000003"
270e0ddfd8dSJin Yao    },
271e0ddfd8dSJin Yao    {
272e0ddfd8dSJin Yao        "AnyThread": "1",
273e0ddfd8dSJin Yao        "BriefDescription": "Core cycles when at least one thread on the physical core is not in halt state.",
274e0ddfd8dSJin Yao        "Counter": "0,1,2,3",
275e0ddfd8dSJin Yao        "CounterHTOff": "0,1,2,3,4,5,6,7",
276e0ddfd8dSJin Yao        "EventCode": "0x3C",
277e0ddfd8dSJin Yao        "EventName": "CPU_CLK_UNHALTED.THREAD_P_ANY",
278e0ddfd8dSJin Yao        "SampleAfterValue": "2000003"
279e0ddfd8dSJin Yao    },
280e0ddfd8dSJin Yao    {
281e0ddfd8dSJin Yao        "BriefDescription": "Cycles while L1 cache miss demand load is outstanding.",
282e0ddfd8dSJin Yao        "Counter": "0,1,2,3",
283e0ddfd8dSJin Yao        "CounterHTOff": "0,1,2,3,4,5,6,7",
284e0ddfd8dSJin Yao        "CounterMask": "8",
285e0ddfd8dSJin Yao        "EventCode": "0xA3",
286e0ddfd8dSJin Yao        "EventName": "CYCLE_ACTIVITY.CYCLES_L1D_MISS",
287e0ddfd8dSJin Yao        "SampleAfterValue": "2000003",
288e0ddfd8dSJin Yao        "UMask": "0x8"
289e0ddfd8dSJin Yao    },
290e0ddfd8dSJin Yao    {
291e0ddfd8dSJin Yao        "BriefDescription": "Cycles while L2 cache miss demand load is outstanding.",
292e0ddfd8dSJin Yao        "Counter": "0,1,2,3",
293e0ddfd8dSJin Yao        "CounterHTOff": "0,1,2,3,4,5,6,7",
294e0ddfd8dSJin Yao        "CounterMask": "1",
295e0ddfd8dSJin Yao        "EventCode": "0xA3",
296e0ddfd8dSJin Yao        "EventName": "CYCLE_ACTIVITY.CYCLES_L2_MISS",
297e0ddfd8dSJin Yao        "SampleAfterValue": "2000003",
298e0ddfd8dSJin Yao        "UMask": "0x1"
299e0ddfd8dSJin Yao    },
300e0ddfd8dSJin Yao    {
301e0ddfd8dSJin Yao        "BriefDescription": "Cycles while memory subsystem has an outstanding load.",
302e0ddfd8dSJin Yao        "Counter": "0,1,2,3",
303e0ddfd8dSJin Yao        "CounterHTOff": "0,1,2,3,4,5,6,7",
304e0ddfd8dSJin Yao        "CounterMask": "16",
305e0ddfd8dSJin Yao        "EventCode": "0xA3",
306e0ddfd8dSJin Yao        "EventName": "CYCLE_ACTIVITY.CYCLES_MEM_ANY",
307e0ddfd8dSJin Yao        "SampleAfterValue": "2000003",
308e0ddfd8dSJin Yao        "UMask": "0x10"
309e0ddfd8dSJin Yao    },
310e0ddfd8dSJin Yao    {
311e0ddfd8dSJin Yao        "BriefDescription": "Execution stalls while L1 cache miss demand load is outstanding.",
312e0ddfd8dSJin Yao        "Counter": "0,1,2,3",
313e0ddfd8dSJin Yao        "CounterHTOff": "0,1,2,3,4,5,6,7",
314e0ddfd8dSJin Yao        "CounterMask": "12",
315e0ddfd8dSJin Yao        "EventCode": "0xA3",
316e0ddfd8dSJin Yao        "EventName": "CYCLE_ACTIVITY.STALLS_L1D_MISS",
317e0ddfd8dSJin Yao        "SampleAfterValue": "2000003",
318e0ddfd8dSJin Yao        "UMask": "0xc"
319e0ddfd8dSJin Yao    },
320e0ddfd8dSJin Yao    {
321e0ddfd8dSJin Yao        "BriefDescription": "Execution stalls while L2 cache miss demand load is outstanding.",
322e0ddfd8dSJin Yao        "Counter": "0,1,2,3",
323e0ddfd8dSJin Yao        "CounterHTOff": "0,1,2,3,4,5,6,7",
324e0ddfd8dSJin Yao        "CounterMask": "5",
325e0ddfd8dSJin Yao        "EventCode": "0xA3",
326e0ddfd8dSJin Yao        "EventName": "CYCLE_ACTIVITY.STALLS_L2_MISS",
327e0ddfd8dSJin Yao        "SampleAfterValue": "2000003",
328e0ddfd8dSJin Yao        "UMask": "0x5"
329e0ddfd8dSJin Yao    },
330e0ddfd8dSJin Yao    {
331e0ddfd8dSJin Yao        "BriefDescription": "Execution stalls while memory subsystem has an outstanding load.",
332e0ddfd8dSJin Yao        "Counter": "0,1,2,3",
333e0ddfd8dSJin Yao        "CounterHTOff": "0,1,2,3",
334e0ddfd8dSJin Yao        "CounterMask": "20",
335e0ddfd8dSJin Yao        "EventCode": "0xA3",
336e0ddfd8dSJin Yao        "EventName": "CYCLE_ACTIVITY.STALLS_MEM_ANY",
337e0ddfd8dSJin Yao        "SampleAfterValue": "2000003",
338e0ddfd8dSJin Yao        "UMask": "0x14"
339e0ddfd8dSJin Yao    },
340e0ddfd8dSJin Yao    {
341e0ddfd8dSJin Yao        "BriefDescription": "Total execution stalls.",
342e0ddfd8dSJin Yao        "Counter": "0,1,2,3",
343e0ddfd8dSJin Yao        "CounterHTOff": "0,1,2,3,4,5,6,7",
344e0ddfd8dSJin Yao        "CounterMask": "4",
345e0ddfd8dSJin Yao        "EventCode": "0xA3",
346e0ddfd8dSJin Yao        "EventName": "CYCLE_ACTIVITY.STALLS_TOTAL",
347e0ddfd8dSJin Yao        "SampleAfterValue": "2000003",
348e0ddfd8dSJin Yao        "UMask": "0x4"
349e0ddfd8dSJin Yao    },
350e0ddfd8dSJin Yao    {
351e0ddfd8dSJin Yao        "BriefDescription": "Cycles total of 1 uop is executed on all ports and Reservation Station was not empty.",
352e0ddfd8dSJin Yao        "Counter": "0,1,2,3",
353e0ddfd8dSJin Yao        "CounterHTOff": "0,1,2,3,4,5,6,7",
354e0ddfd8dSJin Yao        "EventCode": "0xA6",
355e0ddfd8dSJin Yao        "EventName": "EXE_ACTIVITY.1_PORTS_UTIL",
356e0ddfd8dSJin Yao        "PublicDescription": "Counts cycles during which a total of 1 uop was executed on all ports and Reservation Station (RS) was not empty.",
357e0ddfd8dSJin Yao        "SampleAfterValue": "2000003",
358e0ddfd8dSJin Yao        "UMask": "0x2"
359e0ddfd8dSJin Yao    },
360e0ddfd8dSJin Yao    {
361e0ddfd8dSJin Yao        "BriefDescription": "Cycles total of 2 uops are executed on all ports and Reservation Station was not empty.",
362e0ddfd8dSJin Yao        "Counter": "0,1,2,3",
363e0ddfd8dSJin Yao        "CounterHTOff": "0,1,2,3,4,5,6,7",
364e0ddfd8dSJin Yao        "EventCode": "0xA6",
365e0ddfd8dSJin Yao        "EventName": "EXE_ACTIVITY.2_PORTS_UTIL",
366e0ddfd8dSJin Yao        "PublicDescription": "Counts cycles during which a total of 2 uops were executed on all ports and Reservation Station (RS) was not empty.",
367e0ddfd8dSJin Yao        "SampleAfterValue": "2000003",
368e0ddfd8dSJin Yao        "UMask": "0x4"
369e0ddfd8dSJin Yao    },
370e0ddfd8dSJin Yao    {
371e0ddfd8dSJin Yao        "BriefDescription": "Cycles total of 3 uops are executed on all ports and Reservation Station was not empty.",
372e0ddfd8dSJin Yao        "Counter": "0,1,2,3",
373e0ddfd8dSJin Yao        "CounterHTOff": "0,1,2,3,4,5,6,7",
374e0ddfd8dSJin Yao        "EventCode": "0xA6",
375e0ddfd8dSJin Yao        "EventName": "EXE_ACTIVITY.3_PORTS_UTIL",
376e0ddfd8dSJin Yao        "PublicDescription": "Cycles total of 3 uops are executed on all ports and Reservation Station (RS) was not empty.",
377e0ddfd8dSJin Yao        "SampleAfterValue": "2000003",
378e0ddfd8dSJin Yao        "UMask": "0x8"
379e0ddfd8dSJin Yao    },
380e0ddfd8dSJin Yao    {
381e0ddfd8dSJin Yao        "BriefDescription": "Cycles total of 4 uops are executed on all ports and Reservation Station was not empty.",
382e0ddfd8dSJin Yao        "Counter": "0,1,2,3",
383e0ddfd8dSJin Yao        "CounterHTOff": "0,1,2,3,4,5,6,7",
384e0ddfd8dSJin Yao        "EventCode": "0xA6",
385e0ddfd8dSJin Yao        "EventName": "EXE_ACTIVITY.4_PORTS_UTIL",
386e0ddfd8dSJin Yao        "PublicDescription": "Cycles total of 4 uops are executed on all ports and Reservation Station (RS) was not empty.",
387e0ddfd8dSJin Yao        "SampleAfterValue": "2000003",
388e0ddfd8dSJin Yao        "UMask": "0x10"
389e0ddfd8dSJin Yao    },
390e0ddfd8dSJin Yao    {
391e0ddfd8dSJin Yao        "BriefDescription": "Cycles where the Store Buffer was full and no outstanding load.",
392e0ddfd8dSJin Yao        "Counter": "0,1,2,3",
393e0ddfd8dSJin Yao        "CounterHTOff": "0,1,2,3,4,5,6,7",
394e0ddfd8dSJin Yao        "EventCode": "0xA6",
395e0ddfd8dSJin Yao        "EventName": "EXE_ACTIVITY.BOUND_ON_STORES",
396e0ddfd8dSJin Yao        "SampleAfterValue": "2000003",
397e0ddfd8dSJin Yao        "UMask": "0x40"
398e0ddfd8dSJin Yao    },
399e0ddfd8dSJin Yao    {
400e0ddfd8dSJin Yao        "BriefDescription": "Cycles where no uops were executed, the Reservation Station was not empty, the Store Buffer was full and there was no outstanding load.",
401e0ddfd8dSJin Yao        "Counter": "0,1,2,3",
402e0ddfd8dSJin Yao        "CounterHTOff": "0,1,2,3,4,5,6,7",
403e0ddfd8dSJin Yao        "EventCode": "0xA6",
404e0ddfd8dSJin Yao        "EventName": "EXE_ACTIVITY.EXE_BOUND_0_PORTS",
405e0ddfd8dSJin Yao        "PublicDescription": "Counts cycles during which no uops were executed on all ports and Reservation Station (RS) was not empty.",
406e0ddfd8dSJin Yao        "SampleAfterValue": "2000003",
407e0ddfd8dSJin Yao        "UMask": "0x1"
408e0ddfd8dSJin Yao    },
409e0ddfd8dSJin Yao    {
410e0ddfd8dSJin Yao        "BriefDescription": "Stalls caused by changing prefix length of the instruction.",
411e0ddfd8dSJin Yao        "Counter": "0,1,2,3",
412e0ddfd8dSJin Yao        "CounterHTOff": "0,1,2,3,4,5,6,7",
413e0ddfd8dSJin Yao        "EventCode": "0x87",
414e0ddfd8dSJin Yao        "EventName": "ILD_STALL.LCP",
415e0ddfd8dSJin Yao        "PublicDescription": "Counts cycles that the Instruction Length decoder (ILD) stalls occurred due to dynamically changing prefix length of the decoded instruction (by operand size prefix instruction 0x66, address size prefix instruction 0x67 or REX.W for Intel64). Count is proportional to the number of prefixes in a 16B-line. This may result in a three-cycle penalty for each LCP (Length changing prefix) in a 16-byte chunk.",
416e0ddfd8dSJin Yao        "SampleAfterValue": "2000003",
417e0ddfd8dSJin Yao        "UMask": "0x1"
418e0ddfd8dSJin Yao    },
419e0ddfd8dSJin Yao    {
420*1ce7fc6fSIan Rogers        "BriefDescription": "Instruction decoders utilized in a cycle",
421*1ce7fc6fSIan Rogers        "Counter": "0,1,2,3",
422*1ce7fc6fSIan Rogers        "CounterHTOff": "0,1,2,3,4,5,6,7",
423*1ce7fc6fSIan Rogers        "EventCode": "0x55",
424*1ce7fc6fSIan Rogers        "EventName": "INST_DECODED.DECODERS",
425*1ce7fc6fSIan Rogers        "PublicDescription": "Number of decoders utilized in a cycle when the MITE (legacy decode pipeline) fetches instructions.",
426*1ce7fc6fSIan Rogers        "SampleAfterValue": "2000003",
427*1ce7fc6fSIan Rogers        "UMask": "0x1"
428*1ce7fc6fSIan Rogers    },
429*1ce7fc6fSIan Rogers    {
430e0ddfd8dSJin Yao        "BriefDescription": "Instructions retired from execution.",
431e0ddfd8dSJin Yao        "Counter": "Fixed counter 0",
432e0ddfd8dSJin Yao        "CounterHTOff": "Fixed counter 0",
433e0ddfd8dSJin Yao        "EventName": "INST_RETIRED.ANY",
434e0ddfd8dSJin Yao        "PublicDescription": "Counts the number of instructions retired from execution. For instructions that consist of multiple micro-ops, Counts the retirement of the last micro-op of the instruction. Counting continues during hardware interrupts, traps, and inside interrupt handlers. Notes: INST_RETIRED.ANY is counted by a designated fixed counter, leaving the four (eight when Hyperthreading is disabled) programmable counters available for other events. INST_RETIRED.ANY_P is counted by a programmable counter and it is an architectural performance event. Counting: Faulting executions of GETSEC/VM entry/VM Exit/MWait will not count as retired instructions.",
435e0ddfd8dSJin Yao        "SampleAfterValue": "2000003",
436e0ddfd8dSJin Yao        "UMask": "0x1"
437e0ddfd8dSJin Yao    },
438e0ddfd8dSJin Yao    {
439e0ddfd8dSJin Yao        "BriefDescription": "Number of instructions retired. General Counter - architectural event",
440e0ddfd8dSJin Yao        "Counter": "0,1,2,3",
441e0ddfd8dSJin Yao        "CounterHTOff": "0,1,2,3,4,5,6,7",
442e0ddfd8dSJin Yao        "Errata": "SKL091, SKL044",
443e0ddfd8dSJin Yao        "EventCode": "0xC0",
444e0ddfd8dSJin Yao        "EventName": "INST_RETIRED.ANY_P",
445e0ddfd8dSJin Yao        "PublicDescription": "Counts the number of instructions (EOMs) retired. Counting covers macro-fused instructions individually (that is, increments by two).",
446e0ddfd8dSJin Yao        "SampleAfterValue": "2000003"
447e0ddfd8dSJin Yao    },
448e0ddfd8dSJin Yao    {
44949898fefSIan Rogers        "BriefDescription": "Number of all retired NOP instructions.",
45049898fefSIan Rogers        "Counter": "0,1,2,3",
45149898fefSIan Rogers        "CounterHTOff": "0,1,2,3,4,5,6,7",
45249898fefSIan Rogers        "Errata": "SKL091, SKL044",
45349898fefSIan Rogers        "EventCode": "0xC0",
45449898fefSIan Rogers        "EventName": "INST_RETIRED.NOP",
45549898fefSIan Rogers        "PEBS": "1",
45649898fefSIan Rogers        "SampleAfterValue": "2000003",
45749898fefSIan Rogers        "UMask": "0x2"
45849898fefSIan Rogers    },
45949898fefSIan Rogers    {
460e0ddfd8dSJin Yao        "BriefDescription": "Precise instruction retired event with HW to reduce effect of PEBS shadow in IP distribution",
461e0ddfd8dSJin Yao        "Counter": "1",
462e0ddfd8dSJin Yao        "CounterHTOff": "1",
463e0ddfd8dSJin Yao        "Errata": "SKL091, SKL044",
464e0ddfd8dSJin Yao        "EventCode": "0xC0",
465e0ddfd8dSJin Yao        "EventName": "INST_RETIRED.PREC_DIST",
466e0ddfd8dSJin Yao        "PEBS": "2",
467e0ddfd8dSJin Yao        "PublicDescription": "A version of INST_RETIRED that allows for a more unbiased distribution of samples across instructions retired. It utilizes the Precise Distribution of Instructions Retired (PDIR) feature to mitigate some bias in how retired instructions get sampled.",
468e0ddfd8dSJin Yao        "SampleAfterValue": "2000003",
469e0ddfd8dSJin Yao        "UMask": "0x1"
470e0ddfd8dSJin Yao    },
471e0ddfd8dSJin Yao    {
472e0ddfd8dSJin Yao        "BriefDescription": "Number of cycles using always true condition applied to  PEBS instructions retired event.",
473e0ddfd8dSJin Yao        "Counter": "0,2,3",
474e0ddfd8dSJin Yao        "CounterHTOff": "0,2,3",
475e0ddfd8dSJin Yao        "CounterMask": "10",
476e0ddfd8dSJin Yao        "Errata": "SKL091, SKL044",
477e0ddfd8dSJin Yao        "EventCode": "0xC0",
478e0ddfd8dSJin Yao        "EventName": "INST_RETIRED.TOTAL_CYCLES_PS",
479e0ddfd8dSJin Yao        "Invert": "1",
480e0ddfd8dSJin Yao        "PEBS": "2",
481e0ddfd8dSJin Yao        "PublicDescription": "Number of cycles using an always true condition applied to  PEBS instructions retired event. (inst_ret< 16)",
482e0ddfd8dSJin Yao        "SampleAfterValue": "2000003",
483e0ddfd8dSJin Yao        "UMask": "0x1"
484e0ddfd8dSJin Yao    },
485e0ddfd8dSJin Yao    {
486e0ddfd8dSJin Yao        "BriefDescription": "Cycles the issue-stage is waiting for front-end to fetch from resteered path following branch misprediction or machine clear events.",
487e0ddfd8dSJin Yao        "Counter": "0,1,2,3",
488e0ddfd8dSJin Yao        "CounterHTOff": "0,1,2,3,4,5,6,7",
489e0ddfd8dSJin Yao        "EventCode": "0x0D",
490e0ddfd8dSJin Yao        "EventName": "INT_MISC.CLEAR_RESTEER_CYCLES",
491e0ddfd8dSJin Yao        "SampleAfterValue": "2000003",
492e0ddfd8dSJin Yao        "UMask": "0x80"
493e0ddfd8dSJin Yao    },
494e0ddfd8dSJin Yao    {
495e0ddfd8dSJin Yao        "BriefDescription": "Core cycles the allocator was stalled due to recovery from earlier clear event for this thread (e.g. misprediction or memory nuke)",
496e0ddfd8dSJin Yao        "Counter": "0,1,2,3",
497e0ddfd8dSJin Yao        "CounterHTOff": "0,1,2,3,4,5,6,7",
498e0ddfd8dSJin Yao        "EventCode": "0x0D",
499e0ddfd8dSJin Yao        "EventName": "INT_MISC.RECOVERY_CYCLES",
500e0ddfd8dSJin Yao        "PublicDescription": "Core cycles the Resource allocator was stalled due to recovery from an earlier branch misprediction or machine clear event.",
501e0ddfd8dSJin Yao        "SampleAfterValue": "2000003",
502e0ddfd8dSJin Yao        "UMask": "0x1"
503e0ddfd8dSJin Yao    },
504e0ddfd8dSJin Yao    {
505e0ddfd8dSJin Yao        "AnyThread": "1",
506e0ddfd8dSJin Yao        "BriefDescription": "Core cycles the allocator was stalled due to recovery from earlier clear event for any thread running on the physical core (e.g. misprediction or memory nuke).",
507e0ddfd8dSJin Yao        "Counter": "0,1,2,3",
508e0ddfd8dSJin Yao        "CounterHTOff": "0,1,2,3,4,5,6,7",
509e0ddfd8dSJin Yao        "EventCode": "0x0D",
510e0ddfd8dSJin Yao        "EventName": "INT_MISC.RECOVERY_CYCLES_ANY",
511e0ddfd8dSJin Yao        "SampleAfterValue": "2000003",
512e0ddfd8dSJin Yao        "UMask": "0x1"
513e0ddfd8dSJin Yao    },
514e0ddfd8dSJin Yao    {
515e0ddfd8dSJin Yao        "BriefDescription": "The number of times that split load operations are temporarily blocked because all resources for handling the split accesses are in use",
516e0ddfd8dSJin Yao        "Counter": "0,1,2,3",
517e0ddfd8dSJin Yao        "CounterHTOff": "0,1,2,3,4,5,6,7",
518e0ddfd8dSJin Yao        "EventCode": "0x03",
519e0ddfd8dSJin Yao        "EventName": "LD_BLOCKS.NO_SR",
520e0ddfd8dSJin Yao        "PublicDescription": "The number of times that split load operations are temporarily blocked because all resources for handling the split accesses are in use.",
521e0ddfd8dSJin Yao        "SampleAfterValue": "100003",
522e0ddfd8dSJin Yao        "UMask": "0x8"
523e0ddfd8dSJin Yao    },
524e0ddfd8dSJin Yao    {
525e0ddfd8dSJin Yao        "BriefDescription": "Loads blocked due to overlapping with a preceding store that cannot be forwarded.",
526e0ddfd8dSJin Yao        "Counter": "0,1,2,3",
527e0ddfd8dSJin Yao        "CounterHTOff": "0,1,2,3,4,5,6,7",
528e0ddfd8dSJin Yao        "EventCode": "0x03",
529e0ddfd8dSJin Yao        "EventName": "LD_BLOCKS.STORE_FORWARD",
530e0ddfd8dSJin Yao        "PublicDescription": "Counts the number of times where store forwarding was prevented for a load operation. The most common case is a load blocked due to the address of memory access (partially) overlapping with a preceding uncompleted store. Note: See the table of not supported store forwards in the Optimization Guide.",
531e0ddfd8dSJin Yao        "SampleAfterValue": "100003",
532e0ddfd8dSJin Yao        "UMask": "0x2"
533e0ddfd8dSJin Yao    },
534e0ddfd8dSJin Yao    {
535e0ddfd8dSJin Yao        "BriefDescription": "False dependencies in MOB due to partial compare on address.",
536e0ddfd8dSJin Yao        "Counter": "0,1,2,3",
537e0ddfd8dSJin Yao        "CounterHTOff": "0,1,2,3,4,5,6,7",
538e0ddfd8dSJin Yao        "EventCode": "0x07",
539e0ddfd8dSJin Yao        "EventName": "LD_BLOCKS_PARTIAL.ADDRESS_ALIAS",
540e0ddfd8dSJin Yao        "PublicDescription": "Counts false dependencies in MOB when the partial comparison upon loose net check and dependency was resolved by the Enhanced Loose net mechanism. This may not result in high performance penalties. Loose net checks can fail when loads and stores are 4k aliased.",
541e0ddfd8dSJin Yao        "SampleAfterValue": "100003",
542e0ddfd8dSJin Yao        "UMask": "0x1"
543e0ddfd8dSJin Yao    },
544e0ddfd8dSJin Yao    {
545e0ddfd8dSJin Yao        "BriefDescription": "Demand load dispatches that hit L1D fill buffer (FB) allocated for software prefetch.",
546e0ddfd8dSJin Yao        "Counter": "0,1,2,3",
547e0ddfd8dSJin Yao        "CounterHTOff": "0,1,2,3,4,5,6,7",
548e0ddfd8dSJin Yao        "EventCode": "0x4C",
549e0ddfd8dSJin Yao        "EventName": "LOAD_HIT_PRE.SW_PF",
550e0ddfd8dSJin Yao        "PublicDescription": "Counts all not software-prefetch load dispatches that hit the fill buffer (FB) allocated for the software prefetch. It can also be incremented by some lock instructions. So it should only be used with profiling so that the locks can be excluded by ASM (Assembly File) inspection of the nearby instructions.",
551e0ddfd8dSJin Yao        "SampleAfterValue": "100003",
552e0ddfd8dSJin Yao        "UMask": "0x1"
553e0ddfd8dSJin Yao    },
554e0ddfd8dSJin Yao    {
555e0ddfd8dSJin Yao        "BriefDescription": "Cycles 4 Uops delivered by the LSD, but didn't come from the decoder.",
556e0ddfd8dSJin Yao        "Counter": "0,1,2,3",
557e0ddfd8dSJin Yao        "CounterHTOff": "0,1,2,3,4,5,6,7",
558e0ddfd8dSJin Yao        "CounterMask": "4",
559e0ddfd8dSJin Yao        "EventCode": "0xA8",
560e0ddfd8dSJin Yao        "EventName": "LSD.CYCLES_4_UOPS",
561e0ddfd8dSJin Yao        "PublicDescription": "Counts the cycles when 4 uops are delivered by the LSD (Loop-stream detector).",
562e0ddfd8dSJin Yao        "SampleAfterValue": "2000003",
563e0ddfd8dSJin Yao        "UMask": "0x1"
564e0ddfd8dSJin Yao    },
565e0ddfd8dSJin Yao    {
566e0ddfd8dSJin Yao        "BriefDescription": "Cycles Uops delivered by the LSD, but didn't come from the decoder.",
567e0ddfd8dSJin Yao        "Counter": "0,1,2,3",
568e0ddfd8dSJin Yao        "CounterHTOff": "0,1,2,3,4,5,6,7",
569e0ddfd8dSJin Yao        "CounterMask": "1",
570e0ddfd8dSJin Yao        "EventCode": "0xA8",
571e0ddfd8dSJin Yao        "EventName": "LSD.CYCLES_ACTIVE",
572e0ddfd8dSJin Yao        "PublicDescription": "Counts the cycles when at least one uop is delivered by the LSD (Loop-stream detector).",
573e0ddfd8dSJin Yao        "SampleAfterValue": "2000003",
574e0ddfd8dSJin Yao        "UMask": "0x1"
575e0ddfd8dSJin Yao    },
576e0ddfd8dSJin Yao    {
577e0ddfd8dSJin Yao        "BriefDescription": "Number of Uops delivered by the LSD.",
578e0ddfd8dSJin Yao        "Counter": "0,1,2,3",
579e0ddfd8dSJin Yao        "CounterHTOff": "0,1,2,3,4,5,6,7",
580e0ddfd8dSJin Yao        "EventCode": "0xA8",
581e0ddfd8dSJin Yao        "EventName": "LSD.UOPS",
582e0ddfd8dSJin Yao        "PublicDescription": "Number of uops delivered to the back-end by the LSD(Loop Stream Detector).",
583e0ddfd8dSJin Yao        "SampleAfterValue": "2000003",
584e0ddfd8dSJin Yao        "UMask": "0x1"
585e0ddfd8dSJin Yao    },
586e0ddfd8dSJin Yao    {
587e0ddfd8dSJin Yao        "BriefDescription": "Number of machine clears (nukes) of any type.",
588e0ddfd8dSJin Yao        "Counter": "0,1,2,3",
589e0ddfd8dSJin Yao        "CounterHTOff": "0,1,2,3,4,5,6,7",
590e0ddfd8dSJin Yao        "CounterMask": "1",
591e0ddfd8dSJin Yao        "EdgeDetect": "1",
592e0ddfd8dSJin Yao        "EventCode": "0xC3",
593e0ddfd8dSJin Yao        "EventName": "MACHINE_CLEARS.COUNT",
594e0ddfd8dSJin Yao        "SampleAfterValue": "100003",
595e0ddfd8dSJin Yao        "UMask": "0x1"
596e0ddfd8dSJin Yao    },
597e0ddfd8dSJin Yao    {
598e0ddfd8dSJin Yao        "BriefDescription": "Self-modifying code (SMC) detected.",
599e0ddfd8dSJin Yao        "Counter": "0,1,2,3",
600e0ddfd8dSJin Yao        "CounterHTOff": "0,1,2,3,4,5,6,7",
601e0ddfd8dSJin Yao        "EventCode": "0xC3",
602e0ddfd8dSJin Yao        "EventName": "MACHINE_CLEARS.SMC",
603e0ddfd8dSJin Yao        "PublicDescription": "Counts self-modifying code (SMC) detected, which causes a machine clear.",
604e0ddfd8dSJin Yao        "SampleAfterValue": "100003",
605e0ddfd8dSJin Yao        "UMask": "0x4"
606e0ddfd8dSJin Yao    },
607e0ddfd8dSJin Yao    {
608e0ddfd8dSJin Yao        "BriefDescription": "Number of times a microcode assist is invoked by HW other than FP-assist. Examples include AD (page Access Dirty) and AVX* related assists.",
609e0ddfd8dSJin Yao        "Counter": "0,1,2,3",
610e0ddfd8dSJin Yao        "CounterHTOff": "0,1,2,3,4,5,6,7",
611e0ddfd8dSJin Yao        "EventCode": "0xC1",
612e0ddfd8dSJin Yao        "EventName": "OTHER_ASSISTS.ANY",
613e0ddfd8dSJin Yao        "SampleAfterValue": "100003",
614e0ddfd8dSJin Yao        "UMask": "0x3f"
615e0ddfd8dSJin Yao    },
616e0ddfd8dSJin Yao    {
617e0ddfd8dSJin Yao        "BriefDescription": "Cycles where the pipeline is stalled due to serializing operations.",
618e0ddfd8dSJin Yao        "Counter": "0,1,2,3",
619e0ddfd8dSJin Yao        "CounterHTOff": "0,1,2,3,4,5,6,7",
620e0ddfd8dSJin Yao        "EventCode": "0x59",
621e0ddfd8dSJin Yao        "EventName": "PARTIAL_RAT_STALLS.SCOREBOARD",
622e0ddfd8dSJin Yao        "PublicDescription": "This event counts cycles during which the microcode scoreboard stalls happen.",
623e0ddfd8dSJin Yao        "SampleAfterValue": "2000003",
624e0ddfd8dSJin Yao        "UMask": "0x1"
625e0ddfd8dSJin Yao    },
626e0ddfd8dSJin Yao    {
627e0ddfd8dSJin Yao        "BriefDescription": "Resource-related stall cycles",
628e0ddfd8dSJin Yao        "Counter": "0,1,2,3",
629e0ddfd8dSJin Yao        "CounterHTOff": "0,1,2,3,4,5,6,7",
630e0ddfd8dSJin Yao        "EventCode": "0xa2",
631e0ddfd8dSJin Yao        "EventName": "RESOURCE_STALLS.ANY",
632e0ddfd8dSJin Yao        "PublicDescription": "Counts resource-related stall cycles.",
633e0ddfd8dSJin Yao        "SampleAfterValue": "2000003",
634e0ddfd8dSJin Yao        "UMask": "0x1"
635e0ddfd8dSJin Yao    },
636e0ddfd8dSJin Yao    {
637e0ddfd8dSJin Yao        "BriefDescription": "Cycles stalled due to no store buffers available. (not including draining form sync).",
638e0ddfd8dSJin Yao        "Counter": "0,1,2,3",
639e0ddfd8dSJin Yao        "CounterHTOff": "0,1,2,3,4,5,6,7",
640e0ddfd8dSJin Yao        "EventCode": "0xA2",
641e0ddfd8dSJin Yao        "EventName": "RESOURCE_STALLS.SB",
642e0ddfd8dSJin Yao        "PublicDescription": "Counts allocation stall cycles caused by the store buffer (SB) being full. This counts cycles that the pipeline back-end blocked uop delivery from the front-end.",
643e0ddfd8dSJin Yao        "SampleAfterValue": "2000003",
644e0ddfd8dSJin Yao        "UMask": "0x8"
645e0ddfd8dSJin Yao    },
646e0ddfd8dSJin Yao    {
647e0ddfd8dSJin Yao        "BriefDescription": "Increments whenever there is an update to the LBR array.",
648e0ddfd8dSJin Yao        "Counter": "0,1,2,3",
649e0ddfd8dSJin Yao        "CounterHTOff": "0,1,2,3,4,5,6,7",
650e0ddfd8dSJin Yao        "EventCode": "0xCC",
651e0ddfd8dSJin Yao        "EventName": "ROB_MISC_EVENTS.LBR_INSERTS",
652e0ddfd8dSJin Yao        "PublicDescription": "Increments when an entry is added to the Last Branch Record (LBR) array (or removed from the array in case of RETURNs in call stack mode). The event requires LBR enable via IA32_DEBUGCTL MSR and branch type selection via MSR_LBR_SELECT.",
653e0ddfd8dSJin Yao        "SampleAfterValue": "2000003",
654e0ddfd8dSJin Yao        "UMask": "0x20"
655e0ddfd8dSJin Yao    },
656e0ddfd8dSJin Yao    {
657e0ddfd8dSJin Yao        "BriefDescription": "Number of retired PAUSE instructions (that do not end up with a VMExit to the VMM; TSX aborted Instructions may be counted). This event is not supported on first SKL and KBL products.",
658e0ddfd8dSJin Yao        "Counter": "0,1,2,3",
659e0ddfd8dSJin Yao        "CounterHTOff": "0,1,2,3,4,5,6,7",
660e0ddfd8dSJin Yao        "EventCode": "0xCC",
661e0ddfd8dSJin Yao        "EventName": "ROB_MISC_EVENTS.PAUSE_INST",
662e0ddfd8dSJin Yao        "SampleAfterValue": "2000003",
663e0ddfd8dSJin Yao        "UMask": "0x40"
664e0ddfd8dSJin Yao    },
665e0ddfd8dSJin Yao    {
666e0ddfd8dSJin Yao        "BriefDescription": "Cycles when Reservation Station (RS) is empty for the thread",
667e0ddfd8dSJin Yao        "Counter": "0,1,2,3",
668e0ddfd8dSJin Yao        "CounterHTOff": "0,1,2,3,4,5,6,7",
669e0ddfd8dSJin Yao        "EventCode": "0x5E",
670e0ddfd8dSJin Yao        "EventName": "RS_EVENTS.EMPTY_CYCLES",
671e0ddfd8dSJin Yao        "PublicDescription": "Counts cycles during which the reservation station (RS) is empty for the thread.; Note: In ST-mode, not active thread should drive 0. This is usually caused by severely costly branch mispredictions, or allocator/FE issues.",
672e0ddfd8dSJin Yao        "SampleAfterValue": "2000003",
673e0ddfd8dSJin Yao        "UMask": "0x1"
674e0ddfd8dSJin Yao    },
675e0ddfd8dSJin Yao    {
676e0ddfd8dSJin Yao        "BriefDescription": "Counts end of periods where the Reservation Station (RS) was empty. Could be useful to precisely locate Frontend Latency Bound issues.",
677e0ddfd8dSJin Yao        "Counter": "0,1,2,3",
678e0ddfd8dSJin Yao        "CounterHTOff": "0,1,2,3,4,5,6,7",
679e0ddfd8dSJin Yao        "CounterMask": "1",
680e0ddfd8dSJin Yao        "EdgeDetect": "1",
681e0ddfd8dSJin Yao        "EventCode": "0x5E",
682e0ddfd8dSJin Yao        "EventName": "RS_EVENTS.EMPTY_END",
683e0ddfd8dSJin Yao        "Invert": "1",
684e0ddfd8dSJin Yao        "PublicDescription": "Counts end of periods where the Reservation Station (RS) was empty. Could be useful to precisely locate front-end Latency Bound issues.",
685e0ddfd8dSJin Yao        "SampleAfterValue": "2000003",
686e0ddfd8dSJin Yao        "UMask": "0x1"
6877fcf1b89SHaiyan Song    },
6887fcf1b89SHaiyan Song    {
6897fcf1b89SHaiyan Song        "BriefDescription": "Cycles per thread when uops are executed in port 0",
6907fcf1b89SHaiyan Song        "Counter": "0,1,2,3",
6917fcf1b89SHaiyan Song        "CounterHTOff": "0,1,2,3,4,5,6,7",
6927fcf1b89SHaiyan Song        "EventCode": "0xA1",
6937fcf1b89SHaiyan Song        "EventName": "UOPS_DISPATCHED_PORT.PORT_0",
6947fcf1b89SHaiyan Song        "PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to port 0.",
6957fcf1b89SHaiyan Song        "SampleAfterValue": "2000003",
6967fcf1b89SHaiyan Song        "UMask": "0x1"
6977fcf1b89SHaiyan Song    },
6987fcf1b89SHaiyan Song    {
6997fcf1b89SHaiyan Song        "BriefDescription": "Cycles per thread when uops are executed in port 1",
7007fcf1b89SHaiyan Song        "Counter": "0,1,2,3",
7017fcf1b89SHaiyan Song        "CounterHTOff": "0,1,2,3,4,5,6,7",
7027fcf1b89SHaiyan Song        "EventCode": "0xA1",
7037fcf1b89SHaiyan Song        "EventName": "UOPS_DISPATCHED_PORT.PORT_1",
7047fcf1b89SHaiyan Song        "PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to port 1.",
7057fcf1b89SHaiyan Song        "SampleAfterValue": "2000003",
7067fcf1b89SHaiyan Song        "UMask": "0x2"
7077fcf1b89SHaiyan Song    },
7087fcf1b89SHaiyan Song    {
7097fcf1b89SHaiyan Song        "BriefDescription": "Cycles per thread when uops are executed in port 2",
7107fcf1b89SHaiyan Song        "Counter": "0,1,2,3",
7117fcf1b89SHaiyan Song        "CounterHTOff": "0,1,2,3,4,5,6,7",
7127fcf1b89SHaiyan Song        "EventCode": "0xA1",
7137fcf1b89SHaiyan Song        "EventName": "UOPS_DISPATCHED_PORT.PORT_2",
7147fcf1b89SHaiyan Song        "PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to port 2.",
7157fcf1b89SHaiyan Song        "SampleAfterValue": "2000003",
7167fcf1b89SHaiyan Song        "UMask": "0x4"
7177fcf1b89SHaiyan Song    },
7187fcf1b89SHaiyan Song    {
7197fcf1b89SHaiyan Song        "BriefDescription": "Cycles per thread when uops are executed in port 3",
7207fcf1b89SHaiyan Song        "Counter": "0,1,2,3",
7217fcf1b89SHaiyan Song        "CounterHTOff": "0,1,2,3,4,5,6,7",
7227fcf1b89SHaiyan Song        "EventCode": "0xA1",
7237fcf1b89SHaiyan Song        "EventName": "UOPS_DISPATCHED_PORT.PORT_3",
7247fcf1b89SHaiyan Song        "PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to port 3.",
7257fcf1b89SHaiyan Song        "SampleAfterValue": "2000003",
7267fcf1b89SHaiyan Song        "UMask": "0x8"
7277fcf1b89SHaiyan Song    },
7287fcf1b89SHaiyan Song    {
7297fcf1b89SHaiyan Song        "BriefDescription": "Cycles per thread when uops are executed in port 4",
7307fcf1b89SHaiyan Song        "Counter": "0,1,2,3",
7317fcf1b89SHaiyan Song        "CounterHTOff": "0,1,2,3,4,5,6,7",
7327fcf1b89SHaiyan Song        "EventCode": "0xA1",
7337fcf1b89SHaiyan Song        "EventName": "UOPS_DISPATCHED_PORT.PORT_4",
7347fcf1b89SHaiyan Song        "PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to port 4.",
7357fcf1b89SHaiyan Song        "SampleAfterValue": "2000003",
7367fcf1b89SHaiyan Song        "UMask": "0x10"
7377fcf1b89SHaiyan Song    },
7387fcf1b89SHaiyan Song    {
7397fcf1b89SHaiyan Song        "BriefDescription": "Cycles per thread when uops are executed in port 5",
7407fcf1b89SHaiyan Song        "Counter": "0,1,2,3",
7417fcf1b89SHaiyan Song        "CounterHTOff": "0,1,2,3,4,5,6,7",
7427fcf1b89SHaiyan Song        "EventCode": "0xA1",
7437fcf1b89SHaiyan Song        "EventName": "UOPS_DISPATCHED_PORT.PORT_5",
7447fcf1b89SHaiyan Song        "PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to port 5.",
7457fcf1b89SHaiyan Song        "SampleAfterValue": "2000003",
7467fcf1b89SHaiyan Song        "UMask": "0x20"
7477fcf1b89SHaiyan Song    },
7487fcf1b89SHaiyan Song    {
7497fcf1b89SHaiyan Song        "BriefDescription": "Cycles per thread when uops are executed in port 6",
7507fcf1b89SHaiyan Song        "Counter": "0,1,2,3",
7517fcf1b89SHaiyan Song        "CounterHTOff": "0,1,2,3,4,5,6,7",
7527fcf1b89SHaiyan Song        "EventCode": "0xA1",
7537fcf1b89SHaiyan Song        "EventName": "UOPS_DISPATCHED_PORT.PORT_6",
7547fcf1b89SHaiyan Song        "PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to port 6.",
7557fcf1b89SHaiyan Song        "SampleAfterValue": "2000003",
7567fcf1b89SHaiyan Song        "UMask": "0x40"
7577fcf1b89SHaiyan Song    },
7587fcf1b89SHaiyan Song    {
7597fcf1b89SHaiyan Song        "BriefDescription": "Cycles per thread when uops are executed in port 7",
7607fcf1b89SHaiyan Song        "Counter": "0,1,2,3",
7617fcf1b89SHaiyan Song        "CounterHTOff": "0,1,2,3,4,5,6,7",
7627fcf1b89SHaiyan Song        "EventCode": "0xA1",
7637fcf1b89SHaiyan Song        "EventName": "UOPS_DISPATCHED_PORT.PORT_7",
7647fcf1b89SHaiyan Song        "PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to port 7.",
7657fcf1b89SHaiyan Song        "SampleAfterValue": "2000003",
7667fcf1b89SHaiyan Song        "UMask": "0x80"
7677fcf1b89SHaiyan Song    },
7687fcf1b89SHaiyan Song    {
769e0ddfd8dSJin Yao        "BriefDescription": "Number of uops executed on the core.",
7707fcf1b89SHaiyan Song        "Counter": "0,1,2,3",
7717fcf1b89SHaiyan Song        "CounterHTOff": "0,1,2,3,4,5,6,7",
7727fcf1b89SHaiyan Song        "EventCode": "0xB1",
773e0ddfd8dSJin Yao        "EventName": "UOPS_EXECUTED.CORE",
774e0ddfd8dSJin Yao        "PublicDescription": "Number of uops executed from any thread.",
7757fcf1b89SHaiyan Song        "SampleAfterValue": "2000003",
7767fcf1b89SHaiyan Song        "UMask": "0x2"
7777fcf1b89SHaiyan Song    },
7787fcf1b89SHaiyan Song    {
779e0ddfd8dSJin Yao        "BriefDescription": "Cycles at least 1 micro-op is executed from any thread on physical core.",
7807fcf1b89SHaiyan Song        "Counter": "0,1,2,3",
7817fcf1b89SHaiyan Song        "CounterHTOff": "0,1,2,3,4,5,6,7",
782e0ddfd8dSJin Yao        "CounterMask": "1",
7837fcf1b89SHaiyan Song        "EventCode": "0xB1",
784e0ddfd8dSJin Yao        "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_1",
785e0ddfd8dSJin Yao        "SampleAfterValue": "2000003",
786e0ddfd8dSJin Yao        "UMask": "0x2"
787e0ddfd8dSJin Yao    },
788e0ddfd8dSJin Yao    {
789e0ddfd8dSJin Yao        "BriefDescription": "Cycles at least 2 micro-op is executed from any thread on physical core.",
790e0ddfd8dSJin Yao        "Counter": "0,1,2,3",
791e0ddfd8dSJin Yao        "CounterHTOff": "0,1,2,3,4,5,6,7",
792e0ddfd8dSJin Yao        "CounterMask": "2",
793e0ddfd8dSJin Yao        "EventCode": "0xB1",
794e0ddfd8dSJin Yao        "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_2",
795e0ddfd8dSJin Yao        "SampleAfterValue": "2000003",
796e0ddfd8dSJin Yao        "UMask": "0x2"
797e0ddfd8dSJin Yao    },
798e0ddfd8dSJin Yao    {
799e0ddfd8dSJin Yao        "BriefDescription": "Cycles at least 3 micro-op is executed from any thread on physical core.",
800e0ddfd8dSJin Yao        "Counter": "0,1,2,3",
801e0ddfd8dSJin Yao        "CounterHTOff": "0,1,2,3,4,5,6,7",
802e0ddfd8dSJin Yao        "CounterMask": "3",
803e0ddfd8dSJin Yao        "EventCode": "0xB1",
804e0ddfd8dSJin Yao        "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_3",
805e0ddfd8dSJin Yao        "SampleAfterValue": "2000003",
806e0ddfd8dSJin Yao        "UMask": "0x2"
807e0ddfd8dSJin Yao    },
808e0ddfd8dSJin Yao    {
809e0ddfd8dSJin Yao        "BriefDescription": "Cycles at least 4 micro-op is executed from any thread on physical core.",
810e0ddfd8dSJin Yao        "Counter": "0,1,2,3",
811e0ddfd8dSJin Yao        "CounterHTOff": "0,1,2,3,4,5,6,7",
812e0ddfd8dSJin Yao        "CounterMask": "4",
813e0ddfd8dSJin Yao        "EventCode": "0xB1",
814e0ddfd8dSJin Yao        "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_4",
815e0ddfd8dSJin Yao        "SampleAfterValue": "2000003",
816e0ddfd8dSJin Yao        "UMask": "0x2"
817e0ddfd8dSJin Yao    },
818e0ddfd8dSJin Yao    {
819e0ddfd8dSJin Yao        "BriefDescription": "Cycles with no micro-ops executed from any thread on physical core.",
820e0ddfd8dSJin Yao        "Counter": "0,1,2,3",
821e0ddfd8dSJin Yao        "CounterHTOff": "0,1,2,3,4,5,6,7",
822e0ddfd8dSJin Yao        "CounterMask": "1",
823e0ddfd8dSJin Yao        "EventCode": "0xB1",
824e0ddfd8dSJin Yao        "EventName": "UOPS_EXECUTED.CORE_CYCLES_NONE",
825e0ddfd8dSJin Yao        "Invert": "1",
826e0ddfd8dSJin Yao        "SampleAfterValue": "2000003",
827e0ddfd8dSJin Yao        "UMask": "0x2"
828e0ddfd8dSJin Yao    },
829e0ddfd8dSJin Yao    {
830e0ddfd8dSJin Yao        "BriefDescription": "Cycles where at least 1 uop was executed per-thread",
831e0ddfd8dSJin Yao        "Counter": "0,1,2,3",
832e0ddfd8dSJin Yao        "CounterHTOff": "0,1,2,3,4,5,6,7",
833e0ddfd8dSJin Yao        "CounterMask": "1",
834e0ddfd8dSJin Yao        "EventCode": "0xB1",
835e0ddfd8dSJin Yao        "EventName": "UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC",
836e0ddfd8dSJin Yao        "PublicDescription": "Cycles where at least 1 uop was executed per-thread.",
837e0ddfd8dSJin Yao        "SampleAfterValue": "2000003",
838e0ddfd8dSJin Yao        "UMask": "0x1"
839e0ddfd8dSJin Yao    },
840e0ddfd8dSJin Yao    {
841e0ddfd8dSJin Yao        "BriefDescription": "Cycles where at least 2 uops were executed per-thread",
842e0ddfd8dSJin Yao        "Counter": "0,1,2,3",
843e0ddfd8dSJin Yao        "CounterHTOff": "0,1,2,3,4,5,6,7",
844e0ddfd8dSJin Yao        "CounterMask": "2",
845e0ddfd8dSJin Yao        "EventCode": "0xB1",
846e0ddfd8dSJin Yao        "EventName": "UOPS_EXECUTED.CYCLES_GE_2_UOPS_EXEC",
847e0ddfd8dSJin Yao        "PublicDescription": "Cycles where at least 2 uops were executed per-thread.",
8487fcf1b89SHaiyan Song        "SampleAfterValue": "2000003",
8497fcf1b89SHaiyan Song        "UMask": "0x1"
8507fcf1b89SHaiyan Song    },
8517fcf1b89SHaiyan Song    {
8527fcf1b89SHaiyan Song        "BriefDescription": "Cycles where at least 3 uops were executed per-thread",
8537fcf1b89SHaiyan Song        "Counter": "0,1,2,3",
8547fcf1b89SHaiyan Song        "CounterHTOff": "0,1,2,3,4,5,6,7",
8557fcf1b89SHaiyan Song        "CounterMask": "3",
8567fcf1b89SHaiyan Song        "EventCode": "0xB1",
8577fcf1b89SHaiyan Song        "EventName": "UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC",
8587fcf1b89SHaiyan Song        "PublicDescription": "Cycles where at least 3 uops were executed per-thread.",
8597fcf1b89SHaiyan Song        "SampleAfterValue": "2000003",
8607fcf1b89SHaiyan Song        "UMask": "0x1"
8617fcf1b89SHaiyan Song    },
8627fcf1b89SHaiyan Song    {
8637fcf1b89SHaiyan Song        "BriefDescription": "Cycles where at least 4 uops were executed per-thread",
8647fcf1b89SHaiyan Song        "Counter": "0,1,2,3",
8657fcf1b89SHaiyan Song        "CounterHTOff": "0,1,2,3,4,5,6,7",
8667fcf1b89SHaiyan Song        "CounterMask": "4",
8677fcf1b89SHaiyan Song        "EventCode": "0xB1",
8687fcf1b89SHaiyan Song        "EventName": "UOPS_EXECUTED.CYCLES_GE_4_UOPS_EXEC",
8697fcf1b89SHaiyan Song        "PublicDescription": "Cycles where at least 4 uops were executed per-thread.",
8707fcf1b89SHaiyan Song        "SampleAfterValue": "2000003",
8717fcf1b89SHaiyan Song        "UMask": "0x1"
8727fcf1b89SHaiyan Song    },
8737fcf1b89SHaiyan Song    {
874e0ddfd8dSJin Yao        "BriefDescription": "Counts number of cycles no uops were dispatched to be executed on this thread.",
8757fcf1b89SHaiyan Song        "Counter": "0,1,2,3",
8767fcf1b89SHaiyan Song        "CounterHTOff": "0,1,2,3,4,5,6,7",
877e0ddfd8dSJin Yao        "CounterMask": "1",
878e0ddfd8dSJin Yao        "EventCode": "0xB1",
879e0ddfd8dSJin Yao        "EventName": "UOPS_EXECUTED.STALL_CYCLES",
880e0ddfd8dSJin Yao        "Invert": "1",
881e0ddfd8dSJin Yao        "PublicDescription": "Counts cycles during which no uops were dispatched from the Reservation Station (RS) per thread.",
8827fcf1b89SHaiyan Song        "SampleAfterValue": "2000003",
8837fcf1b89SHaiyan Song        "UMask": "0x1"
8847fcf1b89SHaiyan Song    },
8857fcf1b89SHaiyan Song    {
886e0ddfd8dSJin Yao        "BriefDescription": "Counts the number of uops to be executed per-thread each cycle.",
8877fcf1b89SHaiyan Song        "Counter": "0,1,2,3",
8887fcf1b89SHaiyan Song        "CounterHTOff": "0,1,2,3,4,5,6,7",
889e0ddfd8dSJin Yao        "EventCode": "0xB1",
890e0ddfd8dSJin Yao        "EventName": "UOPS_EXECUTED.THREAD",
891e0ddfd8dSJin Yao        "PublicDescription": "Number of uops to be executed per-thread each cycle.",
8927fcf1b89SHaiyan Song        "SampleAfterValue": "2000003",
893e0ddfd8dSJin Yao        "UMask": "0x1"
894e0ddfd8dSJin Yao    },
895e0ddfd8dSJin Yao    {
896e0ddfd8dSJin Yao        "BriefDescription": "Counts the number of x87 uops dispatched.",
897e0ddfd8dSJin Yao        "Counter": "0,1,2,3",
898e0ddfd8dSJin Yao        "CounterHTOff": "0,1,2,3,4,5,6,7",
899e0ddfd8dSJin Yao        "EventCode": "0xB1",
900e0ddfd8dSJin Yao        "EventName": "UOPS_EXECUTED.X87",
901e0ddfd8dSJin Yao        "PublicDescription": "Counts the number of x87 uops executed.",
902e0ddfd8dSJin Yao        "SampleAfterValue": "2000003",
903e0ddfd8dSJin Yao        "UMask": "0x10"
904e0ddfd8dSJin Yao    },
905e0ddfd8dSJin Yao    {
906e0ddfd8dSJin Yao        "BriefDescription": "Uops that Resource Allocation Table (RAT) issues to Reservation Station (RS)",
907e0ddfd8dSJin Yao        "Counter": "0,1,2,3",
908e0ddfd8dSJin Yao        "CounterHTOff": "0,1,2,3,4,5,6,7",
909e0ddfd8dSJin Yao        "EventCode": "0x0E",
910e0ddfd8dSJin Yao        "EventName": "UOPS_ISSUED.ANY",
911e0ddfd8dSJin Yao        "PublicDescription": "Counts the number of uops that the Resource Allocation Table (RAT) issues to the Reservation Station (RS).",
912e0ddfd8dSJin Yao        "SampleAfterValue": "2000003",
913e0ddfd8dSJin Yao        "UMask": "0x1"
914e0ddfd8dSJin Yao    },
915e0ddfd8dSJin Yao    {
916e0ddfd8dSJin Yao        "BriefDescription": "Number of slow LEA uops being allocated. A uop is generally considered SlowLea if it has 3 sources (e.g. 2 sources + immediate) regardless if as a result of LEA instruction or not.",
917e0ddfd8dSJin Yao        "Counter": "0,1,2,3",
918e0ddfd8dSJin Yao        "CounterHTOff": "0,1,2,3,4,5,6,7",
919e0ddfd8dSJin Yao        "EventCode": "0x0E",
920e0ddfd8dSJin Yao        "EventName": "UOPS_ISSUED.SLOW_LEA",
921e0ddfd8dSJin Yao        "SampleAfterValue": "2000003",
922e0ddfd8dSJin Yao        "UMask": "0x20"
923e0ddfd8dSJin Yao    },
924e0ddfd8dSJin Yao    {
925e0ddfd8dSJin Yao        "BriefDescription": "Cycles when Resource Allocation Table (RAT) does not issue Uops to Reservation Station (RS) for the thread",
926e0ddfd8dSJin Yao        "Counter": "0,1,2,3",
927e0ddfd8dSJin Yao        "CounterHTOff": "0,1,2,3,4,5,6,7",
928e0ddfd8dSJin Yao        "CounterMask": "1",
929e0ddfd8dSJin Yao        "EventCode": "0x0E",
930e0ddfd8dSJin Yao        "EventName": "UOPS_ISSUED.STALL_CYCLES",
931e0ddfd8dSJin Yao        "Invert": "1",
932e0ddfd8dSJin Yao        "PublicDescription": "Counts cycles during which the Resource Allocation Table (RAT) does not issue any Uops to the reservation station (RS) for the current thread.",
933e0ddfd8dSJin Yao        "SampleAfterValue": "2000003",
934e0ddfd8dSJin Yao        "UMask": "0x1"
9357fcf1b89SHaiyan Song    },
9367fcf1b89SHaiyan Song    {
9377fcf1b89SHaiyan Song        "BriefDescription": "Uops inserted at issue-stage in order to preserve upper bits of vector registers.",
9387fcf1b89SHaiyan Song        "Counter": "0,1,2,3",
9397fcf1b89SHaiyan Song        "CounterHTOff": "0,1,2,3,4,5,6,7",
9407fcf1b89SHaiyan Song        "EventCode": "0x0E",
9417fcf1b89SHaiyan Song        "EventName": "UOPS_ISSUED.VECTOR_WIDTH_MISMATCH",
9427fcf1b89SHaiyan Song        "PublicDescription": "Counts the number of Blend Uops issued by the Resource Allocation Table (RAT) to the reservation station (RS) in order to preserve upper bits of vector registers. Starting with the Skylake microarchitecture, these Blend uops are needed since every Intel SSE instruction executed in Dirty Upper State needs to preserve bits 128-255 of the destination register. For more information, refer to Mixing Intel AVX and Intel SSE Code section of the Optimization Guide.",
9437fcf1b89SHaiyan Song        "SampleAfterValue": "2000003",
9447fcf1b89SHaiyan Song        "UMask": "0x2"
9457fcf1b89SHaiyan Song    },
9467fcf1b89SHaiyan Song    {
947e0ddfd8dSJin Yao        "BriefDescription": "Number of macro-fused uops retired. (non precise)",
9487fcf1b89SHaiyan Song        "Counter": "0,1,2,3",
9497fcf1b89SHaiyan Song        "CounterHTOff": "0,1,2,3,4,5,6,7",
950e0ddfd8dSJin Yao        "EventCode": "0xc2",
951e0ddfd8dSJin Yao        "EventName": "UOPS_RETIRED.MACRO_FUSED",
952e0ddfd8dSJin Yao        "PublicDescription": "Counts the number of macro-fused uops retired. (non precise)",
953e0ddfd8dSJin Yao        "SampleAfterValue": "2000003",
954e0ddfd8dSJin Yao        "UMask": "0x4"
9557fcf1b89SHaiyan Song    },
9567fcf1b89SHaiyan Song    {
957e0ddfd8dSJin Yao        "BriefDescription": "Retirement slots used.",
9587fcf1b89SHaiyan Song        "Counter": "0,1,2,3",
9597fcf1b89SHaiyan Song        "CounterHTOff": "0,1,2,3,4,5,6,7",
960e0ddfd8dSJin Yao        "EventCode": "0xC2",
961e0ddfd8dSJin Yao        "EventName": "UOPS_RETIRED.RETIRE_SLOTS",
962e0ddfd8dSJin Yao        "PublicDescription": "Counts the retirement slots used.",
9637fcf1b89SHaiyan Song        "SampleAfterValue": "2000003",
9647fcf1b89SHaiyan Song        "UMask": "0x2"
9657fcf1b89SHaiyan Song    },
9667fcf1b89SHaiyan Song    {
967e0ddfd8dSJin Yao        "BriefDescription": "Cycles without actually retired uops.",
9687fcf1b89SHaiyan Song        "Counter": "0,1,2,3",
9697fcf1b89SHaiyan Song        "CounterHTOff": "0,1,2,3,4,5,6,7",
970e0ddfd8dSJin Yao        "CounterMask": "1",
971e0ddfd8dSJin Yao        "EventCode": "0xC2",
972e0ddfd8dSJin Yao        "EventName": "UOPS_RETIRED.STALL_CYCLES",
9737fcf1b89SHaiyan Song        "Invert": "1",
974e0ddfd8dSJin Yao        "PublicDescription": "This event counts cycles without actually retired uops.",
9757fcf1b89SHaiyan Song        "SampleAfterValue": "2000003",
9767fcf1b89SHaiyan Song        "UMask": "0x2"
9777fcf1b89SHaiyan Song    },
9787fcf1b89SHaiyan Song    {
979e0ddfd8dSJin Yao        "BriefDescription": "Cycles with less than 10 actually retired uops.",
9807fcf1b89SHaiyan Song        "Counter": "0,1,2,3",
9817fcf1b89SHaiyan Song        "CounterHTOff": "0,1,2,3,4,5,6,7",
982*1ce7fc6fSIan Rogers        "CounterMask": "16",
983e0ddfd8dSJin Yao        "EventCode": "0xC2",
984e0ddfd8dSJin Yao        "EventName": "UOPS_RETIRED.TOTAL_CYCLES",
985e0ddfd8dSJin Yao        "Invert": "1",
986e0ddfd8dSJin Yao        "PublicDescription": "Number of cycles using always true condition (uops_ret < 16) applied to non PEBS uops retired event.",
9877fcf1b89SHaiyan Song        "SampleAfterValue": "2000003",
9887fcf1b89SHaiyan Song        "UMask": "0x2"
989ecd94f1bSKan Liang    }
990ecd94f1bSKan Liang]
991