1[
2    {
3        "EventCode": "0x09",
4        "UMask": "0x1",
5        "Counter": "0,1,2,3",
6        "EventName": "MEMORY_DISAMBIGUATION.HISTORY_RESET",
7        "SampleAfterValue": "2000003",
8        "CounterHTOff": "0,1,2,3,4,5,6,7"
9    },
10    {
11        "EventCode": "0x28",
12        "UMask": "0x7",
13        "BriefDescription": "Core cycles where the core was running in a manner where Turbo may be clipped to the Non-AVX turbo schedule.",
14        "Counter": "0,1,2,3",
15        "EventName": "CORE_POWER.LVL0_TURBO_LICENSE",
16        "PublicDescription": "Core cycles where the core was running with power-delivery for baseline license level 0.  This includes non-AVX codes, SSE, AVX 128-bit, and low-current AVX 256-bit codes.",
17        "SampleAfterValue": "200003",
18        "CounterHTOff": "0,1,2,3,4,5,6,7"
19    },
20    {
21        "EventCode": "0x28",
22        "UMask": "0x18",
23        "BriefDescription": "Core cycles where the core was running in a manner where Turbo may be clipped to the AVX2 turbo schedule.",
24        "Counter": "0,1,2,3",
25        "EventName": "CORE_POWER.LVL1_TURBO_LICENSE",
26        "PublicDescription": "Core cycles where the core was running with power-delivery for license level 1.  This includes high current AVX 256-bit instructions as well as low current AVX 512-bit instructions.",
27        "SampleAfterValue": "200003",
28        "CounterHTOff": "0,1,2,3,4,5,6,7"
29    },
30    {
31        "EventCode": "0x28",
32        "UMask": "0x20",
33        "BriefDescription": "Core cycles where the core was running in a manner where Turbo may be clipped to the AVX512 turbo schedule.",
34        "Counter": "0,1,2,3",
35        "EventName": "CORE_POWER.LVL2_TURBO_LICENSE",
36        "PublicDescription": "Core cycles where the core was running with power-delivery for license level 2 (introduced in Skylake Server michroarchtecture).  This includes high current AVX 512-bit instructions.",
37        "SampleAfterValue": "200003",
38        "CounterHTOff": "0,1,2,3,4,5,6,7"
39    },
40    {
41        "EventCode": "0x28",
42        "UMask": "0x40",
43        "BriefDescription": "Core cycles the core was throttled due to a pending power level request.",
44        "Counter": "0,1,2,3",
45        "EventName": "CORE_POWER.THROTTLE",
46        "PublicDescription": "Core cycles the out-of-order engine was throttled due to a pending power level request.",
47        "SampleAfterValue": "200003",
48        "CounterHTOff": "0,1,2,3,4,5,6,7"
49    },
50    {
51        "EventCode": "0x32",
52        "UMask": "0x1",
53        "BriefDescription": "Number of PREFETCHNTA instructions executed.",
54        "Counter": "0,1,2,3",
55        "EventName": "SW_PREFETCH_ACCESS.NTA",
56        "SampleAfterValue": "2000003",
57        "CounterHTOff": "0,1,2,3,4,5,6,7"
58    },
59    {
60        "EventCode": "0x32",
61        "UMask": "0x2",
62        "BriefDescription": "Number of PREFETCHT0 instructions executed.",
63        "Counter": "0,1,2,3",
64        "EventName": "SW_PREFETCH_ACCESS.T0",
65        "SampleAfterValue": "2000003",
66        "CounterHTOff": "0,1,2,3,4,5,6,7"
67    },
68    {
69        "EventCode": "0x32",
70        "UMask": "0x4",
71        "BriefDescription": "Number of PREFETCHT1 or PREFETCHT2 instructions executed.",
72        "Counter": "0,1,2,3",
73        "EventName": "SW_PREFETCH_ACCESS.T1_T2",
74        "SampleAfterValue": "2000003",
75        "CounterHTOff": "0,1,2,3,4,5,6,7"
76    },
77    {
78        "EventCode": "0x32",
79        "UMask": "0x8",
80        "BriefDescription": "Number of PREFETCHW instructions executed.",
81        "Counter": "0,1,2,3",
82        "EventName": "SW_PREFETCH_ACCESS.PREFETCHW",
83        "SampleAfterValue": "2000003",
84        "CounterHTOff": "0,1,2,3,4,5,6,7"
85    },
86    {
87        "EventCode": "0xCB",
88        "UMask": "0x1",
89        "BriefDescription": "Number of hardware interrupts received by the processor.",
90        "Counter": "0,1,2,3",
91        "EventName": "HW_INTERRUPTS.RECEIVED",
92        "PublicDescription": "Counts the number of hardware interruptions received by the processor.",
93        "SampleAfterValue": "203",
94        "CounterHTOff": "0,1,2,3,4,5,6,7"
95    },
96    {
97        "EventCode": "0xEF",
98        "UMask": "0x1",
99        "Counter": "0,1,2,3",
100        "EventName": "CORE_SNOOP_RESPONSE.RSP_IHITI",
101        "SampleAfterValue": "2000003",
102        "CounterHTOff": "0,1,2,3,4,5,6,7"
103    },
104    {
105        "EventCode": "0xEF",
106        "UMask": "0x2",
107        "Counter": "0,1,2,3",
108        "EventName": "CORE_SNOOP_RESPONSE.RSP_IHITFSE",
109        "SampleAfterValue": "2000003",
110        "CounterHTOff": "0,1,2,3,4,5,6,7"
111    },
112    {
113        "EventCode": "0xEF",
114        "UMask": "0x4",
115        "Counter": "0,1,2,3",
116        "EventName": "CORE_SNOOP_RESPONSE.RSP_SHITFSE",
117        "SampleAfterValue": "2000003",
118        "CounterHTOff": "0,1,2,3,4,5,6,7"
119    },
120    {
121        "EventCode": "0xEF",
122        "UMask": "0x8",
123        "Counter": "0,1,2,3",
124        "EventName": "CORE_SNOOP_RESPONSE.RSP_SFWDM",
125        "SampleAfterValue": "2000003",
126        "CounterHTOff": "0,1,2,3,4,5,6,7"
127    },
128    {
129        "EventCode": "0xEF",
130        "UMask": "0x10",
131        "Counter": "0,1,2,3",
132        "EventName": "CORE_SNOOP_RESPONSE.RSP_IFWDM",
133        "SampleAfterValue": "2000003",
134        "CounterHTOff": "0,1,2,3,4,5,6,7"
135    },
136    {
137        "EventCode": "0xEF",
138        "UMask": "0x20",
139        "Counter": "0,1,2,3",
140        "EventName": "CORE_SNOOP_RESPONSE.RSP_IFWDFE",
141        "SampleAfterValue": "2000003",
142        "CounterHTOff": "0,1,2,3,4,5,6,7"
143    },
144    {
145        "EventCode": "0xEF",
146        "UMask": "0x40",
147        "Counter": "0,1,2,3",
148        "EventName": "CORE_SNOOP_RESPONSE.RSP_SFWDFE",
149        "SampleAfterValue": "2000003",
150        "CounterHTOff": "0,1,2,3,4,5,6,7"
151    },
152    {
153        "EventCode": "0xFE",
154        "UMask": "0x2",
155        "BriefDescription": "Counts number of cache lines that are allocated and written back to L3 with the intention that they are more likely to be reused shortly",
156        "Counter": "0,1,2,3",
157        "EventName": "IDI_MISC.WB_UPGRADE",
158        "PublicDescription": "Counts number of cache lines that are allocated and written back to L3 with the intention that they are more likely to be reused shortly.",
159        "SampleAfterValue": "100003",
160        "CounterHTOff": "0,1,2,3,4,5,6,7"
161    },
162    {
163        "EventCode": "0xFE",
164        "UMask": "0x4",
165        "BriefDescription": "Counts number of cache lines that are dropped and not written back to L3 as they are deemed to be less likely to be reused shortly",
166        "Counter": "0,1,2,3",
167        "EventName": "IDI_MISC.WB_DOWNGRADE",
168        "PublicDescription": "Counts number of cache lines that are dropped and not written back to L3 as they are deemed to be less likely to be reused shortly.",
169        "SampleAfterValue": "100003",
170        "CounterHTOff": "0,1,2,3,4,5,6,7"
171    },
172    {
173        "Offcore": "1",
174        "EventCode": "0xB7, 0xBB",
175        "UMask": "0x1",
176        "BriefDescription": "Counts demand data reads",
177        "MSRValue": "0x0080020001",
178        "Counter": "0,1,2,3",
179        "EventName": "OCR.DEMAND_DATA_RD.SUPPLIER_NONE.SNOOP_NONE",
180        "MSRIndex": "0x1a6,0x1a7",
181        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
182        "SampleAfterValue": "100003",
183        "CounterHTOff": "0,1,2,3"
184    },
185    {
186        "Offcore": "1",
187        "EventCode": "0xB7, 0xBB",
188        "UMask": "0x1",
189        "BriefDescription": "Counts demand data reads  TBD",
190        "MSRValue": "0x0100020001",
191        "Counter": "0,1,2,3",
192        "EventName": "OCR.DEMAND_DATA_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED",
193        "MSRIndex": "0x1a6,0x1a7",
194        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
195        "SampleAfterValue": "100003",
196        "CounterHTOff": "0,1,2,3"
197    },
198    {
199        "Offcore": "1",
200        "EventCode": "0xB7, 0xBB",
201        "UMask": "0x1",
202        "BriefDescription": "Counts demand data reads",
203        "MSRValue": "0x0200020001",
204        "Counter": "0,1,2,3",
205        "EventName": "OCR.DEMAND_DATA_RD.SUPPLIER_NONE.SNOOP_MISS",
206        "MSRIndex": "0x1a6,0x1a7",
207        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
208        "SampleAfterValue": "100003",
209        "CounterHTOff": "0,1,2,3"
210    },
211    {
212        "Offcore": "1",
213        "EventCode": "0xB7, 0xBB",
214        "UMask": "0x1",
215        "BriefDescription": "Counts demand data reads  TBD",
216        "MSRValue": "0x0400020001",
217        "Counter": "0,1,2,3",
218        "EventName": "OCR.DEMAND_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD",
219        "MSRIndex": "0x1a6,0x1a7",
220        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
221        "SampleAfterValue": "100003",
222        "CounterHTOff": "0,1,2,3"
223    },
224    {
225        "Offcore": "1",
226        "EventCode": "0xB7, 0xBB",
227        "UMask": "0x1",
228        "BriefDescription": "Counts demand data reads  TBD",
229        "MSRValue": "0x0800020001",
230        "Counter": "0,1,2,3",
231        "EventName": "OCR.DEMAND_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD",
232        "MSRIndex": "0x1a6,0x1a7",
233        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
234        "SampleAfterValue": "100003",
235        "CounterHTOff": "0,1,2,3"
236    },
237    {
238        "Offcore": "1",
239        "EventCode": "0xB7, 0xBB",
240        "UMask": "0x1",
241        "BriefDescription": "Counts demand data reads  TBD",
242        "MSRValue": "0x1000020001",
243        "Counter": "0,1,2,3",
244        "EventName": "OCR.DEMAND_DATA_RD.SUPPLIER_NONE.HITM_OTHER_CORE",
245        "MSRIndex": "0x1a6,0x1a7",
246        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
247        "SampleAfterValue": "100003",
248        "CounterHTOff": "0,1,2,3"
249    },
250    {
251        "Offcore": "1",
252        "EventCode": "0xB7, 0xBB",
253        "UMask": "0x1",
254        "BriefDescription": "Counts demand data reads  TBD",
255        "MSRValue": "0x3F80020001",
256        "Counter": "0,1,2,3",
257        "EventName": "OCR.DEMAND_DATA_RD.SUPPLIER_NONE.ANY_SNOOP",
258        "MSRIndex": "0x1a6,0x1a7",
259        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
260        "SampleAfterValue": "100003",
261        "CounterHTOff": "0,1,2,3"
262    },
263    {
264        "Offcore": "1",
265        "EventCode": "0xB7, 0xBB",
266        "UMask": "0x1",
267        "BriefDescription": "Counts demand data reads",
268        "MSRValue": "0x0080040001",
269        "Counter": "0,1,2,3",
270        "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_M.SNOOP_NONE",
271        "MSRIndex": "0x1a6,0x1a7",
272        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
273        "SampleAfterValue": "100003",
274        "CounterHTOff": "0,1,2,3"
275    },
276    {
277        "Offcore": "1",
278        "EventCode": "0xB7, 0xBB",
279        "UMask": "0x1",
280        "BriefDescription": "Counts demand data reads  TBD",
281        "MSRValue": "0x0100040001",
282        "Counter": "0,1,2,3",
283        "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDED",
284        "MSRIndex": "0x1a6,0x1a7",
285        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
286        "SampleAfterValue": "100003",
287        "CounterHTOff": "0,1,2,3"
288    },
289    {
290        "Offcore": "1",
291        "EventCode": "0xB7, 0xBB",
292        "UMask": "0x1",
293        "BriefDescription": "Counts demand data reads",
294        "MSRValue": "0x0200040001",
295        "Counter": "0,1,2,3",
296        "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_M.SNOOP_MISS",
297        "MSRIndex": "0x1a6,0x1a7",
298        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
299        "SampleAfterValue": "100003",
300        "CounterHTOff": "0,1,2,3"
301    },
302    {
303        "Offcore": "1",
304        "EventCode": "0xB7, 0xBB",
305        "UMask": "0x1",
306        "BriefDescription": "Counts demand data reads  TBD",
307        "MSRValue": "0x0400040001",
308        "Counter": "0,1,2,3",
309        "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD",
310        "MSRIndex": "0x1a6,0x1a7",
311        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
312        "SampleAfterValue": "100003",
313        "CounterHTOff": "0,1,2,3"
314    },
315    {
316        "Offcore": "1",
317        "EventCode": "0xB7, 0xBB",
318        "UMask": "0x1",
319        "BriefDescription": "Counts demand data reads  TBD",
320        "MSRValue": "0x0800040001",
321        "Counter": "0,1,2,3",
322        "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWD",
323        "MSRIndex": "0x1a6,0x1a7",
324        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
325        "SampleAfterValue": "100003",
326        "CounterHTOff": "0,1,2,3"
327    },
328    {
329        "Offcore": "1",
330        "EventCode": "0xB7, 0xBB",
331        "UMask": "0x1",
332        "BriefDescription": "Counts demand data reads  TBD",
333        "MSRValue": "0x1000040001",
334        "Counter": "0,1,2,3",
335        "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_M.HITM_OTHER_CORE",
336        "MSRIndex": "0x1a6,0x1a7",
337        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
338        "SampleAfterValue": "100003",
339        "CounterHTOff": "0,1,2,3"
340    },
341    {
342        "Offcore": "1",
343        "EventCode": "0xB7, 0xBB",
344        "UMask": "0x1",
345        "BriefDescription": "Counts demand data reads  TBD",
346        "MSRValue": "0x3F80040001",
347        "Counter": "0,1,2,3",
348        "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_M.ANY_SNOOP",
349        "MSRIndex": "0x1a6,0x1a7",
350        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
351        "SampleAfterValue": "100003",
352        "CounterHTOff": "0,1,2,3"
353    },
354    {
355        "Offcore": "1",
356        "EventCode": "0xB7, 0xBB",
357        "UMask": "0x1",
358        "BriefDescription": "Counts demand data reads",
359        "MSRValue": "0x0080080001",
360        "Counter": "0,1,2,3",
361        "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_E.SNOOP_NONE",
362        "MSRIndex": "0x1a6,0x1a7",
363        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
364        "SampleAfterValue": "100003",
365        "CounterHTOff": "0,1,2,3"
366    },
367    {
368        "Offcore": "1",
369        "EventCode": "0xB7, 0xBB",
370        "UMask": "0x1",
371        "BriefDescription": "Counts demand data reads  TBD",
372        "MSRValue": "0x0100080001",
373        "Counter": "0,1,2,3",
374        "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDED",
375        "MSRIndex": "0x1a6,0x1a7",
376        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
377        "SampleAfterValue": "100003",
378        "CounterHTOff": "0,1,2,3"
379    },
380    {
381        "Offcore": "1",
382        "EventCode": "0xB7, 0xBB",
383        "UMask": "0x1",
384        "BriefDescription": "Counts demand data reads",
385        "MSRValue": "0x0200080001",
386        "Counter": "0,1,2,3",
387        "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_E.SNOOP_MISS",
388        "MSRIndex": "0x1a6,0x1a7",
389        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
390        "SampleAfterValue": "100003",
391        "CounterHTOff": "0,1,2,3"
392    },
393    {
394        "Offcore": "1",
395        "EventCode": "0xB7, 0xBB",
396        "UMask": "0x1",
397        "BriefDescription": "Counts demand data reads  TBD",
398        "MSRValue": "0x0400080001",
399        "Counter": "0,1,2,3",
400        "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD",
401        "MSRIndex": "0x1a6,0x1a7",
402        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
403        "SampleAfterValue": "100003",
404        "CounterHTOff": "0,1,2,3"
405    },
406    {
407        "Offcore": "1",
408        "EventCode": "0xB7, 0xBB",
409        "UMask": "0x1",
410        "BriefDescription": "Counts demand data reads  TBD",
411        "MSRValue": "0x0800080001",
412        "Counter": "0,1,2,3",
413        "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWD",
414        "MSRIndex": "0x1a6,0x1a7",
415        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
416        "SampleAfterValue": "100003",
417        "CounterHTOff": "0,1,2,3"
418    },
419    {
420        "Offcore": "1",
421        "EventCode": "0xB7, 0xBB",
422        "UMask": "0x1",
423        "BriefDescription": "Counts demand data reads  TBD",
424        "MSRValue": "0x1000080001",
425        "Counter": "0,1,2,3",
426        "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_E.HITM_OTHER_CORE",
427        "MSRIndex": "0x1a6,0x1a7",
428        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
429        "SampleAfterValue": "100003",
430        "CounterHTOff": "0,1,2,3"
431    },
432    {
433        "Offcore": "1",
434        "EventCode": "0xB7, 0xBB",
435        "UMask": "0x1",
436        "BriefDescription": "Counts demand data reads  TBD",
437        "MSRValue": "0x3F80080001",
438        "Counter": "0,1,2,3",
439        "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_E.ANY_SNOOP",
440        "MSRIndex": "0x1a6,0x1a7",
441        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
442        "SampleAfterValue": "100003",
443        "CounterHTOff": "0,1,2,3"
444    },
445    {
446        "Offcore": "1",
447        "EventCode": "0xB7, 0xBB",
448        "UMask": "0x1",
449        "BriefDescription": "Counts demand data reads",
450        "MSRValue": "0x0080100001",
451        "Counter": "0,1,2,3",
452        "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_S.SNOOP_NONE",
453        "MSRIndex": "0x1a6,0x1a7",
454        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
455        "SampleAfterValue": "100003",
456        "CounterHTOff": "0,1,2,3"
457    },
458    {
459        "Offcore": "1",
460        "EventCode": "0xB7, 0xBB",
461        "UMask": "0x1",
462        "BriefDescription": "Counts demand data reads  TBD",
463        "MSRValue": "0x0100100001",
464        "Counter": "0,1,2,3",
465        "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDED",
466        "MSRIndex": "0x1a6,0x1a7",
467        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
468        "SampleAfterValue": "100003",
469        "CounterHTOff": "0,1,2,3"
470    },
471    {
472        "Offcore": "1",
473        "EventCode": "0xB7, 0xBB",
474        "UMask": "0x1",
475        "BriefDescription": "Counts demand data reads",
476        "MSRValue": "0x0200100001",
477        "Counter": "0,1,2,3",
478        "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_S.SNOOP_MISS",
479        "MSRIndex": "0x1a6,0x1a7",
480        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
481        "SampleAfterValue": "100003",
482        "CounterHTOff": "0,1,2,3"
483    },
484    {
485        "Offcore": "1",
486        "EventCode": "0xB7, 0xBB",
487        "UMask": "0x1",
488        "BriefDescription": "Counts demand data reads  TBD",
489        "MSRValue": "0x0400100001",
490        "Counter": "0,1,2,3",
491        "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD",
492        "MSRIndex": "0x1a6,0x1a7",
493        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
494        "SampleAfterValue": "100003",
495        "CounterHTOff": "0,1,2,3"
496    },
497    {
498        "Offcore": "1",
499        "EventCode": "0xB7, 0xBB",
500        "UMask": "0x1",
501        "BriefDescription": "Counts demand data reads  TBD",
502        "MSRValue": "0x0800100001",
503        "Counter": "0,1,2,3",
504        "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWD",
505        "MSRIndex": "0x1a6,0x1a7",
506        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
507        "SampleAfterValue": "100003",
508        "CounterHTOff": "0,1,2,3"
509    },
510    {
511        "Offcore": "1",
512        "EventCode": "0xB7, 0xBB",
513        "UMask": "0x1",
514        "BriefDescription": "Counts demand data reads  TBD",
515        "MSRValue": "0x1000100001",
516        "Counter": "0,1,2,3",
517        "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_S.HITM_OTHER_CORE",
518        "MSRIndex": "0x1a6,0x1a7",
519        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
520        "SampleAfterValue": "100003",
521        "CounterHTOff": "0,1,2,3"
522    },
523    {
524        "Offcore": "1",
525        "EventCode": "0xB7, 0xBB",
526        "UMask": "0x1",
527        "BriefDescription": "Counts demand data reads  TBD",
528        "MSRValue": "0x3F80100001",
529        "Counter": "0,1,2,3",
530        "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_S.ANY_SNOOP",
531        "MSRIndex": "0x1a6,0x1a7",
532        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
533        "SampleAfterValue": "100003",
534        "CounterHTOff": "0,1,2,3"
535    },
536    {
537        "Offcore": "1",
538        "EventCode": "0xB7, 0xBB",
539        "UMask": "0x1",
540        "BriefDescription": "Counts demand data reads",
541        "MSRValue": "0x0080200001",
542        "Counter": "0,1,2,3",
543        "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_F.SNOOP_NONE",
544        "MSRIndex": "0x1a6,0x1a7",
545        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
546        "SampleAfterValue": "100003",
547        "CounterHTOff": "0,1,2,3"
548    },
549    {
550        "Offcore": "1",
551        "EventCode": "0xB7, 0xBB",
552        "UMask": "0x1",
553        "BriefDescription": "Counts demand data reads  TBD",
554        "MSRValue": "0x0100200001",
555        "Counter": "0,1,2,3",
556        "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDED",
557        "MSRIndex": "0x1a6,0x1a7",
558        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
559        "SampleAfterValue": "100003",
560        "CounterHTOff": "0,1,2,3"
561    },
562    {
563        "Offcore": "1",
564        "EventCode": "0xB7, 0xBB",
565        "UMask": "0x1",
566        "BriefDescription": "Counts demand data reads",
567        "MSRValue": "0x0200200001",
568        "Counter": "0,1,2,3",
569        "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_F.SNOOP_MISS",
570        "MSRIndex": "0x1a6,0x1a7",
571        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
572        "SampleAfterValue": "100003",
573        "CounterHTOff": "0,1,2,3"
574    },
575    {
576        "Offcore": "1",
577        "EventCode": "0xB7, 0xBB",
578        "UMask": "0x1",
579        "BriefDescription": "Counts demand data reads  TBD",
580        "MSRValue": "0x0400200001",
581        "Counter": "0,1,2,3",
582        "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD",
583        "MSRIndex": "0x1a6,0x1a7",
584        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
585        "SampleAfterValue": "100003",
586        "CounterHTOff": "0,1,2,3"
587    },
588    {
589        "Offcore": "1",
590        "EventCode": "0xB7, 0xBB",
591        "UMask": "0x1",
592        "BriefDescription": "Counts demand data reads  TBD",
593        "MSRValue": "0x0800200001",
594        "Counter": "0,1,2,3",
595        "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWD",
596        "MSRIndex": "0x1a6,0x1a7",
597        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
598        "SampleAfterValue": "100003",
599        "CounterHTOff": "0,1,2,3"
600    },
601    {
602        "Offcore": "1",
603        "EventCode": "0xB7, 0xBB",
604        "UMask": "0x1",
605        "BriefDescription": "Counts demand data reads  TBD",
606        "MSRValue": "0x1000200001",
607        "Counter": "0,1,2,3",
608        "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_F.HITM_OTHER_CORE",
609        "MSRIndex": "0x1a6,0x1a7",
610        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
611        "SampleAfterValue": "100003",
612        "CounterHTOff": "0,1,2,3"
613    },
614    {
615        "Offcore": "1",
616        "EventCode": "0xB7, 0xBB",
617        "UMask": "0x1",
618        "BriefDescription": "Counts demand data reads  TBD",
619        "MSRValue": "0x3F80200001",
620        "Counter": "0,1,2,3",
621        "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_F.ANY_SNOOP",
622        "MSRIndex": "0x1a6,0x1a7",
623        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
624        "SampleAfterValue": "100003",
625        "CounterHTOff": "0,1,2,3"
626    },
627    {
628        "Offcore": "1",
629        "EventCode": "0xB7, 0xBB",
630        "UMask": "0x1",
631        "BriefDescription": "Counts demand data reads TBD",
632        "MSRValue": "0x00803C0001",
633        "Counter": "0,1,2,3",
634        "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_NONE",
635        "MSRIndex": "0x1a6,0x1a7",
636        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
637        "SampleAfterValue": "100003",
638        "CounterHTOff": "0,1,2,3"
639    },
640    {
641        "Offcore": "1",
642        "EventCode": "0xB7, 0xBB",
643        "UMask": "0x1",
644        "BriefDescription": "Counts demand data reads TBD TBD",
645        "MSRValue": "0x01003C0001",
646        "Counter": "0,1,2,3",
647        "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.NO_SNOOP_NEEDED",
648        "MSRIndex": "0x1a6,0x1a7",
649        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
650        "SampleAfterValue": "100003",
651        "CounterHTOff": "0,1,2,3"
652    },
653    {
654        "Offcore": "1",
655        "EventCode": "0xB7, 0xBB",
656        "UMask": "0x1",
657        "BriefDescription": "Counts demand data reads TBD",
658        "MSRValue": "0x02003C0001",
659        "Counter": "0,1,2,3",
660        "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_MISS",
661        "MSRIndex": "0x1a6,0x1a7",
662        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
663        "SampleAfterValue": "100003",
664        "CounterHTOff": "0,1,2,3"
665    },
666    {
667        "Offcore": "1",
668        "EventCode": "0xB7, 0xBB",
669        "UMask": "0x1",
670        "BriefDescription": "Counts demand data reads TBD TBD",
671        "MSRValue": "0x04003C0001",
672        "Counter": "0,1,2,3",
673        "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD",
674        "MSRIndex": "0x1a6,0x1a7",
675        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
676        "SampleAfterValue": "100003",
677        "CounterHTOff": "0,1,2,3"
678    },
679    {
680        "Offcore": "1",
681        "EventCode": "0xB7, 0xBB",
682        "UMask": "0x1",
683        "BriefDescription": "Counts demand data reads TBD TBD",
684        "MSRValue": "0x08003C0001",
685        "Counter": "0,1,2,3",
686        "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD",
687        "MSRIndex": "0x1a6,0x1a7",
688        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
689        "SampleAfterValue": "100003",
690        "CounterHTOff": "0,1,2,3"
691    },
692    {
693        "Offcore": "1",
694        "EventCode": "0xB7, 0xBB",
695        "UMask": "0x1",
696        "BriefDescription": "Counts demand data reads TBD TBD",
697        "MSRValue": "0x10003C0001",
698        "Counter": "0,1,2,3",
699        "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.HITM_OTHER_CORE",
700        "MSRIndex": "0x1a6,0x1a7",
701        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
702        "SampleAfterValue": "100003",
703        "CounterHTOff": "0,1,2,3"
704    },
705    {
706        "Offcore": "1",
707        "EventCode": "0xB7, 0xBB",
708        "UMask": "0x1",
709        "BriefDescription": "Counts demand data reads TBD TBD",
710        "MSRValue": "0x3F803C0001",
711        "Counter": "0,1,2,3",
712        "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.ANY_SNOOP",
713        "MSRIndex": "0x1a6,0x1a7",
714        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
715        "SampleAfterValue": "100003",
716        "CounterHTOff": "0,1,2,3"
717    },
718    {
719        "Offcore": "1",
720        "EventCode": "0xB7, 0xBB",
721        "UMask": "0x1",
722        "BriefDescription": "Counts all demand data writes (RFOs)",
723        "MSRValue": "0x0080020002",
724        "Counter": "0,1,2,3",
725        "EventName": "OCR.DEMAND_RFO.SUPPLIER_NONE.SNOOP_NONE",
726        "MSRIndex": "0x1a6,0x1a7",
727        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
728        "SampleAfterValue": "100003",
729        "CounterHTOff": "0,1,2,3"
730    },
731    {
732        "Offcore": "1",
733        "EventCode": "0xB7, 0xBB",
734        "UMask": "0x1",
735        "BriefDescription": "Counts all demand data writes (RFOs)  TBD",
736        "MSRValue": "0x0100020002",
737        "Counter": "0,1,2,3",
738        "EventName": "OCR.DEMAND_RFO.SUPPLIER_NONE.NO_SNOOP_NEEDED",
739        "MSRIndex": "0x1a6,0x1a7",
740        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
741        "SampleAfterValue": "100003",
742        "CounterHTOff": "0,1,2,3"
743    },
744    {
745        "Offcore": "1",
746        "EventCode": "0xB7, 0xBB",
747        "UMask": "0x1",
748        "BriefDescription": "Counts all demand data writes (RFOs)",
749        "MSRValue": "0x0200020002",
750        "Counter": "0,1,2,3",
751        "EventName": "OCR.DEMAND_RFO.SUPPLIER_NONE.SNOOP_MISS",
752        "MSRIndex": "0x1a6,0x1a7",
753        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
754        "SampleAfterValue": "100003",
755        "CounterHTOff": "0,1,2,3"
756    },
757    {
758        "Offcore": "1",
759        "EventCode": "0xB7, 0xBB",
760        "UMask": "0x1",
761        "BriefDescription": "Counts all demand data writes (RFOs)  TBD",
762        "MSRValue": "0x0400020002",
763        "Counter": "0,1,2,3",
764        "EventName": "OCR.DEMAND_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD",
765        "MSRIndex": "0x1a6,0x1a7",
766        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
767        "SampleAfterValue": "100003",
768        "CounterHTOff": "0,1,2,3"
769    },
770    {
771        "Offcore": "1",
772        "EventCode": "0xB7, 0xBB",
773        "UMask": "0x1",
774        "BriefDescription": "Counts all demand data writes (RFOs)  TBD",
775        "MSRValue": "0x0800020002",
776        "Counter": "0,1,2,3",
777        "EventName": "OCR.DEMAND_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_FWD",
778        "MSRIndex": "0x1a6,0x1a7",
779        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
780        "SampleAfterValue": "100003",
781        "CounterHTOff": "0,1,2,3"
782    },
783    {
784        "Offcore": "1",
785        "EventCode": "0xB7, 0xBB",
786        "UMask": "0x1",
787        "BriefDescription": "Counts all demand data writes (RFOs)  TBD",
788        "MSRValue": "0x1000020002",
789        "Counter": "0,1,2,3",
790        "EventName": "OCR.DEMAND_RFO.SUPPLIER_NONE.HITM_OTHER_CORE",
791        "MSRIndex": "0x1a6,0x1a7",
792        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
793        "SampleAfterValue": "100003",
794        "CounterHTOff": "0,1,2,3"
795    },
796    {
797        "Offcore": "1",
798        "EventCode": "0xB7, 0xBB",
799        "UMask": "0x1",
800        "BriefDescription": "Counts all demand data writes (RFOs)  TBD",
801        "MSRValue": "0x3F80020002",
802        "Counter": "0,1,2,3",
803        "EventName": "OCR.DEMAND_RFO.SUPPLIER_NONE.ANY_SNOOP",
804        "MSRIndex": "0x1a6,0x1a7",
805        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
806        "SampleAfterValue": "100003",
807        "CounterHTOff": "0,1,2,3"
808    },
809    {
810        "Offcore": "1",
811        "EventCode": "0xB7, 0xBB",
812        "UMask": "0x1",
813        "BriefDescription": "Counts all demand data writes (RFOs)",
814        "MSRValue": "0x0080040002",
815        "Counter": "0,1,2,3",
816        "EventName": "OCR.DEMAND_RFO.L3_HIT_M.SNOOP_NONE",
817        "MSRIndex": "0x1a6,0x1a7",
818        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
819        "SampleAfterValue": "100003",
820        "CounterHTOff": "0,1,2,3"
821    },
822    {
823        "Offcore": "1",
824        "EventCode": "0xB7, 0xBB",
825        "UMask": "0x1",
826        "BriefDescription": "Counts all demand data writes (RFOs)  TBD",
827        "MSRValue": "0x0100040002",
828        "Counter": "0,1,2,3",
829        "EventName": "OCR.DEMAND_RFO.L3_HIT_M.NO_SNOOP_NEEDED",
830        "MSRIndex": "0x1a6,0x1a7",
831        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
832        "SampleAfterValue": "100003",
833        "CounterHTOff": "0,1,2,3"
834    },
835    {
836        "Offcore": "1",
837        "EventCode": "0xB7, 0xBB",
838        "UMask": "0x1",
839        "BriefDescription": "Counts all demand data writes (RFOs)",
840        "MSRValue": "0x0200040002",
841        "Counter": "0,1,2,3",
842        "EventName": "OCR.DEMAND_RFO.L3_HIT_M.SNOOP_MISS",
843        "MSRIndex": "0x1a6,0x1a7",
844        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
845        "SampleAfterValue": "100003",
846        "CounterHTOff": "0,1,2,3"
847    },
848    {
849        "Offcore": "1",
850        "EventCode": "0xB7, 0xBB",
851        "UMask": "0x1",
852        "BriefDescription": "Counts all demand data writes (RFOs)  TBD",
853        "MSRValue": "0x0400040002",
854        "Counter": "0,1,2,3",
855        "EventName": "OCR.DEMAND_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWD",
856        "MSRIndex": "0x1a6,0x1a7",
857        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
858        "SampleAfterValue": "100003",
859        "CounterHTOff": "0,1,2,3"
860    },
861    {
862        "Offcore": "1",
863        "EventCode": "0xB7, 0xBB",
864        "UMask": "0x1",
865        "BriefDescription": "Counts all demand data writes (RFOs)  TBD",
866        "MSRValue": "0x0800040002",
867        "Counter": "0,1,2,3",
868        "EventName": "OCR.DEMAND_RFO.L3_HIT_M.HIT_OTHER_CORE_FWD",
869        "MSRIndex": "0x1a6,0x1a7",
870        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
871        "SampleAfterValue": "100003",
872        "CounterHTOff": "0,1,2,3"
873    },
874    {
875        "Offcore": "1",
876        "EventCode": "0xB7, 0xBB",
877        "UMask": "0x1",
878        "BriefDescription": "Counts all demand data writes (RFOs)  TBD",
879        "MSRValue": "0x1000040002",
880        "Counter": "0,1,2,3",
881        "EventName": "OCR.DEMAND_RFO.L3_HIT_M.HITM_OTHER_CORE",
882        "MSRIndex": "0x1a6,0x1a7",
883        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
884        "SampleAfterValue": "100003",
885        "CounterHTOff": "0,1,2,3"
886    },
887    {
888        "Offcore": "1",
889        "EventCode": "0xB7, 0xBB",
890        "UMask": "0x1",
891        "BriefDescription": "Counts all demand data writes (RFOs)  TBD",
892        "MSRValue": "0x3F80040002",
893        "Counter": "0,1,2,3",
894        "EventName": "OCR.DEMAND_RFO.L3_HIT_M.ANY_SNOOP",
895        "MSRIndex": "0x1a6,0x1a7",
896        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
897        "SampleAfterValue": "100003",
898        "CounterHTOff": "0,1,2,3"
899    },
900    {
901        "Offcore": "1",
902        "EventCode": "0xB7, 0xBB",
903        "UMask": "0x1",
904        "BriefDescription": "Counts all demand data writes (RFOs)",
905        "MSRValue": "0x0080080002",
906        "Counter": "0,1,2,3",
907        "EventName": "OCR.DEMAND_RFO.L3_HIT_E.SNOOP_NONE",
908        "MSRIndex": "0x1a6,0x1a7",
909        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
910        "SampleAfterValue": "100003",
911        "CounterHTOff": "0,1,2,3"
912    },
913    {
914        "Offcore": "1",
915        "EventCode": "0xB7, 0xBB",
916        "UMask": "0x1",
917        "BriefDescription": "Counts all demand data writes (RFOs)  TBD",
918        "MSRValue": "0x0100080002",
919        "Counter": "0,1,2,3",
920        "EventName": "OCR.DEMAND_RFO.L3_HIT_E.NO_SNOOP_NEEDED",
921        "MSRIndex": "0x1a6,0x1a7",
922        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
923        "SampleAfterValue": "100003",
924        "CounterHTOff": "0,1,2,3"
925    },
926    {
927        "Offcore": "1",
928        "EventCode": "0xB7, 0xBB",
929        "UMask": "0x1",
930        "BriefDescription": "Counts all demand data writes (RFOs)",
931        "MSRValue": "0x0200080002",
932        "Counter": "0,1,2,3",
933        "EventName": "OCR.DEMAND_RFO.L3_HIT_E.SNOOP_MISS",
934        "MSRIndex": "0x1a6,0x1a7",
935        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
936        "SampleAfterValue": "100003",
937        "CounterHTOff": "0,1,2,3"
938    },
939    {
940        "Offcore": "1",
941        "EventCode": "0xB7, 0xBB",
942        "UMask": "0x1",
943        "BriefDescription": "Counts all demand data writes (RFOs)  TBD",
944        "MSRValue": "0x0400080002",
945        "Counter": "0,1,2,3",
946        "EventName": "OCR.DEMAND_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWD",
947        "MSRIndex": "0x1a6,0x1a7",
948        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
949        "SampleAfterValue": "100003",
950        "CounterHTOff": "0,1,2,3"
951    },
952    {
953        "Offcore": "1",
954        "EventCode": "0xB7, 0xBB",
955        "UMask": "0x1",
956        "BriefDescription": "Counts all demand data writes (RFOs)  TBD",
957        "MSRValue": "0x0800080002",
958        "Counter": "0,1,2,3",
959        "EventName": "OCR.DEMAND_RFO.L3_HIT_E.HIT_OTHER_CORE_FWD",
960        "MSRIndex": "0x1a6,0x1a7",
961        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
962        "SampleAfterValue": "100003",
963        "CounterHTOff": "0,1,2,3"
964    },
965    {
966        "Offcore": "1",
967        "EventCode": "0xB7, 0xBB",
968        "UMask": "0x1",
969        "BriefDescription": "Counts all demand data writes (RFOs)  TBD",
970        "MSRValue": "0x1000080002",
971        "Counter": "0,1,2,3",
972        "EventName": "OCR.DEMAND_RFO.L3_HIT_E.HITM_OTHER_CORE",
973        "MSRIndex": "0x1a6,0x1a7",
974        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
975        "SampleAfterValue": "100003",
976        "CounterHTOff": "0,1,2,3"
977    },
978    {
979        "Offcore": "1",
980        "EventCode": "0xB7, 0xBB",
981        "UMask": "0x1",
982        "BriefDescription": "Counts all demand data writes (RFOs)  TBD",
983        "MSRValue": "0x3F80080002",
984        "Counter": "0,1,2,3",
985        "EventName": "OCR.DEMAND_RFO.L3_HIT_E.ANY_SNOOP",
986        "MSRIndex": "0x1a6,0x1a7",
987        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
988        "SampleAfterValue": "100003",
989        "CounterHTOff": "0,1,2,3"
990    },
991    {
992        "Offcore": "1",
993        "EventCode": "0xB7, 0xBB",
994        "UMask": "0x1",
995        "BriefDescription": "Counts all demand data writes (RFOs)",
996        "MSRValue": "0x0080100002",
997        "Counter": "0,1,2,3",
998        "EventName": "OCR.DEMAND_RFO.L3_HIT_S.SNOOP_NONE",
999        "MSRIndex": "0x1a6,0x1a7",
1000        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
1001        "SampleAfterValue": "100003",
1002        "CounterHTOff": "0,1,2,3"
1003    },
1004    {
1005        "Offcore": "1",
1006        "EventCode": "0xB7, 0xBB",
1007        "UMask": "0x1",
1008        "BriefDescription": "Counts all demand data writes (RFOs)  TBD",
1009        "MSRValue": "0x0100100002",
1010        "Counter": "0,1,2,3",
1011        "EventName": "OCR.DEMAND_RFO.L3_HIT_S.NO_SNOOP_NEEDED",
1012        "MSRIndex": "0x1a6,0x1a7",
1013        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
1014        "SampleAfterValue": "100003",
1015        "CounterHTOff": "0,1,2,3"
1016    },
1017    {
1018        "Offcore": "1",
1019        "EventCode": "0xB7, 0xBB",
1020        "UMask": "0x1",
1021        "BriefDescription": "Counts all demand data writes (RFOs)",
1022        "MSRValue": "0x0200100002",
1023        "Counter": "0,1,2,3",
1024        "EventName": "OCR.DEMAND_RFO.L3_HIT_S.SNOOP_MISS",
1025        "MSRIndex": "0x1a6,0x1a7",
1026        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
1027        "SampleAfterValue": "100003",
1028        "CounterHTOff": "0,1,2,3"
1029    },
1030    {
1031        "Offcore": "1",
1032        "EventCode": "0xB7, 0xBB",
1033        "UMask": "0x1",
1034        "BriefDescription": "Counts all demand data writes (RFOs)  TBD",
1035        "MSRValue": "0x0400100002",
1036        "Counter": "0,1,2,3",
1037        "EventName": "OCR.DEMAND_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWD",
1038        "MSRIndex": "0x1a6,0x1a7",
1039        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
1040        "SampleAfterValue": "100003",
1041        "CounterHTOff": "0,1,2,3"
1042    },
1043    {
1044        "Offcore": "1",
1045        "EventCode": "0xB7, 0xBB",
1046        "UMask": "0x1",
1047        "BriefDescription": "Counts all demand data writes (RFOs)  TBD",
1048        "MSRValue": "0x0800100002",
1049        "Counter": "0,1,2,3",
1050        "EventName": "OCR.DEMAND_RFO.L3_HIT_S.HIT_OTHER_CORE_FWD",
1051        "MSRIndex": "0x1a6,0x1a7",
1052        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
1053        "SampleAfterValue": "100003",
1054        "CounterHTOff": "0,1,2,3"
1055    },
1056    {
1057        "Offcore": "1",
1058        "EventCode": "0xB7, 0xBB",
1059        "UMask": "0x1",
1060        "BriefDescription": "Counts all demand data writes (RFOs)  TBD",
1061        "MSRValue": "0x1000100002",
1062        "Counter": "0,1,2,3",
1063        "EventName": "OCR.DEMAND_RFO.L3_HIT_S.HITM_OTHER_CORE",
1064        "MSRIndex": "0x1a6,0x1a7",
1065        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
1066        "SampleAfterValue": "100003",
1067        "CounterHTOff": "0,1,2,3"
1068    },
1069    {
1070        "Offcore": "1",
1071        "EventCode": "0xB7, 0xBB",
1072        "UMask": "0x1",
1073        "BriefDescription": "Counts all demand data writes (RFOs)  TBD",
1074        "MSRValue": "0x3F80100002",
1075        "Counter": "0,1,2,3",
1076        "EventName": "OCR.DEMAND_RFO.L3_HIT_S.ANY_SNOOP",
1077        "MSRIndex": "0x1a6,0x1a7",
1078        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
1079        "SampleAfterValue": "100003",
1080        "CounterHTOff": "0,1,2,3"
1081    },
1082    {
1083        "Offcore": "1",
1084        "EventCode": "0xB7, 0xBB",
1085        "UMask": "0x1",
1086        "BriefDescription": "Counts all demand data writes (RFOs)",
1087        "MSRValue": "0x0080200002",
1088        "Counter": "0,1,2,3",
1089        "EventName": "OCR.DEMAND_RFO.L3_HIT_F.SNOOP_NONE",
1090        "MSRIndex": "0x1a6,0x1a7",
1091        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
1092        "SampleAfterValue": "100003",
1093        "CounterHTOff": "0,1,2,3"
1094    },
1095    {
1096        "Offcore": "1",
1097        "EventCode": "0xB7, 0xBB",
1098        "UMask": "0x1",
1099        "BriefDescription": "Counts all demand data writes (RFOs)  TBD",
1100        "MSRValue": "0x0100200002",
1101        "Counter": "0,1,2,3",
1102        "EventName": "OCR.DEMAND_RFO.L3_HIT_F.NO_SNOOP_NEEDED",
1103        "MSRIndex": "0x1a6,0x1a7",
1104        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
1105        "SampleAfterValue": "100003",
1106        "CounterHTOff": "0,1,2,3"
1107    },
1108    {
1109        "Offcore": "1",
1110        "EventCode": "0xB7, 0xBB",
1111        "UMask": "0x1",
1112        "BriefDescription": "Counts all demand data writes (RFOs)",
1113        "MSRValue": "0x0200200002",
1114        "Counter": "0,1,2,3",
1115        "EventName": "OCR.DEMAND_RFO.L3_HIT_F.SNOOP_MISS",
1116        "MSRIndex": "0x1a6,0x1a7",
1117        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
1118        "SampleAfterValue": "100003",
1119        "CounterHTOff": "0,1,2,3"
1120    },
1121    {
1122        "Offcore": "1",
1123        "EventCode": "0xB7, 0xBB",
1124        "UMask": "0x1",
1125        "BriefDescription": "Counts all demand data writes (RFOs)  TBD",
1126        "MSRValue": "0x0400200002",
1127        "Counter": "0,1,2,3",
1128        "EventName": "OCR.DEMAND_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWD",
1129        "MSRIndex": "0x1a6,0x1a7",
1130        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
1131        "SampleAfterValue": "100003",
1132        "CounterHTOff": "0,1,2,3"
1133    },
1134    {
1135        "Offcore": "1",
1136        "EventCode": "0xB7, 0xBB",
1137        "UMask": "0x1",
1138        "BriefDescription": "Counts all demand data writes (RFOs)  TBD",
1139        "MSRValue": "0x0800200002",
1140        "Counter": "0,1,2,3",
1141        "EventName": "OCR.DEMAND_RFO.L3_HIT_F.HIT_OTHER_CORE_FWD",
1142        "MSRIndex": "0x1a6,0x1a7",
1143        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
1144        "SampleAfterValue": "100003",
1145        "CounterHTOff": "0,1,2,3"
1146    },
1147    {
1148        "Offcore": "1",
1149        "EventCode": "0xB7, 0xBB",
1150        "UMask": "0x1",
1151        "BriefDescription": "Counts all demand data writes (RFOs)  TBD",
1152        "MSRValue": "0x1000200002",
1153        "Counter": "0,1,2,3",
1154        "EventName": "OCR.DEMAND_RFO.L3_HIT_F.HITM_OTHER_CORE",
1155        "MSRIndex": "0x1a6,0x1a7",
1156        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
1157        "SampleAfterValue": "100003",
1158        "CounterHTOff": "0,1,2,3"
1159    },
1160    {
1161        "Offcore": "1",
1162        "EventCode": "0xB7, 0xBB",
1163        "UMask": "0x1",
1164        "BriefDescription": "Counts all demand data writes (RFOs)  TBD",
1165        "MSRValue": "0x3F80200002",
1166        "Counter": "0,1,2,3",
1167        "EventName": "OCR.DEMAND_RFO.L3_HIT_F.ANY_SNOOP",
1168        "MSRIndex": "0x1a6,0x1a7",
1169        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
1170        "SampleAfterValue": "100003",
1171        "CounterHTOff": "0,1,2,3"
1172    },
1173    {
1174        "Offcore": "1",
1175        "EventCode": "0xB7, 0xBB",
1176        "UMask": "0x1",
1177        "BriefDescription": "Counts all demand data writes (RFOs) TBD",
1178        "MSRValue": "0x00803C0002",
1179        "Counter": "0,1,2,3",
1180        "EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_NONE",
1181        "MSRIndex": "0x1a6,0x1a7",
1182        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
1183        "SampleAfterValue": "100003",
1184        "CounterHTOff": "0,1,2,3"
1185    },
1186    {
1187        "Offcore": "1",
1188        "EventCode": "0xB7, 0xBB",
1189        "UMask": "0x1",
1190        "BriefDescription": "Counts all demand data writes (RFOs) TBD TBD",
1191        "MSRValue": "0x01003C0002",
1192        "Counter": "0,1,2,3",
1193        "EventName": "OCR.DEMAND_RFO.L3_HIT.NO_SNOOP_NEEDED",
1194        "MSRIndex": "0x1a6,0x1a7",
1195        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
1196        "SampleAfterValue": "100003",
1197        "CounterHTOff": "0,1,2,3"
1198    },
1199    {
1200        "Offcore": "1",
1201        "EventCode": "0xB7, 0xBB",
1202        "UMask": "0x1",
1203        "BriefDescription": "Counts all demand data writes (RFOs) TBD",
1204        "MSRValue": "0x02003C0002",
1205        "Counter": "0,1,2,3",
1206        "EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_MISS",
1207        "MSRIndex": "0x1a6,0x1a7",
1208        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
1209        "SampleAfterValue": "100003",
1210        "CounterHTOff": "0,1,2,3"
1211    },
1212    {
1213        "Offcore": "1",
1214        "EventCode": "0xB7, 0xBB",
1215        "UMask": "0x1",
1216        "BriefDescription": "Counts all demand data writes (RFOs) TBD TBD",
1217        "MSRValue": "0x04003C0002",
1218        "Counter": "0,1,2,3",
1219        "EventName": "OCR.DEMAND_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD",
1220        "MSRIndex": "0x1a6,0x1a7",
1221        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
1222        "SampleAfterValue": "100003",
1223        "CounterHTOff": "0,1,2,3"
1224    },
1225    {
1226        "Offcore": "1",
1227        "EventCode": "0xB7, 0xBB",
1228        "UMask": "0x1",
1229        "BriefDescription": "Counts all demand data writes (RFOs) TBD TBD",
1230        "MSRValue": "0x08003C0002",
1231        "Counter": "0,1,2,3",
1232        "EventName": "OCR.DEMAND_RFO.L3_HIT.HIT_OTHER_CORE_FWD",
1233        "MSRIndex": "0x1a6,0x1a7",
1234        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
1235        "SampleAfterValue": "100003",
1236        "CounterHTOff": "0,1,2,3"
1237    },
1238    {
1239        "Offcore": "1",
1240        "EventCode": "0xB7, 0xBB",
1241        "UMask": "0x1",
1242        "BriefDescription": "Counts all demand data writes (RFOs) TBD TBD",
1243        "MSRValue": "0x10003C0002",
1244        "Counter": "0,1,2,3",
1245        "EventName": "OCR.DEMAND_RFO.L3_HIT.HITM_OTHER_CORE",
1246        "MSRIndex": "0x1a6,0x1a7",
1247        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
1248        "SampleAfterValue": "100003",
1249        "CounterHTOff": "0,1,2,3"
1250    },
1251    {
1252        "Offcore": "1",
1253        "EventCode": "0xB7, 0xBB",
1254        "UMask": "0x1",
1255        "BriefDescription": "Counts all demand data writes (RFOs) TBD TBD",
1256        "MSRValue": "0x3F803C0002",
1257        "Counter": "0,1,2,3",
1258        "EventName": "OCR.DEMAND_RFO.L3_HIT.ANY_SNOOP",
1259        "MSRIndex": "0x1a6,0x1a7",
1260        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
1261        "SampleAfterValue": "100003",
1262        "CounterHTOff": "0,1,2,3"
1263    },
1264    {
1265        "Offcore": "1",
1266        "EventCode": "0xB7, 0xBB",
1267        "UMask": "0x1",
1268        "BriefDescription": "Counts all demand code reads",
1269        "MSRValue": "0x0080020004",
1270        "Counter": "0,1,2,3",
1271        "EventName": "OCR.DEMAND_CODE_RD.SUPPLIER_NONE.SNOOP_NONE",
1272        "MSRIndex": "0x1a6,0x1a7",
1273        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
1274        "SampleAfterValue": "100003",
1275        "CounterHTOff": "0,1,2,3"
1276    },
1277    {
1278        "Offcore": "1",
1279        "EventCode": "0xB7, 0xBB",
1280        "UMask": "0x1",
1281        "BriefDescription": "Counts all demand code reads  TBD",
1282        "MSRValue": "0x0100020004",
1283        "Counter": "0,1,2,3",
1284        "EventName": "OCR.DEMAND_CODE_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED",
1285        "MSRIndex": "0x1a6,0x1a7",
1286        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
1287        "SampleAfterValue": "100003",
1288        "CounterHTOff": "0,1,2,3"
1289    },
1290    {
1291        "Offcore": "1",
1292        "EventCode": "0xB7, 0xBB",
1293        "UMask": "0x1",
1294        "BriefDescription": "Counts all demand code reads",
1295        "MSRValue": "0x0200020004",
1296        "Counter": "0,1,2,3",
1297        "EventName": "OCR.DEMAND_CODE_RD.SUPPLIER_NONE.SNOOP_MISS",
1298        "MSRIndex": "0x1a6,0x1a7",
1299        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
1300        "SampleAfterValue": "100003",
1301        "CounterHTOff": "0,1,2,3"
1302    },
1303    {
1304        "Offcore": "1",
1305        "EventCode": "0xB7, 0xBB",
1306        "UMask": "0x1",
1307        "BriefDescription": "Counts all demand code reads  TBD",
1308        "MSRValue": "0x0400020004",
1309        "Counter": "0,1,2,3",
1310        "EventName": "OCR.DEMAND_CODE_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD",
1311        "MSRIndex": "0x1a6,0x1a7",
1312        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
1313        "SampleAfterValue": "100003",
1314        "CounterHTOff": "0,1,2,3"
1315    },
1316    {
1317        "Offcore": "1",
1318        "EventCode": "0xB7, 0xBB",
1319        "UMask": "0x1",
1320        "BriefDescription": "Counts all demand code reads  TBD",
1321        "MSRValue": "0x0800020004",
1322        "Counter": "0,1,2,3",
1323        "EventName": "OCR.DEMAND_CODE_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD",
1324        "MSRIndex": "0x1a6,0x1a7",
1325        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
1326        "SampleAfterValue": "100003",
1327        "CounterHTOff": "0,1,2,3"
1328    },
1329    {
1330        "Offcore": "1",
1331        "EventCode": "0xB7, 0xBB",
1332        "UMask": "0x1",
1333        "BriefDescription": "Counts all demand code reads  TBD",
1334        "MSRValue": "0x1000020004",
1335        "Counter": "0,1,2,3",
1336        "EventName": "OCR.DEMAND_CODE_RD.SUPPLIER_NONE.HITM_OTHER_CORE",
1337        "MSRIndex": "0x1a6,0x1a7",
1338        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
1339        "SampleAfterValue": "100003",
1340        "CounterHTOff": "0,1,2,3"
1341    },
1342    {
1343        "Offcore": "1",
1344        "EventCode": "0xB7, 0xBB",
1345        "UMask": "0x1",
1346        "BriefDescription": "Counts all demand code reads  TBD",
1347        "MSRValue": "0x3F80020004",
1348        "Counter": "0,1,2,3",
1349        "EventName": "OCR.DEMAND_CODE_RD.SUPPLIER_NONE.ANY_SNOOP",
1350        "MSRIndex": "0x1a6,0x1a7",
1351        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
1352        "SampleAfterValue": "100003",
1353        "CounterHTOff": "0,1,2,3"
1354    },
1355    {
1356        "Offcore": "1",
1357        "EventCode": "0xB7, 0xBB",
1358        "UMask": "0x1",
1359        "BriefDescription": "Counts all demand code reads",
1360        "MSRValue": "0x0080040004",
1361        "Counter": "0,1,2,3",
1362        "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_M.SNOOP_NONE",
1363        "MSRIndex": "0x1a6,0x1a7",
1364        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
1365        "SampleAfterValue": "100003",
1366        "CounterHTOff": "0,1,2,3"
1367    },
1368    {
1369        "Offcore": "1",
1370        "EventCode": "0xB7, 0xBB",
1371        "UMask": "0x1",
1372        "BriefDescription": "Counts all demand code reads  TBD",
1373        "MSRValue": "0x0100040004",
1374        "Counter": "0,1,2,3",
1375        "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_M.NO_SNOOP_NEEDED",
1376        "MSRIndex": "0x1a6,0x1a7",
1377        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
1378        "SampleAfterValue": "100003",
1379        "CounterHTOff": "0,1,2,3"
1380    },
1381    {
1382        "Offcore": "1",
1383        "EventCode": "0xB7, 0xBB",
1384        "UMask": "0x1",
1385        "BriefDescription": "Counts all demand code reads",
1386        "MSRValue": "0x0200040004",
1387        "Counter": "0,1,2,3",
1388        "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_M.SNOOP_MISS",
1389        "MSRIndex": "0x1a6,0x1a7",
1390        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
1391        "SampleAfterValue": "100003",
1392        "CounterHTOff": "0,1,2,3"
1393    },
1394    {
1395        "Offcore": "1",
1396        "EventCode": "0xB7, 0xBB",
1397        "UMask": "0x1",
1398        "BriefDescription": "Counts all demand code reads  TBD",
1399        "MSRValue": "0x0400040004",
1400        "Counter": "0,1,2,3",
1401        "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD",
1402        "MSRIndex": "0x1a6,0x1a7",
1403        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
1404        "SampleAfterValue": "100003",
1405        "CounterHTOff": "0,1,2,3"
1406    },
1407    {
1408        "Offcore": "1",
1409        "EventCode": "0xB7, 0xBB",
1410        "UMask": "0x1",
1411        "BriefDescription": "Counts all demand code reads  TBD",
1412        "MSRValue": "0x0800040004",
1413        "Counter": "0,1,2,3",
1414        "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_M.HIT_OTHER_CORE_FWD",
1415        "MSRIndex": "0x1a6,0x1a7",
1416        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
1417        "SampleAfterValue": "100003",
1418        "CounterHTOff": "0,1,2,3"
1419    },
1420    {
1421        "Offcore": "1",
1422        "EventCode": "0xB7, 0xBB",
1423        "UMask": "0x1",
1424        "BriefDescription": "Counts all demand code reads  TBD",
1425        "MSRValue": "0x1000040004",
1426        "Counter": "0,1,2,3",
1427        "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_M.HITM_OTHER_CORE",
1428        "MSRIndex": "0x1a6,0x1a7",
1429        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
1430        "SampleAfterValue": "100003",
1431        "CounterHTOff": "0,1,2,3"
1432    },
1433    {
1434        "Offcore": "1",
1435        "EventCode": "0xB7, 0xBB",
1436        "UMask": "0x1",
1437        "BriefDescription": "Counts all demand code reads  TBD",
1438        "MSRValue": "0x3F80040004",
1439        "Counter": "0,1,2,3",
1440        "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_M.ANY_SNOOP",
1441        "MSRIndex": "0x1a6,0x1a7",
1442        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
1443        "SampleAfterValue": "100003",
1444        "CounterHTOff": "0,1,2,3"
1445    },
1446    {
1447        "Offcore": "1",
1448        "EventCode": "0xB7, 0xBB",
1449        "UMask": "0x1",
1450        "BriefDescription": "Counts all demand code reads",
1451        "MSRValue": "0x0080080004",
1452        "Counter": "0,1,2,3",
1453        "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_E.SNOOP_NONE",
1454        "MSRIndex": "0x1a6,0x1a7",
1455        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
1456        "SampleAfterValue": "100003",
1457        "CounterHTOff": "0,1,2,3"
1458    },
1459    {
1460        "Offcore": "1",
1461        "EventCode": "0xB7, 0xBB",
1462        "UMask": "0x1",
1463        "BriefDescription": "Counts all demand code reads  TBD",
1464        "MSRValue": "0x0100080004",
1465        "Counter": "0,1,2,3",
1466        "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_E.NO_SNOOP_NEEDED",
1467        "MSRIndex": "0x1a6,0x1a7",
1468        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
1469        "SampleAfterValue": "100003",
1470        "CounterHTOff": "0,1,2,3"
1471    },
1472    {
1473        "Offcore": "1",
1474        "EventCode": "0xB7, 0xBB",
1475        "UMask": "0x1",
1476        "BriefDescription": "Counts all demand code reads",
1477        "MSRValue": "0x0200080004",
1478        "Counter": "0,1,2,3",
1479        "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_E.SNOOP_MISS",
1480        "MSRIndex": "0x1a6,0x1a7",
1481        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
1482        "SampleAfterValue": "100003",
1483        "CounterHTOff": "0,1,2,3"
1484    },
1485    {
1486        "Offcore": "1",
1487        "EventCode": "0xB7, 0xBB",
1488        "UMask": "0x1",
1489        "BriefDescription": "Counts all demand code reads  TBD",
1490        "MSRValue": "0x0400080004",
1491        "Counter": "0,1,2,3",
1492        "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD",
1493        "MSRIndex": "0x1a6,0x1a7",
1494        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
1495        "SampleAfterValue": "100003",
1496        "CounterHTOff": "0,1,2,3"
1497    },
1498    {
1499        "Offcore": "1",
1500        "EventCode": "0xB7, 0xBB",
1501        "UMask": "0x1",
1502        "BriefDescription": "Counts all demand code reads  TBD",
1503        "MSRValue": "0x0800080004",
1504        "Counter": "0,1,2,3",
1505        "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_E.HIT_OTHER_CORE_FWD",
1506        "MSRIndex": "0x1a6,0x1a7",
1507        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
1508        "SampleAfterValue": "100003",
1509        "CounterHTOff": "0,1,2,3"
1510    },
1511    {
1512        "Offcore": "1",
1513        "EventCode": "0xB7, 0xBB",
1514        "UMask": "0x1",
1515        "BriefDescription": "Counts all demand code reads  TBD",
1516        "MSRValue": "0x1000080004",
1517        "Counter": "0,1,2,3",
1518        "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_E.HITM_OTHER_CORE",
1519        "MSRIndex": "0x1a6,0x1a7",
1520        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
1521        "SampleAfterValue": "100003",
1522        "CounterHTOff": "0,1,2,3"
1523    },
1524    {
1525        "Offcore": "1",
1526        "EventCode": "0xB7, 0xBB",
1527        "UMask": "0x1",
1528        "BriefDescription": "Counts all demand code reads  TBD",
1529        "MSRValue": "0x3F80080004",
1530        "Counter": "0,1,2,3",
1531        "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_E.ANY_SNOOP",
1532        "MSRIndex": "0x1a6,0x1a7",
1533        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
1534        "SampleAfterValue": "100003",
1535        "CounterHTOff": "0,1,2,3"
1536    },
1537    {
1538        "Offcore": "1",
1539        "EventCode": "0xB7, 0xBB",
1540        "UMask": "0x1",
1541        "BriefDescription": "Counts all demand code reads",
1542        "MSRValue": "0x0080100004",
1543        "Counter": "0,1,2,3",
1544        "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_S.SNOOP_NONE",
1545        "MSRIndex": "0x1a6,0x1a7",
1546        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
1547        "SampleAfterValue": "100003",
1548        "CounterHTOff": "0,1,2,3"
1549    },
1550    {
1551        "Offcore": "1",
1552        "EventCode": "0xB7, 0xBB",
1553        "UMask": "0x1",
1554        "BriefDescription": "Counts all demand code reads  TBD",
1555        "MSRValue": "0x0100100004",
1556        "Counter": "0,1,2,3",
1557        "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_S.NO_SNOOP_NEEDED",
1558        "MSRIndex": "0x1a6,0x1a7",
1559        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
1560        "SampleAfterValue": "100003",
1561        "CounterHTOff": "0,1,2,3"
1562    },
1563    {
1564        "Offcore": "1",
1565        "EventCode": "0xB7, 0xBB",
1566        "UMask": "0x1",
1567        "BriefDescription": "Counts all demand code reads",
1568        "MSRValue": "0x0200100004",
1569        "Counter": "0,1,2,3",
1570        "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_S.SNOOP_MISS",
1571        "MSRIndex": "0x1a6,0x1a7",
1572        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
1573        "SampleAfterValue": "100003",
1574        "CounterHTOff": "0,1,2,3"
1575    },
1576    {
1577        "Offcore": "1",
1578        "EventCode": "0xB7, 0xBB",
1579        "UMask": "0x1",
1580        "BriefDescription": "Counts all demand code reads  TBD",
1581        "MSRValue": "0x0400100004",
1582        "Counter": "0,1,2,3",
1583        "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD",
1584        "MSRIndex": "0x1a6,0x1a7",
1585        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
1586        "SampleAfterValue": "100003",
1587        "CounterHTOff": "0,1,2,3"
1588    },
1589    {
1590        "Offcore": "1",
1591        "EventCode": "0xB7, 0xBB",
1592        "UMask": "0x1",
1593        "BriefDescription": "Counts all demand code reads  TBD",
1594        "MSRValue": "0x0800100004",
1595        "Counter": "0,1,2,3",
1596        "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_S.HIT_OTHER_CORE_FWD",
1597        "MSRIndex": "0x1a6,0x1a7",
1598        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
1599        "SampleAfterValue": "100003",
1600        "CounterHTOff": "0,1,2,3"
1601    },
1602    {
1603        "Offcore": "1",
1604        "EventCode": "0xB7, 0xBB",
1605        "UMask": "0x1",
1606        "BriefDescription": "Counts all demand code reads  TBD",
1607        "MSRValue": "0x1000100004",
1608        "Counter": "0,1,2,3",
1609        "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_S.HITM_OTHER_CORE",
1610        "MSRIndex": "0x1a6,0x1a7",
1611        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
1612        "SampleAfterValue": "100003",
1613        "CounterHTOff": "0,1,2,3"
1614    },
1615    {
1616        "Offcore": "1",
1617        "EventCode": "0xB7, 0xBB",
1618        "UMask": "0x1",
1619        "BriefDescription": "Counts all demand code reads  TBD",
1620        "MSRValue": "0x3F80100004",
1621        "Counter": "0,1,2,3",
1622        "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_S.ANY_SNOOP",
1623        "MSRIndex": "0x1a6,0x1a7",
1624        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
1625        "SampleAfterValue": "100003",
1626        "CounterHTOff": "0,1,2,3"
1627    },
1628    {
1629        "Offcore": "1",
1630        "EventCode": "0xB7, 0xBB",
1631        "UMask": "0x1",
1632        "BriefDescription": "Counts all demand code reads",
1633        "MSRValue": "0x0080200004",
1634        "Counter": "0,1,2,3",
1635        "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_F.SNOOP_NONE",
1636        "MSRIndex": "0x1a6,0x1a7",
1637        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
1638        "SampleAfterValue": "100003",
1639        "CounterHTOff": "0,1,2,3"
1640    },
1641    {
1642        "Offcore": "1",
1643        "EventCode": "0xB7, 0xBB",
1644        "UMask": "0x1",
1645        "BriefDescription": "Counts all demand code reads  TBD",
1646        "MSRValue": "0x0100200004",
1647        "Counter": "0,1,2,3",
1648        "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_F.NO_SNOOP_NEEDED",
1649        "MSRIndex": "0x1a6,0x1a7",
1650        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
1651        "SampleAfterValue": "100003",
1652        "CounterHTOff": "0,1,2,3"
1653    },
1654    {
1655        "Offcore": "1",
1656        "EventCode": "0xB7, 0xBB",
1657        "UMask": "0x1",
1658        "BriefDescription": "Counts all demand code reads",
1659        "MSRValue": "0x0200200004",
1660        "Counter": "0,1,2,3",
1661        "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_F.SNOOP_MISS",
1662        "MSRIndex": "0x1a6,0x1a7",
1663        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
1664        "SampleAfterValue": "100003",
1665        "CounterHTOff": "0,1,2,3"
1666    },
1667    {
1668        "Offcore": "1",
1669        "EventCode": "0xB7, 0xBB",
1670        "UMask": "0x1",
1671        "BriefDescription": "Counts all demand code reads  TBD",
1672        "MSRValue": "0x0400200004",
1673        "Counter": "0,1,2,3",
1674        "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD",
1675        "MSRIndex": "0x1a6,0x1a7",
1676        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
1677        "SampleAfterValue": "100003",
1678        "CounterHTOff": "0,1,2,3"
1679    },
1680    {
1681        "Offcore": "1",
1682        "EventCode": "0xB7, 0xBB",
1683        "UMask": "0x1",
1684        "BriefDescription": "Counts all demand code reads  TBD",
1685        "MSRValue": "0x0800200004",
1686        "Counter": "0,1,2,3",
1687        "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_F.HIT_OTHER_CORE_FWD",
1688        "MSRIndex": "0x1a6,0x1a7",
1689        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
1690        "SampleAfterValue": "100003",
1691        "CounterHTOff": "0,1,2,3"
1692    },
1693    {
1694        "Offcore": "1",
1695        "EventCode": "0xB7, 0xBB",
1696        "UMask": "0x1",
1697        "BriefDescription": "Counts all demand code reads  TBD",
1698        "MSRValue": "0x1000200004",
1699        "Counter": "0,1,2,3",
1700        "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_F.HITM_OTHER_CORE",
1701        "MSRIndex": "0x1a6,0x1a7",
1702        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
1703        "SampleAfterValue": "100003",
1704        "CounterHTOff": "0,1,2,3"
1705    },
1706    {
1707        "Offcore": "1",
1708        "EventCode": "0xB7, 0xBB",
1709        "UMask": "0x1",
1710        "BriefDescription": "Counts all demand code reads  TBD",
1711        "MSRValue": "0x3F80200004",
1712        "Counter": "0,1,2,3",
1713        "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_F.ANY_SNOOP",
1714        "MSRIndex": "0x1a6,0x1a7",
1715        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
1716        "SampleAfterValue": "100003",
1717        "CounterHTOff": "0,1,2,3"
1718    },
1719    {
1720        "Offcore": "1",
1721        "EventCode": "0xB7, 0xBB",
1722        "UMask": "0x1",
1723        "BriefDescription": "Counts all demand code reads TBD",
1724        "MSRValue": "0x00803C0004",
1725        "Counter": "0,1,2,3",
1726        "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_NONE",
1727        "MSRIndex": "0x1a6,0x1a7",
1728        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
1729        "SampleAfterValue": "100003",
1730        "CounterHTOff": "0,1,2,3"
1731    },
1732    {
1733        "Offcore": "1",
1734        "EventCode": "0xB7, 0xBB",
1735        "UMask": "0x1",
1736        "BriefDescription": "Counts all demand code reads TBD TBD",
1737        "MSRValue": "0x01003C0004",
1738        "Counter": "0,1,2,3",
1739        "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.NO_SNOOP_NEEDED",
1740        "MSRIndex": "0x1a6,0x1a7",
1741        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
1742        "SampleAfterValue": "100003",
1743        "CounterHTOff": "0,1,2,3"
1744    },
1745    {
1746        "Offcore": "1",
1747        "EventCode": "0xB7, 0xBB",
1748        "UMask": "0x1",
1749        "BriefDescription": "Counts all demand code reads TBD",
1750        "MSRValue": "0x02003C0004",
1751        "Counter": "0,1,2,3",
1752        "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_MISS",
1753        "MSRIndex": "0x1a6,0x1a7",
1754        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
1755        "SampleAfterValue": "100003",
1756        "CounterHTOff": "0,1,2,3"
1757    },
1758    {
1759        "Offcore": "1",
1760        "EventCode": "0xB7, 0xBB",
1761        "UMask": "0x1",
1762        "BriefDescription": "Counts all demand code reads TBD TBD",
1763        "MSRValue": "0x04003C0004",
1764        "Counter": "0,1,2,3",
1765        "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD",
1766        "MSRIndex": "0x1a6,0x1a7",
1767        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
1768        "SampleAfterValue": "100003",
1769        "CounterHTOff": "0,1,2,3"
1770    },
1771    {
1772        "Offcore": "1",
1773        "EventCode": "0xB7, 0xBB",
1774        "UMask": "0x1",
1775        "BriefDescription": "Counts all demand code reads TBD TBD",
1776        "MSRValue": "0x08003C0004",
1777        "Counter": "0,1,2,3",
1778        "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.HIT_OTHER_CORE_FWD",
1779        "MSRIndex": "0x1a6,0x1a7",
1780        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
1781        "SampleAfterValue": "100003",
1782        "CounterHTOff": "0,1,2,3"
1783    },
1784    {
1785        "Offcore": "1",
1786        "EventCode": "0xB7, 0xBB",
1787        "UMask": "0x1",
1788        "BriefDescription": "Counts all demand code reads TBD TBD",
1789        "MSRValue": "0x10003C0004",
1790        "Counter": "0,1,2,3",
1791        "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.HITM_OTHER_CORE",
1792        "MSRIndex": "0x1a6,0x1a7",
1793        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
1794        "SampleAfterValue": "100003",
1795        "CounterHTOff": "0,1,2,3"
1796    },
1797    {
1798        "Offcore": "1",
1799        "EventCode": "0xB7, 0xBB",
1800        "UMask": "0x1",
1801        "BriefDescription": "Counts all demand code reads TBD TBD",
1802        "MSRValue": "0x3F803C0004",
1803        "Counter": "0,1,2,3",
1804        "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.ANY_SNOOP",
1805        "MSRIndex": "0x1a6,0x1a7",
1806        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
1807        "SampleAfterValue": "100003",
1808        "CounterHTOff": "0,1,2,3"
1809    },
1810    {
1811        "Offcore": "1",
1812        "EventCode": "0xB7, 0xBB",
1813        "UMask": "0x1",
1814        "BriefDescription": "Counts prefetch (that bring data to L2) data reads",
1815        "MSRValue": "0x0080020010",
1816        "Counter": "0,1,2,3",
1817        "EventName": "OCR.PF_L2_DATA_RD.SUPPLIER_NONE.SNOOP_NONE",
1818        "MSRIndex": "0x1a6,0x1a7",
1819        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
1820        "SampleAfterValue": "100003",
1821        "CounterHTOff": "0,1,2,3"
1822    },
1823    {
1824        "Offcore": "1",
1825        "EventCode": "0xB7, 0xBB",
1826        "UMask": "0x1",
1827        "BriefDescription": "Counts prefetch (that bring data to L2) data reads  TBD",
1828        "MSRValue": "0x0100020010",
1829        "Counter": "0,1,2,3",
1830        "EventName": "OCR.PF_L2_DATA_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED",
1831        "MSRIndex": "0x1a6,0x1a7",
1832        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
1833        "SampleAfterValue": "100003",
1834        "CounterHTOff": "0,1,2,3"
1835    },
1836    {
1837        "Offcore": "1",
1838        "EventCode": "0xB7, 0xBB",
1839        "UMask": "0x1",
1840        "BriefDescription": "Counts prefetch (that bring data to L2) data reads",
1841        "MSRValue": "0x0200020010",
1842        "Counter": "0,1,2,3",
1843        "EventName": "OCR.PF_L2_DATA_RD.SUPPLIER_NONE.SNOOP_MISS",
1844        "MSRIndex": "0x1a6,0x1a7",
1845        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
1846        "SampleAfterValue": "100003",
1847        "CounterHTOff": "0,1,2,3"
1848    },
1849    {
1850        "Offcore": "1",
1851        "EventCode": "0xB7, 0xBB",
1852        "UMask": "0x1",
1853        "BriefDescription": "Counts prefetch (that bring data to L2) data reads  TBD",
1854        "MSRValue": "0x0400020010",
1855        "Counter": "0,1,2,3",
1856        "EventName": "OCR.PF_L2_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD",
1857        "MSRIndex": "0x1a6,0x1a7",
1858        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
1859        "SampleAfterValue": "100003",
1860        "CounterHTOff": "0,1,2,3"
1861    },
1862    {
1863        "Offcore": "1",
1864        "EventCode": "0xB7, 0xBB",
1865        "UMask": "0x1",
1866        "BriefDescription": "Counts prefetch (that bring data to L2) data reads  TBD",
1867        "MSRValue": "0x0800020010",
1868        "Counter": "0,1,2,3",
1869        "EventName": "OCR.PF_L2_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD",
1870        "MSRIndex": "0x1a6,0x1a7",
1871        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
1872        "SampleAfterValue": "100003",
1873        "CounterHTOff": "0,1,2,3"
1874    },
1875    {
1876        "Offcore": "1",
1877        "EventCode": "0xB7, 0xBB",
1878        "UMask": "0x1",
1879        "BriefDescription": "Counts prefetch (that bring data to L2) data reads  TBD",
1880        "MSRValue": "0x1000020010",
1881        "Counter": "0,1,2,3",
1882        "EventName": "OCR.PF_L2_DATA_RD.SUPPLIER_NONE.HITM_OTHER_CORE",
1883        "MSRIndex": "0x1a6,0x1a7",
1884        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
1885        "SampleAfterValue": "100003",
1886        "CounterHTOff": "0,1,2,3"
1887    },
1888    {
1889        "Offcore": "1",
1890        "EventCode": "0xB7, 0xBB",
1891        "UMask": "0x1",
1892        "BriefDescription": "Counts prefetch (that bring data to L2) data reads  TBD",
1893        "MSRValue": "0x3F80020010",
1894        "Counter": "0,1,2,3",
1895        "EventName": "OCR.PF_L2_DATA_RD.SUPPLIER_NONE.ANY_SNOOP",
1896        "MSRIndex": "0x1a6,0x1a7",
1897        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
1898        "SampleAfterValue": "100003",
1899        "CounterHTOff": "0,1,2,3"
1900    },
1901    {
1902        "Offcore": "1",
1903        "EventCode": "0xB7, 0xBB",
1904        "UMask": "0x1",
1905        "BriefDescription": "Counts prefetch (that bring data to L2) data reads",
1906        "MSRValue": "0x0080040010",
1907        "Counter": "0,1,2,3",
1908        "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_M.SNOOP_NONE",
1909        "MSRIndex": "0x1a6,0x1a7",
1910        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
1911        "SampleAfterValue": "100003",
1912        "CounterHTOff": "0,1,2,3"
1913    },
1914    {
1915        "Offcore": "1",
1916        "EventCode": "0xB7, 0xBB",
1917        "UMask": "0x1",
1918        "BriefDescription": "Counts prefetch (that bring data to L2) data reads  TBD",
1919        "MSRValue": "0x0100040010",
1920        "Counter": "0,1,2,3",
1921        "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDED",
1922        "MSRIndex": "0x1a6,0x1a7",
1923        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
1924        "SampleAfterValue": "100003",
1925        "CounterHTOff": "0,1,2,3"
1926    },
1927    {
1928        "Offcore": "1",
1929        "EventCode": "0xB7, 0xBB",
1930        "UMask": "0x1",
1931        "BriefDescription": "Counts prefetch (that bring data to L2) data reads",
1932        "MSRValue": "0x0200040010",
1933        "Counter": "0,1,2,3",
1934        "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_M.SNOOP_MISS",
1935        "MSRIndex": "0x1a6,0x1a7",
1936        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
1937        "SampleAfterValue": "100003",
1938        "CounterHTOff": "0,1,2,3"
1939    },
1940    {
1941        "Offcore": "1",
1942        "EventCode": "0xB7, 0xBB",
1943        "UMask": "0x1",
1944        "BriefDescription": "Counts prefetch (that bring data to L2) data reads  TBD",
1945        "MSRValue": "0x0400040010",
1946        "Counter": "0,1,2,3",
1947        "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD",
1948        "MSRIndex": "0x1a6,0x1a7",
1949        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
1950        "SampleAfterValue": "100003",
1951        "CounterHTOff": "0,1,2,3"
1952    },
1953    {
1954        "Offcore": "1",
1955        "EventCode": "0xB7, 0xBB",
1956        "UMask": "0x1",
1957        "BriefDescription": "Counts prefetch (that bring data to L2) data reads  TBD",
1958        "MSRValue": "0x0800040010",
1959        "Counter": "0,1,2,3",
1960        "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWD",
1961        "MSRIndex": "0x1a6,0x1a7",
1962        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
1963        "SampleAfterValue": "100003",
1964        "CounterHTOff": "0,1,2,3"
1965    },
1966    {
1967        "Offcore": "1",
1968        "EventCode": "0xB7, 0xBB",
1969        "UMask": "0x1",
1970        "BriefDescription": "Counts prefetch (that bring data to L2) data reads  TBD",
1971        "MSRValue": "0x1000040010",
1972        "Counter": "0,1,2,3",
1973        "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_M.HITM_OTHER_CORE",
1974        "MSRIndex": "0x1a6,0x1a7",
1975        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
1976        "SampleAfterValue": "100003",
1977        "CounterHTOff": "0,1,2,3"
1978    },
1979    {
1980        "Offcore": "1",
1981        "EventCode": "0xB7, 0xBB",
1982        "UMask": "0x1",
1983        "BriefDescription": "Counts prefetch (that bring data to L2) data reads  TBD",
1984        "MSRValue": "0x3F80040010",
1985        "Counter": "0,1,2,3",
1986        "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_M.ANY_SNOOP",
1987        "MSRIndex": "0x1a6,0x1a7",
1988        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
1989        "SampleAfterValue": "100003",
1990        "CounterHTOff": "0,1,2,3"
1991    },
1992    {
1993        "Offcore": "1",
1994        "EventCode": "0xB7, 0xBB",
1995        "UMask": "0x1",
1996        "BriefDescription": "Counts prefetch (that bring data to L2) data reads",
1997        "MSRValue": "0x0080080010",
1998        "Counter": "0,1,2,3",
1999        "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_E.SNOOP_NONE",
2000        "MSRIndex": "0x1a6,0x1a7",
2001        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
2002        "SampleAfterValue": "100003",
2003        "CounterHTOff": "0,1,2,3"
2004    },
2005    {
2006        "Offcore": "1",
2007        "EventCode": "0xB7, 0xBB",
2008        "UMask": "0x1",
2009        "BriefDescription": "Counts prefetch (that bring data to L2) data reads  TBD",
2010        "MSRValue": "0x0100080010",
2011        "Counter": "0,1,2,3",
2012        "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDED",
2013        "MSRIndex": "0x1a6,0x1a7",
2014        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
2015        "SampleAfterValue": "100003",
2016        "CounterHTOff": "0,1,2,3"
2017    },
2018    {
2019        "Offcore": "1",
2020        "EventCode": "0xB7, 0xBB",
2021        "UMask": "0x1",
2022        "BriefDescription": "Counts prefetch (that bring data to L2) data reads",
2023        "MSRValue": "0x0200080010",
2024        "Counter": "0,1,2,3",
2025        "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_E.SNOOP_MISS",
2026        "MSRIndex": "0x1a6,0x1a7",
2027        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
2028        "SampleAfterValue": "100003",
2029        "CounterHTOff": "0,1,2,3"
2030    },
2031    {
2032        "Offcore": "1",
2033        "EventCode": "0xB7, 0xBB",
2034        "UMask": "0x1",
2035        "BriefDescription": "Counts prefetch (that bring data to L2) data reads  TBD",
2036        "MSRValue": "0x0400080010",
2037        "Counter": "0,1,2,3",
2038        "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD",
2039        "MSRIndex": "0x1a6,0x1a7",
2040        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
2041        "SampleAfterValue": "100003",
2042        "CounterHTOff": "0,1,2,3"
2043    },
2044    {
2045        "Offcore": "1",
2046        "EventCode": "0xB7, 0xBB",
2047        "UMask": "0x1",
2048        "BriefDescription": "Counts prefetch (that bring data to L2) data reads  TBD",
2049        "MSRValue": "0x0800080010",
2050        "Counter": "0,1,2,3",
2051        "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWD",
2052        "MSRIndex": "0x1a6,0x1a7",
2053        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
2054        "SampleAfterValue": "100003",
2055        "CounterHTOff": "0,1,2,3"
2056    },
2057    {
2058        "Offcore": "1",
2059        "EventCode": "0xB7, 0xBB",
2060        "UMask": "0x1",
2061        "BriefDescription": "Counts prefetch (that bring data to L2) data reads  TBD",
2062        "MSRValue": "0x1000080010",
2063        "Counter": "0,1,2,3",
2064        "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_E.HITM_OTHER_CORE",
2065        "MSRIndex": "0x1a6,0x1a7",
2066        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
2067        "SampleAfterValue": "100003",
2068        "CounterHTOff": "0,1,2,3"
2069    },
2070    {
2071        "Offcore": "1",
2072        "EventCode": "0xB7, 0xBB",
2073        "UMask": "0x1",
2074        "BriefDescription": "Counts prefetch (that bring data to L2) data reads  TBD",
2075        "MSRValue": "0x3F80080010",
2076        "Counter": "0,1,2,3",
2077        "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_E.ANY_SNOOP",
2078        "MSRIndex": "0x1a6,0x1a7",
2079        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
2080        "SampleAfterValue": "100003",
2081        "CounterHTOff": "0,1,2,3"
2082    },
2083    {
2084        "Offcore": "1",
2085        "EventCode": "0xB7, 0xBB",
2086        "UMask": "0x1",
2087        "BriefDescription": "Counts prefetch (that bring data to L2) data reads",
2088        "MSRValue": "0x0080100010",
2089        "Counter": "0,1,2,3",
2090        "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_S.SNOOP_NONE",
2091        "MSRIndex": "0x1a6,0x1a7",
2092        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
2093        "SampleAfterValue": "100003",
2094        "CounterHTOff": "0,1,2,3"
2095    },
2096    {
2097        "Offcore": "1",
2098        "EventCode": "0xB7, 0xBB",
2099        "UMask": "0x1",
2100        "BriefDescription": "Counts prefetch (that bring data to L2) data reads  TBD",
2101        "MSRValue": "0x0100100010",
2102        "Counter": "0,1,2,3",
2103        "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDED",
2104        "MSRIndex": "0x1a6,0x1a7",
2105        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
2106        "SampleAfterValue": "100003",
2107        "CounterHTOff": "0,1,2,3"
2108    },
2109    {
2110        "Offcore": "1",
2111        "EventCode": "0xB7, 0xBB",
2112        "UMask": "0x1",
2113        "BriefDescription": "Counts prefetch (that bring data to L2) data reads",
2114        "MSRValue": "0x0200100010",
2115        "Counter": "0,1,2,3",
2116        "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_S.SNOOP_MISS",
2117        "MSRIndex": "0x1a6,0x1a7",
2118        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
2119        "SampleAfterValue": "100003",
2120        "CounterHTOff": "0,1,2,3"
2121    },
2122    {
2123        "Offcore": "1",
2124        "EventCode": "0xB7, 0xBB",
2125        "UMask": "0x1",
2126        "BriefDescription": "Counts prefetch (that bring data to L2) data reads  TBD",
2127        "MSRValue": "0x0400100010",
2128        "Counter": "0,1,2,3",
2129        "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD",
2130        "MSRIndex": "0x1a6,0x1a7",
2131        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
2132        "SampleAfterValue": "100003",
2133        "CounterHTOff": "0,1,2,3"
2134    },
2135    {
2136        "Offcore": "1",
2137        "EventCode": "0xB7, 0xBB",
2138        "UMask": "0x1",
2139        "BriefDescription": "Counts prefetch (that bring data to L2) data reads  TBD",
2140        "MSRValue": "0x0800100010",
2141        "Counter": "0,1,2,3",
2142        "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWD",
2143        "MSRIndex": "0x1a6,0x1a7",
2144        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
2145        "SampleAfterValue": "100003",
2146        "CounterHTOff": "0,1,2,3"
2147    },
2148    {
2149        "Offcore": "1",
2150        "EventCode": "0xB7, 0xBB",
2151        "UMask": "0x1",
2152        "BriefDescription": "Counts prefetch (that bring data to L2) data reads  TBD",
2153        "MSRValue": "0x1000100010",
2154        "Counter": "0,1,2,3",
2155        "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_S.HITM_OTHER_CORE",
2156        "MSRIndex": "0x1a6,0x1a7",
2157        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
2158        "SampleAfterValue": "100003",
2159        "CounterHTOff": "0,1,2,3"
2160    },
2161    {
2162        "Offcore": "1",
2163        "EventCode": "0xB7, 0xBB",
2164        "UMask": "0x1",
2165        "BriefDescription": "Counts prefetch (that bring data to L2) data reads  TBD",
2166        "MSRValue": "0x3F80100010",
2167        "Counter": "0,1,2,3",
2168        "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_S.ANY_SNOOP",
2169        "MSRIndex": "0x1a6,0x1a7",
2170        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
2171        "SampleAfterValue": "100003",
2172        "CounterHTOff": "0,1,2,3"
2173    },
2174    {
2175        "Offcore": "1",
2176        "EventCode": "0xB7, 0xBB",
2177        "UMask": "0x1",
2178        "BriefDescription": "Counts prefetch (that bring data to L2) data reads",
2179        "MSRValue": "0x0080200010",
2180        "Counter": "0,1,2,3",
2181        "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_F.SNOOP_NONE",
2182        "MSRIndex": "0x1a6,0x1a7",
2183        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
2184        "SampleAfterValue": "100003",
2185        "CounterHTOff": "0,1,2,3"
2186    },
2187    {
2188        "Offcore": "1",
2189        "EventCode": "0xB7, 0xBB",
2190        "UMask": "0x1",
2191        "BriefDescription": "Counts prefetch (that bring data to L2) data reads  TBD",
2192        "MSRValue": "0x0100200010",
2193        "Counter": "0,1,2,3",
2194        "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDED",
2195        "MSRIndex": "0x1a6,0x1a7",
2196        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
2197        "SampleAfterValue": "100003",
2198        "CounterHTOff": "0,1,2,3"
2199    },
2200    {
2201        "Offcore": "1",
2202        "EventCode": "0xB7, 0xBB",
2203        "UMask": "0x1",
2204        "BriefDescription": "Counts prefetch (that bring data to L2) data reads",
2205        "MSRValue": "0x0200200010",
2206        "Counter": "0,1,2,3",
2207        "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_F.SNOOP_MISS",
2208        "MSRIndex": "0x1a6,0x1a7",
2209        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
2210        "SampleAfterValue": "100003",
2211        "CounterHTOff": "0,1,2,3"
2212    },
2213    {
2214        "Offcore": "1",
2215        "EventCode": "0xB7, 0xBB",
2216        "UMask": "0x1",
2217        "BriefDescription": "Counts prefetch (that bring data to L2) data reads  TBD",
2218        "MSRValue": "0x0400200010",
2219        "Counter": "0,1,2,3",
2220        "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD",
2221        "MSRIndex": "0x1a6,0x1a7",
2222        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
2223        "SampleAfterValue": "100003",
2224        "CounterHTOff": "0,1,2,3"
2225    },
2226    {
2227        "Offcore": "1",
2228        "EventCode": "0xB7, 0xBB",
2229        "UMask": "0x1",
2230        "BriefDescription": "Counts prefetch (that bring data to L2) data reads  TBD",
2231        "MSRValue": "0x0800200010",
2232        "Counter": "0,1,2,3",
2233        "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWD",
2234        "MSRIndex": "0x1a6,0x1a7",
2235        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
2236        "SampleAfterValue": "100003",
2237        "CounterHTOff": "0,1,2,3"
2238    },
2239    {
2240        "Offcore": "1",
2241        "EventCode": "0xB7, 0xBB",
2242        "UMask": "0x1",
2243        "BriefDescription": "Counts prefetch (that bring data to L2) data reads  TBD",
2244        "MSRValue": "0x1000200010",
2245        "Counter": "0,1,2,3",
2246        "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_F.HITM_OTHER_CORE",
2247        "MSRIndex": "0x1a6,0x1a7",
2248        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
2249        "SampleAfterValue": "100003",
2250        "CounterHTOff": "0,1,2,3"
2251    },
2252    {
2253        "Offcore": "1",
2254        "EventCode": "0xB7, 0xBB",
2255        "UMask": "0x1",
2256        "BriefDescription": "Counts prefetch (that bring data to L2) data reads  TBD",
2257        "MSRValue": "0x3F80200010",
2258        "Counter": "0,1,2,3",
2259        "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_F.ANY_SNOOP",
2260        "MSRIndex": "0x1a6,0x1a7",
2261        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
2262        "SampleAfterValue": "100003",
2263        "CounterHTOff": "0,1,2,3"
2264    },
2265    {
2266        "Offcore": "1",
2267        "EventCode": "0xB7, 0xBB",
2268        "UMask": "0x1",
2269        "BriefDescription": "Counts prefetch (that bring data to L2) data reads TBD",
2270        "MSRValue": "0x00803C0010",
2271        "Counter": "0,1,2,3",
2272        "EventName": "OCR.PF_L2_DATA_RD.L3_HIT.SNOOP_NONE",
2273        "MSRIndex": "0x1a6,0x1a7",
2274        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
2275        "SampleAfterValue": "100003",
2276        "CounterHTOff": "0,1,2,3"
2277    },
2278    {
2279        "Offcore": "1",
2280        "EventCode": "0xB7, 0xBB",
2281        "UMask": "0x1",
2282        "BriefDescription": "Counts prefetch (that bring data to L2) data reads TBD TBD",
2283        "MSRValue": "0x01003C0010",
2284        "Counter": "0,1,2,3",
2285        "EventName": "OCR.PF_L2_DATA_RD.L3_HIT.NO_SNOOP_NEEDED",
2286        "MSRIndex": "0x1a6,0x1a7",
2287        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
2288        "SampleAfterValue": "100003",
2289        "CounterHTOff": "0,1,2,3"
2290    },
2291    {
2292        "Offcore": "1",
2293        "EventCode": "0xB7, 0xBB",
2294        "UMask": "0x1",
2295        "BriefDescription": "Counts prefetch (that bring data to L2) data reads TBD",
2296        "MSRValue": "0x02003C0010",
2297        "Counter": "0,1,2,3",
2298        "EventName": "OCR.PF_L2_DATA_RD.L3_HIT.SNOOP_MISS",
2299        "MSRIndex": "0x1a6,0x1a7",
2300        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
2301        "SampleAfterValue": "100003",
2302        "CounterHTOff": "0,1,2,3"
2303    },
2304    {
2305        "Offcore": "1",
2306        "EventCode": "0xB7, 0xBB",
2307        "UMask": "0x1",
2308        "BriefDescription": "Counts prefetch (that bring data to L2) data reads TBD TBD",
2309        "MSRValue": "0x04003C0010",
2310        "Counter": "0,1,2,3",
2311        "EventName": "OCR.PF_L2_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD",
2312        "MSRIndex": "0x1a6,0x1a7",
2313        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
2314        "SampleAfterValue": "100003",
2315        "CounterHTOff": "0,1,2,3"
2316    },
2317    {
2318        "Offcore": "1",
2319        "EventCode": "0xB7, 0xBB",
2320        "UMask": "0x1",
2321        "BriefDescription": "Counts prefetch (that bring data to L2) data reads TBD TBD",
2322        "MSRValue": "0x08003C0010",
2323        "Counter": "0,1,2,3",
2324        "EventName": "OCR.PF_L2_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD",
2325        "MSRIndex": "0x1a6,0x1a7",
2326        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
2327        "SampleAfterValue": "100003",
2328        "CounterHTOff": "0,1,2,3"
2329    },
2330    {
2331        "Offcore": "1",
2332        "EventCode": "0xB7, 0xBB",
2333        "UMask": "0x1",
2334        "BriefDescription": "Counts prefetch (that bring data to L2) data reads TBD TBD",
2335        "MSRValue": "0x10003C0010",
2336        "Counter": "0,1,2,3",
2337        "EventName": "OCR.PF_L2_DATA_RD.L3_HIT.HITM_OTHER_CORE",
2338        "MSRIndex": "0x1a6,0x1a7",
2339        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
2340        "SampleAfterValue": "100003",
2341        "CounterHTOff": "0,1,2,3"
2342    },
2343    {
2344        "Offcore": "1",
2345        "EventCode": "0xB7, 0xBB",
2346        "UMask": "0x1",
2347        "BriefDescription": "Counts prefetch (that bring data to L2) data reads TBD TBD",
2348        "MSRValue": "0x3F803C0010",
2349        "Counter": "0,1,2,3",
2350        "EventName": "OCR.PF_L2_DATA_RD.L3_HIT.ANY_SNOOP",
2351        "MSRIndex": "0x1a6,0x1a7",
2352        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
2353        "SampleAfterValue": "100003",
2354        "CounterHTOff": "0,1,2,3"
2355    },
2356    {
2357        "Offcore": "1",
2358        "EventCode": "0xB7, 0xBB",
2359        "UMask": "0x1",
2360        "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs",
2361        "MSRValue": "0x0080020020",
2362        "Counter": "0,1,2,3",
2363        "EventName": "OCR.PF_L2_RFO.SUPPLIER_NONE.SNOOP_NONE",
2364        "MSRIndex": "0x1a6,0x1a7",
2365        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
2366        "SampleAfterValue": "100003",
2367        "CounterHTOff": "0,1,2,3"
2368    },
2369    {
2370        "Offcore": "1",
2371        "EventCode": "0xB7, 0xBB",
2372        "UMask": "0x1",
2373        "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs  TBD",
2374        "MSRValue": "0x0100020020",
2375        "Counter": "0,1,2,3",
2376        "EventName": "OCR.PF_L2_RFO.SUPPLIER_NONE.NO_SNOOP_NEEDED",
2377        "MSRIndex": "0x1a6,0x1a7",
2378        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
2379        "SampleAfterValue": "100003",
2380        "CounterHTOff": "0,1,2,3"
2381    },
2382    {
2383        "Offcore": "1",
2384        "EventCode": "0xB7, 0xBB",
2385        "UMask": "0x1",
2386        "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs",
2387        "MSRValue": "0x0200020020",
2388        "Counter": "0,1,2,3",
2389        "EventName": "OCR.PF_L2_RFO.SUPPLIER_NONE.SNOOP_MISS",
2390        "MSRIndex": "0x1a6,0x1a7",
2391        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
2392        "SampleAfterValue": "100003",
2393        "CounterHTOff": "0,1,2,3"
2394    },
2395    {
2396        "Offcore": "1",
2397        "EventCode": "0xB7, 0xBB",
2398        "UMask": "0x1",
2399        "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs  TBD",
2400        "MSRValue": "0x0400020020",
2401        "Counter": "0,1,2,3",
2402        "EventName": "OCR.PF_L2_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD",
2403        "MSRIndex": "0x1a6,0x1a7",
2404        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
2405        "SampleAfterValue": "100003",
2406        "CounterHTOff": "0,1,2,3"
2407    },
2408    {
2409        "Offcore": "1",
2410        "EventCode": "0xB7, 0xBB",
2411        "UMask": "0x1",
2412        "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs  TBD",
2413        "MSRValue": "0x0800020020",
2414        "Counter": "0,1,2,3",
2415        "EventName": "OCR.PF_L2_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_FWD",
2416        "MSRIndex": "0x1a6,0x1a7",
2417        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
2418        "SampleAfterValue": "100003",
2419        "CounterHTOff": "0,1,2,3"
2420    },
2421    {
2422        "Offcore": "1",
2423        "EventCode": "0xB7, 0xBB",
2424        "UMask": "0x1",
2425        "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs  TBD",
2426        "MSRValue": "0x1000020020",
2427        "Counter": "0,1,2,3",
2428        "EventName": "OCR.PF_L2_RFO.SUPPLIER_NONE.HITM_OTHER_CORE",
2429        "MSRIndex": "0x1a6,0x1a7",
2430        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
2431        "SampleAfterValue": "100003",
2432        "CounterHTOff": "0,1,2,3"
2433    },
2434    {
2435        "Offcore": "1",
2436        "EventCode": "0xB7, 0xBB",
2437        "UMask": "0x1",
2438        "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs  TBD",
2439        "MSRValue": "0x3F80020020",
2440        "Counter": "0,1,2,3",
2441        "EventName": "OCR.PF_L2_RFO.SUPPLIER_NONE.ANY_SNOOP",
2442        "MSRIndex": "0x1a6,0x1a7",
2443        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
2444        "SampleAfterValue": "100003",
2445        "CounterHTOff": "0,1,2,3"
2446    },
2447    {
2448        "Offcore": "1",
2449        "EventCode": "0xB7, 0xBB",
2450        "UMask": "0x1",
2451        "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs",
2452        "MSRValue": "0x0080040020",
2453        "Counter": "0,1,2,3",
2454        "EventName": "OCR.PF_L2_RFO.L3_HIT_M.SNOOP_NONE",
2455        "MSRIndex": "0x1a6,0x1a7",
2456        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
2457        "SampleAfterValue": "100003",
2458        "CounterHTOff": "0,1,2,3"
2459    },
2460    {
2461        "Offcore": "1",
2462        "EventCode": "0xB7, 0xBB",
2463        "UMask": "0x1",
2464        "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs  TBD",
2465        "MSRValue": "0x0100040020",
2466        "Counter": "0,1,2,3",
2467        "EventName": "OCR.PF_L2_RFO.L3_HIT_M.NO_SNOOP_NEEDED",
2468        "MSRIndex": "0x1a6,0x1a7",
2469        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
2470        "SampleAfterValue": "100003",
2471        "CounterHTOff": "0,1,2,3"
2472    },
2473    {
2474        "Offcore": "1",
2475        "EventCode": "0xB7, 0xBB",
2476        "UMask": "0x1",
2477        "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs",
2478        "MSRValue": "0x0200040020",
2479        "Counter": "0,1,2,3",
2480        "EventName": "OCR.PF_L2_RFO.L3_HIT_M.SNOOP_MISS",
2481        "MSRIndex": "0x1a6,0x1a7",
2482        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
2483        "SampleAfterValue": "100003",
2484        "CounterHTOff": "0,1,2,3"
2485    },
2486    {
2487        "Offcore": "1",
2488        "EventCode": "0xB7, 0xBB",
2489        "UMask": "0x1",
2490        "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs  TBD",
2491        "MSRValue": "0x0400040020",
2492        "Counter": "0,1,2,3",
2493        "EventName": "OCR.PF_L2_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWD",
2494        "MSRIndex": "0x1a6,0x1a7",
2495        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
2496        "SampleAfterValue": "100003",
2497        "CounterHTOff": "0,1,2,3"
2498    },
2499    {
2500        "Offcore": "1",
2501        "EventCode": "0xB7, 0xBB",
2502        "UMask": "0x1",
2503        "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs  TBD",
2504        "MSRValue": "0x0800040020",
2505        "Counter": "0,1,2,3",
2506        "EventName": "OCR.PF_L2_RFO.L3_HIT_M.HIT_OTHER_CORE_FWD",
2507        "MSRIndex": "0x1a6,0x1a7",
2508        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
2509        "SampleAfterValue": "100003",
2510        "CounterHTOff": "0,1,2,3"
2511    },
2512    {
2513        "Offcore": "1",
2514        "EventCode": "0xB7, 0xBB",
2515        "UMask": "0x1",
2516        "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs  TBD",
2517        "MSRValue": "0x1000040020",
2518        "Counter": "0,1,2,3",
2519        "EventName": "OCR.PF_L2_RFO.L3_HIT_M.HITM_OTHER_CORE",
2520        "MSRIndex": "0x1a6,0x1a7",
2521        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
2522        "SampleAfterValue": "100003",
2523        "CounterHTOff": "0,1,2,3"
2524    },
2525    {
2526        "Offcore": "1",
2527        "EventCode": "0xB7, 0xBB",
2528        "UMask": "0x1",
2529        "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs  TBD",
2530        "MSRValue": "0x3F80040020",
2531        "Counter": "0,1,2,3",
2532        "EventName": "OCR.PF_L2_RFO.L3_HIT_M.ANY_SNOOP",
2533        "MSRIndex": "0x1a6,0x1a7",
2534        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
2535        "SampleAfterValue": "100003",
2536        "CounterHTOff": "0,1,2,3"
2537    },
2538    {
2539        "Offcore": "1",
2540        "EventCode": "0xB7, 0xBB",
2541        "UMask": "0x1",
2542        "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs",
2543        "MSRValue": "0x0080080020",
2544        "Counter": "0,1,2,3",
2545        "EventName": "OCR.PF_L2_RFO.L3_HIT_E.SNOOP_NONE",
2546        "MSRIndex": "0x1a6,0x1a7",
2547        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
2548        "SampleAfterValue": "100003",
2549        "CounterHTOff": "0,1,2,3"
2550    },
2551    {
2552        "Offcore": "1",
2553        "EventCode": "0xB7, 0xBB",
2554        "UMask": "0x1",
2555        "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs  TBD",
2556        "MSRValue": "0x0100080020",
2557        "Counter": "0,1,2,3",
2558        "EventName": "OCR.PF_L2_RFO.L3_HIT_E.NO_SNOOP_NEEDED",
2559        "MSRIndex": "0x1a6,0x1a7",
2560        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
2561        "SampleAfterValue": "100003",
2562        "CounterHTOff": "0,1,2,3"
2563    },
2564    {
2565        "Offcore": "1",
2566        "EventCode": "0xB7, 0xBB",
2567        "UMask": "0x1",
2568        "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs",
2569        "MSRValue": "0x0200080020",
2570        "Counter": "0,1,2,3",
2571        "EventName": "OCR.PF_L2_RFO.L3_HIT_E.SNOOP_MISS",
2572        "MSRIndex": "0x1a6,0x1a7",
2573        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
2574        "SampleAfterValue": "100003",
2575        "CounterHTOff": "0,1,2,3"
2576    },
2577    {
2578        "Offcore": "1",
2579        "EventCode": "0xB7, 0xBB",
2580        "UMask": "0x1",
2581        "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs  TBD",
2582        "MSRValue": "0x0400080020",
2583        "Counter": "0,1,2,3",
2584        "EventName": "OCR.PF_L2_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWD",
2585        "MSRIndex": "0x1a6,0x1a7",
2586        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
2587        "SampleAfterValue": "100003",
2588        "CounterHTOff": "0,1,2,3"
2589    },
2590    {
2591        "Offcore": "1",
2592        "EventCode": "0xB7, 0xBB",
2593        "UMask": "0x1",
2594        "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs  TBD",
2595        "MSRValue": "0x0800080020",
2596        "Counter": "0,1,2,3",
2597        "EventName": "OCR.PF_L2_RFO.L3_HIT_E.HIT_OTHER_CORE_FWD",
2598        "MSRIndex": "0x1a6,0x1a7",
2599        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
2600        "SampleAfterValue": "100003",
2601        "CounterHTOff": "0,1,2,3"
2602    },
2603    {
2604        "Offcore": "1",
2605        "EventCode": "0xB7, 0xBB",
2606        "UMask": "0x1",
2607        "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs  TBD",
2608        "MSRValue": "0x1000080020",
2609        "Counter": "0,1,2,3",
2610        "EventName": "OCR.PF_L2_RFO.L3_HIT_E.HITM_OTHER_CORE",
2611        "MSRIndex": "0x1a6,0x1a7",
2612        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
2613        "SampleAfterValue": "100003",
2614        "CounterHTOff": "0,1,2,3"
2615    },
2616    {
2617        "Offcore": "1",
2618        "EventCode": "0xB7, 0xBB",
2619        "UMask": "0x1",
2620        "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs  TBD",
2621        "MSRValue": "0x3F80080020",
2622        "Counter": "0,1,2,3",
2623        "EventName": "OCR.PF_L2_RFO.L3_HIT_E.ANY_SNOOP",
2624        "MSRIndex": "0x1a6,0x1a7",
2625        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
2626        "SampleAfterValue": "100003",
2627        "CounterHTOff": "0,1,2,3"
2628    },
2629    {
2630        "Offcore": "1",
2631        "EventCode": "0xB7, 0xBB",
2632        "UMask": "0x1",
2633        "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs",
2634        "MSRValue": "0x0080100020",
2635        "Counter": "0,1,2,3",
2636        "EventName": "OCR.PF_L2_RFO.L3_HIT_S.SNOOP_NONE",
2637        "MSRIndex": "0x1a6,0x1a7",
2638        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
2639        "SampleAfterValue": "100003",
2640        "CounterHTOff": "0,1,2,3"
2641    },
2642    {
2643        "Offcore": "1",
2644        "EventCode": "0xB7, 0xBB",
2645        "UMask": "0x1",
2646        "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs  TBD",
2647        "MSRValue": "0x0100100020",
2648        "Counter": "0,1,2,3",
2649        "EventName": "OCR.PF_L2_RFO.L3_HIT_S.NO_SNOOP_NEEDED",
2650        "MSRIndex": "0x1a6,0x1a7",
2651        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
2652        "SampleAfterValue": "100003",
2653        "CounterHTOff": "0,1,2,3"
2654    },
2655    {
2656        "Offcore": "1",
2657        "EventCode": "0xB7, 0xBB",
2658        "UMask": "0x1",
2659        "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs",
2660        "MSRValue": "0x0200100020",
2661        "Counter": "0,1,2,3",
2662        "EventName": "OCR.PF_L2_RFO.L3_HIT_S.SNOOP_MISS",
2663        "MSRIndex": "0x1a6,0x1a7",
2664        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
2665        "SampleAfterValue": "100003",
2666        "CounterHTOff": "0,1,2,3"
2667    },
2668    {
2669        "Offcore": "1",
2670        "EventCode": "0xB7, 0xBB",
2671        "UMask": "0x1",
2672        "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs  TBD",
2673        "MSRValue": "0x0400100020",
2674        "Counter": "0,1,2,3",
2675        "EventName": "OCR.PF_L2_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWD",
2676        "MSRIndex": "0x1a6,0x1a7",
2677        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
2678        "SampleAfterValue": "100003",
2679        "CounterHTOff": "0,1,2,3"
2680    },
2681    {
2682        "Offcore": "1",
2683        "EventCode": "0xB7, 0xBB",
2684        "UMask": "0x1",
2685        "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs  TBD",
2686        "MSRValue": "0x0800100020",
2687        "Counter": "0,1,2,3",
2688        "EventName": "OCR.PF_L2_RFO.L3_HIT_S.HIT_OTHER_CORE_FWD",
2689        "MSRIndex": "0x1a6,0x1a7",
2690        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
2691        "SampleAfterValue": "100003",
2692        "CounterHTOff": "0,1,2,3"
2693    },
2694    {
2695        "Offcore": "1",
2696        "EventCode": "0xB7, 0xBB",
2697        "UMask": "0x1",
2698        "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs  TBD",
2699        "MSRValue": "0x1000100020",
2700        "Counter": "0,1,2,3",
2701        "EventName": "OCR.PF_L2_RFO.L3_HIT_S.HITM_OTHER_CORE",
2702        "MSRIndex": "0x1a6,0x1a7",
2703        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
2704        "SampleAfterValue": "100003",
2705        "CounterHTOff": "0,1,2,3"
2706    },
2707    {
2708        "Offcore": "1",
2709        "EventCode": "0xB7, 0xBB",
2710        "UMask": "0x1",
2711        "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs  TBD",
2712        "MSRValue": "0x3F80100020",
2713        "Counter": "0,1,2,3",
2714        "EventName": "OCR.PF_L2_RFO.L3_HIT_S.ANY_SNOOP",
2715        "MSRIndex": "0x1a6,0x1a7",
2716        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
2717        "SampleAfterValue": "100003",
2718        "CounterHTOff": "0,1,2,3"
2719    },
2720    {
2721        "Offcore": "1",
2722        "EventCode": "0xB7, 0xBB",
2723        "UMask": "0x1",
2724        "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs",
2725        "MSRValue": "0x0080200020",
2726        "Counter": "0,1,2,3",
2727        "EventName": "OCR.PF_L2_RFO.L3_HIT_F.SNOOP_NONE",
2728        "MSRIndex": "0x1a6,0x1a7",
2729        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
2730        "SampleAfterValue": "100003",
2731        "CounterHTOff": "0,1,2,3"
2732    },
2733    {
2734        "Offcore": "1",
2735        "EventCode": "0xB7, 0xBB",
2736        "UMask": "0x1",
2737        "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs  TBD",
2738        "MSRValue": "0x0100200020",
2739        "Counter": "0,1,2,3",
2740        "EventName": "OCR.PF_L2_RFO.L3_HIT_F.NO_SNOOP_NEEDED",
2741        "MSRIndex": "0x1a6,0x1a7",
2742        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
2743        "SampleAfterValue": "100003",
2744        "CounterHTOff": "0,1,2,3"
2745    },
2746    {
2747        "Offcore": "1",
2748        "EventCode": "0xB7, 0xBB",
2749        "UMask": "0x1",
2750        "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs",
2751        "MSRValue": "0x0200200020",
2752        "Counter": "0,1,2,3",
2753        "EventName": "OCR.PF_L2_RFO.L3_HIT_F.SNOOP_MISS",
2754        "MSRIndex": "0x1a6,0x1a7",
2755        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
2756        "SampleAfterValue": "100003",
2757        "CounterHTOff": "0,1,2,3"
2758    },
2759    {
2760        "Offcore": "1",
2761        "EventCode": "0xB7, 0xBB",
2762        "UMask": "0x1",
2763        "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs  TBD",
2764        "MSRValue": "0x0400200020",
2765        "Counter": "0,1,2,3",
2766        "EventName": "OCR.PF_L2_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWD",
2767        "MSRIndex": "0x1a6,0x1a7",
2768        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
2769        "SampleAfterValue": "100003",
2770        "CounterHTOff": "0,1,2,3"
2771    },
2772    {
2773        "Offcore": "1",
2774        "EventCode": "0xB7, 0xBB",
2775        "UMask": "0x1",
2776        "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs  TBD",
2777        "MSRValue": "0x0800200020",
2778        "Counter": "0,1,2,3",
2779        "EventName": "OCR.PF_L2_RFO.L3_HIT_F.HIT_OTHER_CORE_FWD",
2780        "MSRIndex": "0x1a6,0x1a7",
2781        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
2782        "SampleAfterValue": "100003",
2783        "CounterHTOff": "0,1,2,3"
2784    },
2785    {
2786        "Offcore": "1",
2787        "EventCode": "0xB7, 0xBB",
2788        "UMask": "0x1",
2789        "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs  TBD",
2790        "MSRValue": "0x1000200020",
2791        "Counter": "0,1,2,3",
2792        "EventName": "OCR.PF_L2_RFO.L3_HIT_F.HITM_OTHER_CORE",
2793        "MSRIndex": "0x1a6,0x1a7",
2794        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
2795        "SampleAfterValue": "100003",
2796        "CounterHTOff": "0,1,2,3"
2797    },
2798    {
2799        "Offcore": "1",
2800        "EventCode": "0xB7, 0xBB",
2801        "UMask": "0x1",
2802        "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs  TBD",
2803        "MSRValue": "0x3F80200020",
2804        "Counter": "0,1,2,3",
2805        "EventName": "OCR.PF_L2_RFO.L3_HIT_F.ANY_SNOOP",
2806        "MSRIndex": "0x1a6,0x1a7",
2807        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
2808        "SampleAfterValue": "100003",
2809        "CounterHTOff": "0,1,2,3"
2810    },
2811    {
2812        "Offcore": "1",
2813        "EventCode": "0xB7, 0xBB",
2814        "UMask": "0x1",
2815        "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs TBD",
2816        "MSRValue": "0x00803C0020",
2817        "Counter": "0,1,2,3",
2818        "EventName": "OCR.PF_L2_RFO.L3_HIT.SNOOP_NONE",
2819        "MSRIndex": "0x1a6,0x1a7",
2820        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
2821        "SampleAfterValue": "100003",
2822        "CounterHTOff": "0,1,2,3"
2823    },
2824    {
2825        "Offcore": "1",
2826        "EventCode": "0xB7, 0xBB",
2827        "UMask": "0x1",
2828        "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs TBD TBD",
2829        "MSRValue": "0x01003C0020",
2830        "Counter": "0,1,2,3",
2831        "EventName": "OCR.PF_L2_RFO.L3_HIT.NO_SNOOP_NEEDED",
2832        "MSRIndex": "0x1a6,0x1a7",
2833        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
2834        "SampleAfterValue": "100003",
2835        "CounterHTOff": "0,1,2,3"
2836    },
2837    {
2838        "Offcore": "1",
2839        "EventCode": "0xB7, 0xBB",
2840        "UMask": "0x1",
2841        "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs TBD",
2842        "MSRValue": "0x02003C0020",
2843        "Counter": "0,1,2,3",
2844        "EventName": "OCR.PF_L2_RFO.L3_HIT.SNOOP_MISS",
2845        "MSRIndex": "0x1a6,0x1a7",
2846        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
2847        "SampleAfterValue": "100003",
2848        "CounterHTOff": "0,1,2,3"
2849    },
2850    {
2851        "Offcore": "1",
2852        "EventCode": "0xB7, 0xBB",
2853        "UMask": "0x1",
2854        "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs TBD TBD",
2855        "MSRValue": "0x04003C0020",
2856        "Counter": "0,1,2,3",
2857        "EventName": "OCR.PF_L2_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD",
2858        "MSRIndex": "0x1a6,0x1a7",
2859        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
2860        "SampleAfterValue": "100003",
2861        "CounterHTOff": "0,1,2,3"
2862    },
2863    {
2864        "Offcore": "1",
2865        "EventCode": "0xB7, 0xBB",
2866        "UMask": "0x1",
2867        "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs TBD TBD",
2868        "MSRValue": "0x08003C0020",
2869        "Counter": "0,1,2,3",
2870        "EventName": "OCR.PF_L2_RFO.L3_HIT.HIT_OTHER_CORE_FWD",
2871        "MSRIndex": "0x1a6,0x1a7",
2872        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
2873        "SampleAfterValue": "100003",
2874        "CounterHTOff": "0,1,2,3"
2875    },
2876    {
2877        "Offcore": "1",
2878        "EventCode": "0xB7, 0xBB",
2879        "UMask": "0x1",
2880        "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs TBD TBD",
2881        "MSRValue": "0x10003C0020",
2882        "Counter": "0,1,2,3",
2883        "EventName": "OCR.PF_L2_RFO.L3_HIT.HITM_OTHER_CORE",
2884        "MSRIndex": "0x1a6,0x1a7",
2885        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
2886        "SampleAfterValue": "100003",
2887        "CounterHTOff": "0,1,2,3"
2888    },
2889    {
2890        "Offcore": "1",
2891        "EventCode": "0xB7, 0xBB",
2892        "UMask": "0x1",
2893        "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs TBD TBD",
2894        "MSRValue": "0x3F803C0020",
2895        "Counter": "0,1,2,3",
2896        "EventName": "OCR.PF_L2_RFO.L3_HIT.ANY_SNOOP",
2897        "MSRIndex": "0x1a6,0x1a7",
2898        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
2899        "SampleAfterValue": "100003",
2900        "CounterHTOff": "0,1,2,3"
2901    },
2902    {
2903        "Offcore": "1",
2904        "EventCode": "0xB7, 0xBB",
2905        "UMask": "0x1",
2906        "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads",
2907        "MSRValue": "0x0080020080",
2908        "Counter": "0,1,2,3",
2909        "EventName": "OCR.PF_L3_DATA_RD.SUPPLIER_NONE.SNOOP_NONE",
2910        "MSRIndex": "0x1a6,0x1a7",
2911        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
2912        "SampleAfterValue": "100003",
2913        "CounterHTOff": "0,1,2,3"
2914    },
2915    {
2916        "Offcore": "1",
2917        "EventCode": "0xB7, 0xBB",
2918        "UMask": "0x1",
2919        "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads  TBD",
2920        "MSRValue": "0x0100020080",
2921        "Counter": "0,1,2,3",
2922        "EventName": "OCR.PF_L3_DATA_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED",
2923        "MSRIndex": "0x1a6,0x1a7",
2924        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
2925        "SampleAfterValue": "100003",
2926        "CounterHTOff": "0,1,2,3"
2927    },
2928    {
2929        "Offcore": "1",
2930        "EventCode": "0xB7, 0xBB",
2931        "UMask": "0x1",
2932        "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads",
2933        "MSRValue": "0x0200020080",
2934        "Counter": "0,1,2,3",
2935        "EventName": "OCR.PF_L3_DATA_RD.SUPPLIER_NONE.SNOOP_MISS",
2936        "MSRIndex": "0x1a6,0x1a7",
2937        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
2938        "SampleAfterValue": "100003",
2939        "CounterHTOff": "0,1,2,3"
2940    },
2941    {
2942        "Offcore": "1",
2943        "EventCode": "0xB7, 0xBB",
2944        "UMask": "0x1",
2945        "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads  TBD",
2946        "MSRValue": "0x0400020080",
2947        "Counter": "0,1,2,3",
2948        "EventName": "OCR.PF_L3_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD",
2949        "MSRIndex": "0x1a6,0x1a7",
2950        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
2951        "SampleAfterValue": "100003",
2952        "CounterHTOff": "0,1,2,3"
2953    },
2954    {
2955        "Offcore": "1",
2956        "EventCode": "0xB7, 0xBB",
2957        "UMask": "0x1",
2958        "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads  TBD",
2959        "MSRValue": "0x0800020080",
2960        "Counter": "0,1,2,3",
2961        "EventName": "OCR.PF_L3_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD",
2962        "MSRIndex": "0x1a6,0x1a7",
2963        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
2964        "SampleAfterValue": "100003",
2965        "CounterHTOff": "0,1,2,3"
2966    },
2967    {
2968        "Offcore": "1",
2969        "EventCode": "0xB7, 0xBB",
2970        "UMask": "0x1",
2971        "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads  TBD",
2972        "MSRValue": "0x1000020080",
2973        "Counter": "0,1,2,3",
2974        "EventName": "OCR.PF_L3_DATA_RD.SUPPLIER_NONE.HITM_OTHER_CORE",
2975        "MSRIndex": "0x1a6,0x1a7",
2976        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
2977        "SampleAfterValue": "100003",
2978        "CounterHTOff": "0,1,2,3"
2979    },
2980    {
2981        "Offcore": "1",
2982        "EventCode": "0xB7, 0xBB",
2983        "UMask": "0x1",
2984        "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads  TBD",
2985        "MSRValue": "0x3F80020080",
2986        "Counter": "0,1,2,3",
2987        "EventName": "OCR.PF_L3_DATA_RD.SUPPLIER_NONE.ANY_SNOOP",
2988        "MSRIndex": "0x1a6,0x1a7",
2989        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
2990        "SampleAfterValue": "100003",
2991        "CounterHTOff": "0,1,2,3"
2992    },
2993    {
2994        "Offcore": "1",
2995        "EventCode": "0xB7, 0xBB",
2996        "UMask": "0x1",
2997        "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads",
2998        "MSRValue": "0x0080040080",
2999        "Counter": "0,1,2,3",
3000        "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_M.SNOOP_NONE",
3001        "MSRIndex": "0x1a6,0x1a7",
3002        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
3003        "SampleAfterValue": "100003",
3004        "CounterHTOff": "0,1,2,3"
3005    },
3006    {
3007        "Offcore": "1",
3008        "EventCode": "0xB7, 0xBB",
3009        "UMask": "0x1",
3010        "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads  TBD",
3011        "MSRValue": "0x0100040080",
3012        "Counter": "0,1,2,3",
3013        "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDED",
3014        "MSRIndex": "0x1a6,0x1a7",
3015        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
3016        "SampleAfterValue": "100003",
3017        "CounterHTOff": "0,1,2,3"
3018    },
3019    {
3020        "Offcore": "1",
3021        "EventCode": "0xB7, 0xBB",
3022        "UMask": "0x1",
3023        "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads",
3024        "MSRValue": "0x0200040080",
3025        "Counter": "0,1,2,3",
3026        "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_M.SNOOP_MISS",
3027        "MSRIndex": "0x1a6,0x1a7",
3028        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
3029        "SampleAfterValue": "100003",
3030        "CounterHTOff": "0,1,2,3"
3031    },
3032    {
3033        "Offcore": "1",
3034        "EventCode": "0xB7, 0xBB",
3035        "UMask": "0x1",
3036        "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads  TBD",
3037        "MSRValue": "0x0400040080",
3038        "Counter": "0,1,2,3",
3039        "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD",
3040        "MSRIndex": "0x1a6,0x1a7",
3041        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
3042        "SampleAfterValue": "100003",
3043        "CounterHTOff": "0,1,2,3"
3044    },
3045    {
3046        "Offcore": "1",
3047        "EventCode": "0xB7, 0xBB",
3048        "UMask": "0x1",
3049        "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads  TBD",
3050        "MSRValue": "0x0800040080",
3051        "Counter": "0,1,2,3",
3052        "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWD",
3053        "MSRIndex": "0x1a6,0x1a7",
3054        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
3055        "SampleAfterValue": "100003",
3056        "CounterHTOff": "0,1,2,3"
3057    },
3058    {
3059        "Offcore": "1",
3060        "EventCode": "0xB7, 0xBB",
3061        "UMask": "0x1",
3062        "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads  TBD",
3063        "MSRValue": "0x1000040080",
3064        "Counter": "0,1,2,3",
3065        "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_M.HITM_OTHER_CORE",
3066        "MSRIndex": "0x1a6,0x1a7",
3067        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
3068        "SampleAfterValue": "100003",
3069        "CounterHTOff": "0,1,2,3"
3070    },
3071    {
3072        "Offcore": "1",
3073        "EventCode": "0xB7, 0xBB",
3074        "UMask": "0x1",
3075        "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads  TBD",
3076        "MSRValue": "0x3F80040080",
3077        "Counter": "0,1,2,3",
3078        "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_M.ANY_SNOOP",
3079        "MSRIndex": "0x1a6,0x1a7",
3080        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
3081        "SampleAfterValue": "100003",
3082        "CounterHTOff": "0,1,2,3"
3083    },
3084    {
3085        "Offcore": "1",
3086        "EventCode": "0xB7, 0xBB",
3087        "UMask": "0x1",
3088        "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads",
3089        "MSRValue": "0x0080080080",
3090        "Counter": "0,1,2,3",
3091        "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_E.SNOOP_NONE",
3092        "MSRIndex": "0x1a6,0x1a7",
3093        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
3094        "SampleAfterValue": "100003",
3095        "CounterHTOff": "0,1,2,3"
3096    },
3097    {
3098        "Offcore": "1",
3099        "EventCode": "0xB7, 0xBB",
3100        "UMask": "0x1",
3101        "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads  TBD",
3102        "MSRValue": "0x0100080080",
3103        "Counter": "0,1,2,3",
3104        "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDED",
3105        "MSRIndex": "0x1a6,0x1a7",
3106        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
3107        "SampleAfterValue": "100003",
3108        "CounterHTOff": "0,1,2,3"
3109    },
3110    {
3111        "Offcore": "1",
3112        "EventCode": "0xB7, 0xBB",
3113        "UMask": "0x1",
3114        "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads",
3115        "MSRValue": "0x0200080080",
3116        "Counter": "0,1,2,3",
3117        "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_E.SNOOP_MISS",
3118        "MSRIndex": "0x1a6,0x1a7",
3119        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
3120        "SampleAfterValue": "100003",
3121        "CounterHTOff": "0,1,2,3"
3122    },
3123    {
3124        "Offcore": "1",
3125        "EventCode": "0xB7, 0xBB",
3126        "UMask": "0x1",
3127        "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads  TBD",
3128        "MSRValue": "0x0400080080",
3129        "Counter": "0,1,2,3",
3130        "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD",
3131        "MSRIndex": "0x1a6,0x1a7",
3132        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
3133        "SampleAfterValue": "100003",
3134        "CounterHTOff": "0,1,2,3"
3135    },
3136    {
3137        "Offcore": "1",
3138        "EventCode": "0xB7, 0xBB",
3139        "UMask": "0x1",
3140        "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads  TBD",
3141        "MSRValue": "0x0800080080",
3142        "Counter": "0,1,2,3",
3143        "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWD",
3144        "MSRIndex": "0x1a6,0x1a7",
3145        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
3146        "SampleAfterValue": "100003",
3147        "CounterHTOff": "0,1,2,3"
3148    },
3149    {
3150        "Offcore": "1",
3151        "EventCode": "0xB7, 0xBB",
3152        "UMask": "0x1",
3153        "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads  TBD",
3154        "MSRValue": "0x1000080080",
3155        "Counter": "0,1,2,3",
3156        "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_E.HITM_OTHER_CORE",
3157        "MSRIndex": "0x1a6,0x1a7",
3158        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
3159        "SampleAfterValue": "100003",
3160        "CounterHTOff": "0,1,2,3"
3161    },
3162    {
3163        "Offcore": "1",
3164        "EventCode": "0xB7, 0xBB",
3165        "UMask": "0x1",
3166        "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads  TBD",
3167        "MSRValue": "0x3F80080080",
3168        "Counter": "0,1,2,3",
3169        "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_E.ANY_SNOOP",
3170        "MSRIndex": "0x1a6,0x1a7",
3171        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
3172        "SampleAfterValue": "100003",
3173        "CounterHTOff": "0,1,2,3"
3174    },
3175    {
3176        "Offcore": "1",
3177        "EventCode": "0xB7, 0xBB",
3178        "UMask": "0x1",
3179        "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads",
3180        "MSRValue": "0x0080100080",
3181        "Counter": "0,1,2,3",
3182        "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_S.SNOOP_NONE",
3183        "MSRIndex": "0x1a6,0x1a7",
3184        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
3185        "SampleAfterValue": "100003",
3186        "CounterHTOff": "0,1,2,3"
3187    },
3188    {
3189        "Offcore": "1",
3190        "EventCode": "0xB7, 0xBB",
3191        "UMask": "0x1",
3192        "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads  TBD",
3193        "MSRValue": "0x0100100080",
3194        "Counter": "0,1,2,3",
3195        "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDED",
3196        "MSRIndex": "0x1a6,0x1a7",
3197        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
3198        "SampleAfterValue": "100003",
3199        "CounterHTOff": "0,1,2,3"
3200    },
3201    {
3202        "Offcore": "1",
3203        "EventCode": "0xB7, 0xBB",
3204        "UMask": "0x1",
3205        "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads",
3206        "MSRValue": "0x0200100080",
3207        "Counter": "0,1,2,3",
3208        "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_S.SNOOP_MISS",
3209        "MSRIndex": "0x1a6,0x1a7",
3210        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
3211        "SampleAfterValue": "100003",
3212        "CounterHTOff": "0,1,2,3"
3213    },
3214    {
3215        "Offcore": "1",
3216        "EventCode": "0xB7, 0xBB",
3217        "UMask": "0x1",
3218        "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads  TBD",
3219        "MSRValue": "0x0400100080",
3220        "Counter": "0,1,2,3",
3221        "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD",
3222        "MSRIndex": "0x1a6,0x1a7",
3223        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
3224        "SampleAfterValue": "100003",
3225        "CounterHTOff": "0,1,2,3"
3226    },
3227    {
3228        "Offcore": "1",
3229        "EventCode": "0xB7, 0xBB",
3230        "UMask": "0x1",
3231        "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads  TBD",
3232        "MSRValue": "0x0800100080",
3233        "Counter": "0,1,2,3",
3234        "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWD",
3235        "MSRIndex": "0x1a6,0x1a7",
3236        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
3237        "SampleAfterValue": "100003",
3238        "CounterHTOff": "0,1,2,3"
3239    },
3240    {
3241        "Offcore": "1",
3242        "EventCode": "0xB7, 0xBB",
3243        "UMask": "0x1",
3244        "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads  TBD",
3245        "MSRValue": "0x1000100080",
3246        "Counter": "0,1,2,3",
3247        "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_S.HITM_OTHER_CORE",
3248        "MSRIndex": "0x1a6,0x1a7",
3249        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
3250        "SampleAfterValue": "100003",
3251        "CounterHTOff": "0,1,2,3"
3252    },
3253    {
3254        "Offcore": "1",
3255        "EventCode": "0xB7, 0xBB",
3256        "UMask": "0x1",
3257        "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads  TBD",
3258        "MSRValue": "0x3F80100080",
3259        "Counter": "0,1,2,3",
3260        "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_S.ANY_SNOOP",
3261        "MSRIndex": "0x1a6,0x1a7",
3262        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
3263        "SampleAfterValue": "100003",
3264        "CounterHTOff": "0,1,2,3"
3265    },
3266    {
3267        "Offcore": "1",
3268        "EventCode": "0xB7, 0xBB",
3269        "UMask": "0x1",
3270        "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads",
3271        "MSRValue": "0x0080200080",
3272        "Counter": "0,1,2,3",
3273        "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_F.SNOOP_NONE",
3274        "MSRIndex": "0x1a6,0x1a7",
3275        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
3276        "SampleAfterValue": "100003",
3277        "CounterHTOff": "0,1,2,3"
3278    },
3279    {
3280        "Offcore": "1",
3281        "EventCode": "0xB7, 0xBB",
3282        "UMask": "0x1",
3283        "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads  TBD",
3284        "MSRValue": "0x0100200080",
3285        "Counter": "0,1,2,3",
3286        "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDED",
3287        "MSRIndex": "0x1a6,0x1a7",
3288        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
3289        "SampleAfterValue": "100003",
3290        "CounterHTOff": "0,1,2,3"
3291    },
3292    {
3293        "Offcore": "1",
3294        "EventCode": "0xB7, 0xBB",
3295        "UMask": "0x1",
3296        "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads",
3297        "MSRValue": "0x0200200080",
3298        "Counter": "0,1,2,3",
3299        "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_F.SNOOP_MISS",
3300        "MSRIndex": "0x1a6,0x1a7",
3301        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
3302        "SampleAfterValue": "100003",
3303        "CounterHTOff": "0,1,2,3"
3304    },
3305    {
3306        "Offcore": "1",
3307        "EventCode": "0xB7, 0xBB",
3308        "UMask": "0x1",
3309        "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads  TBD",
3310        "MSRValue": "0x0400200080",
3311        "Counter": "0,1,2,3",
3312        "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD",
3313        "MSRIndex": "0x1a6,0x1a7",
3314        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
3315        "SampleAfterValue": "100003",
3316        "CounterHTOff": "0,1,2,3"
3317    },
3318    {
3319        "Offcore": "1",
3320        "EventCode": "0xB7, 0xBB",
3321        "UMask": "0x1",
3322        "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads  TBD",
3323        "MSRValue": "0x0800200080",
3324        "Counter": "0,1,2,3",
3325        "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWD",
3326        "MSRIndex": "0x1a6,0x1a7",
3327        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
3328        "SampleAfterValue": "100003",
3329        "CounterHTOff": "0,1,2,3"
3330    },
3331    {
3332        "Offcore": "1",
3333        "EventCode": "0xB7, 0xBB",
3334        "UMask": "0x1",
3335        "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads  TBD",
3336        "MSRValue": "0x1000200080",
3337        "Counter": "0,1,2,3",
3338        "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_F.HITM_OTHER_CORE",
3339        "MSRIndex": "0x1a6,0x1a7",
3340        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
3341        "SampleAfterValue": "100003",
3342        "CounterHTOff": "0,1,2,3"
3343    },
3344    {
3345        "Offcore": "1",
3346        "EventCode": "0xB7, 0xBB",
3347        "UMask": "0x1",
3348        "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads  TBD",
3349        "MSRValue": "0x3F80200080",
3350        "Counter": "0,1,2,3",
3351        "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_F.ANY_SNOOP",
3352        "MSRIndex": "0x1a6,0x1a7",
3353        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
3354        "SampleAfterValue": "100003",
3355        "CounterHTOff": "0,1,2,3"
3356    },
3357    {
3358        "Offcore": "1",
3359        "EventCode": "0xB7, 0xBB",
3360        "UMask": "0x1",
3361        "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads TBD",
3362        "MSRValue": "0x00803C0080",
3363        "Counter": "0,1,2,3",
3364        "EventName": "OCR.PF_L3_DATA_RD.L3_HIT.SNOOP_NONE",
3365        "MSRIndex": "0x1a6,0x1a7",
3366        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
3367        "SampleAfterValue": "100003",
3368        "CounterHTOff": "0,1,2,3"
3369    },
3370    {
3371        "Offcore": "1",
3372        "EventCode": "0xB7, 0xBB",
3373        "UMask": "0x1",
3374        "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads TBD TBD",
3375        "MSRValue": "0x01003C0080",
3376        "Counter": "0,1,2,3",
3377        "EventName": "OCR.PF_L3_DATA_RD.L3_HIT.NO_SNOOP_NEEDED",
3378        "MSRIndex": "0x1a6,0x1a7",
3379        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
3380        "SampleAfterValue": "100003",
3381        "CounterHTOff": "0,1,2,3"
3382    },
3383    {
3384        "Offcore": "1",
3385        "EventCode": "0xB7, 0xBB",
3386        "UMask": "0x1",
3387        "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads TBD",
3388        "MSRValue": "0x02003C0080",
3389        "Counter": "0,1,2,3",
3390        "EventName": "OCR.PF_L3_DATA_RD.L3_HIT.SNOOP_MISS",
3391        "MSRIndex": "0x1a6,0x1a7",
3392        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
3393        "SampleAfterValue": "100003",
3394        "CounterHTOff": "0,1,2,3"
3395    },
3396    {
3397        "Offcore": "1",
3398        "EventCode": "0xB7, 0xBB",
3399        "UMask": "0x1",
3400        "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads TBD TBD",
3401        "MSRValue": "0x04003C0080",
3402        "Counter": "0,1,2,3",
3403        "EventName": "OCR.PF_L3_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD",
3404        "MSRIndex": "0x1a6,0x1a7",
3405        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
3406        "SampleAfterValue": "100003",
3407        "CounterHTOff": "0,1,2,3"
3408    },
3409    {
3410        "Offcore": "1",
3411        "EventCode": "0xB7, 0xBB",
3412        "UMask": "0x1",
3413        "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads TBD TBD",
3414        "MSRValue": "0x08003C0080",
3415        "Counter": "0,1,2,3",
3416        "EventName": "OCR.PF_L3_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD",
3417        "MSRIndex": "0x1a6,0x1a7",
3418        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
3419        "SampleAfterValue": "100003",
3420        "CounterHTOff": "0,1,2,3"
3421    },
3422    {
3423        "Offcore": "1",
3424        "EventCode": "0xB7, 0xBB",
3425        "UMask": "0x1",
3426        "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads TBD TBD",
3427        "MSRValue": "0x10003C0080",
3428        "Counter": "0,1,2,3",
3429        "EventName": "OCR.PF_L3_DATA_RD.L3_HIT.HITM_OTHER_CORE",
3430        "MSRIndex": "0x1a6,0x1a7",
3431        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
3432        "SampleAfterValue": "100003",
3433        "CounterHTOff": "0,1,2,3"
3434    },
3435    {
3436        "Offcore": "1",
3437        "EventCode": "0xB7, 0xBB",
3438        "UMask": "0x1",
3439        "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads TBD TBD",
3440        "MSRValue": "0x3F803C0080",
3441        "Counter": "0,1,2,3",
3442        "EventName": "OCR.PF_L3_DATA_RD.L3_HIT.ANY_SNOOP",
3443        "MSRIndex": "0x1a6,0x1a7",
3444        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
3445        "SampleAfterValue": "100003",
3446        "CounterHTOff": "0,1,2,3"
3447    },
3448    {
3449        "Offcore": "1",
3450        "EventCode": "0xB7, 0xBB",
3451        "UMask": "0x1",
3452        "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs",
3453        "MSRValue": "0x0080020100",
3454        "Counter": "0,1,2,3",
3455        "EventName": "OCR.PF_L3_RFO.SUPPLIER_NONE.SNOOP_NONE",
3456        "MSRIndex": "0x1a6,0x1a7",
3457        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
3458        "SampleAfterValue": "100003",
3459        "CounterHTOff": "0,1,2,3"
3460    },
3461    {
3462        "Offcore": "1",
3463        "EventCode": "0xB7, 0xBB",
3464        "UMask": "0x1",
3465        "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs  TBD",
3466        "MSRValue": "0x0100020100",
3467        "Counter": "0,1,2,3",
3468        "EventName": "OCR.PF_L3_RFO.SUPPLIER_NONE.NO_SNOOP_NEEDED",
3469        "MSRIndex": "0x1a6,0x1a7",
3470        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
3471        "SampleAfterValue": "100003",
3472        "CounterHTOff": "0,1,2,3"
3473    },
3474    {
3475        "Offcore": "1",
3476        "EventCode": "0xB7, 0xBB",
3477        "UMask": "0x1",
3478        "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs",
3479        "MSRValue": "0x0200020100",
3480        "Counter": "0,1,2,3",
3481        "EventName": "OCR.PF_L3_RFO.SUPPLIER_NONE.SNOOP_MISS",
3482        "MSRIndex": "0x1a6,0x1a7",
3483        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
3484        "SampleAfterValue": "100003",
3485        "CounterHTOff": "0,1,2,3"
3486    },
3487    {
3488        "Offcore": "1",
3489        "EventCode": "0xB7, 0xBB",
3490        "UMask": "0x1",
3491        "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs  TBD",
3492        "MSRValue": "0x0400020100",
3493        "Counter": "0,1,2,3",
3494        "EventName": "OCR.PF_L3_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD",
3495        "MSRIndex": "0x1a6,0x1a7",
3496        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
3497        "SampleAfterValue": "100003",
3498        "CounterHTOff": "0,1,2,3"
3499    },
3500    {
3501        "Offcore": "1",
3502        "EventCode": "0xB7, 0xBB",
3503        "UMask": "0x1",
3504        "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs  TBD",
3505        "MSRValue": "0x0800020100",
3506        "Counter": "0,1,2,3",
3507        "EventName": "OCR.PF_L3_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_FWD",
3508        "MSRIndex": "0x1a6,0x1a7",
3509        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
3510        "SampleAfterValue": "100003",
3511        "CounterHTOff": "0,1,2,3"
3512    },
3513    {
3514        "Offcore": "1",
3515        "EventCode": "0xB7, 0xBB",
3516        "UMask": "0x1",
3517        "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs  TBD",
3518        "MSRValue": "0x1000020100",
3519        "Counter": "0,1,2,3",
3520        "EventName": "OCR.PF_L3_RFO.SUPPLIER_NONE.HITM_OTHER_CORE",
3521        "MSRIndex": "0x1a6,0x1a7",
3522        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
3523        "SampleAfterValue": "100003",
3524        "CounterHTOff": "0,1,2,3"
3525    },
3526    {
3527        "Offcore": "1",
3528        "EventCode": "0xB7, 0xBB",
3529        "UMask": "0x1",
3530        "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs  TBD",
3531        "MSRValue": "0x3F80020100",
3532        "Counter": "0,1,2,3",
3533        "EventName": "OCR.PF_L3_RFO.SUPPLIER_NONE.ANY_SNOOP",
3534        "MSRIndex": "0x1a6,0x1a7",
3535        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
3536        "SampleAfterValue": "100003",
3537        "CounterHTOff": "0,1,2,3"
3538    },
3539    {
3540        "Offcore": "1",
3541        "EventCode": "0xB7, 0xBB",
3542        "UMask": "0x1",
3543        "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs",
3544        "MSRValue": "0x0080040100",
3545        "Counter": "0,1,2,3",
3546        "EventName": "OCR.PF_L3_RFO.L3_HIT_M.SNOOP_NONE",
3547        "MSRIndex": "0x1a6,0x1a7",
3548        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
3549        "SampleAfterValue": "100003",
3550        "CounterHTOff": "0,1,2,3"
3551    },
3552    {
3553        "Offcore": "1",
3554        "EventCode": "0xB7, 0xBB",
3555        "UMask": "0x1",
3556        "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs  TBD",
3557        "MSRValue": "0x0100040100",
3558        "Counter": "0,1,2,3",
3559        "EventName": "OCR.PF_L3_RFO.L3_HIT_M.NO_SNOOP_NEEDED",
3560        "MSRIndex": "0x1a6,0x1a7",
3561        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
3562        "SampleAfterValue": "100003",
3563        "CounterHTOff": "0,1,2,3"
3564    },
3565    {
3566        "Offcore": "1",
3567        "EventCode": "0xB7, 0xBB",
3568        "UMask": "0x1",
3569        "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs",
3570        "MSRValue": "0x0200040100",
3571        "Counter": "0,1,2,3",
3572        "EventName": "OCR.PF_L3_RFO.L3_HIT_M.SNOOP_MISS",
3573        "MSRIndex": "0x1a6,0x1a7",
3574        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
3575        "SampleAfterValue": "100003",
3576        "CounterHTOff": "0,1,2,3"
3577    },
3578    {
3579        "Offcore": "1",
3580        "EventCode": "0xB7, 0xBB",
3581        "UMask": "0x1",
3582        "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs  TBD",
3583        "MSRValue": "0x0400040100",
3584        "Counter": "0,1,2,3",
3585        "EventName": "OCR.PF_L3_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWD",
3586        "MSRIndex": "0x1a6,0x1a7",
3587        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
3588        "SampleAfterValue": "100003",
3589        "CounterHTOff": "0,1,2,3"
3590    },
3591    {
3592        "Offcore": "1",
3593        "EventCode": "0xB7, 0xBB",
3594        "UMask": "0x1",
3595        "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs  TBD",
3596        "MSRValue": "0x0800040100",
3597        "Counter": "0,1,2,3",
3598        "EventName": "OCR.PF_L3_RFO.L3_HIT_M.HIT_OTHER_CORE_FWD",
3599        "MSRIndex": "0x1a6,0x1a7",
3600        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
3601        "SampleAfterValue": "100003",
3602        "CounterHTOff": "0,1,2,3"
3603    },
3604    {
3605        "Offcore": "1",
3606        "EventCode": "0xB7, 0xBB",
3607        "UMask": "0x1",
3608        "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs  TBD",
3609        "MSRValue": "0x1000040100",
3610        "Counter": "0,1,2,3",
3611        "EventName": "OCR.PF_L3_RFO.L3_HIT_M.HITM_OTHER_CORE",
3612        "MSRIndex": "0x1a6,0x1a7",
3613        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
3614        "SampleAfterValue": "100003",
3615        "CounterHTOff": "0,1,2,3"
3616    },
3617    {
3618        "Offcore": "1",
3619        "EventCode": "0xB7, 0xBB",
3620        "UMask": "0x1",
3621        "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs  TBD",
3622        "MSRValue": "0x3F80040100",
3623        "Counter": "0,1,2,3",
3624        "EventName": "OCR.PF_L3_RFO.L3_HIT_M.ANY_SNOOP",
3625        "MSRIndex": "0x1a6,0x1a7",
3626        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
3627        "SampleAfterValue": "100003",
3628        "CounterHTOff": "0,1,2,3"
3629    },
3630    {
3631        "Offcore": "1",
3632        "EventCode": "0xB7, 0xBB",
3633        "UMask": "0x1",
3634        "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs",
3635        "MSRValue": "0x0080080100",
3636        "Counter": "0,1,2,3",
3637        "EventName": "OCR.PF_L3_RFO.L3_HIT_E.SNOOP_NONE",
3638        "MSRIndex": "0x1a6,0x1a7",
3639        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
3640        "SampleAfterValue": "100003",
3641        "CounterHTOff": "0,1,2,3"
3642    },
3643    {
3644        "Offcore": "1",
3645        "EventCode": "0xB7, 0xBB",
3646        "UMask": "0x1",
3647        "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs  TBD",
3648        "MSRValue": "0x0100080100",
3649        "Counter": "0,1,2,3",
3650        "EventName": "OCR.PF_L3_RFO.L3_HIT_E.NO_SNOOP_NEEDED",
3651        "MSRIndex": "0x1a6,0x1a7",
3652        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
3653        "SampleAfterValue": "100003",
3654        "CounterHTOff": "0,1,2,3"
3655    },
3656    {
3657        "Offcore": "1",
3658        "EventCode": "0xB7, 0xBB",
3659        "UMask": "0x1",
3660        "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs",
3661        "MSRValue": "0x0200080100",
3662        "Counter": "0,1,2,3",
3663        "EventName": "OCR.PF_L3_RFO.L3_HIT_E.SNOOP_MISS",
3664        "MSRIndex": "0x1a6,0x1a7",
3665        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
3666        "SampleAfterValue": "100003",
3667        "CounterHTOff": "0,1,2,3"
3668    },
3669    {
3670        "Offcore": "1",
3671        "EventCode": "0xB7, 0xBB",
3672        "UMask": "0x1",
3673        "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs  TBD",
3674        "MSRValue": "0x0400080100",
3675        "Counter": "0,1,2,3",
3676        "EventName": "OCR.PF_L3_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWD",
3677        "MSRIndex": "0x1a6,0x1a7",
3678        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
3679        "SampleAfterValue": "100003",
3680        "CounterHTOff": "0,1,2,3"
3681    },
3682    {
3683        "Offcore": "1",
3684        "EventCode": "0xB7, 0xBB",
3685        "UMask": "0x1",
3686        "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs  TBD",
3687        "MSRValue": "0x0800080100",
3688        "Counter": "0,1,2,3",
3689        "EventName": "OCR.PF_L3_RFO.L3_HIT_E.HIT_OTHER_CORE_FWD",
3690        "MSRIndex": "0x1a6,0x1a7",
3691        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
3692        "SampleAfterValue": "100003",
3693        "CounterHTOff": "0,1,2,3"
3694    },
3695    {
3696        "Offcore": "1",
3697        "EventCode": "0xB7, 0xBB",
3698        "UMask": "0x1",
3699        "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs  TBD",
3700        "MSRValue": "0x1000080100",
3701        "Counter": "0,1,2,3",
3702        "EventName": "OCR.PF_L3_RFO.L3_HIT_E.HITM_OTHER_CORE",
3703        "MSRIndex": "0x1a6,0x1a7",
3704        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
3705        "SampleAfterValue": "100003",
3706        "CounterHTOff": "0,1,2,3"
3707    },
3708    {
3709        "Offcore": "1",
3710        "EventCode": "0xB7, 0xBB",
3711        "UMask": "0x1",
3712        "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs  TBD",
3713        "MSRValue": "0x3F80080100",
3714        "Counter": "0,1,2,3",
3715        "EventName": "OCR.PF_L3_RFO.L3_HIT_E.ANY_SNOOP",
3716        "MSRIndex": "0x1a6,0x1a7",
3717        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
3718        "SampleAfterValue": "100003",
3719        "CounterHTOff": "0,1,2,3"
3720    },
3721    {
3722        "Offcore": "1",
3723        "EventCode": "0xB7, 0xBB",
3724        "UMask": "0x1",
3725        "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs",
3726        "MSRValue": "0x0080100100",
3727        "Counter": "0,1,2,3",
3728        "EventName": "OCR.PF_L3_RFO.L3_HIT_S.SNOOP_NONE",
3729        "MSRIndex": "0x1a6,0x1a7",
3730        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
3731        "SampleAfterValue": "100003",
3732        "CounterHTOff": "0,1,2,3"
3733    },
3734    {
3735        "Offcore": "1",
3736        "EventCode": "0xB7, 0xBB",
3737        "UMask": "0x1",
3738        "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs  TBD",
3739        "MSRValue": "0x0100100100",
3740        "Counter": "0,1,2,3",
3741        "EventName": "OCR.PF_L3_RFO.L3_HIT_S.NO_SNOOP_NEEDED",
3742        "MSRIndex": "0x1a6,0x1a7",
3743        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
3744        "SampleAfterValue": "100003",
3745        "CounterHTOff": "0,1,2,3"
3746    },
3747    {
3748        "Offcore": "1",
3749        "EventCode": "0xB7, 0xBB",
3750        "UMask": "0x1",
3751        "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs",
3752        "MSRValue": "0x0200100100",
3753        "Counter": "0,1,2,3",
3754        "EventName": "OCR.PF_L3_RFO.L3_HIT_S.SNOOP_MISS",
3755        "MSRIndex": "0x1a6,0x1a7",
3756        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
3757        "SampleAfterValue": "100003",
3758        "CounterHTOff": "0,1,2,3"
3759    },
3760    {
3761        "Offcore": "1",
3762        "EventCode": "0xB7, 0xBB",
3763        "UMask": "0x1",
3764        "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs  TBD",
3765        "MSRValue": "0x0400100100",
3766        "Counter": "0,1,2,3",
3767        "EventName": "OCR.PF_L3_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWD",
3768        "MSRIndex": "0x1a6,0x1a7",
3769        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
3770        "SampleAfterValue": "100003",
3771        "CounterHTOff": "0,1,2,3"
3772    },
3773    {
3774        "Offcore": "1",
3775        "EventCode": "0xB7, 0xBB",
3776        "UMask": "0x1",
3777        "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs  TBD",
3778        "MSRValue": "0x0800100100",
3779        "Counter": "0,1,2,3",
3780        "EventName": "OCR.PF_L3_RFO.L3_HIT_S.HIT_OTHER_CORE_FWD",
3781        "MSRIndex": "0x1a6,0x1a7",
3782        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
3783        "SampleAfterValue": "100003",
3784        "CounterHTOff": "0,1,2,3"
3785    },
3786    {
3787        "Offcore": "1",
3788        "EventCode": "0xB7, 0xBB",
3789        "UMask": "0x1",
3790        "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs  TBD",
3791        "MSRValue": "0x1000100100",
3792        "Counter": "0,1,2,3",
3793        "EventName": "OCR.PF_L3_RFO.L3_HIT_S.HITM_OTHER_CORE",
3794        "MSRIndex": "0x1a6,0x1a7",
3795        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
3796        "SampleAfterValue": "100003",
3797        "CounterHTOff": "0,1,2,3"
3798    },
3799    {
3800        "Offcore": "1",
3801        "EventCode": "0xB7, 0xBB",
3802        "UMask": "0x1",
3803        "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs  TBD",
3804        "MSRValue": "0x3F80100100",
3805        "Counter": "0,1,2,3",
3806        "EventName": "OCR.PF_L3_RFO.L3_HIT_S.ANY_SNOOP",
3807        "MSRIndex": "0x1a6,0x1a7",
3808        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
3809        "SampleAfterValue": "100003",
3810        "CounterHTOff": "0,1,2,3"
3811    },
3812    {
3813        "Offcore": "1",
3814        "EventCode": "0xB7, 0xBB",
3815        "UMask": "0x1",
3816        "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs",
3817        "MSRValue": "0x0080200100",
3818        "Counter": "0,1,2,3",
3819        "EventName": "OCR.PF_L3_RFO.L3_HIT_F.SNOOP_NONE",
3820        "MSRIndex": "0x1a6,0x1a7",
3821        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
3822        "SampleAfterValue": "100003",
3823        "CounterHTOff": "0,1,2,3"
3824    },
3825    {
3826        "Offcore": "1",
3827        "EventCode": "0xB7, 0xBB",
3828        "UMask": "0x1",
3829        "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs  TBD",
3830        "MSRValue": "0x0100200100",
3831        "Counter": "0,1,2,3",
3832        "EventName": "OCR.PF_L3_RFO.L3_HIT_F.NO_SNOOP_NEEDED",
3833        "MSRIndex": "0x1a6,0x1a7",
3834        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
3835        "SampleAfterValue": "100003",
3836        "CounterHTOff": "0,1,2,3"
3837    },
3838    {
3839        "Offcore": "1",
3840        "EventCode": "0xB7, 0xBB",
3841        "UMask": "0x1",
3842        "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs",
3843        "MSRValue": "0x0200200100",
3844        "Counter": "0,1,2,3",
3845        "EventName": "OCR.PF_L3_RFO.L3_HIT_F.SNOOP_MISS",
3846        "MSRIndex": "0x1a6,0x1a7",
3847        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
3848        "SampleAfterValue": "100003",
3849        "CounterHTOff": "0,1,2,3"
3850    },
3851    {
3852        "Offcore": "1",
3853        "EventCode": "0xB7, 0xBB",
3854        "UMask": "0x1",
3855        "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs  TBD",
3856        "MSRValue": "0x0400200100",
3857        "Counter": "0,1,2,3",
3858        "EventName": "OCR.PF_L3_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWD",
3859        "MSRIndex": "0x1a6,0x1a7",
3860        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
3861        "SampleAfterValue": "100003",
3862        "CounterHTOff": "0,1,2,3"
3863    },
3864    {
3865        "Offcore": "1",
3866        "EventCode": "0xB7, 0xBB",
3867        "UMask": "0x1",
3868        "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs  TBD",
3869        "MSRValue": "0x0800200100",
3870        "Counter": "0,1,2,3",
3871        "EventName": "OCR.PF_L3_RFO.L3_HIT_F.HIT_OTHER_CORE_FWD",
3872        "MSRIndex": "0x1a6,0x1a7",
3873        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
3874        "SampleAfterValue": "100003",
3875        "CounterHTOff": "0,1,2,3"
3876    },
3877    {
3878        "Offcore": "1",
3879        "EventCode": "0xB7, 0xBB",
3880        "UMask": "0x1",
3881        "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs  TBD",
3882        "MSRValue": "0x1000200100",
3883        "Counter": "0,1,2,3",
3884        "EventName": "OCR.PF_L3_RFO.L3_HIT_F.HITM_OTHER_CORE",
3885        "MSRIndex": "0x1a6,0x1a7",
3886        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
3887        "SampleAfterValue": "100003",
3888        "CounterHTOff": "0,1,2,3"
3889    },
3890    {
3891        "Offcore": "1",
3892        "EventCode": "0xB7, 0xBB",
3893        "UMask": "0x1",
3894        "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs  TBD",
3895        "MSRValue": "0x3F80200100",
3896        "Counter": "0,1,2,3",
3897        "EventName": "OCR.PF_L3_RFO.L3_HIT_F.ANY_SNOOP",
3898        "MSRIndex": "0x1a6,0x1a7",
3899        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
3900        "SampleAfterValue": "100003",
3901        "CounterHTOff": "0,1,2,3"
3902    },
3903    {
3904        "Offcore": "1",
3905        "EventCode": "0xB7, 0xBB",
3906        "UMask": "0x1",
3907        "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs TBD",
3908        "MSRValue": "0x00803C0100",
3909        "Counter": "0,1,2,3",
3910        "EventName": "OCR.PF_L3_RFO.L3_HIT.SNOOP_NONE",
3911        "MSRIndex": "0x1a6,0x1a7",
3912        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
3913        "SampleAfterValue": "100003",
3914        "CounterHTOff": "0,1,2,3"
3915    },
3916    {
3917        "Offcore": "1",
3918        "EventCode": "0xB7, 0xBB",
3919        "UMask": "0x1",
3920        "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs TBD TBD",
3921        "MSRValue": "0x01003C0100",
3922        "Counter": "0,1,2,3",
3923        "EventName": "OCR.PF_L3_RFO.L3_HIT.NO_SNOOP_NEEDED",
3924        "MSRIndex": "0x1a6,0x1a7",
3925        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
3926        "SampleAfterValue": "100003",
3927        "CounterHTOff": "0,1,2,3"
3928    },
3929    {
3930        "Offcore": "1",
3931        "EventCode": "0xB7, 0xBB",
3932        "UMask": "0x1",
3933        "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs TBD",
3934        "MSRValue": "0x02003C0100",
3935        "Counter": "0,1,2,3",
3936        "EventName": "OCR.PF_L3_RFO.L3_HIT.SNOOP_MISS",
3937        "MSRIndex": "0x1a6,0x1a7",
3938        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
3939        "SampleAfterValue": "100003",
3940        "CounterHTOff": "0,1,2,3"
3941    },
3942    {
3943        "Offcore": "1",
3944        "EventCode": "0xB7, 0xBB",
3945        "UMask": "0x1",
3946        "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs TBD TBD",
3947        "MSRValue": "0x04003C0100",
3948        "Counter": "0,1,2,3",
3949        "EventName": "OCR.PF_L3_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD",
3950        "MSRIndex": "0x1a6,0x1a7",
3951        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
3952        "SampleAfterValue": "100003",
3953        "CounterHTOff": "0,1,2,3"
3954    },
3955    {
3956        "Offcore": "1",
3957        "EventCode": "0xB7, 0xBB",
3958        "UMask": "0x1",
3959        "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs TBD TBD",
3960        "MSRValue": "0x08003C0100",
3961        "Counter": "0,1,2,3",
3962        "EventName": "OCR.PF_L3_RFO.L3_HIT.HIT_OTHER_CORE_FWD",
3963        "MSRIndex": "0x1a6,0x1a7",
3964        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
3965        "SampleAfterValue": "100003",
3966        "CounterHTOff": "0,1,2,3"
3967    },
3968    {
3969        "Offcore": "1",
3970        "EventCode": "0xB7, 0xBB",
3971        "UMask": "0x1",
3972        "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs TBD TBD",
3973        "MSRValue": "0x10003C0100",
3974        "Counter": "0,1,2,3",
3975        "EventName": "OCR.PF_L3_RFO.L3_HIT.HITM_OTHER_CORE",
3976        "MSRIndex": "0x1a6,0x1a7",
3977        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
3978        "SampleAfterValue": "100003",
3979        "CounterHTOff": "0,1,2,3"
3980    },
3981    {
3982        "Offcore": "1",
3983        "EventCode": "0xB7, 0xBB",
3984        "UMask": "0x1",
3985        "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs TBD TBD",
3986        "MSRValue": "0x3F803C0100",
3987        "Counter": "0,1,2,3",
3988        "EventName": "OCR.PF_L3_RFO.L3_HIT.ANY_SNOOP",
3989        "MSRIndex": "0x1a6,0x1a7",
3990        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
3991        "SampleAfterValue": "100003",
3992        "CounterHTOff": "0,1,2,3"
3993    },
3994    {
3995        "Offcore": "1",
3996        "EventCode": "0xB7, 0xBB",
3997        "UMask": "0x1",
3998        "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests",
3999        "MSRValue": "0x0080020400",
4000        "Counter": "0,1,2,3",
4001        "EventName": "OCR.PF_L1D_AND_SW.SUPPLIER_NONE.SNOOP_NONE",
4002        "MSRIndex": "0x1a6,0x1a7",
4003        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
4004        "SampleAfterValue": "100003",
4005        "CounterHTOff": "0,1,2,3"
4006    },
4007    {
4008        "Offcore": "1",
4009        "EventCode": "0xB7, 0xBB",
4010        "UMask": "0x1",
4011        "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests  TBD",
4012        "MSRValue": "0x0100020400",
4013        "Counter": "0,1,2,3",
4014        "EventName": "OCR.PF_L1D_AND_SW.SUPPLIER_NONE.NO_SNOOP_NEEDED",
4015        "MSRIndex": "0x1a6,0x1a7",
4016        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
4017        "SampleAfterValue": "100003",
4018        "CounterHTOff": "0,1,2,3"
4019    },
4020    {
4021        "Offcore": "1",
4022        "EventCode": "0xB7, 0xBB",
4023        "UMask": "0x1",
4024        "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests",
4025        "MSRValue": "0x0200020400",
4026        "Counter": "0,1,2,3",
4027        "EventName": "OCR.PF_L1D_AND_SW.SUPPLIER_NONE.SNOOP_MISS",
4028        "MSRIndex": "0x1a6,0x1a7",
4029        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
4030        "SampleAfterValue": "100003",
4031        "CounterHTOff": "0,1,2,3"
4032    },
4033    {
4034        "Offcore": "1",
4035        "EventCode": "0xB7, 0xBB",
4036        "UMask": "0x1",
4037        "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests  TBD",
4038        "MSRValue": "0x0400020400",
4039        "Counter": "0,1,2,3",
4040        "EventName": "OCR.PF_L1D_AND_SW.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD",
4041        "MSRIndex": "0x1a6,0x1a7",
4042        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
4043        "SampleAfterValue": "100003",
4044        "CounterHTOff": "0,1,2,3"
4045    },
4046    {
4047        "Offcore": "1",
4048        "EventCode": "0xB7, 0xBB",
4049        "UMask": "0x1",
4050        "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests  TBD",
4051        "MSRValue": "0x0800020400",
4052        "Counter": "0,1,2,3",
4053        "EventName": "OCR.PF_L1D_AND_SW.SUPPLIER_NONE.HIT_OTHER_CORE_FWD",
4054        "MSRIndex": "0x1a6,0x1a7",
4055        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
4056        "SampleAfterValue": "100003",
4057        "CounterHTOff": "0,1,2,3"
4058    },
4059    {
4060        "Offcore": "1",
4061        "EventCode": "0xB7, 0xBB",
4062        "UMask": "0x1",
4063        "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests  TBD",
4064        "MSRValue": "0x1000020400",
4065        "Counter": "0,1,2,3",
4066        "EventName": "OCR.PF_L1D_AND_SW.SUPPLIER_NONE.HITM_OTHER_CORE",
4067        "MSRIndex": "0x1a6,0x1a7",
4068        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
4069        "SampleAfterValue": "100003",
4070        "CounterHTOff": "0,1,2,3"
4071    },
4072    {
4073        "Offcore": "1",
4074        "EventCode": "0xB7, 0xBB",
4075        "UMask": "0x1",
4076        "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests  TBD",
4077        "MSRValue": "0x3F80020400",
4078        "Counter": "0,1,2,3",
4079        "EventName": "OCR.PF_L1D_AND_SW.SUPPLIER_NONE.ANY_SNOOP",
4080        "MSRIndex": "0x1a6,0x1a7",
4081        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
4082        "SampleAfterValue": "100003",
4083        "CounterHTOff": "0,1,2,3"
4084    },
4085    {
4086        "Offcore": "1",
4087        "EventCode": "0xB7, 0xBB",
4088        "UMask": "0x1",
4089        "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests",
4090        "MSRValue": "0x0080040400",
4091        "Counter": "0,1,2,3",
4092        "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_M.SNOOP_NONE",
4093        "MSRIndex": "0x1a6,0x1a7",
4094        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
4095        "SampleAfterValue": "100003",
4096        "CounterHTOff": "0,1,2,3"
4097    },
4098    {
4099        "Offcore": "1",
4100        "EventCode": "0xB7, 0xBB",
4101        "UMask": "0x1",
4102        "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests  TBD",
4103        "MSRValue": "0x0100040400",
4104        "Counter": "0,1,2,3",
4105        "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_M.NO_SNOOP_NEEDED",
4106        "MSRIndex": "0x1a6,0x1a7",
4107        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
4108        "SampleAfterValue": "100003",
4109        "CounterHTOff": "0,1,2,3"
4110    },
4111    {
4112        "Offcore": "1",
4113        "EventCode": "0xB7, 0xBB",
4114        "UMask": "0x1",
4115        "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests",
4116        "MSRValue": "0x0200040400",
4117        "Counter": "0,1,2,3",
4118        "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_M.SNOOP_MISS",
4119        "MSRIndex": "0x1a6,0x1a7",
4120        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
4121        "SampleAfterValue": "100003",
4122        "CounterHTOff": "0,1,2,3"
4123    },
4124    {
4125        "Offcore": "1",
4126        "EventCode": "0xB7, 0xBB",
4127        "UMask": "0x1",
4128        "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests  TBD",
4129        "MSRValue": "0x0400040400",
4130        "Counter": "0,1,2,3",
4131        "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_M.HIT_OTHER_CORE_NO_FWD",
4132        "MSRIndex": "0x1a6,0x1a7",
4133        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
4134        "SampleAfterValue": "100003",
4135        "CounterHTOff": "0,1,2,3"
4136    },
4137    {
4138        "Offcore": "1",
4139        "EventCode": "0xB7, 0xBB",
4140        "UMask": "0x1",
4141        "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests  TBD",
4142        "MSRValue": "0x0800040400",
4143        "Counter": "0,1,2,3",
4144        "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_M.HIT_OTHER_CORE_FWD",
4145        "MSRIndex": "0x1a6,0x1a7",
4146        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
4147        "SampleAfterValue": "100003",
4148        "CounterHTOff": "0,1,2,3"
4149    },
4150    {
4151        "Offcore": "1",
4152        "EventCode": "0xB7, 0xBB",
4153        "UMask": "0x1",
4154        "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests  TBD",
4155        "MSRValue": "0x1000040400",
4156        "Counter": "0,1,2,3",
4157        "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_M.HITM_OTHER_CORE",
4158        "MSRIndex": "0x1a6,0x1a7",
4159        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
4160        "SampleAfterValue": "100003",
4161        "CounterHTOff": "0,1,2,3"
4162    },
4163    {
4164        "Offcore": "1",
4165        "EventCode": "0xB7, 0xBB",
4166        "UMask": "0x1",
4167        "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests  TBD",
4168        "MSRValue": "0x3F80040400",
4169        "Counter": "0,1,2,3",
4170        "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_M.ANY_SNOOP",
4171        "MSRIndex": "0x1a6,0x1a7",
4172        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
4173        "SampleAfterValue": "100003",
4174        "CounterHTOff": "0,1,2,3"
4175    },
4176    {
4177        "Offcore": "1",
4178        "EventCode": "0xB7, 0xBB",
4179        "UMask": "0x1",
4180        "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests",
4181        "MSRValue": "0x0080080400",
4182        "Counter": "0,1,2,3",
4183        "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_E.SNOOP_NONE",
4184        "MSRIndex": "0x1a6,0x1a7",
4185        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
4186        "SampleAfterValue": "100003",
4187        "CounterHTOff": "0,1,2,3"
4188    },
4189    {
4190        "Offcore": "1",
4191        "EventCode": "0xB7, 0xBB",
4192        "UMask": "0x1",
4193        "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests  TBD",
4194        "MSRValue": "0x0100080400",
4195        "Counter": "0,1,2,3",
4196        "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_E.NO_SNOOP_NEEDED",
4197        "MSRIndex": "0x1a6,0x1a7",
4198        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
4199        "SampleAfterValue": "100003",
4200        "CounterHTOff": "0,1,2,3"
4201    },
4202    {
4203        "Offcore": "1",
4204        "EventCode": "0xB7, 0xBB",
4205        "UMask": "0x1",
4206        "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests",
4207        "MSRValue": "0x0200080400",
4208        "Counter": "0,1,2,3",
4209        "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_E.SNOOP_MISS",
4210        "MSRIndex": "0x1a6,0x1a7",
4211        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
4212        "SampleAfterValue": "100003",
4213        "CounterHTOff": "0,1,2,3"
4214    },
4215    {
4216        "Offcore": "1",
4217        "EventCode": "0xB7, 0xBB",
4218        "UMask": "0x1",
4219        "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests  TBD",
4220        "MSRValue": "0x0400080400",
4221        "Counter": "0,1,2,3",
4222        "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_E.HIT_OTHER_CORE_NO_FWD",
4223        "MSRIndex": "0x1a6,0x1a7",
4224        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
4225        "SampleAfterValue": "100003",
4226        "CounterHTOff": "0,1,2,3"
4227    },
4228    {
4229        "Offcore": "1",
4230        "EventCode": "0xB7, 0xBB",
4231        "UMask": "0x1",
4232        "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests  TBD",
4233        "MSRValue": "0x0800080400",
4234        "Counter": "0,1,2,3",
4235        "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_E.HIT_OTHER_CORE_FWD",
4236        "MSRIndex": "0x1a6,0x1a7",
4237        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
4238        "SampleAfterValue": "100003",
4239        "CounterHTOff": "0,1,2,3"
4240    },
4241    {
4242        "Offcore": "1",
4243        "EventCode": "0xB7, 0xBB",
4244        "UMask": "0x1",
4245        "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests  TBD",
4246        "MSRValue": "0x1000080400",
4247        "Counter": "0,1,2,3",
4248        "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_E.HITM_OTHER_CORE",
4249        "MSRIndex": "0x1a6,0x1a7",
4250        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
4251        "SampleAfterValue": "100003",
4252        "CounterHTOff": "0,1,2,3"
4253    },
4254    {
4255        "Offcore": "1",
4256        "EventCode": "0xB7, 0xBB",
4257        "UMask": "0x1",
4258        "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests  TBD",
4259        "MSRValue": "0x3F80080400",
4260        "Counter": "0,1,2,3",
4261        "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_E.ANY_SNOOP",
4262        "MSRIndex": "0x1a6,0x1a7",
4263        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
4264        "SampleAfterValue": "100003",
4265        "CounterHTOff": "0,1,2,3"
4266    },
4267    {
4268        "Offcore": "1",
4269        "EventCode": "0xB7, 0xBB",
4270        "UMask": "0x1",
4271        "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests",
4272        "MSRValue": "0x0080100400",
4273        "Counter": "0,1,2,3",
4274        "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_S.SNOOP_NONE",
4275        "MSRIndex": "0x1a6,0x1a7",
4276        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
4277        "SampleAfterValue": "100003",
4278        "CounterHTOff": "0,1,2,3"
4279    },
4280    {
4281        "Offcore": "1",
4282        "EventCode": "0xB7, 0xBB",
4283        "UMask": "0x1",
4284        "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests  TBD",
4285        "MSRValue": "0x0100100400",
4286        "Counter": "0,1,2,3",
4287        "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_S.NO_SNOOP_NEEDED",
4288        "MSRIndex": "0x1a6,0x1a7",
4289        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
4290        "SampleAfterValue": "100003",
4291        "CounterHTOff": "0,1,2,3"
4292    },
4293    {
4294        "Offcore": "1",
4295        "EventCode": "0xB7, 0xBB",
4296        "UMask": "0x1",
4297        "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests",
4298        "MSRValue": "0x0200100400",
4299        "Counter": "0,1,2,3",
4300        "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_S.SNOOP_MISS",
4301        "MSRIndex": "0x1a6,0x1a7",
4302        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
4303        "SampleAfterValue": "100003",
4304        "CounterHTOff": "0,1,2,3"
4305    },
4306    {
4307        "Offcore": "1",
4308        "EventCode": "0xB7, 0xBB",
4309        "UMask": "0x1",
4310        "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests  TBD",
4311        "MSRValue": "0x0400100400",
4312        "Counter": "0,1,2,3",
4313        "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_S.HIT_OTHER_CORE_NO_FWD",
4314        "MSRIndex": "0x1a6,0x1a7",
4315        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
4316        "SampleAfterValue": "100003",
4317        "CounterHTOff": "0,1,2,3"
4318    },
4319    {
4320        "Offcore": "1",
4321        "EventCode": "0xB7, 0xBB",
4322        "UMask": "0x1",
4323        "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests  TBD",
4324        "MSRValue": "0x0800100400",
4325        "Counter": "0,1,2,3",
4326        "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_S.HIT_OTHER_CORE_FWD",
4327        "MSRIndex": "0x1a6,0x1a7",
4328        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
4329        "SampleAfterValue": "100003",
4330        "CounterHTOff": "0,1,2,3"
4331    },
4332    {
4333        "Offcore": "1",
4334        "EventCode": "0xB7, 0xBB",
4335        "UMask": "0x1",
4336        "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests  TBD",
4337        "MSRValue": "0x1000100400",
4338        "Counter": "0,1,2,3",
4339        "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_S.HITM_OTHER_CORE",
4340        "MSRIndex": "0x1a6,0x1a7",
4341        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
4342        "SampleAfterValue": "100003",
4343        "CounterHTOff": "0,1,2,3"
4344    },
4345    {
4346        "Offcore": "1",
4347        "EventCode": "0xB7, 0xBB",
4348        "UMask": "0x1",
4349        "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests  TBD",
4350        "MSRValue": "0x3F80100400",
4351        "Counter": "0,1,2,3",
4352        "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_S.ANY_SNOOP",
4353        "MSRIndex": "0x1a6,0x1a7",
4354        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
4355        "SampleAfterValue": "100003",
4356        "CounterHTOff": "0,1,2,3"
4357    },
4358    {
4359        "Offcore": "1",
4360        "EventCode": "0xB7, 0xBB",
4361        "UMask": "0x1",
4362        "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests",
4363        "MSRValue": "0x0080200400",
4364        "Counter": "0,1,2,3",
4365        "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_F.SNOOP_NONE",
4366        "MSRIndex": "0x1a6,0x1a7",
4367        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
4368        "SampleAfterValue": "100003",
4369        "CounterHTOff": "0,1,2,3"
4370    },
4371    {
4372        "Offcore": "1",
4373        "EventCode": "0xB7, 0xBB",
4374        "UMask": "0x1",
4375        "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests  TBD",
4376        "MSRValue": "0x0100200400",
4377        "Counter": "0,1,2,3",
4378        "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_F.NO_SNOOP_NEEDED",
4379        "MSRIndex": "0x1a6,0x1a7",
4380        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
4381        "SampleAfterValue": "100003",
4382        "CounterHTOff": "0,1,2,3"
4383    },
4384    {
4385        "Offcore": "1",
4386        "EventCode": "0xB7, 0xBB",
4387        "UMask": "0x1",
4388        "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests",
4389        "MSRValue": "0x0200200400",
4390        "Counter": "0,1,2,3",
4391        "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_F.SNOOP_MISS",
4392        "MSRIndex": "0x1a6,0x1a7",
4393        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
4394        "SampleAfterValue": "100003",
4395        "CounterHTOff": "0,1,2,3"
4396    },
4397    {
4398        "Offcore": "1",
4399        "EventCode": "0xB7, 0xBB",
4400        "UMask": "0x1",
4401        "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests  TBD",
4402        "MSRValue": "0x0400200400",
4403        "Counter": "0,1,2,3",
4404        "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_F.HIT_OTHER_CORE_NO_FWD",
4405        "MSRIndex": "0x1a6,0x1a7",
4406        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
4407        "SampleAfterValue": "100003",
4408        "CounterHTOff": "0,1,2,3"
4409    },
4410    {
4411        "Offcore": "1",
4412        "EventCode": "0xB7, 0xBB",
4413        "UMask": "0x1",
4414        "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests  TBD",
4415        "MSRValue": "0x0800200400",
4416        "Counter": "0,1,2,3",
4417        "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_F.HIT_OTHER_CORE_FWD",
4418        "MSRIndex": "0x1a6,0x1a7",
4419        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
4420        "SampleAfterValue": "100003",
4421        "CounterHTOff": "0,1,2,3"
4422    },
4423    {
4424        "Offcore": "1",
4425        "EventCode": "0xB7, 0xBB",
4426        "UMask": "0x1",
4427        "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests  TBD",
4428        "MSRValue": "0x1000200400",
4429        "Counter": "0,1,2,3",
4430        "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_F.HITM_OTHER_CORE",
4431        "MSRIndex": "0x1a6,0x1a7",
4432        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
4433        "SampleAfterValue": "100003",
4434        "CounterHTOff": "0,1,2,3"
4435    },
4436    {
4437        "Offcore": "1",
4438        "EventCode": "0xB7, 0xBB",
4439        "UMask": "0x1",
4440        "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests  TBD",
4441        "MSRValue": "0x3F80200400",
4442        "Counter": "0,1,2,3",
4443        "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_F.ANY_SNOOP",
4444        "MSRIndex": "0x1a6,0x1a7",
4445        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
4446        "SampleAfterValue": "100003",
4447        "CounterHTOff": "0,1,2,3"
4448    },
4449    {
4450        "Offcore": "1",
4451        "EventCode": "0xB7, 0xBB",
4452        "UMask": "0x1",
4453        "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests TBD",
4454        "MSRValue": "0x00803C0400",
4455        "Counter": "0,1,2,3",
4456        "EventName": "OCR.PF_L1D_AND_SW.L3_HIT.SNOOP_NONE",
4457        "MSRIndex": "0x1a6,0x1a7",
4458        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
4459        "SampleAfterValue": "100003",
4460        "CounterHTOff": "0,1,2,3"
4461    },
4462    {
4463        "Offcore": "1",
4464        "EventCode": "0xB7, 0xBB",
4465        "UMask": "0x1",
4466        "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests TBD TBD",
4467        "MSRValue": "0x01003C0400",
4468        "Counter": "0,1,2,3",
4469        "EventName": "OCR.PF_L1D_AND_SW.L3_HIT.NO_SNOOP_NEEDED",
4470        "MSRIndex": "0x1a6,0x1a7",
4471        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
4472        "SampleAfterValue": "100003",
4473        "CounterHTOff": "0,1,2,3"
4474    },
4475    {
4476        "Offcore": "1",
4477        "EventCode": "0xB7, 0xBB",
4478        "UMask": "0x1",
4479        "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests TBD",
4480        "MSRValue": "0x02003C0400",
4481        "Counter": "0,1,2,3",
4482        "EventName": "OCR.PF_L1D_AND_SW.L3_HIT.SNOOP_MISS",
4483        "MSRIndex": "0x1a6,0x1a7",
4484        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
4485        "SampleAfterValue": "100003",
4486        "CounterHTOff": "0,1,2,3"
4487    },
4488    {
4489        "Offcore": "1",
4490        "EventCode": "0xB7, 0xBB",
4491        "UMask": "0x1",
4492        "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests TBD TBD",
4493        "MSRValue": "0x04003C0400",
4494        "Counter": "0,1,2,3",
4495        "EventName": "OCR.PF_L1D_AND_SW.L3_HIT.HIT_OTHER_CORE_NO_FWD",
4496        "MSRIndex": "0x1a6,0x1a7",
4497        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
4498        "SampleAfterValue": "100003",
4499        "CounterHTOff": "0,1,2,3"
4500    },
4501    {
4502        "Offcore": "1",
4503        "EventCode": "0xB7, 0xBB",
4504        "UMask": "0x1",
4505        "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests TBD TBD",
4506        "MSRValue": "0x08003C0400",
4507        "Counter": "0,1,2,3",
4508        "EventName": "OCR.PF_L1D_AND_SW.L3_HIT.HIT_OTHER_CORE_FWD",
4509        "MSRIndex": "0x1a6,0x1a7",
4510        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
4511        "SampleAfterValue": "100003",
4512        "CounterHTOff": "0,1,2,3"
4513    },
4514    {
4515        "Offcore": "1",
4516        "EventCode": "0xB7, 0xBB",
4517        "UMask": "0x1",
4518        "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests TBD TBD",
4519        "MSRValue": "0x10003C0400",
4520        "Counter": "0,1,2,3",
4521        "EventName": "OCR.PF_L1D_AND_SW.L3_HIT.HITM_OTHER_CORE",
4522        "MSRIndex": "0x1a6,0x1a7",
4523        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
4524        "SampleAfterValue": "100003",
4525        "CounterHTOff": "0,1,2,3"
4526    },
4527    {
4528        "Offcore": "1",
4529        "EventCode": "0xB7, 0xBB",
4530        "UMask": "0x1",
4531        "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests TBD TBD",
4532        "MSRValue": "0x3F803C0400",
4533        "Counter": "0,1,2,3",
4534        "EventName": "OCR.PF_L1D_AND_SW.L3_HIT.ANY_SNOOP",
4535        "MSRIndex": "0x1a6,0x1a7",
4536        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
4537        "SampleAfterValue": "100003",
4538        "CounterHTOff": "0,1,2,3"
4539    },
4540    {
4541        "Offcore": "1",
4542        "EventCode": "0xB7, 0xBB",
4543        "UMask": "0x1",
4544        "BriefDescription": "Counts any other requests",
4545        "MSRValue": "0x0080028000",
4546        "Counter": "0,1,2,3",
4547        "EventName": "OCR.OTHER.SUPPLIER_NONE.SNOOP_NONE",
4548        "MSRIndex": "0x1a6,0x1a7",
4549        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
4550        "SampleAfterValue": "100003",
4551        "CounterHTOff": "0,1,2,3"
4552    },
4553    {
4554        "Offcore": "1",
4555        "EventCode": "0xB7, 0xBB",
4556        "UMask": "0x1",
4557        "BriefDescription": "Counts any other requests  TBD",
4558        "MSRValue": "0x0100028000",
4559        "Counter": "0,1,2,3",
4560        "EventName": "OCR.OTHER.SUPPLIER_NONE.NO_SNOOP_NEEDED",
4561        "MSRIndex": "0x1a6,0x1a7",
4562        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
4563        "SampleAfterValue": "100003",
4564        "CounterHTOff": "0,1,2,3"
4565    },
4566    {
4567        "Offcore": "1",
4568        "EventCode": "0xB7, 0xBB",
4569        "UMask": "0x1",
4570        "BriefDescription": "Counts any other requests",
4571        "MSRValue": "0x0200028000",
4572        "Counter": "0,1,2,3",
4573        "EventName": "OCR.OTHER.SUPPLIER_NONE.SNOOP_MISS",
4574        "MSRIndex": "0x1a6,0x1a7",
4575        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
4576        "SampleAfterValue": "100003",
4577        "CounterHTOff": "0,1,2,3"
4578    },
4579    {
4580        "Offcore": "1",
4581        "EventCode": "0xB7, 0xBB",
4582        "UMask": "0x1",
4583        "BriefDescription": "Counts any other requests  TBD",
4584        "MSRValue": "0x0400028000",
4585        "Counter": "0,1,2,3",
4586        "EventName": "OCR.OTHER.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD",
4587        "MSRIndex": "0x1a6,0x1a7",
4588        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
4589        "SampleAfterValue": "100003",
4590        "CounterHTOff": "0,1,2,3"
4591    },
4592    {
4593        "Offcore": "1",
4594        "EventCode": "0xB7, 0xBB",
4595        "UMask": "0x1",
4596        "BriefDescription": "Counts any other requests  TBD",
4597        "MSRValue": "0x0800028000",
4598        "Counter": "0,1,2,3",
4599        "EventName": "OCR.OTHER.SUPPLIER_NONE.HIT_OTHER_CORE_FWD",
4600        "MSRIndex": "0x1a6,0x1a7",
4601        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
4602        "SampleAfterValue": "100003",
4603        "CounterHTOff": "0,1,2,3"
4604    },
4605    {
4606        "Offcore": "1",
4607        "EventCode": "0xB7, 0xBB",
4608        "UMask": "0x1",
4609        "BriefDescription": "Counts any other requests  TBD",
4610        "MSRValue": "0x1000028000",
4611        "Counter": "0,1,2,3",
4612        "EventName": "OCR.OTHER.SUPPLIER_NONE.HITM_OTHER_CORE",
4613        "MSRIndex": "0x1a6,0x1a7",
4614        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
4615        "SampleAfterValue": "100003",
4616        "CounterHTOff": "0,1,2,3"
4617    },
4618    {
4619        "Offcore": "1",
4620        "EventCode": "0xB7, 0xBB",
4621        "UMask": "0x1",
4622        "BriefDescription": "Counts any other requests  TBD",
4623        "MSRValue": "0x3F80028000",
4624        "Counter": "0,1,2,3",
4625        "EventName": "OCR.OTHER.SUPPLIER_NONE.ANY_SNOOP",
4626        "MSRIndex": "0x1a6,0x1a7",
4627        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
4628        "SampleAfterValue": "100003",
4629        "CounterHTOff": "0,1,2,3"
4630    },
4631    {
4632        "Offcore": "1",
4633        "EventCode": "0xB7, 0xBB",
4634        "UMask": "0x1",
4635        "BriefDescription": "Counts any other requests",
4636        "MSRValue": "0x0080048000",
4637        "Counter": "0,1,2,3",
4638        "EventName": "OCR.OTHER.L3_HIT_M.SNOOP_NONE",
4639        "MSRIndex": "0x1a6,0x1a7",
4640        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
4641        "SampleAfterValue": "100003",
4642        "CounterHTOff": "0,1,2,3"
4643    },
4644    {
4645        "Offcore": "1",
4646        "EventCode": "0xB7, 0xBB",
4647        "UMask": "0x1",
4648        "BriefDescription": "Counts any other requests  TBD",
4649        "MSRValue": "0x0100048000",
4650        "Counter": "0,1,2,3",
4651        "EventName": "OCR.OTHER.L3_HIT_M.NO_SNOOP_NEEDED",
4652        "MSRIndex": "0x1a6,0x1a7",
4653        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
4654        "SampleAfterValue": "100003",
4655        "CounterHTOff": "0,1,2,3"
4656    },
4657    {
4658        "Offcore": "1",
4659        "EventCode": "0xB7, 0xBB",
4660        "UMask": "0x1",
4661        "BriefDescription": "Counts any other requests",
4662        "MSRValue": "0x0200048000",
4663        "Counter": "0,1,2,3",
4664        "EventName": "OCR.OTHER.L3_HIT_M.SNOOP_MISS",
4665        "MSRIndex": "0x1a6,0x1a7",
4666        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
4667        "SampleAfterValue": "100003",
4668        "CounterHTOff": "0,1,2,3"
4669    },
4670    {
4671        "Offcore": "1",
4672        "EventCode": "0xB7, 0xBB",
4673        "UMask": "0x1",
4674        "BriefDescription": "Counts any other requests  TBD",
4675        "MSRValue": "0x0400048000",
4676        "Counter": "0,1,2,3",
4677        "EventName": "OCR.OTHER.L3_HIT_M.HIT_OTHER_CORE_NO_FWD",
4678        "MSRIndex": "0x1a6,0x1a7",
4679        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
4680        "SampleAfterValue": "100003",
4681        "CounterHTOff": "0,1,2,3"
4682    },
4683    {
4684        "Offcore": "1",
4685        "EventCode": "0xB7, 0xBB",
4686        "UMask": "0x1",
4687        "BriefDescription": "Counts any other requests  TBD",
4688        "MSRValue": "0x0800048000",
4689        "Counter": "0,1,2,3",
4690        "EventName": "OCR.OTHER.L3_HIT_M.HIT_OTHER_CORE_FWD",
4691        "MSRIndex": "0x1a6,0x1a7",
4692        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
4693        "SampleAfterValue": "100003",
4694        "CounterHTOff": "0,1,2,3"
4695    },
4696    {
4697        "Offcore": "1",
4698        "EventCode": "0xB7, 0xBB",
4699        "UMask": "0x1",
4700        "BriefDescription": "Counts any other requests  TBD",
4701        "MSRValue": "0x1000048000",
4702        "Counter": "0,1,2,3",
4703        "EventName": "OCR.OTHER.L3_HIT_M.HITM_OTHER_CORE",
4704        "MSRIndex": "0x1a6,0x1a7",
4705        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
4706        "SampleAfterValue": "100003",
4707        "CounterHTOff": "0,1,2,3"
4708    },
4709    {
4710        "Offcore": "1",
4711        "EventCode": "0xB7, 0xBB",
4712        "UMask": "0x1",
4713        "BriefDescription": "Counts any other requests  TBD",
4714        "MSRValue": "0x3F80048000",
4715        "Counter": "0,1,2,3",
4716        "EventName": "OCR.OTHER.L3_HIT_M.ANY_SNOOP",
4717        "MSRIndex": "0x1a6,0x1a7",
4718        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
4719        "SampleAfterValue": "100003",
4720        "CounterHTOff": "0,1,2,3"
4721    },
4722    {
4723        "Offcore": "1",
4724        "EventCode": "0xB7, 0xBB",
4725        "UMask": "0x1",
4726        "BriefDescription": "Counts any other requests",
4727        "MSRValue": "0x0080088000",
4728        "Counter": "0,1,2,3",
4729        "EventName": "OCR.OTHER.L3_HIT_E.SNOOP_NONE",
4730        "MSRIndex": "0x1a6,0x1a7",
4731        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
4732        "SampleAfterValue": "100003",
4733        "CounterHTOff": "0,1,2,3"
4734    },
4735    {
4736        "Offcore": "1",
4737        "EventCode": "0xB7, 0xBB",
4738        "UMask": "0x1",
4739        "BriefDescription": "Counts any other requests  TBD",
4740        "MSRValue": "0x0100088000",
4741        "Counter": "0,1,2,3",
4742        "EventName": "OCR.OTHER.L3_HIT_E.NO_SNOOP_NEEDED",
4743        "MSRIndex": "0x1a6,0x1a7",
4744        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
4745        "SampleAfterValue": "100003",
4746        "CounterHTOff": "0,1,2,3"
4747    },
4748    {
4749        "Offcore": "1",
4750        "EventCode": "0xB7, 0xBB",
4751        "UMask": "0x1",
4752        "BriefDescription": "Counts any other requests",
4753        "MSRValue": "0x0200088000",
4754        "Counter": "0,1,2,3",
4755        "EventName": "OCR.OTHER.L3_HIT_E.SNOOP_MISS",
4756        "MSRIndex": "0x1a6,0x1a7",
4757        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
4758        "SampleAfterValue": "100003",
4759        "CounterHTOff": "0,1,2,3"
4760    },
4761    {
4762        "Offcore": "1",
4763        "EventCode": "0xB7, 0xBB",
4764        "UMask": "0x1",
4765        "BriefDescription": "Counts any other requests  TBD",
4766        "MSRValue": "0x0400088000",
4767        "Counter": "0,1,2,3",
4768        "EventName": "OCR.OTHER.L3_HIT_E.HIT_OTHER_CORE_NO_FWD",
4769        "MSRIndex": "0x1a6,0x1a7",
4770        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
4771        "SampleAfterValue": "100003",
4772        "CounterHTOff": "0,1,2,3"
4773    },
4774    {
4775        "Offcore": "1",
4776        "EventCode": "0xB7, 0xBB",
4777        "UMask": "0x1",
4778        "BriefDescription": "Counts any other requests  TBD",
4779        "MSRValue": "0x0800088000",
4780        "Counter": "0,1,2,3",
4781        "EventName": "OCR.OTHER.L3_HIT_E.HIT_OTHER_CORE_FWD",
4782        "MSRIndex": "0x1a6,0x1a7",
4783        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
4784        "SampleAfterValue": "100003",
4785        "CounterHTOff": "0,1,2,3"
4786    },
4787    {
4788        "Offcore": "1",
4789        "EventCode": "0xB7, 0xBB",
4790        "UMask": "0x1",
4791        "BriefDescription": "Counts any other requests  TBD",
4792        "MSRValue": "0x1000088000",
4793        "Counter": "0,1,2,3",
4794        "EventName": "OCR.OTHER.L3_HIT_E.HITM_OTHER_CORE",
4795        "MSRIndex": "0x1a6,0x1a7",
4796        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
4797        "SampleAfterValue": "100003",
4798        "CounterHTOff": "0,1,2,3"
4799    },
4800    {
4801        "Offcore": "1",
4802        "EventCode": "0xB7, 0xBB",
4803        "UMask": "0x1",
4804        "BriefDescription": "Counts any other requests  TBD",
4805        "MSRValue": "0x3F80088000",
4806        "Counter": "0,1,2,3",
4807        "EventName": "OCR.OTHER.L3_HIT_E.ANY_SNOOP",
4808        "MSRIndex": "0x1a6,0x1a7",
4809        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
4810        "SampleAfterValue": "100003",
4811        "CounterHTOff": "0,1,2,3"
4812    },
4813    {
4814        "Offcore": "1",
4815        "EventCode": "0xB7, 0xBB",
4816        "UMask": "0x1",
4817        "BriefDescription": "Counts any other requests",
4818        "MSRValue": "0x0080108000",
4819        "Counter": "0,1,2,3",
4820        "EventName": "OCR.OTHER.L3_HIT_S.SNOOP_NONE",
4821        "MSRIndex": "0x1a6,0x1a7",
4822        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
4823        "SampleAfterValue": "100003",
4824        "CounterHTOff": "0,1,2,3"
4825    },
4826    {
4827        "Offcore": "1",
4828        "EventCode": "0xB7, 0xBB",
4829        "UMask": "0x1",
4830        "BriefDescription": "Counts any other requests  TBD",
4831        "MSRValue": "0x0100108000",
4832        "Counter": "0,1,2,3",
4833        "EventName": "OCR.OTHER.L3_HIT_S.NO_SNOOP_NEEDED",
4834        "MSRIndex": "0x1a6,0x1a7",
4835        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
4836        "SampleAfterValue": "100003",
4837        "CounterHTOff": "0,1,2,3"
4838    },
4839    {
4840        "Offcore": "1",
4841        "EventCode": "0xB7, 0xBB",
4842        "UMask": "0x1",
4843        "BriefDescription": "Counts any other requests",
4844        "MSRValue": "0x0200108000",
4845        "Counter": "0,1,2,3",
4846        "EventName": "OCR.OTHER.L3_HIT_S.SNOOP_MISS",
4847        "MSRIndex": "0x1a6,0x1a7",
4848        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
4849        "SampleAfterValue": "100003",
4850        "CounterHTOff": "0,1,2,3"
4851    },
4852    {
4853        "Offcore": "1",
4854        "EventCode": "0xB7, 0xBB",
4855        "UMask": "0x1",
4856        "BriefDescription": "Counts any other requests  TBD",
4857        "MSRValue": "0x0400108000",
4858        "Counter": "0,1,2,3",
4859        "EventName": "OCR.OTHER.L3_HIT_S.HIT_OTHER_CORE_NO_FWD",
4860        "MSRIndex": "0x1a6,0x1a7",
4861        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
4862        "SampleAfterValue": "100003",
4863        "CounterHTOff": "0,1,2,3"
4864    },
4865    {
4866        "Offcore": "1",
4867        "EventCode": "0xB7, 0xBB",
4868        "UMask": "0x1",
4869        "BriefDescription": "Counts any other requests  TBD",
4870        "MSRValue": "0x0800108000",
4871        "Counter": "0,1,2,3",
4872        "EventName": "OCR.OTHER.L3_HIT_S.HIT_OTHER_CORE_FWD",
4873        "MSRIndex": "0x1a6,0x1a7",
4874        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
4875        "SampleAfterValue": "100003",
4876        "CounterHTOff": "0,1,2,3"
4877    },
4878    {
4879        "Offcore": "1",
4880        "EventCode": "0xB7, 0xBB",
4881        "UMask": "0x1",
4882        "BriefDescription": "Counts any other requests  TBD",
4883        "MSRValue": "0x1000108000",
4884        "Counter": "0,1,2,3",
4885        "EventName": "OCR.OTHER.L3_HIT_S.HITM_OTHER_CORE",
4886        "MSRIndex": "0x1a6,0x1a7",
4887        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
4888        "SampleAfterValue": "100003",
4889        "CounterHTOff": "0,1,2,3"
4890    },
4891    {
4892        "Offcore": "1",
4893        "EventCode": "0xB7, 0xBB",
4894        "UMask": "0x1",
4895        "BriefDescription": "Counts any other requests  TBD",
4896        "MSRValue": "0x3F80108000",
4897        "Counter": "0,1,2,3",
4898        "EventName": "OCR.OTHER.L3_HIT_S.ANY_SNOOP",
4899        "MSRIndex": "0x1a6,0x1a7",
4900        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
4901        "SampleAfterValue": "100003",
4902        "CounterHTOff": "0,1,2,3"
4903    },
4904    {
4905        "Offcore": "1",
4906        "EventCode": "0xB7, 0xBB",
4907        "UMask": "0x1",
4908        "BriefDescription": "Counts any other requests",
4909        "MSRValue": "0x0080208000",
4910        "Counter": "0,1,2,3",
4911        "EventName": "OCR.OTHER.L3_HIT_F.SNOOP_NONE",
4912        "MSRIndex": "0x1a6,0x1a7",
4913        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
4914        "SampleAfterValue": "100003",
4915        "CounterHTOff": "0,1,2,3"
4916    },
4917    {
4918        "Offcore": "1",
4919        "EventCode": "0xB7, 0xBB",
4920        "UMask": "0x1",
4921        "BriefDescription": "Counts any other requests  TBD",
4922        "MSRValue": "0x0100208000",
4923        "Counter": "0,1,2,3",
4924        "EventName": "OCR.OTHER.L3_HIT_F.NO_SNOOP_NEEDED",
4925        "MSRIndex": "0x1a6,0x1a7",
4926        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
4927        "SampleAfterValue": "100003",
4928        "CounterHTOff": "0,1,2,3"
4929    },
4930    {
4931        "Offcore": "1",
4932        "EventCode": "0xB7, 0xBB",
4933        "UMask": "0x1",
4934        "BriefDescription": "Counts any other requests",
4935        "MSRValue": "0x0200208000",
4936        "Counter": "0,1,2,3",
4937        "EventName": "OCR.OTHER.L3_HIT_F.SNOOP_MISS",
4938        "MSRIndex": "0x1a6,0x1a7",
4939        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
4940        "SampleAfterValue": "100003",
4941        "CounterHTOff": "0,1,2,3"
4942    },
4943    {
4944        "Offcore": "1",
4945        "EventCode": "0xB7, 0xBB",
4946        "UMask": "0x1",
4947        "BriefDescription": "Counts any other requests  TBD",
4948        "MSRValue": "0x0400208000",
4949        "Counter": "0,1,2,3",
4950        "EventName": "OCR.OTHER.L3_HIT_F.HIT_OTHER_CORE_NO_FWD",
4951        "MSRIndex": "0x1a6,0x1a7",
4952        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
4953        "SampleAfterValue": "100003",
4954        "CounterHTOff": "0,1,2,3"
4955    },
4956    {
4957        "Offcore": "1",
4958        "EventCode": "0xB7, 0xBB",
4959        "UMask": "0x1",
4960        "BriefDescription": "Counts any other requests  TBD",
4961        "MSRValue": "0x0800208000",
4962        "Counter": "0,1,2,3",
4963        "EventName": "OCR.OTHER.L3_HIT_F.HIT_OTHER_CORE_FWD",
4964        "MSRIndex": "0x1a6,0x1a7",
4965        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
4966        "SampleAfterValue": "100003",
4967        "CounterHTOff": "0,1,2,3"
4968    },
4969    {
4970        "Offcore": "1",
4971        "EventCode": "0xB7, 0xBB",
4972        "UMask": "0x1",
4973        "BriefDescription": "Counts any other requests  TBD",
4974        "MSRValue": "0x1000208000",
4975        "Counter": "0,1,2,3",
4976        "EventName": "OCR.OTHER.L3_HIT_F.HITM_OTHER_CORE",
4977        "MSRIndex": "0x1a6,0x1a7",
4978        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
4979        "SampleAfterValue": "100003",
4980        "CounterHTOff": "0,1,2,3"
4981    },
4982    {
4983        "Offcore": "1",
4984        "EventCode": "0xB7, 0xBB",
4985        "UMask": "0x1",
4986        "BriefDescription": "Counts any other requests  TBD",
4987        "MSRValue": "0x3F80208000",
4988        "Counter": "0,1,2,3",
4989        "EventName": "OCR.OTHER.L3_HIT_F.ANY_SNOOP",
4990        "MSRIndex": "0x1a6,0x1a7",
4991        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
4992        "SampleAfterValue": "100003",
4993        "CounterHTOff": "0,1,2,3"
4994    },
4995    {
4996        "Offcore": "1",
4997        "EventCode": "0xB7, 0xBB",
4998        "UMask": "0x1",
4999        "BriefDescription": "Counts any other requests TBD",
5000        "MSRValue": "0x00803C8000",
5001        "Counter": "0,1,2,3",
5002        "EventName": "OCR.OTHER.L3_HIT.SNOOP_NONE",
5003        "MSRIndex": "0x1a6,0x1a7",
5004        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
5005        "SampleAfterValue": "100003",
5006        "CounterHTOff": "0,1,2,3"
5007    },
5008    {
5009        "Offcore": "1",
5010        "EventCode": "0xB7, 0xBB",
5011        "UMask": "0x1",
5012        "BriefDescription": "Counts any other requests TBD TBD",
5013        "MSRValue": "0x01003C8000",
5014        "Counter": "0,1,2,3",
5015        "EventName": "OCR.OTHER.L3_HIT.NO_SNOOP_NEEDED",
5016        "MSRIndex": "0x1a6,0x1a7",
5017        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
5018        "SampleAfterValue": "100003",
5019        "CounterHTOff": "0,1,2,3"
5020    },
5021    {
5022        "Offcore": "1",
5023        "EventCode": "0xB7, 0xBB",
5024        "UMask": "0x1",
5025        "BriefDescription": "Counts any other requests TBD",
5026        "MSRValue": "0x02003C8000",
5027        "Counter": "0,1,2,3",
5028        "EventName": "OCR.OTHER.L3_HIT.SNOOP_MISS",
5029        "MSRIndex": "0x1a6,0x1a7",
5030        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
5031        "SampleAfterValue": "100003",
5032        "CounterHTOff": "0,1,2,3"
5033    },
5034    {
5035        "Offcore": "1",
5036        "EventCode": "0xB7, 0xBB",
5037        "UMask": "0x1",
5038        "BriefDescription": "Counts any other requests TBD TBD",
5039        "MSRValue": "0x04003C8000",
5040        "Counter": "0,1,2,3",
5041        "EventName": "OCR.OTHER.L3_HIT.HIT_OTHER_CORE_NO_FWD",
5042        "MSRIndex": "0x1a6,0x1a7",
5043        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
5044        "SampleAfterValue": "100003",
5045        "CounterHTOff": "0,1,2,3"
5046    },
5047    {
5048        "Offcore": "1",
5049        "EventCode": "0xB7, 0xBB",
5050        "UMask": "0x1",
5051        "BriefDescription": "Counts any other requests TBD TBD",
5052        "MSRValue": "0x08003C8000",
5053        "Counter": "0,1,2,3",
5054        "EventName": "OCR.OTHER.L3_HIT.HIT_OTHER_CORE_FWD",
5055        "MSRIndex": "0x1a6,0x1a7",
5056        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
5057        "SampleAfterValue": "100003",
5058        "CounterHTOff": "0,1,2,3"
5059    },
5060    {
5061        "Offcore": "1",
5062        "EventCode": "0xB7, 0xBB",
5063        "UMask": "0x1",
5064        "BriefDescription": "Counts any other requests TBD TBD",
5065        "MSRValue": "0x10003C8000",
5066        "Counter": "0,1,2,3",
5067        "EventName": "OCR.OTHER.L3_HIT.HITM_OTHER_CORE",
5068        "MSRIndex": "0x1a6,0x1a7",
5069        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
5070        "SampleAfterValue": "100003",
5071        "CounterHTOff": "0,1,2,3"
5072    },
5073    {
5074        "Offcore": "1",
5075        "EventCode": "0xB7, 0xBB",
5076        "UMask": "0x1",
5077        "BriefDescription": "Counts any other requests TBD TBD",
5078        "MSRValue": "0x3F803C8000",
5079        "Counter": "0,1,2,3",
5080        "EventName": "OCR.OTHER.L3_HIT.ANY_SNOOP",
5081        "MSRIndex": "0x1a6,0x1a7",
5082        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
5083        "SampleAfterValue": "100003",
5084        "CounterHTOff": "0,1,2,3"
5085    },
5086    {
5087        "Offcore": "1",
5088        "EventCode": "0xB7, 0xBB",
5089        "UMask": "0x1",
5090        "BriefDescription": "TBD",
5091        "MSRValue": "0x0080020490",
5092        "Counter": "0,1,2,3",
5093        "EventName": "OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.SNOOP_NONE",
5094        "MSRIndex": "0x1a6,0x1a7",
5095        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
5096        "SampleAfterValue": "100003",
5097        "CounterHTOff": "0,1,2,3"
5098    },
5099    {
5100        "Offcore": "1",
5101        "EventCode": "0xB7, 0xBB",
5102        "UMask": "0x1",
5103        "BriefDescription": "TBD  TBD",
5104        "MSRValue": "0x0100020490",
5105        "Counter": "0,1,2,3",
5106        "EventName": "OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED",
5107        "MSRIndex": "0x1a6,0x1a7",
5108        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
5109        "SampleAfterValue": "100003",
5110        "CounterHTOff": "0,1,2,3"
5111    },
5112    {
5113        "Offcore": "1",
5114        "EventCode": "0xB7, 0xBB",
5115        "UMask": "0x1",
5116        "BriefDescription": "TBD",
5117        "MSRValue": "0x0200020490",
5118        "Counter": "0,1,2,3",
5119        "EventName": "OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.SNOOP_MISS",
5120        "MSRIndex": "0x1a6,0x1a7",
5121        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
5122        "SampleAfterValue": "100003",
5123        "CounterHTOff": "0,1,2,3"
5124    },
5125    {
5126        "Offcore": "1",
5127        "EventCode": "0xB7, 0xBB",
5128        "UMask": "0x1",
5129        "BriefDescription": "TBD  TBD",
5130        "MSRValue": "0x0400020490",
5131        "Counter": "0,1,2,3",
5132        "EventName": "OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD",
5133        "MSRIndex": "0x1a6,0x1a7",
5134        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
5135        "SampleAfterValue": "100003",
5136        "CounterHTOff": "0,1,2,3"
5137    },
5138    {
5139        "Offcore": "1",
5140        "EventCode": "0xB7, 0xBB",
5141        "UMask": "0x1",
5142        "BriefDescription": "TBD  TBD",
5143        "MSRValue": "0x0800020490",
5144        "Counter": "0,1,2,3",
5145        "EventName": "OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD",
5146        "MSRIndex": "0x1a6,0x1a7",
5147        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
5148        "SampleAfterValue": "100003",
5149        "CounterHTOff": "0,1,2,3"
5150    },
5151    {
5152        "Offcore": "1",
5153        "EventCode": "0xB7, 0xBB",
5154        "UMask": "0x1",
5155        "BriefDescription": "TBD  TBD",
5156        "MSRValue": "0x1000020490",
5157        "Counter": "0,1,2,3",
5158        "EventName": "OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.HITM_OTHER_CORE",
5159        "MSRIndex": "0x1a6,0x1a7",
5160        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
5161        "SampleAfterValue": "100003",
5162        "CounterHTOff": "0,1,2,3"
5163    },
5164    {
5165        "Offcore": "1",
5166        "EventCode": "0xB7, 0xBB",
5167        "UMask": "0x1",
5168        "BriefDescription": "TBD  TBD",
5169        "MSRValue": "0x3F80020490",
5170        "Counter": "0,1,2,3",
5171        "EventName": "OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.ANY_SNOOP",
5172        "MSRIndex": "0x1a6,0x1a7",
5173        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
5174        "SampleAfterValue": "100003",
5175        "CounterHTOff": "0,1,2,3"
5176    },
5177    {
5178        "Offcore": "1",
5179        "EventCode": "0xB7, 0xBB",
5180        "UMask": "0x1",
5181        "BriefDescription": "TBD",
5182        "MSRValue": "0x0080040490",
5183        "Counter": "0,1,2,3",
5184        "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_M.SNOOP_NONE",
5185        "MSRIndex": "0x1a6,0x1a7",
5186        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
5187        "SampleAfterValue": "100003",
5188        "CounterHTOff": "0,1,2,3"
5189    },
5190    {
5191        "Offcore": "1",
5192        "EventCode": "0xB7, 0xBB",
5193        "UMask": "0x1",
5194        "BriefDescription": "TBD  TBD",
5195        "MSRValue": "0x0100040490",
5196        "Counter": "0,1,2,3",
5197        "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDED",
5198        "MSRIndex": "0x1a6,0x1a7",
5199        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
5200        "SampleAfterValue": "100003",
5201        "CounterHTOff": "0,1,2,3"
5202    },
5203    {
5204        "Offcore": "1",
5205        "EventCode": "0xB7, 0xBB",
5206        "UMask": "0x1",
5207        "BriefDescription": "TBD",
5208        "MSRValue": "0x0200040490",
5209        "Counter": "0,1,2,3",
5210        "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_M.SNOOP_MISS",
5211        "MSRIndex": "0x1a6,0x1a7",
5212        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
5213        "SampleAfterValue": "100003",
5214        "CounterHTOff": "0,1,2,3"
5215    },
5216    {
5217        "Offcore": "1",
5218        "EventCode": "0xB7, 0xBB",
5219        "UMask": "0x1",
5220        "BriefDescription": "TBD  TBD",
5221        "MSRValue": "0x0400040490",
5222        "Counter": "0,1,2,3",
5223        "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD",
5224        "MSRIndex": "0x1a6,0x1a7",
5225        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
5226        "SampleAfterValue": "100003",
5227        "CounterHTOff": "0,1,2,3"
5228    },
5229    {
5230        "Offcore": "1",
5231        "EventCode": "0xB7, 0xBB",
5232        "UMask": "0x1",
5233        "BriefDescription": "TBD  TBD",
5234        "MSRValue": "0x0800040490",
5235        "Counter": "0,1,2,3",
5236        "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWD",
5237        "MSRIndex": "0x1a6,0x1a7",
5238        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
5239        "SampleAfterValue": "100003",
5240        "CounterHTOff": "0,1,2,3"
5241    },
5242    {
5243        "Offcore": "1",
5244        "EventCode": "0xB7, 0xBB",
5245        "UMask": "0x1",
5246        "BriefDescription": "TBD  TBD",
5247        "MSRValue": "0x1000040490",
5248        "Counter": "0,1,2,3",
5249        "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_M.HITM_OTHER_CORE",
5250        "MSRIndex": "0x1a6,0x1a7",
5251        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
5252        "SampleAfterValue": "100003",
5253        "CounterHTOff": "0,1,2,3"
5254    },
5255    {
5256        "Offcore": "1",
5257        "EventCode": "0xB7, 0xBB",
5258        "UMask": "0x1",
5259        "BriefDescription": "TBD  TBD",
5260        "MSRValue": "0x3F80040490",
5261        "Counter": "0,1,2,3",
5262        "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_M.ANY_SNOOP",
5263        "MSRIndex": "0x1a6,0x1a7",
5264        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
5265        "SampleAfterValue": "100003",
5266        "CounterHTOff": "0,1,2,3"
5267    },
5268    {
5269        "Offcore": "1",
5270        "EventCode": "0xB7, 0xBB",
5271        "UMask": "0x1",
5272        "BriefDescription": "TBD",
5273        "MSRValue": "0x0080080490",
5274        "Counter": "0,1,2,3",
5275        "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_E.SNOOP_NONE",
5276        "MSRIndex": "0x1a6,0x1a7",
5277        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
5278        "SampleAfterValue": "100003",
5279        "CounterHTOff": "0,1,2,3"
5280    },
5281    {
5282        "Offcore": "1",
5283        "EventCode": "0xB7, 0xBB",
5284        "UMask": "0x1",
5285        "BriefDescription": "TBD  TBD",
5286        "MSRValue": "0x0100080490",
5287        "Counter": "0,1,2,3",
5288        "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDED",
5289        "MSRIndex": "0x1a6,0x1a7",
5290        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
5291        "SampleAfterValue": "100003",
5292        "CounterHTOff": "0,1,2,3"
5293    },
5294    {
5295        "Offcore": "1",
5296        "EventCode": "0xB7, 0xBB",
5297        "UMask": "0x1",
5298        "BriefDescription": "TBD",
5299        "MSRValue": "0x0200080490",
5300        "Counter": "0,1,2,3",
5301        "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_E.SNOOP_MISS",
5302        "MSRIndex": "0x1a6,0x1a7",
5303        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
5304        "SampleAfterValue": "100003",
5305        "CounterHTOff": "0,1,2,3"
5306    },
5307    {
5308        "Offcore": "1",
5309        "EventCode": "0xB7, 0xBB",
5310        "UMask": "0x1",
5311        "BriefDescription": "TBD  TBD",
5312        "MSRValue": "0x0400080490",
5313        "Counter": "0,1,2,3",
5314        "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD",
5315        "MSRIndex": "0x1a6,0x1a7",
5316        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
5317        "SampleAfterValue": "100003",
5318        "CounterHTOff": "0,1,2,3"
5319    },
5320    {
5321        "Offcore": "1",
5322        "EventCode": "0xB7, 0xBB",
5323        "UMask": "0x1",
5324        "BriefDescription": "TBD  TBD",
5325        "MSRValue": "0x0800080490",
5326        "Counter": "0,1,2,3",
5327        "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWD",
5328        "MSRIndex": "0x1a6,0x1a7",
5329        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
5330        "SampleAfterValue": "100003",
5331        "CounterHTOff": "0,1,2,3"
5332    },
5333    {
5334        "Offcore": "1",
5335        "EventCode": "0xB7, 0xBB",
5336        "UMask": "0x1",
5337        "BriefDescription": "TBD  TBD",
5338        "MSRValue": "0x1000080490",
5339        "Counter": "0,1,2,3",
5340        "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_E.HITM_OTHER_CORE",
5341        "MSRIndex": "0x1a6,0x1a7",
5342        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
5343        "SampleAfterValue": "100003",
5344        "CounterHTOff": "0,1,2,3"
5345    },
5346    {
5347        "Offcore": "1",
5348        "EventCode": "0xB7, 0xBB",
5349        "UMask": "0x1",
5350        "BriefDescription": "TBD  TBD",
5351        "MSRValue": "0x3F80080490",
5352        "Counter": "0,1,2,3",
5353        "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_E.ANY_SNOOP",
5354        "MSRIndex": "0x1a6,0x1a7",
5355        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
5356        "SampleAfterValue": "100003",
5357        "CounterHTOff": "0,1,2,3"
5358    },
5359    {
5360        "Offcore": "1",
5361        "EventCode": "0xB7, 0xBB",
5362        "UMask": "0x1",
5363        "BriefDescription": "TBD",
5364        "MSRValue": "0x0080100490",
5365        "Counter": "0,1,2,3",
5366        "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_S.SNOOP_NONE",
5367        "MSRIndex": "0x1a6,0x1a7",
5368        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
5369        "SampleAfterValue": "100003",
5370        "CounterHTOff": "0,1,2,3"
5371    },
5372    {
5373        "Offcore": "1",
5374        "EventCode": "0xB7, 0xBB",
5375        "UMask": "0x1",
5376        "BriefDescription": "TBD  TBD",
5377        "MSRValue": "0x0100100490",
5378        "Counter": "0,1,2,3",
5379        "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDED",
5380        "MSRIndex": "0x1a6,0x1a7",
5381        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
5382        "SampleAfterValue": "100003",
5383        "CounterHTOff": "0,1,2,3"
5384    },
5385    {
5386        "Offcore": "1",
5387        "EventCode": "0xB7, 0xBB",
5388        "UMask": "0x1",
5389        "BriefDescription": "TBD",
5390        "MSRValue": "0x0200100490",
5391        "Counter": "0,1,2,3",
5392        "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_S.SNOOP_MISS",
5393        "MSRIndex": "0x1a6,0x1a7",
5394        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
5395        "SampleAfterValue": "100003",
5396        "CounterHTOff": "0,1,2,3"
5397    },
5398    {
5399        "Offcore": "1",
5400        "EventCode": "0xB7, 0xBB",
5401        "UMask": "0x1",
5402        "BriefDescription": "TBD  TBD",
5403        "MSRValue": "0x0400100490",
5404        "Counter": "0,1,2,3",
5405        "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD",
5406        "MSRIndex": "0x1a6,0x1a7",
5407        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
5408        "SampleAfterValue": "100003",
5409        "CounterHTOff": "0,1,2,3"
5410    },
5411    {
5412        "Offcore": "1",
5413        "EventCode": "0xB7, 0xBB",
5414        "UMask": "0x1",
5415        "BriefDescription": "TBD  TBD",
5416        "MSRValue": "0x0800100490",
5417        "Counter": "0,1,2,3",
5418        "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWD",
5419        "MSRIndex": "0x1a6,0x1a7",
5420        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
5421        "SampleAfterValue": "100003",
5422        "CounterHTOff": "0,1,2,3"
5423    },
5424    {
5425        "Offcore": "1",
5426        "EventCode": "0xB7, 0xBB",
5427        "UMask": "0x1",
5428        "BriefDescription": "TBD  TBD",
5429        "MSRValue": "0x1000100490",
5430        "Counter": "0,1,2,3",
5431        "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_S.HITM_OTHER_CORE",
5432        "MSRIndex": "0x1a6,0x1a7",
5433        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
5434        "SampleAfterValue": "100003",
5435        "CounterHTOff": "0,1,2,3"
5436    },
5437    {
5438        "Offcore": "1",
5439        "EventCode": "0xB7, 0xBB",
5440        "UMask": "0x1",
5441        "BriefDescription": "TBD  TBD",
5442        "MSRValue": "0x3F80100490",
5443        "Counter": "0,1,2,3",
5444        "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_S.ANY_SNOOP",
5445        "MSRIndex": "0x1a6,0x1a7",
5446        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
5447        "SampleAfterValue": "100003",
5448        "CounterHTOff": "0,1,2,3"
5449    },
5450    {
5451        "Offcore": "1",
5452        "EventCode": "0xB7, 0xBB",
5453        "UMask": "0x1",
5454        "BriefDescription": "TBD",
5455        "MSRValue": "0x0080200490",
5456        "Counter": "0,1,2,3",
5457        "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_F.SNOOP_NONE",
5458        "MSRIndex": "0x1a6,0x1a7",
5459        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
5460        "SampleAfterValue": "100003",
5461        "CounterHTOff": "0,1,2,3"
5462    },
5463    {
5464        "Offcore": "1",
5465        "EventCode": "0xB7, 0xBB",
5466        "UMask": "0x1",
5467        "BriefDescription": "TBD  TBD",
5468        "MSRValue": "0x0100200490",
5469        "Counter": "0,1,2,3",
5470        "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDED",
5471        "MSRIndex": "0x1a6,0x1a7",
5472        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
5473        "SampleAfterValue": "100003",
5474        "CounterHTOff": "0,1,2,3"
5475    },
5476    {
5477        "Offcore": "1",
5478        "EventCode": "0xB7, 0xBB",
5479        "UMask": "0x1",
5480        "BriefDescription": "TBD",
5481        "MSRValue": "0x0200200490",
5482        "Counter": "0,1,2,3",
5483        "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_F.SNOOP_MISS",
5484        "MSRIndex": "0x1a6,0x1a7",
5485        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
5486        "SampleAfterValue": "100003",
5487        "CounterHTOff": "0,1,2,3"
5488    },
5489    {
5490        "Offcore": "1",
5491        "EventCode": "0xB7, 0xBB",
5492        "UMask": "0x1",
5493        "BriefDescription": "TBD  TBD",
5494        "MSRValue": "0x0400200490",
5495        "Counter": "0,1,2,3",
5496        "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD",
5497        "MSRIndex": "0x1a6,0x1a7",
5498        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
5499        "SampleAfterValue": "100003",
5500        "CounterHTOff": "0,1,2,3"
5501    },
5502    {
5503        "Offcore": "1",
5504        "EventCode": "0xB7, 0xBB",
5505        "UMask": "0x1",
5506        "BriefDescription": "TBD  TBD",
5507        "MSRValue": "0x0800200490",
5508        "Counter": "0,1,2,3",
5509        "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWD",
5510        "MSRIndex": "0x1a6,0x1a7",
5511        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
5512        "SampleAfterValue": "100003",
5513        "CounterHTOff": "0,1,2,3"
5514    },
5515    {
5516        "Offcore": "1",
5517        "EventCode": "0xB7, 0xBB",
5518        "UMask": "0x1",
5519        "BriefDescription": "TBD  TBD",
5520        "MSRValue": "0x1000200490",
5521        "Counter": "0,1,2,3",
5522        "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_F.HITM_OTHER_CORE",
5523        "MSRIndex": "0x1a6,0x1a7",
5524        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
5525        "SampleAfterValue": "100003",
5526        "CounterHTOff": "0,1,2,3"
5527    },
5528    {
5529        "Offcore": "1",
5530        "EventCode": "0xB7, 0xBB",
5531        "UMask": "0x1",
5532        "BriefDescription": "TBD  TBD",
5533        "MSRValue": "0x3F80200490",
5534        "Counter": "0,1,2,3",
5535        "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_F.ANY_SNOOP",
5536        "MSRIndex": "0x1a6,0x1a7",
5537        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
5538        "SampleAfterValue": "100003",
5539        "CounterHTOff": "0,1,2,3"
5540    },
5541    {
5542        "Offcore": "1",
5543        "EventCode": "0xB7, 0xBB",
5544        "UMask": "0x1",
5545        "BriefDescription": "TBD TBD",
5546        "MSRValue": "0x00803C0490",
5547        "Counter": "0,1,2,3",
5548        "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT.SNOOP_NONE",
5549        "MSRIndex": "0x1a6,0x1a7",
5550        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
5551        "SampleAfterValue": "100003",
5552        "CounterHTOff": "0,1,2,3"
5553    },
5554    {
5555        "Offcore": "1",
5556        "EventCode": "0xB7, 0xBB",
5557        "UMask": "0x1",
5558        "BriefDescription": "TBD TBD TBD",
5559        "MSRValue": "0x01003C0490",
5560        "Counter": "0,1,2,3",
5561        "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT.NO_SNOOP_NEEDED",
5562        "MSRIndex": "0x1a6,0x1a7",
5563        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
5564        "SampleAfterValue": "100003",
5565        "CounterHTOff": "0,1,2,3"
5566    },
5567    {
5568        "Offcore": "1",
5569        "EventCode": "0xB7, 0xBB",
5570        "UMask": "0x1",
5571        "BriefDescription": "TBD TBD",
5572        "MSRValue": "0x02003C0490",
5573        "Counter": "0,1,2,3",
5574        "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT.SNOOP_MISS",
5575        "MSRIndex": "0x1a6,0x1a7",
5576        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
5577        "SampleAfterValue": "100003",
5578        "CounterHTOff": "0,1,2,3"
5579    },
5580    {
5581        "Offcore": "1",
5582        "EventCode": "0xB7, 0xBB",
5583        "UMask": "0x1",
5584        "BriefDescription": "TBD TBD TBD",
5585        "MSRValue": "0x04003C0490",
5586        "Counter": "0,1,2,3",
5587        "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD",
5588        "MSRIndex": "0x1a6,0x1a7",
5589        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
5590        "SampleAfterValue": "100003",
5591        "CounterHTOff": "0,1,2,3"
5592    },
5593    {
5594        "Offcore": "1",
5595        "EventCode": "0xB7, 0xBB",
5596        "UMask": "0x1",
5597        "BriefDescription": "TBD TBD TBD",
5598        "MSRValue": "0x08003C0490",
5599        "Counter": "0,1,2,3",
5600        "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD",
5601        "MSRIndex": "0x1a6,0x1a7",
5602        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
5603        "SampleAfterValue": "100003",
5604        "CounterHTOff": "0,1,2,3"
5605    },
5606    {
5607        "Offcore": "1",
5608        "EventCode": "0xB7, 0xBB",
5609        "UMask": "0x1",
5610        "BriefDescription": "TBD TBD TBD",
5611        "MSRValue": "0x10003C0490",
5612        "Counter": "0,1,2,3",
5613        "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT.HITM_OTHER_CORE",
5614        "MSRIndex": "0x1a6,0x1a7",
5615        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
5616        "SampleAfterValue": "100003",
5617        "CounterHTOff": "0,1,2,3"
5618    },
5619    {
5620        "Offcore": "1",
5621        "EventCode": "0xB7, 0xBB",
5622        "UMask": "0x1",
5623        "BriefDescription": "TBD TBD TBD",
5624        "MSRValue": "0x3F803C0490",
5625        "Counter": "0,1,2,3",
5626        "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT.ANY_SNOOP",
5627        "MSRIndex": "0x1a6,0x1a7",
5628        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
5629        "SampleAfterValue": "100003",
5630        "CounterHTOff": "0,1,2,3"
5631    },
5632    {
5633        "Offcore": "1",
5634        "EventCode": "0xB7, 0xBB",
5635        "UMask": "0x1",
5636        "BriefDescription": "TBD",
5637        "MSRValue": "0x0080020120",
5638        "Counter": "0,1,2,3",
5639        "EventName": "OCR.ALL_PF_RFO.SUPPLIER_NONE.SNOOP_NONE",
5640        "MSRIndex": "0x1a6,0x1a7",
5641        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
5642        "SampleAfterValue": "100003",
5643        "CounterHTOff": "0,1,2,3"
5644    },
5645    {
5646        "Offcore": "1",
5647        "EventCode": "0xB7, 0xBB",
5648        "UMask": "0x1",
5649        "BriefDescription": "TBD  TBD",
5650        "MSRValue": "0x0100020120",
5651        "Counter": "0,1,2,3",
5652        "EventName": "OCR.ALL_PF_RFO.SUPPLIER_NONE.NO_SNOOP_NEEDED",
5653        "MSRIndex": "0x1a6,0x1a7",
5654        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
5655        "SampleAfterValue": "100003",
5656        "CounterHTOff": "0,1,2,3"
5657    },
5658    {
5659        "Offcore": "1",
5660        "EventCode": "0xB7, 0xBB",
5661        "UMask": "0x1",
5662        "BriefDescription": "TBD",
5663        "MSRValue": "0x0200020120",
5664        "Counter": "0,1,2,3",
5665        "EventName": "OCR.ALL_PF_RFO.SUPPLIER_NONE.SNOOP_MISS",
5666        "MSRIndex": "0x1a6,0x1a7",
5667        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
5668        "SampleAfterValue": "100003",
5669        "CounterHTOff": "0,1,2,3"
5670    },
5671    {
5672        "Offcore": "1",
5673        "EventCode": "0xB7, 0xBB",
5674        "UMask": "0x1",
5675        "BriefDescription": "TBD  TBD",
5676        "MSRValue": "0x0400020120",
5677        "Counter": "0,1,2,3",
5678        "EventName": "OCR.ALL_PF_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD",
5679        "MSRIndex": "0x1a6,0x1a7",
5680        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
5681        "SampleAfterValue": "100003",
5682        "CounterHTOff": "0,1,2,3"
5683    },
5684    {
5685        "Offcore": "1",
5686        "EventCode": "0xB7, 0xBB",
5687        "UMask": "0x1",
5688        "BriefDescription": "TBD  TBD",
5689        "MSRValue": "0x0800020120",
5690        "Counter": "0,1,2,3",
5691        "EventName": "OCR.ALL_PF_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_FWD",
5692        "MSRIndex": "0x1a6,0x1a7",
5693        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
5694        "SampleAfterValue": "100003",
5695        "CounterHTOff": "0,1,2,3"
5696    },
5697    {
5698        "Offcore": "1",
5699        "EventCode": "0xB7, 0xBB",
5700        "UMask": "0x1",
5701        "BriefDescription": "TBD  TBD",
5702        "MSRValue": "0x1000020120",
5703        "Counter": "0,1,2,3",
5704        "EventName": "OCR.ALL_PF_RFO.SUPPLIER_NONE.HITM_OTHER_CORE",
5705        "MSRIndex": "0x1a6,0x1a7",
5706        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
5707        "SampleAfterValue": "100003",
5708        "CounterHTOff": "0,1,2,3"
5709    },
5710    {
5711        "Offcore": "1",
5712        "EventCode": "0xB7, 0xBB",
5713        "UMask": "0x1",
5714        "BriefDescription": "TBD  TBD",
5715        "MSRValue": "0x3F80020120",
5716        "Counter": "0,1,2,3",
5717        "EventName": "OCR.ALL_PF_RFO.SUPPLIER_NONE.ANY_SNOOP",
5718        "MSRIndex": "0x1a6,0x1a7",
5719        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
5720        "SampleAfterValue": "100003",
5721        "CounterHTOff": "0,1,2,3"
5722    },
5723    {
5724        "Offcore": "1",
5725        "EventCode": "0xB7, 0xBB",
5726        "UMask": "0x1",
5727        "BriefDescription": "TBD",
5728        "MSRValue": "0x0080040120",
5729        "Counter": "0,1,2,3",
5730        "EventName": "OCR.ALL_PF_RFO.L3_HIT_M.SNOOP_NONE",
5731        "MSRIndex": "0x1a6,0x1a7",
5732        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
5733        "SampleAfterValue": "100003",
5734        "CounterHTOff": "0,1,2,3"
5735    },
5736    {
5737        "Offcore": "1",
5738        "EventCode": "0xB7, 0xBB",
5739        "UMask": "0x1",
5740        "BriefDescription": "TBD  TBD",
5741        "MSRValue": "0x0100040120",
5742        "Counter": "0,1,2,3",
5743        "EventName": "OCR.ALL_PF_RFO.L3_HIT_M.NO_SNOOP_NEEDED",
5744        "MSRIndex": "0x1a6,0x1a7",
5745        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
5746        "SampleAfterValue": "100003",
5747        "CounterHTOff": "0,1,2,3"
5748    },
5749    {
5750        "Offcore": "1",
5751        "EventCode": "0xB7, 0xBB",
5752        "UMask": "0x1",
5753        "BriefDescription": "TBD",
5754        "MSRValue": "0x0200040120",
5755        "Counter": "0,1,2,3",
5756        "EventName": "OCR.ALL_PF_RFO.L3_HIT_M.SNOOP_MISS",
5757        "MSRIndex": "0x1a6,0x1a7",
5758        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
5759        "SampleAfterValue": "100003",
5760        "CounterHTOff": "0,1,2,3"
5761    },
5762    {
5763        "Offcore": "1",
5764        "EventCode": "0xB7, 0xBB",
5765        "UMask": "0x1",
5766        "BriefDescription": "TBD  TBD",
5767        "MSRValue": "0x0400040120",
5768        "Counter": "0,1,2,3",
5769        "EventName": "OCR.ALL_PF_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWD",
5770        "MSRIndex": "0x1a6,0x1a7",
5771        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
5772        "SampleAfterValue": "100003",
5773        "CounterHTOff": "0,1,2,3"
5774    },
5775    {
5776        "Offcore": "1",
5777        "EventCode": "0xB7, 0xBB",
5778        "UMask": "0x1",
5779        "BriefDescription": "TBD  TBD",
5780        "MSRValue": "0x0800040120",
5781        "Counter": "0,1,2,3",
5782        "EventName": "OCR.ALL_PF_RFO.L3_HIT_M.HIT_OTHER_CORE_FWD",
5783        "MSRIndex": "0x1a6,0x1a7",
5784        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
5785        "SampleAfterValue": "100003",
5786        "CounterHTOff": "0,1,2,3"
5787    },
5788    {
5789        "Offcore": "1",
5790        "EventCode": "0xB7, 0xBB",
5791        "UMask": "0x1",
5792        "BriefDescription": "TBD  TBD",
5793        "MSRValue": "0x1000040120",
5794        "Counter": "0,1,2,3",
5795        "EventName": "OCR.ALL_PF_RFO.L3_HIT_M.HITM_OTHER_CORE",
5796        "MSRIndex": "0x1a6,0x1a7",
5797        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
5798        "SampleAfterValue": "100003",
5799        "CounterHTOff": "0,1,2,3"
5800    },
5801    {
5802        "Offcore": "1",
5803        "EventCode": "0xB7, 0xBB",
5804        "UMask": "0x1",
5805        "BriefDescription": "TBD  TBD",
5806        "MSRValue": "0x3F80040120",
5807        "Counter": "0,1,2,3",
5808        "EventName": "OCR.ALL_PF_RFO.L3_HIT_M.ANY_SNOOP",
5809        "MSRIndex": "0x1a6,0x1a7",
5810        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
5811        "SampleAfterValue": "100003",
5812        "CounterHTOff": "0,1,2,3"
5813    },
5814    {
5815        "Offcore": "1",
5816        "EventCode": "0xB7, 0xBB",
5817        "UMask": "0x1",
5818        "BriefDescription": "TBD",
5819        "MSRValue": "0x0080080120",
5820        "Counter": "0,1,2,3",
5821        "EventName": "OCR.ALL_PF_RFO.L3_HIT_E.SNOOP_NONE",
5822        "MSRIndex": "0x1a6,0x1a7",
5823        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
5824        "SampleAfterValue": "100003",
5825        "CounterHTOff": "0,1,2,3"
5826    },
5827    {
5828        "Offcore": "1",
5829        "EventCode": "0xB7, 0xBB",
5830        "UMask": "0x1",
5831        "BriefDescription": "TBD  TBD",
5832        "MSRValue": "0x0100080120",
5833        "Counter": "0,1,2,3",
5834        "EventName": "OCR.ALL_PF_RFO.L3_HIT_E.NO_SNOOP_NEEDED",
5835        "MSRIndex": "0x1a6,0x1a7",
5836        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
5837        "SampleAfterValue": "100003",
5838        "CounterHTOff": "0,1,2,3"
5839    },
5840    {
5841        "Offcore": "1",
5842        "EventCode": "0xB7, 0xBB",
5843        "UMask": "0x1",
5844        "BriefDescription": "TBD",
5845        "MSRValue": "0x0200080120",
5846        "Counter": "0,1,2,3",
5847        "EventName": "OCR.ALL_PF_RFO.L3_HIT_E.SNOOP_MISS",
5848        "MSRIndex": "0x1a6,0x1a7",
5849        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
5850        "SampleAfterValue": "100003",
5851        "CounterHTOff": "0,1,2,3"
5852    },
5853    {
5854        "Offcore": "1",
5855        "EventCode": "0xB7, 0xBB",
5856        "UMask": "0x1",
5857        "BriefDescription": "TBD  TBD",
5858        "MSRValue": "0x0400080120",
5859        "Counter": "0,1,2,3",
5860        "EventName": "OCR.ALL_PF_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWD",
5861        "MSRIndex": "0x1a6,0x1a7",
5862        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
5863        "SampleAfterValue": "100003",
5864        "CounterHTOff": "0,1,2,3"
5865    },
5866    {
5867        "Offcore": "1",
5868        "EventCode": "0xB7, 0xBB",
5869        "UMask": "0x1",
5870        "BriefDescription": "TBD  TBD",
5871        "MSRValue": "0x0800080120",
5872        "Counter": "0,1,2,3",
5873        "EventName": "OCR.ALL_PF_RFO.L3_HIT_E.HIT_OTHER_CORE_FWD",
5874        "MSRIndex": "0x1a6,0x1a7",
5875        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
5876        "SampleAfterValue": "100003",
5877        "CounterHTOff": "0,1,2,3"
5878    },
5879    {
5880        "Offcore": "1",
5881        "EventCode": "0xB7, 0xBB",
5882        "UMask": "0x1",
5883        "BriefDescription": "TBD  TBD",
5884        "MSRValue": "0x1000080120",
5885        "Counter": "0,1,2,3",
5886        "EventName": "OCR.ALL_PF_RFO.L3_HIT_E.HITM_OTHER_CORE",
5887        "MSRIndex": "0x1a6,0x1a7",
5888        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
5889        "SampleAfterValue": "100003",
5890        "CounterHTOff": "0,1,2,3"
5891    },
5892    {
5893        "Offcore": "1",
5894        "EventCode": "0xB7, 0xBB",
5895        "UMask": "0x1",
5896        "BriefDescription": "TBD  TBD",
5897        "MSRValue": "0x3F80080120",
5898        "Counter": "0,1,2,3",
5899        "EventName": "OCR.ALL_PF_RFO.L3_HIT_E.ANY_SNOOP",
5900        "MSRIndex": "0x1a6,0x1a7",
5901        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
5902        "SampleAfterValue": "100003",
5903        "CounterHTOff": "0,1,2,3"
5904    },
5905    {
5906        "Offcore": "1",
5907        "EventCode": "0xB7, 0xBB",
5908        "UMask": "0x1",
5909        "BriefDescription": "TBD",
5910        "MSRValue": "0x0080100120",
5911        "Counter": "0,1,2,3",
5912        "EventName": "OCR.ALL_PF_RFO.L3_HIT_S.SNOOP_NONE",
5913        "MSRIndex": "0x1a6,0x1a7",
5914        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
5915        "SampleAfterValue": "100003",
5916        "CounterHTOff": "0,1,2,3"
5917    },
5918    {
5919        "Offcore": "1",
5920        "EventCode": "0xB7, 0xBB",
5921        "UMask": "0x1",
5922        "BriefDescription": "TBD  TBD",
5923        "MSRValue": "0x0100100120",
5924        "Counter": "0,1,2,3",
5925        "EventName": "OCR.ALL_PF_RFO.L3_HIT_S.NO_SNOOP_NEEDED",
5926        "MSRIndex": "0x1a6,0x1a7",
5927        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
5928        "SampleAfterValue": "100003",
5929        "CounterHTOff": "0,1,2,3"
5930    },
5931    {
5932        "Offcore": "1",
5933        "EventCode": "0xB7, 0xBB",
5934        "UMask": "0x1",
5935        "BriefDescription": "TBD",
5936        "MSRValue": "0x0200100120",
5937        "Counter": "0,1,2,3",
5938        "EventName": "OCR.ALL_PF_RFO.L3_HIT_S.SNOOP_MISS",
5939        "MSRIndex": "0x1a6,0x1a7",
5940        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
5941        "SampleAfterValue": "100003",
5942        "CounterHTOff": "0,1,2,3"
5943    },
5944    {
5945        "Offcore": "1",
5946        "EventCode": "0xB7, 0xBB",
5947        "UMask": "0x1",
5948        "BriefDescription": "TBD  TBD",
5949        "MSRValue": "0x0400100120",
5950        "Counter": "0,1,2,3",
5951        "EventName": "OCR.ALL_PF_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWD",
5952        "MSRIndex": "0x1a6,0x1a7",
5953        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
5954        "SampleAfterValue": "100003",
5955        "CounterHTOff": "0,1,2,3"
5956    },
5957    {
5958        "Offcore": "1",
5959        "EventCode": "0xB7, 0xBB",
5960        "UMask": "0x1",
5961        "BriefDescription": "TBD  TBD",
5962        "MSRValue": "0x0800100120",
5963        "Counter": "0,1,2,3",
5964        "EventName": "OCR.ALL_PF_RFO.L3_HIT_S.HIT_OTHER_CORE_FWD",
5965        "MSRIndex": "0x1a6,0x1a7",
5966        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
5967        "SampleAfterValue": "100003",
5968        "CounterHTOff": "0,1,2,3"
5969    },
5970    {
5971        "Offcore": "1",
5972        "EventCode": "0xB7, 0xBB",
5973        "UMask": "0x1",
5974        "BriefDescription": "TBD  TBD",
5975        "MSRValue": "0x1000100120",
5976        "Counter": "0,1,2,3",
5977        "EventName": "OCR.ALL_PF_RFO.L3_HIT_S.HITM_OTHER_CORE",
5978        "MSRIndex": "0x1a6,0x1a7",
5979        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
5980        "SampleAfterValue": "100003",
5981        "CounterHTOff": "0,1,2,3"
5982    },
5983    {
5984        "Offcore": "1",
5985        "EventCode": "0xB7, 0xBB",
5986        "UMask": "0x1",
5987        "BriefDescription": "TBD  TBD",
5988        "MSRValue": "0x3F80100120",
5989        "Counter": "0,1,2,3",
5990        "EventName": "OCR.ALL_PF_RFO.L3_HIT_S.ANY_SNOOP",
5991        "MSRIndex": "0x1a6,0x1a7",
5992        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
5993        "SampleAfterValue": "100003",
5994        "CounterHTOff": "0,1,2,3"
5995    },
5996    {
5997        "Offcore": "1",
5998        "EventCode": "0xB7, 0xBB",
5999        "UMask": "0x1",
6000        "BriefDescription": "TBD",
6001        "MSRValue": "0x0080200120",
6002        "Counter": "0,1,2,3",
6003        "EventName": "OCR.ALL_PF_RFO.L3_HIT_F.SNOOP_NONE",
6004        "MSRIndex": "0x1a6,0x1a7",
6005        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
6006        "SampleAfterValue": "100003",
6007        "CounterHTOff": "0,1,2,3"
6008    },
6009    {
6010        "Offcore": "1",
6011        "EventCode": "0xB7, 0xBB",
6012        "UMask": "0x1",
6013        "BriefDescription": "TBD  TBD",
6014        "MSRValue": "0x0100200120",
6015        "Counter": "0,1,2,3",
6016        "EventName": "OCR.ALL_PF_RFO.L3_HIT_F.NO_SNOOP_NEEDED",
6017        "MSRIndex": "0x1a6,0x1a7",
6018        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
6019        "SampleAfterValue": "100003",
6020        "CounterHTOff": "0,1,2,3"
6021    },
6022    {
6023        "Offcore": "1",
6024        "EventCode": "0xB7, 0xBB",
6025        "UMask": "0x1",
6026        "BriefDescription": "TBD",
6027        "MSRValue": "0x0200200120",
6028        "Counter": "0,1,2,3",
6029        "EventName": "OCR.ALL_PF_RFO.L3_HIT_F.SNOOP_MISS",
6030        "MSRIndex": "0x1a6,0x1a7",
6031        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
6032        "SampleAfterValue": "100003",
6033        "CounterHTOff": "0,1,2,3"
6034    },
6035    {
6036        "Offcore": "1",
6037        "EventCode": "0xB7, 0xBB",
6038        "UMask": "0x1",
6039        "BriefDescription": "TBD  TBD",
6040        "MSRValue": "0x0400200120",
6041        "Counter": "0,1,2,3",
6042        "EventName": "OCR.ALL_PF_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWD",
6043        "MSRIndex": "0x1a6,0x1a7",
6044        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
6045        "SampleAfterValue": "100003",
6046        "CounterHTOff": "0,1,2,3"
6047    },
6048    {
6049        "Offcore": "1",
6050        "EventCode": "0xB7, 0xBB",
6051        "UMask": "0x1",
6052        "BriefDescription": "TBD  TBD",
6053        "MSRValue": "0x0800200120",
6054        "Counter": "0,1,2,3",
6055        "EventName": "OCR.ALL_PF_RFO.L3_HIT_F.HIT_OTHER_CORE_FWD",
6056        "MSRIndex": "0x1a6,0x1a7",
6057        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
6058        "SampleAfterValue": "100003",
6059        "CounterHTOff": "0,1,2,3"
6060    },
6061    {
6062        "Offcore": "1",
6063        "EventCode": "0xB7, 0xBB",
6064        "UMask": "0x1",
6065        "BriefDescription": "TBD  TBD",
6066        "MSRValue": "0x1000200120",
6067        "Counter": "0,1,2,3",
6068        "EventName": "OCR.ALL_PF_RFO.L3_HIT_F.HITM_OTHER_CORE",
6069        "MSRIndex": "0x1a6,0x1a7",
6070        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
6071        "SampleAfterValue": "100003",
6072        "CounterHTOff": "0,1,2,3"
6073    },
6074    {
6075        "Offcore": "1",
6076        "EventCode": "0xB7, 0xBB",
6077        "UMask": "0x1",
6078        "BriefDescription": "TBD  TBD",
6079        "MSRValue": "0x3F80200120",
6080        "Counter": "0,1,2,3",
6081        "EventName": "OCR.ALL_PF_RFO.L3_HIT_F.ANY_SNOOP",
6082        "MSRIndex": "0x1a6,0x1a7",
6083        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
6084        "SampleAfterValue": "100003",
6085        "CounterHTOff": "0,1,2,3"
6086    },
6087    {
6088        "Offcore": "1",
6089        "EventCode": "0xB7, 0xBB",
6090        "UMask": "0x1",
6091        "BriefDescription": "TBD TBD",
6092        "MSRValue": "0x00803C0120",
6093        "Counter": "0,1,2,3",
6094        "EventName": "OCR.ALL_PF_RFO.L3_HIT.SNOOP_NONE",
6095        "MSRIndex": "0x1a6,0x1a7",
6096        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
6097        "SampleAfterValue": "100003",
6098        "CounterHTOff": "0,1,2,3"
6099    },
6100    {
6101        "Offcore": "1",
6102        "EventCode": "0xB7, 0xBB",
6103        "UMask": "0x1",
6104        "BriefDescription": "TBD TBD TBD",
6105        "MSRValue": "0x01003C0120",
6106        "Counter": "0,1,2,3",
6107        "EventName": "OCR.ALL_PF_RFO.L3_HIT.NO_SNOOP_NEEDED",
6108        "MSRIndex": "0x1a6,0x1a7",
6109        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
6110        "SampleAfterValue": "100003",
6111        "CounterHTOff": "0,1,2,3"
6112    },
6113    {
6114        "Offcore": "1",
6115        "EventCode": "0xB7, 0xBB",
6116        "UMask": "0x1",
6117        "BriefDescription": "TBD TBD",
6118        "MSRValue": "0x02003C0120",
6119        "Counter": "0,1,2,3",
6120        "EventName": "OCR.ALL_PF_RFO.L3_HIT.SNOOP_MISS",
6121        "MSRIndex": "0x1a6,0x1a7",
6122        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
6123        "SampleAfterValue": "100003",
6124        "CounterHTOff": "0,1,2,3"
6125    },
6126    {
6127        "Offcore": "1",
6128        "EventCode": "0xB7, 0xBB",
6129        "UMask": "0x1",
6130        "BriefDescription": "TBD TBD TBD",
6131        "MSRValue": "0x04003C0120",
6132        "Counter": "0,1,2,3",
6133        "EventName": "OCR.ALL_PF_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD",
6134        "MSRIndex": "0x1a6,0x1a7",
6135        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
6136        "SampleAfterValue": "100003",
6137        "CounterHTOff": "0,1,2,3"
6138    },
6139    {
6140        "Offcore": "1",
6141        "EventCode": "0xB7, 0xBB",
6142        "UMask": "0x1",
6143        "BriefDescription": "TBD TBD TBD",
6144        "MSRValue": "0x08003C0120",
6145        "Counter": "0,1,2,3",
6146        "EventName": "OCR.ALL_PF_RFO.L3_HIT.HIT_OTHER_CORE_FWD",
6147        "MSRIndex": "0x1a6,0x1a7",
6148        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
6149        "SampleAfterValue": "100003",
6150        "CounterHTOff": "0,1,2,3"
6151    },
6152    {
6153        "Offcore": "1",
6154        "EventCode": "0xB7, 0xBB",
6155        "UMask": "0x1",
6156        "BriefDescription": "TBD TBD TBD",
6157        "MSRValue": "0x10003C0120",
6158        "Counter": "0,1,2,3",
6159        "EventName": "OCR.ALL_PF_RFO.L3_HIT.HITM_OTHER_CORE",
6160        "MSRIndex": "0x1a6,0x1a7",
6161        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
6162        "SampleAfterValue": "100003",
6163        "CounterHTOff": "0,1,2,3"
6164    },
6165    {
6166        "Offcore": "1",
6167        "EventCode": "0xB7, 0xBB",
6168        "UMask": "0x1",
6169        "BriefDescription": "TBD TBD TBD",
6170        "MSRValue": "0x3F803C0120",
6171        "Counter": "0,1,2,3",
6172        "EventName": "OCR.ALL_PF_RFO.L3_HIT.ANY_SNOOP",
6173        "MSRIndex": "0x1a6,0x1a7",
6174        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
6175        "SampleAfterValue": "100003",
6176        "CounterHTOff": "0,1,2,3"
6177    },
6178    {
6179        "Offcore": "1",
6180        "EventCode": "0xB7, 0xBB",
6181        "UMask": "0x1",
6182        "BriefDescription": "TBD",
6183        "MSRValue": "0x0080020491",
6184        "Counter": "0,1,2,3",
6185        "EventName": "OCR.ALL_DATA_RD.SUPPLIER_NONE.SNOOP_NONE",
6186        "MSRIndex": "0x1a6,0x1a7",
6187        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
6188        "SampleAfterValue": "100003",
6189        "CounterHTOff": "0,1,2,3"
6190    },
6191    {
6192        "Offcore": "1",
6193        "EventCode": "0xB7, 0xBB",
6194        "UMask": "0x1",
6195        "BriefDescription": "TBD  TBD",
6196        "MSRValue": "0x0100020491",
6197        "Counter": "0,1,2,3",
6198        "EventName": "OCR.ALL_DATA_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED",
6199        "MSRIndex": "0x1a6,0x1a7",
6200        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
6201        "SampleAfterValue": "100003",
6202        "CounterHTOff": "0,1,2,3"
6203    },
6204    {
6205        "Offcore": "1",
6206        "EventCode": "0xB7, 0xBB",
6207        "UMask": "0x1",
6208        "BriefDescription": "TBD",
6209        "MSRValue": "0x0200020491",
6210        "Counter": "0,1,2,3",
6211        "EventName": "OCR.ALL_DATA_RD.SUPPLIER_NONE.SNOOP_MISS",
6212        "MSRIndex": "0x1a6,0x1a7",
6213        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
6214        "SampleAfterValue": "100003",
6215        "CounterHTOff": "0,1,2,3"
6216    },
6217    {
6218        "Offcore": "1",
6219        "EventCode": "0xB7, 0xBB",
6220        "UMask": "0x1",
6221        "BriefDescription": "TBD  TBD",
6222        "MSRValue": "0x0400020491",
6223        "Counter": "0,1,2,3",
6224        "EventName": "OCR.ALL_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD",
6225        "MSRIndex": "0x1a6,0x1a7",
6226        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
6227        "SampleAfterValue": "100003",
6228        "CounterHTOff": "0,1,2,3"
6229    },
6230    {
6231        "Offcore": "1",
6232        "EventCode": "0xB7, 0xBB",
6233        "UMask": "0x1",
6234        "BriefDescription": "TBD  TBD",
6235        "MSRValue": "0x0800020491",
6236        "Counter": "0,1,2,3",
6237        "EventName": "OCR.ALL_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD",
6238        "MSRIndex": "0x1a6,0x1a7",
6239        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
6240        "SampleAfterValue": "100003",
6241        "CounterHTOff": "0,1,2,3"
6242    },
6243    {
6244        "Offcore": "1",
6245        "EventCode": "0xB7, 0xBB",
6246        "UMask": "0x1",
6247        "BriefDescription": "TBD  TBD",
6248        "MSRValue": "0x1000020491",
6249        "Counter": "0,1,2,3",
6250        "EventName": "OCR.ALL_DATA_RD.SUPPLIER_NONE.HITM_OTHER_CORE",
6251        "MSRIndex": "0x1a6,0x1a7",
6252        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
6253        "SampleAfterValue": "100003",
6254        "CounterHTOff": "0,1,2,3"
6255    },
6256    {
6257        "Offcore": "1",
6258        "EventCode": "0xB7, 0xBB",
6259        "UMask": "0x1",
6260        "BriefDescription": "TBD  TBD",
6261        "MSRValue": "0x3F80020491",
6262        "Counter": "0,1,2,3",
6263        "EventName": "OCR.ALL_DATA_RD.SUPPLIER_NONE.ANY_SNOOP",
6264        "MSRIndex": "0x1a6,0x1a7",
6265        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
6266        "SampleAfterValue": "100003",
6267        "CounterHTOff": "0,1,2,3"
6268    },
6269    {
6270        "Offcore": "1",
6271        "EventCode": "0xB7, 0xBB",
6272        "UMask": "0x1",
6273        "BriefDescription": "TBD",
6274        "MSRValue": "0x0080040491",
6275        "Counter": "0,1,2,3",
6276        "EventName": "OCR.ALL_DATA_RD.L3_HIT_M.SNOOP_NONE",
6277        "MSRIndex": "0x1a6,0x1a7",
6278        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
6279        "SampleAfterValue": "100003",
6280        "CounterHTOff": "0,1,2,3"
6281    },
6282    {
6283        "Offcore": "1",
6284        "EventCode": "0xB7, 0xBB",
6285        "UMask": "0x1",
6286        "BriefDescription": "TBD  TBD",
6287        "MSRValue": "0x0100040491",
6288        "Counter": "0,1,2,3",
6289        "EventName": "OCR.ALL_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDED",
6290        "MSRIndex": "0x1a6,0x1a7",
6291        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
6292        "SampleAfterValue": "100003",
6293        "CounterHTOff": "0,1,2,3"
6294    },
6295    {
6296        "Offcore": "1",
6297        "EventCode": "0xB7, 0xBB",
6298        "UMask": "0x1",
6299        "BriefDescription": "TBD",
6300        "MSRValue": "0x0200040491",
6301        "Counter": "0,1,2,3",
6302        "EventName": "OCR.ALL_DATA_RD.L3_HIT_M.SNOOP_MISS",
6303        "MSRIndex": "0x1a6,0x1a7",
6304        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
6305        "SampleAfterValue": "100003",
6306        "CounterHTOff": "0,1,2,3"
6307    },
6308    {
6309        "Offcore": "1",
6310        "EventCode": "0xB7, 0xBB",
6311        "UMask": "0x1",
6312        "BriefDescription": "TBD  TBD",
6313        "MSRValue": "0x0400040491",
6314        "Counter": "0,1,2,3",
6315        "EventName": "OCR.ALL_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD",
6316        "MSRIndex": "0x1a6,0x1a7",
6317        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
6318        "SampleAfterValue": "100003",
6319        "CounterHTOff": "0,1,2,3"
6320    },
6321    {
6322        "Offcore": "1",
6323        "EventCode": "0xB7, 0xBB",
6324        "UMask": "0x1",
6325        "BriefDescription": "TBD  TBD",
6326        "MSRValue": "0x0800040491",
6327        "Counter": "0,1,2,3",
6328        "EventName": "OCR.ALL_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWD",
6329        "MSRIndex": "0x1a6,0x1a7",
6330        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
6331        "SampleAfterValue": "100003",
6332        "CounterHTOff": "0,1,2,3"
6333    },
6334    {
6335        "Offcore": "1",
6336        "EventCode": "0xB7, 0xBB",
6337        "UMask": "0x1",
6338        "BriefDescription": "TBD  TBD",
6339        "MSRValue": "0x1000040491",
6340        "Counter": "0,1,2,3",
6341        "EventName": "OCR.ALL_DATA_RD.L3_HIT_M.HITM_OTHER_CORE",
6342        "MSRIndex": "0x1a6,0x1a7",
6343        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
6344        "SampleAfterValue": "100003",
6345        "CounterHTOff": "0,1,2,3"
6346    },
6347    {
6348        "Offcore": "1",
6349        "EventCode": "0xB7, 0xBB",
6350        "UMask": "0x1",
6351        "BriefDescription": "TBD  TBD",
6352        "MSRValue": "0x3F80040491",
6353        "Counter": "0,1,2,3",
6354        "EventName": "OCR.ALL_DATA_RD.L3_HIT_M.ANY_SNOOP",
6355        "MSRIndex": "0x1a6,0x1a7",
6356        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
6357        "SampleAfterValue": "100003",
6358        "CounterHTOff": "0,1,2,3"
6359    },
6360    {
6361        "Offcore": "1",
6362        "EventCode": "0xB7, 0xBB",
6363        "UMask": "0x1",
6364        "BriefDescription": "TBD",
6365        "MSRValue": "0x0080080491",
6366        "Counter": "0,1,2,3",
6367        "EventName": "OCR.ALL_DATA_RD.L3_HIT_E.SNOOP_NONE",
6368        "MSRIndex": "0x1a6,0x1a7",
6369        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
6370        "SampleAfterValue": "100003",
6371        "CounterHTOff": "0,1,2,3"
6372    },
6373    {
6374        "Offcore": "1",
6375        "EventCode": "0xB7, 0xBB",
6376        "UMask": "0x1",
6377        "BriefDescription": "TBD  TBD",
6378        "MSRValue": "0x0100080491",
6379        "Counter": "0,1,2,3",
6380        "EventName": "OCR.ALL_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDED",
6381        "MSRIndex": "0x1a6,0x1a7",
6382        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
6383        "SampleAfterValue": "100003",
6384        "CounterHTOff": "0,1,2,3"
6385    },
6386    {
6387        "Offcore": "1",
6388        "EventCode": "0xB7, 0xBB",
6389        "UMask": "0x1",
6390        "BriefDescription": "TBD",
6391        "MSRValue": "0x0200080491",
6392        "Counter": "0,1,2,3",
6393        "EventName": "OCR.ALL_DATA_RD.L3_HIT_E.SNOOP_MISS",
6394        "MSRIndex": "0x1a6,0x1a7",
6395        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
6396        "SampleAfterValue": "100003",
6397        "CounterHTOff": "0,1,2,3"
6398    },
6399    {
6400        "Offcore": "1",
6401        "EventCode": "0xB7, 0xBB",
6402        "UMask": "0x1",
6403        "BriefDescription": "TBD  TBD",
6404        "MSRValue": "0x0400080491",
6405        "Counter": "0,1,2,3",
6406        "EventName": "OCR.ALL_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD",
6407        "MSRIndex": "0x1a6,0x1a7",
6408        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
6409        "SampleAfterValue": "100003",
6410        "CounterHTOff": "0,1,2,3"
6411    },
6412    {
6413        "Offcore": "1",
6414        "EventCode": "0xB7, 0xBB",
6415        "UMask": "0x1",
6416        "BriefDescription": "TBD  TBD",
6417        "MSRValue": "0x0800080491",
6418        "Counter": "0,1,2,3",
6419        "EventName": "OCR.ALL_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWD",
6420        "MSRIndex": "0x1a6,0x1a7",
6421        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
6422        "SampleAfterValue": "100003",
6423        "CounterHTOff": "0,1,2,3"
6424    },
6425    {
6426        "Offcore": "1",
6427        "EventCode": "0xB7, 0xBB",
6428        "UMask": "0x1",
6429        "BriefDescription": "TBD  TBD",
6430        "MSRValue": "0x1000080491",
6431        "Counter": "0,1,2,3",
6432        "EventName": "OCR.ALL_DATA_RD.L3_HIT_E.HITM_OTHER_CORE",
6433        "MSRIndex": "0x1a6,0x1a7",
6434        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
6435        "SampleAfterValue": "100003",
6436        "CounterHTOff": "0,1,2,3"
6437    },
6438    {
6439        "Offcore": "1",
6440        "EventCode": "0xB7, 0xBB",
6441        "UMask": "0x1",
6442        "BriefDescription": "TBD  TBD",
6443        "MSRValue": "0x3F80080491",
6444        "Counter": "0,1,2,3",
6445        "EventName": "OCR.ALL_DATA_RD.L3_HIT_E.ANY_SNOOP",
6446        "MSRIndex": "0x1a6,0x1a7",
6447        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
6448        "SampleAfterValue": "100003",
6449        "CounterHTOff": "0,1,2,3"
6450    },
6451    {
6452        "Offcore": "1",
6453        "EventCode": "0xB7, 0xBB",
6454        "UMask": "0x1",
6455        "BriefDescription": "TBD",
6456        "MSRValue": "0x0080100491",
6457        "Counter": "0,1,2,3",
6458        "EventName": "OCR.ALL_DATA_RD.L3_HIT_S.SNOOP_NONE",
6459        "MSRIndex": "0x1a6,0x1a7",
6460        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
6461        "SampleAfterValue": "100003",
6462        "CounterHTOff": "0,1,2,3"
6463    },
6464    {
6465        "Offcore": "1",
6466        "EventCode": "0xB7, 0xBB",
6467        "UMask": "0x1",
6468        "BriefDescription": "TBD  TBD",
6469        "MSRValue": "0x0100100491",
6470        "Counter": "0,1,2,3",
6471        "EventName": "OCR.ALL_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDED",
6472        "MSRIndex": "0x1a6,0x1a7",
6473        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
6474        "SampleAfterValue": "100003",
6475        "CounterHTOff": "0,1,2,3"
6476    },
6477    {
6478        "Offcore": "1",
6479        "EventCode": "0xB7, 0xBB",
6480        "UMask": "0x1",
6481        "BriefDescription": "TBD",
6482        "MSRValue": "0x0200100491",
6483        "Counter": "0,1,2,3",
6484        "EventName": "OCR.ALL_DATA_RD.L3_HIT_S.SNOOP_MISS",
6485        "MSRIndex": "0x1a6,0x1a7",
6486        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
6487        "SampleAfterValue": "100003",
6488        "CounterHTOff": "0,1,2,3"
6489    },
6490    {
6491        "Offcore": "1",
6492        "EventCode": "0xB7, 0xBB",
6493        "UMask": "0x1",
6494        "BriefDescription": "TBD  TBD",
6495        "MSRValue": "0x0400100491",
6496        "Counter": "0,1,2,3",
6497        "EventName": "OCR.ALL_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD",
6498        "MSRIndex": "0x1a6,0x1a7",
6499        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
6500        "SampleAfterValue": "100003",
6501        "CounterHTOff": "0,1,2,3"
6502    },
6503    {
6504        "Offcore": "1",
6505        "EventCode": "0xB7, 0xBB",
6506        "UMask": "0x1",
6507        "BriefDescription": "TBD  TBD",
6508        "MSRValue": "0x0800100491",
6509        "Counter": "0,1,2,3",
6510        "EventName": "OCR.ALL_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWD",
6511        "MSRIndex": "0x1a6,0x1a7",
6512        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
6513        "SampleAfterValue": "100003",
6514        "CounterHTOff": "0,1,2,3"
6515    },
6516    {
6517        "Offcore": "1",
6518        "EventCode": "0xB7, 0xBB",
6519        "UMask": "0x1",
6520        "BriefDescription": "TBD  TBD",
6521        "MSRValue": "0x1000100491",
6522        "Counter": "0,1,2,3",
6523        "EventName": "OCR.ALL_DATA_RD.L3_HIT_S.HITM_OTHER_CORE",
6524        "MSRIndex": "0x1a6,0x1a7",
6525        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
6526        "SampleAfterValue": "100003",
6527        "CounterHTOff": "0,1,2,3"
6528    },
6529    {
6530        "Offcore": "1",
6531        "EventCode": "0xB7, 0xBB",
6532        "UMask": "0x1",
6533        "BriefDescription": "TBD  TBD",
6534        "MSRValue": "0x3F80100491",
6535        "Counter": "0,1,2,3",
6536        "EventName": "OCR.ALL_DATA_RD.L3_HIT_S.ANY_SNOOP",
6537        "MSRIndex": "0x1a6,0x1a7",
6538        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
6539        "SampleAfterValue": "100003",
6540        "CounterHTOff": "0,1,2,3"
6541    },
6542    {
6543        "Offcore": "1",
6544        "EventCode": "0xB7, 0xBB",
6545        "UMask": "0x1",
6546        "BriefDescription": "TBD",
6547        "MSRValue": "0x0080200491",
6548        "Counter": "0,1,2,3",
6549        "EventName": "OCR.ALL_DATA_RD.L3_HIT_F.SNOOP_NONE",
6550        "MSRIndex": "0x1a6,0x1a7",
6551        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
6552        "SampleAfterValue": "100003",
6553        "CounterHTOff": "0,1,2,3"
6554    },
6555    {
6556        "Offcore": "1",
6557        "EventCode": "0xB7, 0xBB",
6558        "UMask": "0x1",
6559        "BriefDescription": "TBD  TBD",
6560        "MSRValue": "0x0100200491",
6561        "Counter": "0,1,2,3",
6562        "EventName": "OCR.ALL_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDED",
6563        "MSRIndex": "0x1a6,0x1a7",
6564        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
6565        "SampleAfterValue": "100003",
6566        "CounterHTOff": "0,1,2,3"
6567    },
6568    {
6569        "Offcore": "1",
6570        "EventCode": "0xB7, 0xBB",
6571        "UMask": "0x1",
6572        "BriefDescription": "TBD",
6573        "MSRValue": "0x0200200491",
6574        "Counter": "0,1,2,3",
6575        "EventName": "OCR.ALL_DATA_RD.L3_HIT_F.SNOOP_MISS",
6576        "MSRIndex": "0x1a6,0x1a7",
6577        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
6578        "SampleAfterValue": "100003",
6579        "CounterHTOff": "0,1,2,3"
6580    },
6581    {
6582        "Offcore": "1",
6583        "EventCode": "0xB7, 0xBB",
6584        "UMask": "0x1",
6585        "BriefDescription": "TBD  TBD",
6586        "MSRValue": "0x0400200491",
6587        "Counter": "0,1,2,3",
6588        "EventName": "OCR.ALL_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD",
6589        "MSRIndex": "0x1a6,0x1a7",
6590        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
6591        "SampleAfterValue": "100003",
6592        "CounterHTOff": "0,1,2,3"
6593    },
6594    {
6595        "Offcore": "1",
6596        "EventCode": "0xB7, 0xBB",
6597        "UMask": "0x1",
6598        "BriefDescription": "TBD  TBD",
6599        "MSRValue": "0x0800200491",
6600        "Counter": "0,1,2,3",
6601        "EventName": "OCR.ALL_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWD",
6602        "MSRIndex": "0x1a6,0x1a7",
6603        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
6604        "SampleAfterValue": "100003",
6605        "CounterHTOff": "0,1,2,3"
6606    },
6607    {
6608        "Offcore": "1",
6609        "EventCode": "0xB7, 0xBB",
6610        "UMask": "0x1",
6611        "BriefDescription": "TBD  TBD",
6612        "MSRValue": "0x1000200491",
6613        "Counter": "0,1,2,3",
6614        "EventName": "OCR.ALL_DATA_RD.L3_HIT_F.HITM_OTHER_CORE",
6615        "MSRIndex": "0x1a6,0x1a7",
6616        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
6617        "SampleAfterValue": "100003",
6618        "CounterHTOff": "0,1,2,3"
6619    },
6620    {
6621        "Offcore": "1",
6622        "EventCode": "0xB7, 0xBB",
6623        "UMask": "0x1",
6624        "BriefDescription": "TBD  TBD",
6625        "MSRValue": "0x3F80200491",
6626        "Counter": "0,1,2,3",
6627        "EventName": "OCR.ALL_DATA_RD.L3_HIT_F.ANY_SNOOP",
6628        "MSRIndex": "0x1a6,0x1a7",
6629        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
6630        "SampleAfterValue": "100003",
6631        "CounterHTOff": "0,1,2,3"
6632    },
6633    {
6634        "Offcore": "1",
6635        "EventCode": "0xB7, 0xBB",
6636        "UMask": "0x1",
6637        "BriefDescription": "TBD TBD",
6638        "MSRValue": "0x00803C0491",
6639        "Counter": "0,1,2,3",
6640        "EventName": "OCR.ALL_DATA_RD.L3_HIT.SNOOP_NONE",
6641        "MSRIndex": "0x1a6,0x1a7",
6642        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
6643        "SampleAfterValue": "100003",
6644        "CounterHTOff": "0,1,2,3"
6645    },
6646    {
6647        "Offcore": "1",
6648        "EventCode": "0xB7, 0xBB",
6649        "UMask": "0x1",
6650        "BriefDescription": "TBD TBD TBD",
6651        "MSRValue": "0x01003C0491",
6652        "Counter": "0,1,2,3",
6653        "EventName": "OCR.ALL_DATA_RD.L3_HIT.NO_SNOOP_NEEDED",
6654        "MSRIndex": "0x1a6,0x1a7",
6655        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
6656        "SampleAfterValue": "100003",
6657        "CounterHTOff": "0,1,2,3"
6658    },
6659    {
6660        "Offcore": "1",
6661        "EventCode": "0xB7, 0xBB",
6662        "UMask": "0x1",
6663        "BriefDescription": "TBD TBD",
6664        "MSRValue": "0x02003C0491",
6665        "Counter": "0,1,2,3",
6666        "EventName": "OCR.ALL_DATA_RD.L3_HIT.SNOOP_MISS",
6667        "MSRIndex": "0x1a6,0x1a7",
6668        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
6669        "SampleAfterValue": "100003",
6670        "CounterHTOff": "0,1,2,3"
6671    },
6672    {
6673        "Offcore": "1",
6674        "EventCode": "0xB7, 0xBB",
6675        "UMask": "0x1",
6676        "BriefDescription": "TBD TBD TBD",
6677        "MSRValue": "0x04003C0491",
6678        "Counter": "0,1,2,3",
6679        "EventName": "OCR.ALL_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD",
6680        "MSRIndex": "0x1a6,0x1a7",
6681        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
6682        "SampleAfterValue": "100003",
6683        "CounterHTOff": "0,1,2,3"
6684    },
6685    {
6686        "Offcore": "1",
6687        "EventCode": "0xB7, 0xBB",
6688        "UMask": "0x1",
6689        "BriefDescription": "TBD TBD TBD",
6690        "MSRValue": "0x08003C0491",
6691        "Counter": "0,1,2,3",
6692        "EventName": "OCR.ALL_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD",
6693        "MSRIndex": "0x1a6,0x1a7",
6694        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
6695        "SampleAfterValue": "100003",
6696        "CounterHTOff": "0,1,2,3"
6697    },
6698    {
6699        "Offcore": "1",
6700        "EventCode": "0xB7, 0xBB",
6701        "UMask": "0x1",
6702        "BriefDescription": "TBD TBD TBD",
6703        "MSRValue": "0x10003C0491",
6704        "Counter": "0,1,2,3",
6705        "EventName": "OCR.ALL_DATA_RD.L3_HIT.HITM_OTHER_CORE",
6706        "MSRIndex": "0x1a6,0x1a7",
6707        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
6708        "SampleAfterValue": "100003",
6709        "CounterHTOff": "0,1,2,3"
6710    },
6711    {
6712        "Offcore": "1",
6713        "EventCode": "0xB7, 0xBB",
6714        "UMask": "0x1",
6715        "BriefDescription": "TBD TBD TBD",
6716        "MSRValue": "0x3F803C0491",
6717        "Counter": "0,1,2,3",
6718        "EventName": "OCR.ALL_DATA_RD.L3_HIT.ANY_SNOOP",
6719        "MSRIndex": "0x1a6,0x1a7",
6720        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
6721        "SampleAfterValue": "100003",
6722        "CounterHTOff": "0,1,2,3"
6723    },
6724    {
6725        "Offcore": "1",
6726        "EventCode": "0xB7, 0xBB",
6727        "UMask": "0x1",
6728        "BriefDescription": "TBD",
6729        "MSRValue": "0x0080020122",
6730        "Counter": "0,1,2,3",
6731        "EventName": "OCR.ALL_RFO.SUPPLIER_NONE.SNOOP_NONE",
6732        "MSRIndex": "0x1a6,0x1a7",
6733        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
6734        "SampleAfterValue": "100003",
6735        "CounterHTOff": "0,1,2,3"
6736    },
6737    {
6738        "Offcore": "1",
6739        "EventCode": "0xB7, 0xBB",
6740        "UMask": "0x1",
6741        "BriefDescription": "TBD  TBD",
6742        "MSRValue": "0x0100020122",
6743        "Counter": "0,1,2,3",
6744        "EventName": "OCR.ALL_RFO.SUPPLIER_NONE.NO_SNOOP_NEEDED",
6745        "MSRIndex": "0x1a6,0x1a7",
6746        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
6747        "SampleAfterValue": "100003",
6748        "CounterHTOff": "0,1,2,3"
6749    },
6750    {
6751        "Offcore": "1",
6752        "EventCode": "0xB7, 0xBB",
6753        "UMask": "0x1",
6754        "BriefDescription": "TBD",
6755        "MSRValue": "0x0200020122",
6756        "Counter": "0,1,2,3",
6757        "EventName": "OCR.ALL_RFO.SUPPLIER_NONE.SNOOP_MISS",
6758        "MSRIndex": "0x1a6,0x1a7",
6759        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
6760        "SampleAfterValue": "100003",
6761        "CounterHTOff": "0,1,2,3"
6762    },
6763    {
6764        "Offcore": "1",
6765        "EventCode": "0xB7, 0xBB",
6766        "UMask": "0x1",
6767        "BriefDescription": "TBD  TBD",
6768        "MSRValue": "0x0400020122",
6769        "Counter": "0,1,2,3",
6770        "EventName": "OCR.ALL_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD",
6771        "MSRIndex": "0x1a6,0x1a7",
6772        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
6773        "SampleAfterValue": "100003",
6774        "CounterHTOff": "0,1,2,3"
6775    },
6776    {
6777        "Offcore": "1",
6778        "EventCode": "0xB7, 0xBB",
6779        "UMask": "0x1",
6780        "BriefDescription": "TBD  TBD",
6781        "MSRValue": "0x0800020122",
6782        "Counter": "0,1,2,3",
6783        "EventName": "OCR.ALL_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_FWD",
6784        "MSRIndex": "0x1a6,0x1a7",
6785        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
6786        "SampleAfterValue": "100003",
6787        "CounterHTOff": "0,1,2,3"
6788    },
6789    {
6790        "Offcore": "1",
6791        "EventCode": "0xB7, 0xBB",
6792        "UMask": "0x1",
6793        "BriefDescription": "TBD  TBD",
6794        "MSRValue": "0x1000020122",
6795        "Counter": "0,1,2,3",
6796        "EventName": "OCR.ALL_RFO.SUPPLIER_NONE.HITM_OTHER_CORE",
6797        "MSRIndex": "0x1a6,0x1a7",
6798        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
6799        "SampleAfterValue": "100003",
6800        "CounterHTOff": "0,1,2,3"
6801    },
6802    {
6803        "Offcore": "1",
6804        "EventCode": "0xB7, 0xBB",
6805        "UMask": "0x1",
6806        "BriefDescription": "TBD  TBD",
6807        "MSRValue": "0x3F80020122",
6808        "Counter": "0,1,2,3",
6809        "EventName": "OCR.ALL_RFO.SUPPLIER_NONE.ANY_SNOOP",
6810        "MSRIndex": "0x1a6,0x1a7",
6811        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
6812        "SampleAfterValue": "100003",
6813        "CounterHTOff": "0,1,2,3"
6814    },
6815    {
6816        "Offcore": "1",
6817        "EventCode": "0xB7, 0xBB",
6818        "UMask": "0x1",
6819        "BriefDescription": "TBD",
6820        "MSRValue": "0x0080040122",
6821        "Counter": "0,1,2,3",
6822        "EventName": "OCR.ALL_RFO.L3_HIT_M.SNOOP_NONE",
6823        "MSRIndex": "0x1a6,0x1a7",
6824        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
6825        "SampleAfterValue": "100003",
6826        "CounterHTOff": "0,1,2,3"
6827    },
6828    {
6829        "Offcore": "1",
6830        "EventCode": "0xB7, 0xBB",
6831        "UMask": "0x1",
6832        "BriefDescription": "TBD  TBD",
6833        "MSRValue": "0x0100040122",
6834        "Counter": "0,1,2,3",
6835        "EventName": "OCR.ALL_RFO.L3_HIT_M.NO_SNOOP_NEEDED",
6836        "MSRIndex": "0x1a6,0x1a7",
6837        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
6838        "SampleAfterValue": "100003",
6839        "CounterHTOff": "0,1,2,3"
6840    },
6841    {
6842        "Offcore": "1",
6843        "EventCode": "0xB7, 0xBB",
6844        "UMask": "0x1",
6845        "BriefDescription": "TBD",
6846        "MSRValue": "0x0200040122",
6847        "Counter": "0,1,2,3",
6848        "EventName": "OCR.ALL_RFO.L3_HIT_M.SNOOP_MISS",
6849        "MSRIndex": "0x1a6,0x1a7",
6850        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
6851        "SampleAfterValue": "100003",
6852        "CounterHTOff": "0,1,2,3"
6853    },
6854    {
6855        "Offcore": "1",
6856        "EventCode": "0xB7, 0xBB",
6857        "UMask": "0x1",
6858        "BriefDescription": "TBD  TBD",
6859        "MSRValue": "0x0400040122",
6860        "Counter": "0,1,2,3",
6861        "EventName": "OCR.ALL_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWD",
6862        "MSRIndex": "0x1a6,0x1a7",
6863        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
6864        "SampleAfterValue": "100003",
6865        "CounterHTOff": "0,1,2,3"
6866    },
6867    {
6868        "Offcore": "1",
6869        "EventCode": "0xB7, 0xBB",
6870        "UMask": "0x1",
6871        "BriefDescription": "TBD  TBD",
6872        "MSRValue": "0x0800040122",
6873        "Counter": "0,1,2,3",
6874        "EventName": "OCR.ALL_RFO.L3_HIT_M.HIT_OTHER_CORE_FWD",
6875        "MSRIndex": "0x1a6,0x1a7",
6876        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
6877        "SampleAfterValue": "100003",
6878        "CounterHTOff": "0,1,2,3"
6879    },
6880    {
6881        "Offcore": "1",
6882        "EventCode": "0xB7, 0xBB",
6883        "UMask": "0x1",
6884        "BriefDescription": "TBD  TBD",
6885        "MSRValue": "0x1000040122",
6886        "Counter": "0,1,2,3",
6887        "EventName": "OCR.ALL_RFO.L3_HIT_M.HITM_OTHER_CORE",
6888        "MSRIndex": "0x1a6,0x1a7",
6889        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
6890        "SampleAfterValue": "100003",
6891        "CounterHTOff": "0,1,2,3"
6892    },
6893    {
6894        "Offcore": "1",
6895        "EventCode": "0xB7, 0xBB",
6896        "UMask": "0x1",
6897        "BriefDescription": "TBD  TBD",
6898        "MSRValue": "0x3F80040122",
6899        "Counter": "0,1,2,3",
6900        "EventName": "OCR.ALL_RFO.L3_HIT_M.ANY_SNOOP",
6901        "MSRIndex": "0x1a6,0x1a7",
6902        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
6903        "SampleAfterValue": "100003",
6904        "CounterHTOff": "0,1,2,3"
6905    },
6906    {
6907        "Offcore": "1",
6908        "EventCode": "0xB7, 0xBB",
6909        "UMask": "0x1",
6910        "BriefDescription": "TBD",
6911        "MSRValue": "0x0080080122",
6912        "Counter": "0,1,2,3",
6913        "EventName": "OCR.ALL_RFO.L3_HIT_E.SNOOP_NONE",
6914        "MSRIndex": "0x1a6,0x1a7",
6915        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
6916        "SampleAfterValue": "100003",
6917        "CounterHTOff": "0,1,2,3"
6918    },
6919    {
6920        "Offcore": "1",
6921        "EventCode": "0xB7, 0xBB",
6922        "UMask": "0x1",
6923        "BriefDescription": "TBD  TBD",
6924        "MSRValue": "0x0100080122",
6925        "Counter": "0,1,2,3",
6926        "EventName": "OCR.ALL_RFO.L3_HIT_E.NO_SNOOP_NEEDED",
6927        "MSRIndex": "0x1a6,0x1a7",
6928        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
6929        "SampleAfterValue": "100003",
6930        "CounterHTOff": "0,1,2,3"
6931    },
6932    {
6933        "Offcore": "1",
6934        "EventCode": "0xB7, 0xBB",
6935        "UMask": "0x1",
6936        "BriefDescription": "TBD",
6937        "MSRValue": "0x0200080122",
6938        "Counter": "0,1,2,3",
6939        "EventName": "OCR.ALL_RFO.L3_HIT_E.SNOOP_MISS",
6940        "MSRIndex": "0x1a6,0x1a7",
6941        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
6942        "SampleAfterValue": "100003",
6943        "CounterHTOff": "0,1,2,3"
6944    },
6945    {
6946        "Offcore": "1",
6947        "EventCode": "0xB7, 0xBB",
6948        "UMask": "0x1",
6949        "BriefDescription": "TBD  TBD",
6950        "MSRValue": "0x0400080122",
6951        "Counter": "0,1,2,3",
6952        "EventName": "OCR.ALL_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWD",
6953        "MSRIndex": "0x1a6,0x1a7",
6954        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
6955        "SampleAfterValue": "100003",
6956        "CounterHTOff": "0,1,2,3"
6957    },
6958    {
6959        "Offcore": "1",
6960        "EventCode": "0xB7, 0xBB",
6961        "UMask": "0x1",
6962        "BriefDescription": "TBD  TBD",
6963        "MSRValue": "0x0800080122",
6964        "Counter": "0,1,2,3",
6965        "EventName": "OCR.ALL_RFO.L3_HIT_E.HIT_OTHER_CORE_FWD",
6966        "MSRIndex": "0x1a6,0x1a7",
6967        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
6968        "SampleAfterValue": "100003",
6969        "CounterHTOff": "0,1,2,3"
6970    },
6971    {
6972        "Offcore": "1",
6973        "EventCode": "0xB7, 0xBB",
6974        "UMask": "0x1",
6975        "BriefDescription": "TBD  TBD",
6976        "MSRValue": "0x1000080122",
6977        "Counter": "0,1,2,3",
6978        "EventName": "OCR.ALL_RFO.L3_HIT_E.HITM_OTHER_CORE",
6979        "MSRIndex": "0x1a6,0x1a7",
6980        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
6981        "SampleAfterValue": "100003",
6982        "CounterHTOff": "0,1,2,3"
6983    },
6984    {
6985        "Offcore": "1",
6986        "EventCode": "0xB7, 0xBB",
6987        "UMask": "0x1",
6988        "BriefDescription": "TBD  TBD",
6989        "MSRValue": "0x3F80080122",
6990        "Counter": "0,1,2,3",
6991        "EventName": "OCR.ALL_RFO.L3_HIT_E.ANY_SNOOP",
6992        "MSRIndex": "0x1a6,0x1a7",
6993        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
6994        "SampleAfterValue": "100003",
6995        "CounterHTOff": "0,1,2,3"
6996    },
6997    {
6998        "Offcore": "1",
6999        "EventCode": "0xB7, 0xBB",
7000        "UMask": "0x1",
7001        "BriefDescription": "TBD",
7002        "MSRValue": "0x0080100122",
7003        "Counter": "0,1,2,3",
7004        "EventName": "OCR.ALL_RFO.L3_HIT_S.SNOOP_NONE",
7005        "MSRIndex": "0x1a6,0x1a7",
7006        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
7007        "SampleAfterValue": "100003",
7008        "CounterHTOff": "0,1,2,3"
7009    },
7010    {
7011        "Offcore": "1",
7012        "EventCode": "0xB7, 0xBB",
7013        "UMask": "0x1",
7014        "BriefDescription": "TBD  TBD",
7015        "MSRValue": "0x0100100122",
7016        "Counter": "0,1,2,3",
7017        "EventName": "OCR.ALL_RFO.L3_HIT_S.NO_SNOOP_NEEDED",
7018        "MSRIndex": "0x1a6,0x1a7",
7019        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
7020        "SampleAfterValue": "100003",
7021        "CounterHTOff": "0,1,2,3"
7022    },
7023    {
7024        "Offcore": "1",
7025        "EventCode": "0xB7, 0xBB",
7026        "UMask": "0x1",
7027        "BriefDescription": "TBD",
7028        "MSRValue": "0x0200100122",
7029        "Counter": "0,1,2,3",
7030        "EventName": "OCR.ALL_RFO.L3_HIT_S.SNOOP_MISS",
7031        "MSRIndex": "0x1a6,0x1a7",
7032        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
7033        "SampleAfterValue": "100003",
7034        "CounterHTOff": "0,1,2,3"
7035    },
7036    {
7037        "Offcore": "1",
7038        "EventCode": "0xB7, 0xBB",
7039        "UMask": "0x1",
7040        "BriefDescription": "TBD  TBD",
7041        "MSRValue": "0x0400100122",
7042        "Counter": "0,1,2,3",
7043        "EventName": "OCR.ALL_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWD",
7044        "MSRIndex": "0x1a6,0x1a7",
7045        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
7046        "SampleAfterValue": "100003",
7047        "CounterHTOff": "0,1,2,3"
7048    },
7049    {
7050        "Offcore": "1",
7051        "EventCode": "0xB7, 0xBB",
7052        "UMask": "0x1",
7053        "BriefDescription": "TBD  TBD",
7054        "MSRValue": "0x0800100122",
7055        "Counter": "0,1,2,3",
7056        "EventName": "OCR.ALL_RFO.L3_HIT_S.HIT_OTHER_CORE_FWD",
7057        "MSRIndex": "0x1a6,0x1a7",
7058        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
7059        "SampleAfterValue": "100003",
7060        "CounterHTOff": "0,1,2,3"
7061    },
7062    {
7063        "Offcore": "1",
7064        "EventCode": "0xB7, 0xBB",
7065        "UMask": "0x1",
7066        "BriefDescription": "TBD  TBD",
7067        "MSRValue": "0x1000100122",
7068        "Counter": "0,1,2,3",
7069        "EventName": "OCR.ALL_RFO.L3_HIT_S.HITM_OTHER_CORE",
7070        "MSRIndex": "0x1a6,0x1a7",
7071        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
7072        "SampleAfterValue": "100003",
7073        "CounterHTOff": "0,1,2,3"
7074    },
7075    {
7076        "Offcore": "1",
7077        "EventCode": "0xB7, 0xBB",
7078        "UMask": "0x1",
7079        "BriefDescription": "TBD  TBD",
7080        "MSRValue": "0x3F80100122",
7081        "Counter": "0,1,2,3",
7082        "EventName": "OCR.ALL_RFO.L3_HIT_S.ANY_SNOOP",
7083        "MSRIndex": "0x1a6,0x1a7",
7084        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
7085        "SampleAfterValue": "100003",
7086        "CounterHTOff": "0,1,2,3"
7087    },
7088    {
7089        "Offcore": "1",
7090        "EventCode": "0xB7, 0xBB",
7091        "UMask": "0x1",
7092        "BriefDescription": "TBD",
7093        "MSRValue": "0x0080200122",
7094        "Counter": "0,1,2,3",
7095        "EventName": "OCR.ALL_RFO.L3_HIT_F.SNOOP_NONE",
7096        "MSRIndex": "0x1a6,0x1a7",
7097        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
7098        "SampleAfterValue": "100003",
7099        "CounterHTOff": "0,1,2,3"
7100    },
7101    {
7102        "Offcore": "1",
7103        "EventCode": "0xB7, 0xBB",
7104        "UMask": "0x1",
7105        "BriefDescription": "TBD  TBD",
7106        "MSRValue": "0x0100200122",
7107        "Counter": "0,1,2,3",
7108        "EventName": "OCR.ALL_RFO.L3_HIT_F.NO_SNOOP_NEEDED",
7109        "MSRIndex": "0x1a6,0x1a7",
7110        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
7111        "SampleAfterValue": "100003",
7112        "CounterHTOff": "0,1,2,3"
7113    },
7114    {
7115        "Offcore": "1",
7116        "EventCode": "0xB7, 0xBB",
7117        "UMask": "0x1",
7118        "BriefDescription": "TBD",
7119        "MSRValue": "0x0200200122",
7120        "Counter": "0,1,2,3",
7121        "EventName": "OCR.ALL_RFO.L3_HIT_F.SNOOP_MISS",
7122        "MSRIndex": "0x1a6,0x1a7",
7123        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
7124        "SampleAfterValue": "100003",
7125        "CounterHTOff": "0,1,2,3"
7126    },
7127    {
7128        "Offcore": "1",
7129        "EventCode": "0xB7, 0xBB",
7130        "UMask": "0x1",
7131        "BriefDescription": "TBD  TBD",
7132        "MSRValue": "0x0400200122",
7133        "Counter": "0,1,2,3",
7134        "EventName": "OCR.ALL_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWD",
7135        "MSRIndex": "0x1a6,0x1a7",
7136        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
7137        "SampleAfterValue": "100003",
7138        "CounterHTOff": "0,1,2,3"
7139    },
7140    {
7141        "Offcore": "1",
7142        "EventCode": "0xB7, 0xBB",
7143        "UMask": "0x1",
7144        "BriefDescription": "TBD  TBD",
7145        "MSRValue": "0x0800200122",
7146        "Counter": "0,1,2,3",
7147        "EventName": "OCR.ALL_RFO.L3_HIT_F.HIT_OTHER_CORE_FWD",
7148        "MSRIndex": "0x1a6,0x1a7",
7149        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
7150        "SampleAfterValue": "100003",
7151        "CounterHTOff": "0,1,2,3"
7152    },
7153    {
7154        "Offcore": "1",
7155        "EventCode": "0xB7, 0xBB",
7156        "UMask": "0x1",
7157        "BriefDescription": "TBD  TBD",
7158        "MSRValue": "0x1000200122",
7159        "Counter": "0,1,2,3",
7160        "EventName": "OCR.ALL_RFO.L3_HIT_F.HITM_OTHER_CORE",
7161        "MSRIndex": "0x1a6,0x1a7",
7162        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
7163        "SampleAfterValue": "100003",
7164        "CounterHTOff": "0,1,2,3"
7165    },
7166    {
7167        "Offcore": "1",
7168        "EventCode": "0xB7, 0xBB",
7169        "UMask": "0x1",
7170        "BriefDescription": "TBD  TBD",
7171        "MSRValue": "0x3F80200122",
7172        "Counter": "0,1,2,3",
7173        "EventName": "OCR.ALL_RFO.L3_HIT_F.ANY_SNOOP",
7174        "MSRIndex": "0x1a6,0x1a7",
7175        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
7176        "SampleAfterValue": "100003",
7177        "CounterHTOff": "0,1,2,3"
7178    },
7179    {
7180        "Offcore": "1",
7181        "EventCode": "0xB7, 0xBB",
7182        "UMask": "0x1",
7183        "BriefDescription": "TBD TBD",
7184        "MSRValue": "0x00803C0122",
7185        "Counter": "0,1,2,3",
7186        "EventName": "OCR.ALL_RFO.L3_HIT.SNOOP_NONE",
7187        "MSRIndex": "0x1a6,0x1a7",
7188        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
7189        "SampleAfterValue": "100003",
7190        "CounterHTOff": "0,1,2,3"
7191    },
7192    {
7193        "Offcore": "1",
7194        "EventCode": "0xB7, 0xBB",
7195        "UMask": "0x1",
7196        "BriefDescription": "TBD TBD TBD",
7197        "MSRValue": "0x01003C0122",
7198        "Counter": "0,1,2,3",
7199        "EventName": "OCR.ALL_RFO.L3_HIT.NO_SNOOP_NEEDED",
7200        "MSRIndex": "0x1a6,0x1a7",
7201        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
7202        "SampleAfterValue": "100003",
7203        "CounterHTOff": "0,1,2,3"
7204    },
7205    {
7206        "Offcore": "1",
7207        "EventCode": "0xB7, 0xBB",
7208        "UMask": "0x1",
7209        "BriefDescription": "TBD TBD",
7210        "MSRValue": "0x02003C0122",
7211        "Counter": "0,1,2,3",
7212        "EventName": "OCR.ALL_RFO.L3_HIT.SNOOP_MISS",
7213        "MSRIndex": "0x1a6,0x1a7",
7214        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
7215        "SampleAfterValue": "100003",
7216        "CounterHTOff": "0,1,2,3"
7217    },
7218    {
7219        "Offcore": "1",
7220        "EventCode": "0xB7, 0xBB",
7221        "UMask": "0x1",
7222        "BriefDescription": "TBD TBD TBD",
7223        "MSRValue": "0x04003C0122",
7224        "Counter": "0,1,2,3",
7225        "EventName": "OCR.ALL_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD",
7226        "MSRIndex": "0x1a6,0x1a7",
7227        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
7228        "SampleAfterValue": "100003",
7229        "CounterHTOff": "0,1,2,3"
7230    },
7231    {
7232        "Offcore": "1",
7233        "EventCode": "0xB7, 0xBB",
7234        "UMask": "0x1",
7235        "BriefDescription": "TBD TBD TBD",
7236        "MSRValue": "0x08003C0122",
7237        "Counter": "0,1,2,3",
7238        "EventName": "OCR.ALL_RFO.L3_HIT.HIT_OTHER_CORE_FWD",
7239        "MSRIndex": "0x1a6,0x1a7",
7240        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
7241        "SampleAfterValue": "100003",
7242        "CounterHTOff": "0,1,2,3"
7243    },
7244    {
7245        "Offcore": "1",
7246        "EventCode": "0xB7, 0xBB",
7247        "UMask": "0x1",
7248        "BriefDescription": "TBD TBD TBD",
7249        "MSRValue": "0x10003C0122",
7250        "Counter": "0,1,2,3",
7251        "EventName": "OCR.ALL_RFO.L3_HIT.HITM_OTHER_CORE",
7252        "MSRIndex": "0x1a6,0x1a7",
7253        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
7254        "SampleAfterValue": "100003",
7255        "CounterHTOff": "0,1,2,3"
7256    },
7257    {
7258        "Offcore": "1",
7259        "EventCode": "0xB7, 0xBB",
7260        "UMask": "0x1",
7261        "BriefDescription": "TBD TBD TBD",
7262        "MSRValue": "0x3F803C0122",
7263        "Counter": "0,1,2,3",
7264        "EventName": "OCR.ALL_RFO.L3_HIT.ANY_SNOOP",
7265        "MSRIndex": "0x1a6,0x1a7",
7266        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
7267        "SampleAfterValue": "100003",
7268        "CounterHTOff": "0,1,2,3"
7269    },
7270    {
7271        "Offcore": "1",
7272        "EventCode": "0xB7, 0xBB",
7273        "UMask": "0x1",
7274        "BriefDescription": "TBD",
7275        "MSRValue": "0x00800207F7",
7276        "Counter": "0,1,2,3",
7277        "EventName": "OCR.ALL_READS.SUPPLIER_NONE.SNOOP_NONE",
7278        "MSRIndex": "0x1a6,0x1a7",
7279        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
7280        "SampleAfterValue": "100003",
7281        "CounterHTOff": "0,1,2,3"
7282    },
7283    {
7284        "Offcore": "1",
7285        "EventCode": "0xB7, 0xBB",
7286        "UMask": "0x1",
7287        "BriefDescription": "TBD  TBD",
7288        "MSRValue": "0x01000207F7",
7289        "Counter": "0,1,2,3",
7290        "EventName": "OCR.ALL_READS.SUPPLIER_NONE.NO_SNOOP_NEEDED",
7291        "MSRIndex": "0x1a6,0x1a7",
7292        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
7293        "SampleAfterValue": "100003",
7294        "CounterHTOff": "0,1,2,3"
7295    },
7296    {
7297        "Offcore": "1",
7298        "EventCode": "0xB7, 0xBB",
7299        "UMask": "0x1",
7300        "BriefDescription": "TBD",
7301        "MSRValue": "0x02000207F7",
7302        "Counter": "0,1,2,3",
7303        "EventName": "OCR.ALL_READS.SUPPLIER_NONE.SNOOP_MISS",
7304        "MSRIndex": "0x1a6,0x1a7",
7305        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
7306        "SampleAfterValue": "100003",
7307        "CounterHTOff": "0,1,2,3"
7308    },
7309    {
7310        "Offcore": "1",
7311        "EventCode": "0xB7, 0xBB",
7312        "UMask": "0x1",
7313        "BriefDescription": "TBD  TBD",
7314        "MSRValue": "0x04000207F7",
7315        "Counter": "0,1,2,3",
7316        "EventName": "OCR.ALL_READS.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD",
7317        "MSRIndex": "0x1a6,0x1a7",
7318        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
7319        "SampleAfterValue": "100003",
7320        "CounterHTOff": "0,1,2,3"
7321    },
7322    {
7323        "Offcore": "1",
7324        "EventCode": "0xB7, 0xBB",
7325        "UMask": "0x1",
7326        "BriefDescription": "TBD  TBD",
7327        "MSRValue": "0x08000207F7",
7328        "Counter": "0,1,2,3",
7329        "EventName": "OCR.ALL_READS.SUPPLIER_NONE.HIT_OTHER_CORE_FWD",
7330        "MSRIndex": "0x1a6,0x1a7",
7331        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
7332        "SampleAfterValue": "100003",
7333        "CounterHTOff": "0,1,2,3"
7334    },
7335    {
7336        "Offcore": "1",
7337        "EventCode": "0xB7, 0xBB",
7338        "UMask": "0x1",
7339        "BriefDescription": "TBD  TBD",
7340        "MSRValue": "0x10000207F7",
7341        "Counter": "0,1,2,3",
7342        "EventName": "OCR.ALL_READS.SUPPLIER_NONE.HITM_OTHER_CORE",
7343        "MSRIndex": "0x1a6,0x1a7",
7344        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
7345        "SampleAfterValue": "100003",
7346        "CounterHTOff": "0,1,2,3"
7347    },
7348    {
7349        "Offcore": "1",
7350        "EventCode": "0xB7, 0xBB",
7351        "UMask": "0x1",
7352        "BriefDescription": "TBD  TBD",
7353        "MSRValue": "0x3F800207F7",
7354        "Counter": "0,1,2,3",
7355        "EventName": "OCR.ALL_READS.SUPPLIER_NONE.ANY_SNOOP",
7356        "MSRIndex": "0x1a6,0x1a7",
7357        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
7358        "SampleAfterValue": "100003",
7359        "CounterHTOff": "0,1,2,3"
7360    },
7361    {
7362        "Offcore": "1",
7363        "EventCode": "0xB7, 0xBB",
7364        "UMask": "0x1",
7365        "BriefDescription": "TBD",
7366        "MSRValue": "0x00800407F7",
7367        "Counter": "0,1,2,3",
7368        "EventName": "OCR.ALL_READS.L3_HIT_M.SNOOP_NONE",
7369        "MSRIndex": "0x1a6,0x1a7",
7370        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
7371        "SampleAfterValue": "100003",
7372        "CounterHTOff": "0,1,2,3"
7373    },
7374    {
7375        "Offcore": "1",
7376        "EventCode": "0xB7, 0xBB",
7377        "UMask": "0x1",
7378        "BriefDescription": "TBD  TBD",
7379        "MSRValue": "0x01000407F7",
7380        "Counter": "0,1,2,3",
7381        "EventName": "OCR.ALL_READS.L3_HIT_M.NO_SNOOP_NEEDED",
7382        "MSRIndex": "0x1a6,0x1a7",
7383        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
7384        "SampleAfterValue": "100003",
7385        "CounterHTOff": "0,1,2,3"
7386    },
7387    {
7388        "Offcore": "1",
7389        "EventCode": "0xB7, 0xBB",
7390        "UMask": "0x1",
7391        "BriefDescription": "TBD",
7392        "MSRValue": "0x02000407F7",
7393        "Counter": "0,1,2,3",
7394        "EventName": "OCR.ALL_READS.L3_HIT_M.SNOOP_MISS",
7395        "MSRIndex": "0x1a6,0x1a7",
7396        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
7397        "SampleAfterValue": "100003",
7398        "CounterHTOff": "0,1,2,3"
7399    },
7400    {
7401        "Offcore": "1",
7402        "EventCode": "0xB7, 0xBB",
7403        "UMask": "0x1",
7404        "BriefDescription": "TBD  TBD",
7405        "MSRValue": "0x04000407F7",
7406        "Counter": "0,1,2,3",
7407        "EventName": "OCR.ALL_READS.L3_HIT_M.HIT_OTHER_CORE_NO_FWD",
7408        "MSRIndex": "0x1a6,0x1a7",
7409        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
7410        "SampleAfterValue": "100003",
7411        "CounterHTOff": "0,1,2,3"
7412    },
7413    {
7414        "Offcore": "1",
7415        "EventCode": "0xB7, 0xBB",
7416        "UMask": "0x1",
7417        "BriefDescription": "TBD  TBD",
7418        "MSRValue": "0x08000407F7",
7419        "Counter": "0,1,2,3",
7420        "EventName": "OCR.ALL_READS.L3_HIT_M.HIT_OTHER_CORE_FWD",
7421        "MSRIndex": "0x1a6,0x1a7",
7422        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
7423        "SampleAfterValue": "100003",
7424        "CounterHTOff": "0,1,2,3"
7425    },
7426    {
7427        "Offcore": "1",
7428        "EventCode": "0xB7, 0xBB",
7429        "UMask": "0x1",
7430        "BriefDescription": "TBD  TBD",
7431        "MSRValue": "0x10000407F7",
7432        "Counter": "0,1,2,3",
7433        "EventName": "OCR.ALL_READS.L3_HIT_M.HITM_OTHER_CORE",
7434        "MSRIndex": "0x1a6,0x1a7",
7435        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
7436        "SampleAfterValue": "100003",
7437        "CounterHTOff": "0,1,2,3"
7438    },
7439    {
7440        "Offcore": "1",
7441        "EventCode": "0xB7, 0xBB",
7442        "UMask": "0x1",
7443        "BriefDescription": "TBD  TBD",
7444        "MSRValue": "0x3F800407F7",
7445        "Counter": "0,1,2,3",
7446        "EventName": "OCR.ALL_READS.L3_HIT_M.ANY_SNOOP",
7447        "MSRIndex": "0x1a6,0x1a7",
7448        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
7449        "SampleAfterValue": "100003",
7450        "CounterHTOff": "0,1,2,3"
7451    },
7452    {
7453        "Offcore": "1",
7454        "EventCode": "0xB7, 0xBB",
7455        "UMask": "0x1",
7456        "BriefDescription": "TBD",
7457        "MSRValue": "0x00800807F7",
7458        "Counter": "0,1,2,3",
7459        "EventName": "OCR.ALL_READS.L3_HIT_E.SNOOP_NONE",
7460        "MSRIndex": "0x1a6,0x1a7",
7461        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
7462        "SampleAfterValue": "100003",
7463        "CounterHTOff": "0,1,2,3"
7464    },
7465    {
7466        "Offcore": "1",
7467        "EventCode": "0xB7, 0xBB",
7468        "UMask": "0x1",
7469        "BriefDescription": "TBD  TBD",
7470        "MSRValue": "0x01000807F7",
7471        "Counter": "0,1,2,3",
7472        "EventName": "OCR.ALL_READS.L3_HIT_E.NO_SNOOP_NEEDED",
7473        "MSRIndex": "0x1a6,0x1a7",
7474        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
7475        "SampleAfterValue": "100003",
7476        "CounterHTOff": "0,1,2,3"
7477    },
7478    {
7479        "Offcore": "1",
7480        "EventCode": "0xB7, 0xBB",
7481        "UMask": "0x1",
7482        "BriefDescription": "TBD",
7483        "MSRValue": "0x02000807F7",
7484        "Counter": "0,1,2,3",
7485        "EventName": "OCR.ALL_READS.L3_HIT_E.SNOOP_MISS",
7486        "MSRIndex": "0x1a6,0x1a7",
7487        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
7488        "SampleAfterValue": "100003",
7489        "CounterHTOff": "0,1,2,3"
7490    },
7491    {
7492        "Offcore": "1",
7493        "EventCode": "0xB7, 0xBB",
7494        "UMask": "0x1",
7495        "BriefDescription": "TBD  TBD",
7496        "MSRValue": "0x04000807F7",
7497        "Counter": "0,1,2,3",
7498        "EventName": "OCR.ALL_READS.L3_HIT_E.HIT_OTHER_CORE_NO_FWD",
7499        "MSRIndex": "0x1a6,0x1a7",
7500        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
7501        "SampleAfterValue": "100003",
7502        "CounterHTOff": "0,1,2,3"
7503    },
7504    {
7505        "Offcore": "1",
7506        "EventCode": "0xB7, 0xBB",
7507        "UMask": "0x1",
7508        "BriefDescription": "TBD  TBD",
7509        "MSRValue": "0x08000807F7",
7510        "Counter": "0,1,2,3",
7511        "EventName": "OCR.ALL_READS.L3_HIT_E.HIT_OTHER_CORE_FWD",
7512        "MSRIndex": "0x1a6,0x1a7",
7513        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
7514        "SampleAfterValue": "100003",
7515        "CounterHTOff": "0,1,2,3"
7516    },
7517    {
7518        "Offcore": "1",
7519        "EventCode": "0xB7, 0xBB",
7520        "UMask": "0x1",
7521        "BriefDescription": "TBD  TBD",
7522        "MSRValue": "0x10000807F7",
7523        "Counter": "0,1,2,3",
7524        "EventName": "OCR.ALL_READS.L3_HIT_E.HITM_OTHER_CORE",
7525        "MSRIndex": "0x1a6,0x1a7",
7526        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
7527        "SampleAfterValue": "100003",
7528        "CounterHTOff": "0,1,2,3"
7529    },
7530    {
7531        "Offcore": "1",
7532        "EventCode": "0xB7, 0xBB",
7533        "UMask": "0x1",
7534        "BriefDescription": "TBD  TBD",
7535        "MSRValue": "0x3F800807F7",
7536        "Counter": "0,1,2,3",
7537        "EventName": "OCR.ALL_READS.L3_HIT_E.ANY_SNOOP",
7538        "MSRIndex": "0x1a6,0x1a7",
7539        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
7540        "SampleAfterValue": "100003",
7541        "CounterHTOff": "0,1,2,3"
7542    },
7543    {
7544        "Offcore": "1",
7545        "EventCode": "0xB7, 0xBB",
7546        "UMask": "0x1",
7547        "BriefDescription": "TBD",
7548        "MSRValue": "0x00801007F7",
7549        "Counter": "0,1,2,3",
7550        "EventName": "OCR.ALL_READS.L3_HIT_S.SNOOP_NONE",
7551        "MSRIndex": "0x1a6,0x1a7",
7552        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
7553        "SampleAfterValue": "100003",
7554        "CounterHTOff": "0,1,2,3"
7555    },
7556    {
7557        "Offcore": "1",
7558        "EventCode": "0xB7, 0xBB",
7559        "UMask": "0x1",
7560        "BriefDescription": "TBD  TBD",
7561        "MSRValue": "0x01001007F7",
7562        "Counter": "0,1,2,3",
7563        "EventName": "OCR.ALL_READS.L3_HIT_S.NO_SNOOP_NEEDED",
7564        "MSRIndex": "0x1a6,0x1a7",
7565        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
7566        "SampleAfterValue": "100003",
7567        "CounterHTOff": "0,1,2,3"
7568    },
7569    {
7570        "Offcore": "1",
7571        "EventCode": "0xB7, 0xBB",
7572        "UMask": "0x1",
7573        "BriefDescription": "TBD",
7574        "MSRValue": "0x02001007F7",
7575        "Counter": "0,1,2,3",
7576        "EventName": "OCR.ALL_READS.L3_HIT_S.SNOOP_MISS",
7577        "MSRIndex": "0x1a6,0x1a7",
7578        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
7579        "SampleAfterValue": "100003",
7580        "CounterHTOff": "0,1,2,3"
7581    },
7582    {
7583        "Offcore": "1",
7584        "EventCode": "0xB7, 0xBB",
7585        "UMask": "0x1",
7586        "BriefDescription": "TBD  TBD",
7587        "MSRValue": "0x04001007F7",
7588        "Counter": "0,1,2,3",
7589        "EventName": "OCR.ALL_READS.L3_HIT_S.HIT_OTHER_CORE_NO_FWD",
7590        "MSRIndex": "0x1a6,0x1a7",
7591        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
7592        "SampleAfterValue": "100003",
7593        "CounterHTOff": "0,1,2,3"
7594    },
7595    {
7596        "Offcore": "1",
7597        "EventCode": "0xB7, 0xBB",
7598        "UMask": "0x1",
7599        "BriefDescription": "TBD  TBD",
7600        "MSRValue": "0x08001007F7",
7601        "Counter": "0,1,2,3",
7602        "EventName": "OCR.ALL_READS.L3_HIT_S.HIT_OTHER_CORE_FWD",
7603        "MSRIndex": "0x1a6,0x1a7",
7604        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
7605        "SampleAfterValue": "100003",
7606        "CounterHTOff": "0,1,2,3"
7607    },
7608    {
7609        "Offcore": "1",
7610        "EventCode": "0xB7, 0xBB",
7611        "UMask": "0x1",
7612        "BriefDescription": "TBD  TBD",
7613        "MSRValue": "0x10001007F7",
7614        "Counter": "0,1,2,3",
7615        "EventName": "OCR.ALL_READS.L3_HIT_S.HITM_OTHER_CORE",
7616        "MSRIndex": "0x1a6,0x1a7",
7617        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
7618        "SampleAfterValue": "100003",
7619        "CounterHTOff": "0,1,2,3"
7620    },
7621    {
7622        "Offcore": "1",
7623        "EventCode": "0xB7, 0xBB",
7624        "UMask": "0x1",
7625        "BriefDescription": "TBD  TBD",
7626        "MSRValue": "0x3F801007F7",
7627        "Counter": "0,1,2,3",
7628        "EventName": "OCR.ALL_READS.L3_HIT_S.ANY_SNOOP",
7629        "MSRIndex": "0x1a6,0x1a7",
7630        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
7631        "SampleAfterValue": "100003",
7632        "CounterHTOff": "0,1,2,3"
7633    },
7634    {
7635        "Offcore": "1",
7636        "EventCode": "0xB7, 0xBB",
7637        "UMask": "0x1",
7638        "BriefDescription": "TBD",
7639        "MSRValue": "0x00802007F7",
7640        "Counter": "0,1,2,3",
7641        "EventName": "OCR.ALL_READS.L3_HIT_F.SNOOP_NONE",
7642        "MSRIndex": "0x1a6,0x1a7",
7643        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
7644        "SampleAfterValue": "100003",
7645        "CounterHTOff": "0,1,2,3"
7646    },
7647    {
7648        "Offcore": "1",
7649        "EventCode": "0xB7, 0xBB",
7650        "UMask": "0x1",
7651        "BriefDescription": "TBD  TBD",
7652        "MSRValue": "0x01002007F7",
7653        "Counter": "0,1,2,3",
7654        "EventName": "OCR.ALL_READS.L3_HIT_F.NO_SNOOP_NEEDED",
7655        "MSRIndex": "0x1a6,0x1a7",
7656        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
7657        "SampleAfterValue": "100003",
7658        "CounterHTOff": "0,1,2,3"
7659    },
7660    {
7661        "Offcore": "1",
7662        "EventCode": "0xB7, 0xBB",
7663        "UMask": "0x1",
7664        "BriefDescription": "TBD",
7665        "MSRValue": "0x02002007F7",
7666        "Counter": "0,1,2,3",
7667        "EventName": "OCR.ALL_READS.L3_HIT_F.SNOOP_MISS",
7668        "MSRIndex": "0x1a6,0x1a7",
7669        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
7670        "SampleAfterValue": "100003",
7671        "CounterHTOff": "0,1,2,3"
7672    },
7673    {
7674        "Offcore": "1",
7675        "EventCode": "0xB7, 0xBB",
7676        "UMask": "0x1",
7677        "BriefDescription": "TBD  TBD",
7678        "MSRValue": "0x04002007F7",
7679        "Counter": "0,1,2,3",
7680        "EventName": "OCR.ALL_READS.L3_HIT_F.HIT_OTHER_CORE_NO_FWD",
7681        "MSRIndex": "0x1a6,0x1a7",
7682        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
7683        "SampleAfterValue": "100003",
7684        "CounterHTOff": "0,1,2,3"
7685    },
7686    {
7687        "Offcore": "1",
7688        "EventCode": "0xB7, 0xBB",
7689        "UMask": "0x1",
7690        "BriefDescription": "TBD  TBD",
7691        "MSRValue": "0x08002007F7",
7692        "Counter": "0,1,2,3",
7693        "EventName": "OCR.ALL_READS.L3_HIT_F.HIT_OTHER_CORE_FWD",
7694        "MSRIndex": "0x1a6,0x1a7",
7695        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
7696        "SampleAfterValue": "100003",
7697        "CounterHTOff": "0,1,2,3"
7698    },
7699    {
7700        "Offcore": "1",
7701        "EventCode": "0xB7, 0xBB",
7702        "UMask": "0x1",
7703        "BriefDescription": "TBD  TBD",
7704        "MSRValue": "0x10002007F7",
7705        "Counter": "0,1,2,3",
7706        "EventName": "OCR.ALL_READS.L3_HIT_F.HITM_OTHER_CORE",
7707        "MSRIndex": "0x1a6,0x1a7",
7708        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
7709        "SampleAfterValue": "100003",
7710        "CounterHTOff": "0,1,2,3"
7711    },
7712    {
7713        "Offcore": "1",
7714        "EventCode": "0xB7, 0xBB",
7715        "UMask": "0x1",
7716        "BriefDescription": "TBD  TBD",
7717        "MSRValue": "0x3F802007F7",
7718        "Counter": "0,1,2,3",
7719        "EventName": "OCR.ALL_READS.L3_HIT_F.ANY_SNOOP",
7720        "MSRIndex": "0x1a6,0x1a7",
7721        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
7722        "SampleAfterValue": "100003",
7723        "CounterHTOff": "0,1,2,3"
7724    },
7725    {
7726        "Offcore": "1",
7727        "EventCode": "0xB7, 0xBB",
7728        "UMask": "0x1",
7729        "BriefDescription": "TBD TBD",
7730        "MSRValue": "0x00803C07F7",
7731        "Counter": "0,1,2,3",
7732        "EventName": "OCR.ALL_READS.L3_HIT.SNOOP_NONE",
7733        "MSRIndex": "0x1a6,0x1a7",
7734        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
7735        "SampleAfterValue": "100003",
7736        "CounterHTOff": "0,1,2,3"
7737    },
7738    {
7739        "Offcore": "1",
7740        "EventCode": "0xB7, 0xBB",
7741        "UMask": "0x1",
7742        "BriefDescription": "TBD TBD TBD",
7743        "MSRValue": "0x01003C07F7",
7744        "Counter": "0,1,2,3",
7745        "EventName": "OCR.ALL_READS.L3_HIT.NO_SNOOP_NEEDED",
7746        "MSRIndex": "0x1a6,0x1a7",
7747        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
7748        "SampleAfterValue": "100003",
7749        "CounterHTOff": "0,1,2,3"
7750    },
7751    {
7752        "Offcore": "1",
7753        "EventCode": "0xB7, 0xBB",
7754        "UMask": "0x1",
7755        "BriefDescription": "TBD TBD",
7756        "MSRValue": "0x02003C07F7",
7757        "Counter": "0,1,2,3",
7758        "EventName": "OCR.ALL_READS.L3_HIT.SNOOP_MISS",
7759        "MSRIndex": "0x1a6,0x1a7",
7760        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
7761        "SampleAfterValue": "100003",
7762        "CounterHTOff": "0,1,2,3"
7763    },
7764    {
7765        "Offcore": "1",
7766        "EventCode": "0xB7, 0xBB",
7767        "UMask": "0x1",
7768        "BriefDescription": "TBD TBD TBD",
7769        "MSRValue": "0x04003C07F7",
7770        "Counter": "0,1,2,3",
7771        "EventName": "OCR.ALL_READS.L3_HIT.HIT_OTHER_CORE_NO_FWD",
7772        "MSRIndex": "0x1a6,0x1a7",
7773        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
7774        "SampleAfterValue": "100003",
7775        "CounterHTOff": "0,1,2,3"
7776    },
7777    {
7778        "Offcore": "1",
7779        "EventCode": "0xB7, 0xBB",
7780        "UMask": "0x1",
7781        "BriefDescription": "TBD TBD TBD",
7782        "MSRValue": "0x08003C07F7",
7783        "Counter": "0,1,2,3",
7784        "EventName": "OCR.ALL_READS.L3_HIT.HIT_OTHER_CORE_FWD",
7785        "MSRIndex": "0x1a6,0x1a7",
7786        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
7787        "SampleAfterValue": "100003",
7788        "CounterHTOff": "0,1,2,3"
7789    },
7790    {
7791        "Offcore": "1",
7792        "EventCode": "0xB7, 0xBB",
7793        "UMask": "0x1",
7794        "BriefDescription": "TBD TBD TBD",
7795        "MSRValue": "0x10003C07F7",
7796        "Counter": "0,1,2,3",
7797        "EventName": "OCR.ALL_READS.L3_HIT.HITM_OTHER_CORE",
7798        "MSRIndex": "0x1a6,0x1a7",
7799        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
7800        "SampleAfterValue": "100003",
7801        "CounterHTOff": "0,1,2,3"
7802    },
7803    {
7804        "Offcore": "1",
7805        "EventCode": "0xB7, 0xBB",
7806        "UMask": "0x1",
7807        "BriefDescription": "TBD TBD TBD",
7808        "MSRValue": "0x3F803C07F7",
7809        "Counter": "0,1,2,3",
7810        "EventName": "OCR.ALL_READS.L3_HIT.ANY_SNOOP",
7811        "MSRIndex": "0x1a6,0x1a7",
7812        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
7813        "SampleAfterValue": "100003",
7814        "CounterHTOff": "0,1,2,3"
7815    },
7816    {
7817        "Offcore": "1",
7818        "EventCode": "0xB7, 0xBB",
7819        "UMask": "0x1",
7820        "BriefDescription": "Counts demand data reads have any response type.",
7821        "MSRValue": "0x0000010001",
7822        "Counter": "0,1,2,3",
7823        "EventName": "OCR.DEMAND_DATA_RD.ANY_RESPONSE",
7824        "MSRIndex": "0x1a6,0x1a7",
7825        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
7826        "SampleAfterValue": "100003",
7827        "CounterHTOff": "0,1,2,3"
7828    },
7829    {
7830        "Offcore": "1",
7831        "EventCode": "0xB7, 0xBB",
7832        "UMask": "0x1",
7833        "BriefDescription": "Counts demand data reads hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.",
7834        "MSRValue": "0x01003C0001",
7835        "Counter": "0,1,2,3",
7836        "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.NO_SNOOP_NEEDED",
7837        "MSRIndex": "0x1a6,0x1a7",
7838        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
7839        "SampleAfterValue": "100003",
7840        "CounterHTOff": "0,1,2,3"
7841    },
7842    {
7843        "Offcore": "1",
7844        "EventCode": "0xB7, 0xBB",
7845        "UMask": "0x1",
7846        "BriefDescription": "Counts demand data reads",
7847        "MSRValue": "0x08007C0001",
7848        "Counter": "0,1,2,3",
7849        "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD",
7850        "MSRIndex": "0x1a6,0x1a7",
7851        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
7852        "SampleAfterValue": "100003",
7853        "CounterHTOff": "0,1,2,3"
7854    },
7855    {
7856        "Offcore": "1",
7857        "EventCode": "0xB7, 0xBB",
7858        "UMask": "0x1",
7859        "BriefDescription": "Counts all demand data writes (RFOs) have any response type.",
7860        "MSRValue": "0x0000010002",
7861        "Counter": "0,1,2,3",
7862        "EventName": "OCR.DEMAND_RFO.ANY_RESPONSE",
7863        "MSRIndex": "0x1a6,0x1a7",
7864        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
7865        "SampleAfterValue": "100003",
7866        "CounterHTOff": "0,1,2,3"
7867    },
7868    {
7869        "Offcore": "1",
7870        "EventCode": "0xB7, 0xBB",
7871        "UMask": "0x1",
7872        "BriefDescription": "Counts all demand data writes (RFOs) hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.",
7873        "MSRValue": "0x01003C0002",
7874        "Counter": "0,1,2,3",
7875        "EventName": "OCR.DEMAND_RFO.L3_HIT.NO_SNOOP_NEEDED",
7876        "MSRIndex": "0x1a6,0x1a7",
7877        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
7878        "SampleAfterValue": "100003",
7879        "CounterHTOff": "0,1,2,3"
7880    },
7881    {
7882        "Offcore": "1",
7883        "EventCode": "0xB7, 0xBB",
7884        "UMask": "0x1",
7885        "BriefDescription": "Counts all demand data writes (RFOs)",
7886        "MSRValue": "0x08007C0002",
7887        "Counter": "0,1,2,3",
7888        "EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_HIT_WITH_FWD",
7889        "MSRIndex": "0x1a6,0x1a7",
7890        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
7891        "SampleAfterValue": "100003",
7892        "CounterHTOff": "0,1,2,3"
7893    },
7894    {
7895        "Offcore": "1",
7896        "EventCode": "0xB7, 0xBB",
7897        "UMask": "0x1",
7898        "BriefDescription": "Counts all demand code reads have any response type.",
7899        "MSRValue": "0x0000010004",
7900        "Counter": "0,1,2,3",
7901        "EventName": "OCR.DEMAND_CODE_RD.ANY_RESPONSE",
7902        "MSRIndex": "0x1a6,0x1a7",
7903        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
7904        "SampleAfterValue": "100003",
7905        "CounterHTOff": "0,1,2,3"
7906    },
7907    {
7908        "Offcore": "1",
7909        "EventCode": "0xB7, 0xBB",
7910        "UMask": "0x1",
7911        "BriefDescription": "Counts all demand code reads hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.",
7912        "MSRValue": "0x01003C0004",
7913        "Counter": "0,1,2,3",
7914        "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.NO_SNOOP_NEEDED",
7915        "MSRIndex": "0x1a6,0x1a7",
7916        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
7917        "SampleAfterValue": "100003",
7918        "CounterHTOff": "0,1,2,3"
7919    },
7920    {
7921        "Offcore": "1",
7922        "EventCode": "0xB7, 0xBB",
7923        "UMask": "0x1",
7924        "BriefDescription": "Counts all demand code reads",
7925        "MSRValue": "0x08007C0004",
7926        "Counter": "0,1,2,3",
7927        "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_HIT_WITH_FWD",
7928        "MSRIndex": "0x1a6,0x1a7",
7929        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
7930        "SampleAfterValue": "100003",
7931        "CounterHTOff": "0,1,2,3"
7932    },
7933    {
7934        "Offcore": "1",
7935        "EventCode": "0xB7, 0xBB",
7936        "UMask": "0x1",
7937        "BriefDescription": "Counts prefetch (that bring data to L2) data reads have any response type.",
7938        "MSRValue": "0x0000010010",
7939        "Counter": "0,1,2,3",
7940        "EventName": "OCR.PF_L2_DATA_RD.ANY_RESPONSE",
7941        "MSRIndex": "0x1a6,0x1a7",
7942        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
7943        "SampleAfterValue": "100003",
7944        "CounterHTOff": "0,1,2,3"
7945    },
7946    {
7947        "Offcore": "1",
7948        "EventCode": "0xB7, 0xBB",
7949        "UMask": "0x1",
7950        "BriefDescription": "Counts prefetch (that bring data to L2) data reads hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.",
7951        "MSRValue": "0x01003C0010",
7952        "Counter": "0,1,2,3",
7953        "EventName": "OCR.PF_L2_DATA_RD.L3_HIT.NO_SNOOP_NEEDED",
7954        "MSRIndex": "0x1a6,0x1a7",
7955        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
7956        "SampleAfterValue": "100003",
7957        "CounterHTOff": "0,1,2,3"
7958    },
7959    {
7960        "Offcore": "1",
7961        "EventCode": "0xB7, 0xBB",
7962        "UMask": "0x1",
7963        "BriefDescription": "Counts prefetch (that bring data to L2) data reads",
7964        "MSRValue": "0x08007C0010",
7965        "Counter": "0,1,2,3",
7966        "EventName": "OCR.PF_L2_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD",
7967        "MSRIndex": "0x1a6,0x1a7",
7968        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
7969        "SampleAfterValue": "100003",
7970        "CounterHTOff": "0,1,2,3"
7971    },
7972    {
7973        "Offcore": "1",
7974        "EventCode": "0xB7, 0xBB",
7975        "UMask": "0x1",
7976        "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs have any response type.",
7977        "MSRValue": "0x0000010020",
7978        "Counter": "0,1,2,3",
7979        "EventName": "OCR.PF_L2_RFO.ANY_RESPONSE",
7980        "MSRIndex": "0x1a6,0x1a7",
7981        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
7982        "SampleAfterValue": "100003",
7983        "CounterHTOff": "0,1,2,3"
7984    },
7985    {
7986        "Offcore": "1",
7987        "EventCode": "0xB7, 0xBB",
7988        "UMask": "0x1",
7989        "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.",
7990        "MSRValue": "0x01003C0020",
7991        "Counter": "0,1,2,3",
7992        "EventName": "OCR.PF_L2_RFO.L3_HIT.NO_SNOOP_NEEDED",
7993        "MSRIndex": "0x1a6,0x1a7",
7994        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
7995        "SampleAfterValue": "100003",
7996        "CounterHTOff": "0,1,2,3"
7997    },
7998    {
7999        "Offcore": "1",
8000        "EventCode": "0xB7, 0xBB",
8001        "UMask": "0x1",
8002        "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs",
8003        "MSRValue": "0x08007C0020",
8004        "Counter": "0,1,2,3",
8005        "EventName": "OCR.PF_L2_RFO.L3_HIT.SNOOP_HIT_WITH_FWD",
8006        "MSRIndex": "0x1a6,0x1a7",
8007        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
8008        "SampleAfterValue": "100003",
8009        "CounterHTOff": "0,1,2,3"
8010    },
8011    {
8012        "Offcore": "1",
8013        "EventCode": "0xB7, 0xBB",
8014        "UMask": "0x1",
8015        "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads have any response type.",
8016        "MSRValue": "0x0000010080",
8017        "Counter": "0,1,2,3",
8018        "EventName": "OCR.PF_L3_DATA_RD.ANY_RESPONSE",
8019        "MSRIndex": "0x1a6,0x1a7",
8020        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
8021        "SampleAfterValue": "100003",
8022        "CounterHTOff": "0,1,2,3"
8023    },
8024    {
8025        "Offcore": "1",
8026        "EventCode": "0xB7, 0xBB",
8027        "UMask": "0x1",
8028        "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.",
8029        "MSRValue": "0x01003C0080",
8030        "Counter": "0,1,2,3",
8031        "EventName": "OCR.PF_L3_DATA_RD.L3_HIT.NO_SNOOP_NEEDED",
8032        "MSRIndex": "0x1a6,0x1a7",
8033        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
8034        "SampleAfterValue": "100003",
8035        "CounterHTOff": "0,1,2,3"
8036    },
8037    {
8038        "Offcore": "1",
8039        "EventCode": "0xB7, 0xBB",
8040        "UMask": "0x1",
8041        "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads",
8042        "MSRValue": "0x08007C0080",
8043        "Counter": "0,1,2,3",
8044        "EventName": "OCR.PF_L3_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD",
8045        "MSRIndex": "0x1a6,0x1a7",
8046        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
8047        "SampleAfterValue": "100003",
8048        "CounterHTOff": "0,1,2,3"
8049    },
8050    {
8051        "Offcore": "1",
8052        "EventCode": "0xB7, 0xBB",
8053        "UMask": "0x1",
8054        "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs have any response type.",
8055        "MSRValue": "0x0000010100",
8056        "Counter": "0,1,2,3",
8057        "EventName": "OCR.PF_L3_RFO.ANY_RESPONSE",
8058        "MSRIndex": "0x1a6,0x1a7",
8059        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
8060        "SampleAfterValue": "100003",
8061        "CounterHTOff": "0,1,2,3"
8062    },
8063    {
8064        "Offcore": "1",
8065        "EventCode": "0xB7, 0xBB",
8066        "UMask": "0x1",
8067        "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.",
8068        "MSRValue": "0x01003C0100",
8069        "Counter": "0,1,2,3",
8070        "EventName": "OCR.PF_L3_RFO.L3_HIT.NO_SNOOP_NEEDED",
8071        "MSRIndex": "0x1a6,0x1a7",
8072        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
8073        "SampleAfterValue": "100003",
8074        "CounterHTOff": "0,1,2,3"
8075    },
8076    {
8077        "Offcore": "1",
8078        "EventCode": "0xB7, 0xBB",
8079        "UMask": "0x1",
8080        "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs",
8081        "MSRValue": "0x08007C0100",
8082        "Counter": "0,1,2,3",
8083        "EventName": "OCR.PF_L3_RFO.L3_HIT.SNOOP_HIT_WITH_FWD",
8084        "MSRIndex": "0x1a6,0x1a7",
8085        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
8086        "SampleAfterValue": "100003",
8087        "CounterHTOff": "0,1,2,3"
8088    },
8089    {
8090        "Offcore": "1",
8091        "EventCode": "0xB7, 0xBB",
8092        "UMask": "0x1",
8093        "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests have any response type.",
8094        "MSRValue": "0x0000010400",
8095        "Counter": "0,1,2,3",
8096        "EventName": "OCR.PF_L1D_AND_SW.ANY_RESPONSE",
8097        "MSRIndex": "0x1a6,0x1a7",
8098        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
8099        "SampleAfterValue": "100003",
8100        "CounterHTOff": "0,1,2,3"
8101    },
8102    {
8103        "Offcore": "1",
8104        "EventCode": "0xB7, 0xBB",
8105        "UMask": "0x1",
8106        "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.",
8107        "MSRValue": "0x01003C0400",
8108        "Counter": "0,1,2,3",
8109        "EventName": "OCR.PF_L1D_AND_SW.L3_HIT.NO_SNOOP_NEEDED",
8110        "MSRIndex": "0x1a6,0x1a7",
8111        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
8112        "SampleAfterValue": "100003",
8113        "CounterHTOff": "0,1,2,3"
8114    },
8115    {
8116        "Offcore": "1",
8117        "EventCode": "0xB7, 0xBB",
8118        "UMask": "0x1",
8119        "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests",
8120        "MSRValue": "0x08007C0400",
8121        "Counter": "0,1,2,3",
8122        "EventName": "OCR.PF_L1D_AND_SW.L3_HIT.SNOOP_HIT_WITH_FWD",
8123        "MSRIndex": "0x1a6,0x1a7",
8124        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
8125        "SampleAfterValue": "100003",
8126        "CounterHTOff": "0,1,2,3"
8127    },
8128    {
8129        "Offcore": "1",
8130        "EventCode": "0xB7, 0xBB",
8131        "UMask": "0x1",
8132        "BriefDescription": "Counts any other requests have any response type.",
8133        "MSRValue": "0x0000018000",
8134        "Counter": "0,1,2,3",
8135        "EventName": "OCR.OTHER.ANY_RESPONSE",
8136        "MSRIndex": "0x1a6,0x1a7",
8137        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
8138        "SampleAfterValue": "100003",
8139        "CounterHTOff": "0,1,2,3"
8140    },
8141    {
8142        "Offcore": "1",
8143        "EventCode": "0xB7, 0xBB",
8144        "UMask": "0x1",
8145        "BriefDescription": "Counts any other requests hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.",
8146        "MSRValue": "0x01003C8000",
8147        "Counter": "0,1,2,3",
8148        "EventName": "OCR.OTHER.L3_HIT.NO_SNOOP_NEEDED",
8149        "MSRIndex": "0x1a6,0x1a7",
8150        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
8151        "SampleAfterValue": "100003",
8152        "CounterHTOff": "0,1,2,3"
8153    },
8154    {
8155        "Offcore": "1",
8156        "EventCode": "0xB7, 0xBB",
8157        "UMask": "0x1",
8158        "BriefDescription": "Counts any other requests",
8159        "MSRValue": "0x08007C8000",
8160        "Counter": "0,1,2,3",
8161        "EventName": "OCR.OTHER.L3_HIT.SNOOP_HIT_WITH_FWD",
8162        "MSRIndex": "0x1a6,0x1a7",
8163        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
8164        "SampleAfterValue": "100003",
8165        "CounterHTOff": "0,1,2,3"
8166    },
8167    {
8168        "Offcore": "1",
8169        "EventCode": "0xB7, 0xBB",
8170        "UMask": "0x1",
8171        "BriefDescription": "TBD have any response type.",
8172        "MSRValue": "0x0000010490",
8173        "Counter": "0,1,2,3",
8174        "EventName": "OCR.ALL_PF_DATA_RD.ANY_RESPONSE",
8175        "MSRIndex": "0x1a6,0x1a7",
8176        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
8177        "SampleAfterValue": "100003",
8178        "CounterHTOff": "0,1,2,3"
8179    },
8180    {
8181        "Offcore": "1",
8182        "EventCode": "0xB7, 0xBB",
8183        "UMask": "0x1",
8184        "BriefDescription": "TBD hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.",
8185        "MSRValue": "0x01003C0490",
8186        "Counter": "0,1,2,3",
8187        "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT.NO_SNOOP_NEEDED",
8188        "MSRIndex": "0x1a6,0x1a7",
8189        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
8190        "SampleAfterValue": "100003",
8191        "CounterHTOff": "0,1,2,3"
8192    },
8193    {
8194        "Offcore": "1",
8195        "EventCode": "0xB7, 0xBB",
8196        "UMask": "0x1",
8197        "BriefDescription": "TBD",
8198        "MSRValue": "0x08007C0490",
8199        "Counter": "0,1,2,3",
8200        "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD",
8201        "MSRIndex": "0x1a6,0x1a7",
8202        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
8203        "SampleAfterValue": "100003",
8204        "CounterHTOff": "0,1,2,3"
8205    },
8206    {
8207        "Offcore": "1",
8208        "EventCode": "0xB7, 0xBB",
8209        "UMask": "0x1",
8210        "BriefDescription": "TBD have any response type.",
8211        "MSRValue": "0x0000010120",
8212        "Counter": "0,1,2,3",
8213        "EventName": "OCR.ALL_PF_RFO.ANY_RESPONSE",
8214        "MSRIndex": "0x1a6,0x1a7",
8215        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
8216        "SampleAfterValue": "100003",
8217        "CounterHTOff": "0,1,2,3"
8218    },
8219    {
8220        "Offcore": "1",
8221        "EventCode": "0xB7, 0xBB",
8222        "UMask": "0x1",
8223        "BriefDescription": "TBD hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.",
8224        "MSRValue": "0x01003C0120",
8225        "Counter": "0,1,2,3",
8226        "EventName": "OCR.ALL_PF_RFO.L3_HIT.NO_SNOOP_NEEDED",
8227        "MSRIndex": "0x1a6,0x1a7",
8228        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
8229        "SampleAfterValue": "100003",
8230        "CounterHTOff": "0,1,2,3"
8231    },
8232    {
8233        "Offcore": "1",
8234        "EventCode": "0xB7, 0xBB",
8235        "UMask": "0x1",
8236        "BriefDescription": "TBD",
8237        "MSRValue": "0x08007C0120",
8238        "Counter": "0,1,2,3",
8239        "EventName": "OCR.ALL_PF_RFO.L3_HIT.SNOOP_HIT_WITH_FWD",
8240        "MSRIndex": "0x1a6,0x1a7",
8241        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
8242        "SampleAfterValue": "100003",
8243        "CounterHTOff": "0,1,2,3"
8244    },
8245    {
8246        "Offcore": "1",
8247        "EventCode": "0xB7, 0xBB",
8248        "UMask": "0x1",
8249        "BriefDescription": "TBD have any response type.",
8250        "MSRValue": "0x0000010491",
8251        "Counter": "0,1,2,3",
8252        "EventName": "OCR.ALL_DATA_RD.ANY_RESPONSE",
8253        "MSRIndex": "0x1a6,0x1a7",
8254        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
8255        "SampleAfterValue": "100003",
8256        "CounterHTOff": "0,1,2,3"
8257    },
8258    {
8259        "Offcore": "1",
8260        "EventCode": "0xB7, 0xBB",
8261        "UMask": "0x1",
8262        "BriefDescription": "TBD hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.",
8263        "MSRValue": "0x01003C0491",
8264        "Counter": "0,1,2,3",
8265        "EventName": "OCR.ALL_DATA_RD.L3_HIT.NO_SNOOP_NEEDED",
8266        "MSRIndex": "0x1a6,0x1a7",
8267        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
8268        "SampleAfterValue": "100003",
8269        "CounterHTOff": "0,1,2,3"
8270    },
8271    {
8272        "Offcore": "1",
8273        "EventCode": "0xB7, 0xBB",
8274        "UMask": "0x1",
8275        "BriefDescription": "TBD",
8276        "MSRValue": "0x08007C0491",
8277        "Counter": "0,1,2,3",
8278        "EventName": "OCR.ALL_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD",
8279        "MSRIndex": "0x1a6,0x1a7",
8280        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
8281        "SampleAfterValue": "100003",
8282        "CounterHTOff": "0,1,2,3"
8283    },
8284    {
8285        "Offcore": "1",
8286        "EventCode": "0xB7, 0xBB",
8287        "UMask": "0x1",
8288        "BriefDescription": "TBD have any response type.",
8289        "MSRValue": "0x0000010122",
8290        "Counter": "0,1,2,3",
8291        "EventName": "OCR.ALL_RFO.ANY_RESPONSE",
8292        "MSRIndex": "0x1a6,0x1a7",
8293        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
8294        "SampleAfterValue": "100003",
8295        "CounterHTOff": "0,1,2,3"
8296    },
8297    {
8298        "Offcore": "1",
8299        "EventCode": "0xB7, 0xBB",
8300        "UMask": "0x1",
8301        "BriefDescription": "TBD hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.",
8302        "MSRValue": "0x01003C0122",
8303        "Counter": "0,1,2,3",
8304        "EventName": "OCR.ALL_RFO.L3_HIT.NO_SNOOP_NEEDED",
8305        "MSRIndex": "0x1a6,0x1a7",
8306        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
8307        "SampleAfterValue": "100003",
8308        "CounterHTOff": "0,1,2,3"
8309    },
8310    {
8311        "Offcore": "1",
8312        "EventCode": "0xB7, 0xBB",
8313        "UMask": "0x1",
8314        "BriefDescription": "TBD",
8315        "MSRValue": "0x08007C0122",
8316        "Counter": "0,1,2,3",
8317        "EventName": "OCR.ALL_RFO.L3_HIT.SNOOP_HIT_WITH_FWD",
8318        "MSRIndex": "0x1a6,0x1a7",
8319        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
8320        "SampleAfterValue": "100003",
8321        "CounterHTOff": "0,1,2,3"
8322    },
8323    {
8324        "Offcore": "1",
8325        "EventCode": "0xB7, 0xBB",
8326        "UMask": "0x1",
8327        "BriefDescription": "TBD have any response type.",
8328        "MSRValue": "0x00000107F7",
8329        "Counter": "0,1,2,3",
8330        "EventName": "OCR.ALL_READS.ANY_RESPONSE",
8331        "MSRIndex": "0x1a6,0x1a7",
8332        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
8333        "SampleAfterValue": "100003",
8334        "CounterHTOff": "0,1,2,3"
8335    },
8336    {
8337        "Offcore": "1",
8338        "EventCode": "0xB7, 0xBB",
8339        "UMask": "0x1",
8340        "BriefDescription": "TBD hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.",
8341        "MSRValue": "0x01003C07F7",
8342        "Counter": "0,1,2,3",
8343        "EventName": "OCR.ALL_READS.L3_HIT.NO_SNOOP_NEEDED",
8344        "MSRIndex": "0x1a6,0x1a7",
8345        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
8346        "SampleAfterValue": "100003",
8347        "CounterHTOff": "0,1,2,3"
8348    },
8349    {
8350        "Offcore": "1",
8351        "EventCode": "0xB7, 0xBB",
8352        "UMask": "0x1",
8353        "BriefDescription": "TBD",
8354        "MSRValue": "0x08007C07F7",
8355        "Counter": "0,1,2,3",
8356        "EventName": "OCR.ALL_READS.L3_HIT.SNOOP_HIT_WITH_FWD",
8357        "MSRIndex": "0x1a6,0x1a7",
8358        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
8359        "SampleAfterValue": "100003",
8360        "CounterHTOff": "0,1,2,3"
8361    },
8362    {
8363        "Offcore": "1",
8364        "EventCode": "0xB7, 0xBB",
8365        "UMask": "0x1",
8366        "BriefDescription": "Counts demand data reads TBD",
8367        "MSRValue": "0x0100400001",
8368        "Counter": "0,1,2,3",
8369        "EventName": "OCR.DEMAND_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED",
8370        "MSRIndex": "0x1a6,0x1a7",
8371        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
8372        "SampleAfterValue": "100003",
8373        "CounterHTOff": "0,1,2,3"
8374    },
8375    {
8376        "Offcore": "1",
8377        "EventCode": "0xB7, 0xBB",
8378        "UMask": "0x1",
8379        "BriefDescription": "Counts demand data reads TBD",
8380        "MSRValue": "0x0080400001",
8381        "Counter": "0,1,2,3",
8382        "EventName": "OCR.DEMAND_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE",
8383        "MSRIndex": "0x1a6,0x1a7",
8384        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
8385        "SampleAfterValue": "100003",
8386        "CounterHTOff": "0,1,2,3"
8387    },
8388    {
8389        "Offcore": "1",
8390        "EventCode": "0xB7, 0xBB",
8391        "UMask": "0x1",
8392        "BriefDescription": "Counts all demand data writes (RFOs) TBD",
8393        "MSRValue": "0x0100400002",
8394        "Counter": "0,1,2,3",
8395        "EventName": "OCR.DEMAND_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED",
8396        "MSRIndex": "0x1a6,0x1a7",
8397        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
8398        "SampleAfterValue": "100003",
8399        "CounterHTOff": "0,1,2,3"
8400    },
8401    {
8402        "Offcore": "1",
8403        "EventCode": "0xB7, 0xBB",
8404        "UMask": "0x1",
8405        "BriefDescription": "Counts all demand data writes (RFOs) TBD",
8406        "MSRValue": "0x0080400002",
8407        "Counter": "0,1,2,3",
8408        "EventName": "OCR.DEMAND_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NONE",
8409        "MSRIndex": "0x1a6,0x1a7",
8410        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
8411        "SampleAfterValue": "100003",
8412        "CounterHTOff": "0,1,2,3"
8413    },
8414    {
8415        "Offcore": "1",
8416        "EventCode": "0xB7, 0xBB",
8417        "UMask": "0x1",
8418        "BriefDescription": "Counts all demand code reads TBD",
8419        "MSRValue": "0x0100400004",
8420        "Counter": "0,1,2,3",
8421        "EventName": "OCR.DEMAND_CODE_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED",
8422        "MSRIndex": "0x1a6,0x1a7",
8423        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
8424        "SampleAfterValue": "100003",
8425        "CounterHTOff": "0,1,2,3"
8426    },
8427    {
8428        "Offcore": "1",
8429        "EventCode": "0xB7, 0xBB",
8430        "UMask": "0x1",
8431        "BriefDescription": "Counts all demand code reads TBD",
8432        "MSRValue": "0x0080400004",
8433        "Counter": "0,1,2,3",
8434        "EventName": "OCR.DEMAND_CODE_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE",
8435        "MSRIndex": "0x1a6,0x1a7",
8436        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
8437        "SampleAfterValue": "100003",
8438        "CounterHTOff": "0,1,2,3"
8439    },
8440    {
8441        "Offcore": "1",
8442        "EventCode": "0xB7, 0xBB",
8443        "UMask": "0x1",
8444        "BriefDescription": "Counts prefetch (that bring data to L2) data reads TBD",
8445        "MSRValue": "0x0100400010",
8446        "Counter": "0,1,2,3",
8447        "EventName": "OCR.PF_L2_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED",
8448        "MSRIndex": "0x1a6,0x1a7",
8449        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
8450        "SampleAfterValue": "100003",
8451        "CounterHTOff": "0,1,2,3"
8452    },
8453    {
8454        "Offcore": "1",
8455        "EventCode": "0xB7, 0xBB",
8456        "UMask": "0x1",
8457        "BriefDescription": "Counts prefetch (that bring data to L2) data reads TBD",
8458        "MSRValue": "0x0080400010",
8459        "Counter": "0,1,2,3",
8460        "EventName": "OCR.PF_L2_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE",
8461        "MSRIndex": "0x1a6,0x1a7",
8462        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
8463        "SampleAfterValue": "100003",
8464        "CounterHTOff": "0,1,2,3"
8465    },
8466    {
8467        "Offcore": "1",
8468        "EventCode": "0xB7, 0xBB",
8469        "UMask": "0x1",
8470        "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs TBD",
8471        "MSRValue": "0x0100400020",
8472        "Counter": "0,1,2,3",
8473        "EventName": "OCR.PF_L2_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED",
8474        "MSRIndex": "0x1a6,0x1a7",
8475        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
8476        "SampleAfterValue": "100003",
8477        "CounterHTOff": "0,1,2,3"
8478    },
8479    {
8480        "Offcore": "1",
8481        "EventCode": "0xB7, 0xBB",
8482        "UMask": "0x1",
8483        "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs TBD",
8484        "MSRValue": "0x0080400020",
8485        "Counter": "0,1,2,3",
8486        "EventName": "OCR.PF_L2_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NONE",
8487        "MSRIndex": "0x1a6,0x1a7",
8488        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
8489        "SampleAfterValue": "100003",
8490        "CounterHTOff": "0,1,2,3"
8491    },
8492    {
8493        "Offcore": "1",
8494        "EventCode": "0xB7, 0xBB",
8495        "UMask": "0x1",
8496        "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads TBD",
8497        "MSRValue": "0x0100400080",
8498        "Counter": "0,1,2,3",
8499        "EventName": "OCR.PF_L3_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED",
8500        "MSRIndex": "0x1a6,0x1a7",
8501        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
8502        "SampleAfterValue": "100003",
8503        "CounterHTOff": "0,1,2,3"
8504    },
8505    {
8506        "Offcore": "1",
8507        "EventCode": "0xB7, 0xBB",
8508        "UMask": "0x1",
8509        "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads TBD",
8510        "MSRValue": "0x0080400080",
8511        "Counter": "0,1,2,3",
8512        "EventName": "OCR.PF_L3_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE",
8513        "MSRIndex": "0x1a6,0x1a7",
8514        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
8515        "SampleAfterValue": "100003",
8516        "CounterHTOff": "0,1,2,3"
8517    },
8518    {
8519        "Offcore": "1",
8520        "EventCode": "0xB7, 0xBB",
8521        "UMask": "0x1",
8522        "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs TBD",
8523        "MSRValue": "0x0100400100",
8524        "Counter": "0,1,2,3",
8525        "EventName": "OCR.PF_L3_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED",
8526        "MSRIndex": "0x1a6,0x1a7",
8527        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
8528        "SampleAfterValue": "100003",
8529        "CounterHTOff": "0,1,2,3"
8530    },
8531    {
8532        "Offcore": "1",
8533        "EventCode": "0xB7, 0xBB",
8534        "UMask": "0x1",
8535        "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs TBD",
8536        "MSRValue": "0x0080400100",
8537        "Counter": "0,1,2,3",
8538        "EventName": "OCR.PF_L3_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NONE",
8539        "MSRIndex": "0x1a6,0x1a7",
8540        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
8541        "SampleAfterValue": "100003",
8542        "CounterHTOff": "0,1,2,3"
8543    },
8544    {
8545        "Offcore": "1",
8546        "EventCode": "0xB7, 0xBB",
8547        "UMask": "0x1",
8548        "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests TBD",
8549        "MSRValue": "0x0100400400",
8550        "Counter": "0,1,2,3",
8551        "EventName": "OCR.PF_L1D_AND_SW.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED",
8552        "MSRIndex": "0x1a6,0x1a7",
8553        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
8554        "SampleAfterValue": "100003",
8555        "CounterHTOff": "0,1,2,3"
8556    },
8557    {
8558        "Offcore": "1",
8559        "EventCode": "0xB7, 0xBB",
8560        "UMask": "0x1",
8561        "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests TBD",
8562        "MSRValue": "0x0080400400",
8563        "Counter": "0,1,2,3",
8564        "EventName": "OCR.PF_L1D_AND_SW.PMM_HIT_LOCAL_PMM.SNOOP_NONE",
8565        "MSRIndex": "0x1a6,0x1a7",
8566        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
8567        "SampleAfterValue": "100003",
8568        "CounterHTOff": "0,1,2,3"
8569    },
8570    {
8571        "Offcore": "1",
8572        "EventCode": "0xB7, 0xBB",
8573        "UMask": "0x1",
8574        "BriefDescription": "Counts any other requests TBD",
8575        "MSRValue": "0x0100408000",
8576        "Counter": "0,1,2,3",
8577        "EventName": "OCR.OTHER.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED",
8578        "MSRIndex": "0x1a6,0x1a7",
8579        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
8580        "SampleAfterValue": "100003",
8581        "CounterHTOff": "0,1,2,3"
8582    },
8583    {
8584        "Offcore": "1",
8585        "EventCode": "0xB7, 0xBB",
8586        "UMask": "0x1",
8587        "BriefDescription": "Counts any other requests TBD",
8588        "MSRValue": "0x0080408000",
8589        "Counter": "0,1,2,3",
8590        "EventName": "OCR.OTHER.PMM_HIT_LOCAL_PMM.SNOOP_NONE",
8591        "MSRIndex": "0x1a6,0x1a7",
8592        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
8593        "SampleAfterValue": "100003",
8594        "CounterHTOff": "0,1,2,3"
8595    },
8596    {
8597        "Offcore": "1",
8598        "EventCode": "0xB7, 0xBB",
8599        "UMask": "0x1",
8600        "BriefDescription": "TBD TBD",
8601        "MSRValue": "0x0100400490",
8602        "Counter": "0,1,2,3",
8603        "EventName": "OCR.ALL_PF_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED",
8604        "MSRIndex": "0x1a6,0x1a7",
8605        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
8606        "SampleAfterValue": "100003",
8607        "CounterHTOff": "0,1,2,3"
8608    },
8609    {
8610        "Offcore": "1",
8611        "EventCode": "0xB7, 0xBB",
8612        "UMask": "0x1",
8613        "BriefDescription": "TBD TBD",
8614        "MSRValue": "0x0080400490",
8615        "Counter": "0,1,2,3",
8616        "EventName": "OCR.ALL_PF_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE",
8617        "MSRIndex": "0x1a6,0x1a7",
8618        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
8619        "SampleAfterValue": "100003",
8620        "CounterHTOff": "0,1,2,3"
8621    },
8622    {
8623        "Offcore": "1",
8624        "EventCode": "0xB7, 0xBB",
8625        "UMask": "0x1",
8626        "BriefDescription": "TBD TBD",
8627        "MSRValue": "0x0100400120",
8628        "Counter": "0,1,2,3",
8629        "EventName": "OCR.ALL_PF_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED",
8630        "MSRIndex": "0x1a6,0x1a7",
8631        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
8632        "SampleAfterValue": "100003",
8633        "CounterHTOff": "0,1,2,3"
8634    },
8635    {
8636        "Offcore": "1",
8637        "EventCode": "0xB7, 0xBB",
8638        "UMask": "0x1",
8639        "BriefDescription": "TBD TBD",
8640        "MSRValue": "0x0080400120",
8641        "Counter": "0,1,2,3",
8642        "EventName": "OCR.ALL_PF_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NONE",
8643        "MSRIndex": "0x1a6,0x1a7",
8644        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
8645        "SampleAfterValue": "100003",
8646        "CounterHTOff": "0,1,2,3"
8647    },
8648    {
8649        "Offcore": "1",
8650        "EventCode": "0xB7, 0xBB",
8651        "UMask": "0x1",
8652        "BriefDescription": "TBD TBD",
8653        "MSRValue": "0x0100400491",
8654        "Counter": "0,1,2,3",
8655        "EventName": "OCR.ALL_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED",
8656        "MSRIndex": "0x1a6,0x1a7",
8657        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
8658        "SampleAfterValue": "100003",
8659        "CounterHTOff": "0,1,2,3"
8660    },
8661    {
8662        "Offcore": "1",
8663        "EventCode": "0xB7, 0xBB",
8664        "UMask": "0x1",
8665        "BriefDescription": "TBD TBD",
8666        "MSRValue": "0x0080400491",
8667        "Counter": "0,1,2,3",
8668        "EventName": "OCR.ALL_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE",
8669        "MSRIndex": "0x1a6,0x1a7",
8670        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
8671        "SampleAfterValue": "100003",
8672        "CounterHTOff": "0,1,2,3"
8673    },
8674    {
8675        "Offcore": "1",
8676        "EventCode": "0xB7, 0xBB",
8677        "UMask": "0x1",
8678        "BriefDescription": "TBD TBD",
8679        "MSRValue": "0x0100400122",
8680        "Counter": "0,1,2,3",
8681        "EventName": "OCR.ALL_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED",
8682        "MSRIndex": "0x1a6,0x1a7",
8683        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
8684        "SampleAfterValue": "100003",
8685        "CounterHTOff": "0,1,2,3"
8686    },
8687    {
8688        "Offcore": "1",
8689        "EventCode": "0xB7, 0xBB",
8690        "UMask": "0x1",
8691        "BriefDescription": "TBD TBD",
8692        "MSRValue": "0x0080400122",
8693        "Counter": "0,1,2,3",
8694        "EventName": "OCR.ALL_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NONE",
8695        "MSRIndex": "0x1a6,0x1a7",
8696        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
8697        "SampleAfterValue": "100003",
8698        "CounterHTOff": "0,1,2,3"
8699    },
8700    {
8701        "Offcore": "1",
8702        "EventCode": "0xB7, 0xBB",
8703        "UMask": "0x1",
8704        "BriefDescription": "TBD TBD",
8705        "MSRValue": "0x01004007F7",
8706        "Counter": "0,1,2,3",
8707        "EventName": "OCR.ALL_READS.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED",
8708        "MSRIndex": "0x1a6,0x1a7",
8709        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
8710        "SampleAfterValue": "100003",
8711        "CounterHTOff": "0,1,2,3"
8712    },
8713    {
8714        "Offcore": "1",
8715        "EventCode": "0xB7, 0xBB",
8716        "UMask": "0x1",
8717        "BriefDescription": "TBD TBD",
8718        "MSRValue": "0x00804007F7",
8719        "Counter": "0,1,2,3",
8720        "EventName": "OCR.ALL_READS.PMM_HIT_LOCAL_PMM.SNOOP_NONE",
8721        "MSRIndex": "0x1a6,0x1a7",
8722        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
8723        "SampleAfterValue": "100003",
8724        "CounterHTOff": "0,1,2,3"
8725    },
8726    {
8727        "Offcore": "1",
8728        "EventCode": "0xB7, 0xBB",
8729        "UMask": "0x1",
8730        "BriefDescription": "Counts demand data reads TBD",
8731        "MSRValue": "0x3F80400001",
8732        "Counter": "0,1,2,3",
8733        "EventName": "OCR.DEMAND_DATA_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOP",
8734        "MSRIndex": "0x1a6,0x1a7",
8735        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
8736        "SampleAfterValue": "100003",
8737        "CounterHTOff": "0,1,2,3"
8738    },
8739    {
8740        "Offcore": "1",
8741        "EventCode": "0xB7, 0xBB",
8742        "UMask": "0x1",
8743        "BriefDescription": "Counts all demand data writes (RFOs) TBD",
8744        "MSRValue": "0x3F80400002",
8745        "Counter": "0,1,2,3",
8746        "EventName": "OCR.DEMAND_RFO.PMM_HIT_LOCAL_PMM.ANY_SNOOP",
8747        "MSRIndex": "0x1a6,0x1a7",
8748        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
8749        "SampleAfterValue": "100003",
8750        "CounterHTOff": "0,1,2,3"
8751    },
8752    {
8753        "Offcore": "1",
8754        "EventCode": "0xB7, 0xBB",
8755        "UMask": "0x1",
8756        "BriefDescription": "Counts all demand code reads TBD",
8757        "MSRValue": "0x3F80400004",
8758        "Counter": "0,1,2,3",
8759        "EventName": "OCR.DEMAND_CODE_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOP",
8760        "MSRIndex": "0x1a6,0x1a7",
8761        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
8762        "SampleAfterValue": "100003",
8763        "CounterHTOff": "0,1,2,3"
8764    },
8765    {
8766        "Offcore": "1",
8767        "EventCode": "0xB7, 0xBB",
8768        "UMask": "0x1",
8769        "BriefDescription": "Counts prefetch (that bring data to L2) data reads TBD",
8770        "MSRValue": "0x3F80400010",
8771        "Counter": "0,1,2,3",
8772        "EventName": "OCR.PF_L2_DATA_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOP",
8773        "MSRIndex": "0x1a6,0x1a7",
8774        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
8775        "SampleAfterValue": "100003",
8776        "CounterHTOff": "0,1,2,3"
8777    },
8778    {
8779        "Offcore": "1",
8780        "EventCode": "0xB7, 0xBB",
8781        "UMask": "0x1",
8782        "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs TBD",
8783        "MSRValue": "0x3F80400020",
8784        "Counter": "0,1,2,3",
8785        "EventName": "OCR.PF_L2_RFO.PMM_HIT_LOCAL_PMM.ANY_SNOOP",
8786        "MSRIndex": "0x1a6,0x1a7",
8787        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
8788        "SampleAfterValue": "100003",
8789        "CounterHTOff": "0,1,2,3"
8790    },
8791    {
8792        "Offcore": "1",
8793        "EventCode": "0xB7, 0xBB",
8794        "UMask": "0x1",
8795        "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads TBD",
8796        "MSRValue": "0x3F80400080",
8797        "Counter": "0,1,2,3",
8798        "EventName": "OCR.PF_L3_DATA_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOP",
8799        "MSRIndex": "0x1a6,0x1a7",
8800        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
8801        "SampleAfterValue": "100003",
8802        "CounterHTOff": "0,1,2,3"
8803    },
8804    {
8805        "Offcore": "1",
8806        "EventCode": "0xB7, 0xBB",
8807        "UMask": "0x1",
8808        "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs TBD",
8809        "MSRValue": "0x3F80400100",
8810        "Counter": "0,1,2,3",
8811        "EventName": "OCR.PF_L3_RFO.PMM_HIT_LOCAL_PMM.ANY_SNOOP",
8812        "MSRIndex": "0x1a6,0x1a7",
8813        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
8814        "SampleAfterValue": "100003",
8815        "CounterHTOff": "0,1,2,3"
8816    },
8817    {
8818        "Offcore": "1",
8819        "EventCode": "0xB7, 0xBB",
8820        "UMask": "0x1",
8821        "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests TBD",
8822        "MSRValue": "0x3F80400400",
8823        "Counter": "0,1,2,3",
8824        "EventName": "OCR.PF_L1D_AND_SW.PMM_HIT_LOCAL_PMM.ANY_SNOOP",
8825        "MSRIndex": "0x1a6,0x1a7",
8826        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
8827        "SampleAfterValue": "100003",
8828        "CounterHTOff": "0,1,2,3"
8829    },
8830    {
8831        "Offcore": "1",
8832        "EventCode": "0xB7, 0xBB",
8833        "UMask": "0x1",
8834        "BriefDescription": "Counts any other requests TBD",
8835        "MSRValue": "0x3F80408000",
8836        "Counter": "0,1,2,3",
8837        "EventName": "OCR.OTHER.PMM_HIT_LOCAL_PMM.ANY_SNOOP",
8838        "MSRIndex": "0x1a6,0x1a7",
8839        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
8840        "SampleAfterValue": "100003",
8841        "CounterHTOff": "0,1,2,3"
8842    },
8843    {
8844        "Offcore": "1",
8845        "EventCode": "0xB7, 0xBB",
8846        "UMask": "0x1",
8847        "BriefDescription": "TBD TBD",
8848        "MSRValue": "0x3F80400490",
8849        "Counter": "0,1,2,3",
8850        "EventName": "OCR.ALL_PF_DATA_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOP",
8851        "MSRIndex": "0x1a6,0x1a7",
8852        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
8853        "SampleAfterValue": "100003",
8854        "CounterHTOff": "0,1,2,3"
8855    },
8856    {
8857        "Offcore": "1",
8858        "EventCode": "0xB7, 0xBB",
8859        "UMask": "0x1",
8860        "BriefDescription": "TBD TBD",
8861        "MSRValue": "0x3F80400120",
8862        "Counter": "0,1,2,3",
8863        "EventName": "OCR.ALL_PF_RFO.PMM_HIT_LOCAL_PMM.ANY_SNOOP",
8864        "MSRIndex": "0x1a6,0x1a7",
8865        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
8866        "SampleAfterValue": "100003",
8867        "CounterHTOff": "0,1,2,3"
8868    },
8869    {
8870        "Offcore": "1",
8871        "EventCode": "0xB7, 0xBB",
8872        "UMask": "0x1",
8873        "BriefDescription": "TBD TBD",
8874        "MSRValue": "0x3F80400491",
8875        "Counter": "0,1,2,3",
8876        "EventName": "OCR.ALL_DATA_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOP",
8877        "MSRIndex": "0x1a6,0x1a7",
8878        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
8879        "SampleAfterValue": "100003",
8880        "CounterHTOff": "0,1,2,3"
8881    },
8882    {
8883        "Offcore": "1",
8884        "EventCode": "0xB7, 0xBB",
8885        "UMask": "0x1",
8886        "BriefDescription": "TBD TBD",
8887        "MSRValue": "0x3F80400122",
8888        "Counter": "0,1,2,3",
8889        "EventName": "OCR.ALL_RFO.PMM_HIT_LOCAL_PMM.ANY_SNOOP",
8890        "MSRIndex": "0x1a6,0x1a7",
8891        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
8892        "SampleAfterValue": "100003",
8893        "CounterHTOff": "0,1,2,3"
8894    },
8895    {
8896        "Offcore": "1",
8897        "EventCode": "0xB7, 0xBB",
8898        "UMask": "0x1",
8899        "BriefDescription": "TBD TBD",
8900        "MSRValue": "0x3F804007F7",
8901        "Counter": "0,1,2,3",
8902        "EventName": "OCR.ALL_READS.PMM_HIT_LOCAL_PMM.ANY_SNOOP",
8903        "MSRIndex": "0x1a6,0x1a7",
8904        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
8905        "SampleAfterValue": "100003",
8906        "CounterHTOff": "0,1,2,3"
8907    }
8908]