1[ 2 { 3 "BriefDescription": "Counts prefetch (that bring data to L2) data reads PF_L2_DATA_RD & L3_HIT_S & HIT_OTHER_CORE_NO_FWD", 4 "Counter": "0,1,2,3", 5 "CounterHTOff": "0,1,2,3", 6 "EventCode": "0xB7, 0xBB", 7 "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", 8 "MSRIndex": "0x1a6,0x1a7", 9 "MSRValue": "0x0400100010", 10 "Offcore": "1", 11 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 12 "SampleAfterValue": "100003", 13 "UMask": "0x1" 14 }, 15 { 16 "BriefDescription": "ALL_PF_RFO & L3_HIT_S & HITM_OTHER_CORE", 17 "Counter": "0,1,2,3", 18 "CounterHTOff": "0,1,2,3", 19 "EventCode": "0xB7, 0xBB", 20 "EventName": "OCR.ALL_PF_RFO.L3_HIT_S.HITM_OTHER_CORE", 21 "MSRIndex": "0x1a6,0x1a7", 22 "MSRValue": "0x1000100120", 23 "Offcore": "1", 24 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 25 "SampleAfterValue": "100003", 26 "UMask": "0x1" 27 }, 28 { 29 "BriefDescription": "ALL_READS & L3_HIT_F & NO_SNOOP_NEEDED", 30 "Counter": "0,1,2,3", 31 "CounterHTOff": "0,1,2,3", 32 "EventCode": "0xB7, 0xBB", 33 "EventName": "OCR.ALL_READS.L3_HIT_F.NO_SNOOP_NEEDED", 34 "MSRIndex": "0x1a6,0x1a7", 35 "MSRValue": "0x01002007F7", 36 "Offcore": "1", 37 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 38 "SampleAfterValue": "100003", 39 "UMask": "0x1" 40 }, 41 { 42 "BriefDescription": "ALL_DATA_RD & L3_HIT & SNOOP_HIT_WITH_FWD", 43 "Counter": "0,1,2,3", 44 "CounterHTOff": "0,1,2,3", 45 "EventCode": "0xB7, 0xBB", 46 "EventName": "OCR.ALL_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD", 47 "MSRIndex": "0x1a6,0x1a7", 48 "MSRValue": "0x08007C0491", 49 "Offcore": "1", 50 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 51 "SampleAfterValue": "100003", 52 "UMask": "0x1" 53 }, 54 { 55 "BriefDescription": "ALL_RFO & SUPPLIER_NONE & SNOOP_MISS", 56 "Counter": "0,1,2,3", 57 "CounterHTOff": "0,1,2,3", 58 "EventCode": "0xB7, 0xBB", 59 "EventName": "OCR.ALL_RFO.SUPPLIER_NONE.SNOOP_MISS", 60 "MSRIndex": "0x1a6,0x1a7", 61 "MSRValue": "0x0200020122", 62 "Offcore": "1", 63 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 64 "SampleAfterValue": "100003", 65 "UMask": "0x1" 66 }, 67 { 68 "BriefDescription": "ALL_READS & L3_HIT_M & HIT_OTHER_CORE_FWD", 69 "Counter": "0,1,2,3", 70 "CounterHTOff": "0,1,2,3", 71 "EventCode": "0xB7, 0xBB", 72 "EventName": "OCR.ALL_READS.L3_HIT_M.HIT_OTHER_CORE_FWD", 73 "MSRIndex": "0x1a6,0x1a7", 74 "MSRValue": "0x08000407F7", 75 "Offcore": "1", 76 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 77 "SampleAfterValue": "100003", 78 "UMask": "0x1" 79 }, 80 { 81 "BriefDescription": "Counts all demand code reads DEMAND_CODE_RD & L3_HIT_S & HITM_OTHER_CORE", 82 "Counter": "0,1,2,3", 83 "CounterHTOff": "0,1,2,3", 84 "EventCode": "0xB7, 0xBB", 85 "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_S.HITM_OTHER_CORE", 86 "MSRIndex": "0x1a6,0x1a7", 87 "MSRValue": "0x1000100004", 88 "Offcore": "1", 89 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 90 "SampleAfterValue": "100003", 91 "UMask": "0x1" 92 }, 93 { 94 "BriefDescription": "Counts any other requests", 95 "Counter": "0,1,2,3", 96 "CounterHTOff": "0,1,2,3", 97 "EventCode": "0xB7, 0xBB", 98 "EventName": "OCR.OTHER.L3_HIT_E.SNOOP_NONE", 99 "MSRIndex": "0x1a6,0x1a7", 100 "MSRValue": "0x0080088000", 101 "Offcore": "1", 102 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 103 "SampleAfterValue": "100003", 104 "UMask": "0x1" 105 }, 106 { 107 "BriefDescription": "Counts demand data reads DEMAND_DATA_RD & L3_HIT_S & NO_SNOOP_NEEDED", 108 "Counter": "0,1,2,3", 109 "CounterHTOff": "0,1,2,3", 110 "EventCode": "0xB7, 0xBB", 111 "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDED", 112 "MSRIndex": "0x1a6,0x1a7", 113 "MSRValue": "0x0100100001", 114 "Offcore": "1", 115 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 116 "SampleAfterValue": "100003", 117 "UMask": "0x1" 118 }, 119 { 120 "BriefDescription": "ALL_RFO & L3_HIT_S & NO_SNOOP_NEEDED", 121 "Counter": "0,1,2,3", 122 "CounterHTOff": "0,1,2,3", 123 "EventCode": "0xB7, 0xBB", 124 "EventName": "OCR.ALL_RFO.L3_HIT_S.NO_SNOOP_NEEDED", 125 "MSRIndex": "0x1a6,0x1a7", 126 "MSRValue": "0x0100100122", 127 "Offcore": "1", 128 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 129 "SampleAfterValue": "100003", 130 "UMask": "0x1" 131 }, 132 { 133 "BriefDescription": "Counts any other requests OTHER & SUPPLIER_NONE & HITM_OTHER_CORE", 134 "Counter": "0,1,2,3", 135 "CounterHTOff": "0,1,2,3", 136 "EventCode": "0xB7, 0xBB", 137 "EventName": "OCR.OTHER.SUPPLIER_NONE.HITM_OTHER_CORE", 138 "MSRIndex": "0x1a6,0x1a7", 139 "MSRValue": "0x1000028000", 140 "Offcore": "1", 141 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 142 "SampleAfterValue": "100003", 143 "UMask": "0x1" 144 }, 145 { 146 "BriefDescription": "Counts all demand data writes (RFOs) DEMAND_RFO & L3_HIT_M & NO_SNOOP_NEEDED", 147 "Counter": "0,1,2,3", 148 "CounterHTOff": "0,1,2,3", 149 "EventCode": "0xB7, 0xBB", 150 "EventName": "OCR.DEMAND_RFO.L3_HIT_M.NO_SNOOP_NEEDED", 151 "MSRIndex": "0x1a6,0x1a7", 152 "MSRValue": "0x0100040002", 153 "Offcore": "1", 154 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 155 "SampleAfterValue": "100003", 156 "UMask": "0x1" 157 }, 158 { 159 "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs PF_L2_RFO & L3_HIT_F & HIT_OTHER_CORE_NO_FWD", 160 "Counter": "0,1,2,3", 161 "CounterHTOff": "0,1,2,3", 162 "EventCode": "0xB7, 0xBB", 163 "EventName": "OCR.PF_L2_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", 164 "MSRIndex": "0x1a6,0x1a7", 165 "MSRValue": "0x0400200020", 166 "Offcore": "1", 167 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 168 "SampleAfterValue": "100003", 169 "UMask": "0x1" 170 }, 171 { 172 "BriefDescription": "ALL_PF_RFO & L3_HIT_S & HIT_OTHER_CORE_FWD", 173 "Counter": "0,1,2,3", 174 "CounterHTOff": "0,1,2,3", 175 "EventCode": "0xB7, 0xBB", 176 "EventName": "OCR.ALL_PF_RFO.L3_HIT_S.HIT_OTHER_CORE_FWD", 177 "MSRIndex": "0x1a6,0x1a7", 178 "MSRValue": "0x0800100120", 179 "Offcore": "1", 180 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 181 "SampleAfterValue": "100003", 182 "UMask": "0x1" 183 }, 184 { 185 "BriefDescription": "Counts all demand code reads DEMAND_CODE_RD & L3_HIT_E & ANY_SNOOP", 186 "Counter": "0,1,2,3", 187 "CounterHTOff": "0,1,2,3", 188 "EventCode": "0xB7, 0xBB", 189 "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_E.ANY_SNOOP", 190 "MSRIndex": "0x1a6,0x1a7", 191 "MSRValue": "0x3F80080004", 192 "Offcore": "1", 193 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 194 "SampleAfterValue": "100003", 195 "UMask": "0x1" 196 }, 197 { 198 "BriefDescription": "ALL_PF_RFO & L3_HIT & ANY_SNOOP", 199 "Counter": "0,1,2,3", 200 "CounterHTOff": "0,1,2,3", 201 "EventCode": "0xB7, 0xBB", 202 "EventName": "OCR.ALL_PF_RFO.L3_HIT.ANY_SNOOP", 203 "MSRIndex": "0x1a6,0x1a7", 204 "MSRValue": "0x3F803C0120", 205 "Offcore": "1", 206 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 207 "SampleAfterValue": "100003", 208 "UMask": "0x1" 209 }, 210 { 211 "BriefDescription": "ALL_DATA_RD & L3_HIT_S & HITM_OTHER_CORE", 212 "Counter": "0,1,2,3", 213 "CounterHTOff": "0,1,2,3", 214 "EventCode": "0xB7, 0xBB", 215 "EventName": "OCR.ALL_DATA_RD.L3_HIT_S.HITM_OTHER_CORE", 216 "MSRIndex": "0x1a6,0x1a7", 217 "MSRValue": "0x1000100491", 218 "Offcore": "1", 219 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 220 "SampleAfterValue": "100003", 221 "UMask": "0x1" 222 }, 223 { 224 "BriefDescription": "ALL_PF_RFO & L3_HIT_S & ANY_SNOOP", 225 "Counter": "0,1,2,3", 226 "CounterHTOff": "0,1,2,3", 227 "EventCode": "0xB7, 0xBB", 228 "EventName": "OCR.ALL_PF_RFO.L3_HIT_S.ANY_SNOOP", 229 "MSRIndex": "0x1a6,0x1a7", 230 "MSRValue": "0x3F80100120", 231 "Offcore": "1", 232 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 233 "SampleAfterValue": "100003", 234 "UMask": "0x1" 235 }, 236 { 237 "BriefDescription": "Counts demand data reads DEMAND_DATA_RD & L3_HIT_S & HIT_OTHER_CORE_NO_FWD", 238 "Counter": "0,1,2,3", 239 "CounterHTOff": "0,1,2,3", 240 "EventCode": "0xB7, 0xBB", 241 "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", 242 "MSRIndex": "0x1a6,0x1a7", 243 "MSRValue": "0x0400100001", 244 "Offcore": "1", 245 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 246 "SampleAfterValue": "100003", 247 "UMask": "0x1" 248 }, 249 { 250 "BriefDescription": "Counts demand data reads DEMAND_DATA_RD & L3_HIT & SNOOP_MISS", 251 "Counter": "0,1,2,3", 252 "CounterHTOff": "0,1,2,3", 253 "EventCode": "0xB7, 0xBB", 254 "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_MISS", 255 "MSRIndex": "0x1a6,0x1a7", 256 "MSRValue": "0x02003C0001", 257 "Offcore": "1", 258 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 259 "SampleAfterValue": "100003", 260 "UMask": "0x1" 261 }, 262 { 263 "BriefDescription": "Counts any other requests OTHER & L3_HIT_M & HITM_OTHER_CORE", 264 "Counter": "0,1,2,3", 265 "CounterHTOff": "0,1,2,3", 266 "EventCode": "0xB7, 0xBB", 267 "EventName": "OCR.OTHER.L3_HIT_M.HITM_OTHER_CORE", 268 "MSRIndex": "0x1a6,0x1a7", 269 "MSRValue": "0x1000048000", 270 "Offcore": "1", 271 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 272 "SampleAfterValue": "100003", 273 "UMask": "0x1" 274 }, 275 { 276 "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs PF_L2_RFO & SUPPLIER_NONE & HIT_OTHER_CORE_NO_FWD", 277 "Counter": "0,1,2,3", 278 "CounterHTOff": "0,1,2,3", 279 "EventCode": "0xB7, 0xBB", 280 "EventName": "OCR.PF_L2_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", 281 "MSRIndex": "0x1a6,0x1a7", 282 "MSRValue": "0x0400020020", 283 "Offcore": "1", 284 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 285 "SampleAfterValue": "100003", 286 "UMask": "0x1" 287 }, 288 { 289 "BriefDescription": "Counts all demand data writes (RFOs)", 290 "Counter": "0,1,2,3", 291 "CounterHTOff": "0,1,2,3", 292 "EventCode": "0xB7, 0xBB", 293 "EventName": "OCR.DEMAND_RFO.L3_HIT_S.SNOOP_NONE", 294 "MSRIndex": "0x1a6,0x1a7", 295 "MSRValue": "0x0080100002", 296 "Offcore": "1", 297 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 298 "SampleAfterValue": "100003", 299 "UMask": "0x1" 300 }, 301 { 302 "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads PF_L3_DATA_RD & L3_HIT_E & HIT_OTHER_CORE_NO_FWD", 303 "Counter": "0,1,2,3", 304 "CounterHTOff": "0,1,2,3", 305 "EventCode": "0xB7, 0xBB", 306 "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", 307 "MSRIndex": "0x1a6,0x1a7", 308 "MSRValue": "0x0400080080", 309 "Offcore": "1", 310 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 311 "SampleAfterValue": "100003", 312 "UMask": "0x1" 313 }, 314 { 315 "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads PF_L3_DATA_RD & L3_HIT_F & HIT_OTHER_CORE_NO_FWD", 316 "Counter": "0,1,2,3", 317 "CounterHTOff": "0,1,2,3", 318 "EventCode": "0xB7, 0xBB", 319 "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", 320 "MSRIndex": "0x1a6,0x1a7", 321 "MSRValue": "0x0400200080", 322 "Offcore": "1", 323 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 324 "SampleAfterValue": "100003", 325 "UMask": "0x1" 326 }, 327 { 328 "BriefDescription": "ALL_READS & L3_HIT_M & NO_SNOOP_NEEDED", 329 "Counter": "0,1,2,3", 330 "CounterHTOff": "0,1,2,3", 331 "EventCode": "0xB7, 0xBB", 332 "EventName": "OCR.ALL_READS.L3_HIT_M.NO_SNOOP_NEEDED", 333 "MSRIndex": "0x1a6,0x1a7", 334 "MSRValue": "0x01000407F7", 335 "Offcore": "1", 336 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 337 "SampleAfterValue": "100003", 338 "UMask": "0x1" 339 }, 340 { 341 "BriefDescription": "Counts any other requests OTHER & L3_HIT_E & ANY_SNOOP", 342 "Counter": "0,1,2,3", 343 "CounterHTOff": "0,1,2,3", 344 "EventCode": "0xB7, 0xBB", 345 "EventName": "OCR.OTHER.L3_HIT_E.ANY_SNOOP", 346 "MSRIndex": "0x1a6,0x1a7", 347 "MSRValue": "0x3F80088000", 348 "Offcore": "1", 349 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 350 "SampleAfterValue": "100003", 351 "UMask": "0x1" 352 }, 353 { 354 "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs PF_L2_RFO & L3_HIT & HIT_OTHER_CORE_FWD", 355 "Counter": "0,1,2,3", 356 "CounterHTOff": "0,1,2,3", 357 "EventCode": "0xB7, 0xBB", 358 "EventName": "OCR.PF_L2_RFO.L3_HIT.HIT_OTHER_CORE_FWD", 359 "MSRIndex": "0x1a6,0x1a7", 360 "MSRValue": "0x08003C0020", 361 "Offcore": "1", 362 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 363 "SampleAfterValue": "100003", 364 "UMask": "0x1" 365 }, 366 { 367 "BriefDescription": "ALL_PF_RFO & L3_HIT_E & HITM_OTHER_CORE", 368 "Counter": "0,1,2,3", 369 "CounterHTOff": "0,1,2,3", 370 "EventCode": "0xB7, 0xBB", 371 "EventName": "OCR.ALL_PF_RFO.L3_HIT_E.HITM_OTHER_CORE", 372 "MSRIndex": "0x1a6,0x1a7", 373 "MSRValue": "0x1000080120", 374 "Offcore": "1", 375 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 376 "SampleAfterValue": "100003", 377 "UMask": "0x1" 378 }, 379 { 380 "BriefDescription": "ALL_PF_DATA_RD & L3_HIT & HITM_OTHER_CORE", 381 "Counter": "0,1,2,3", 382 "CounterHTOff": "0,1,2,3", 383 "EventCode": "0xB7, 0xBB", 384 "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT.HITM_OTHER_CORE", 385 "MSRIndex": "0x1a6,0x1a7", 386 "MSRValue": "0x10003C0490", 387 "Offcore": "1", 388 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 389 "SampleAfterValue": "100003", 390 "UMask": "0x1" 391 }, 392 { 393 "BriefDescription": "ALL_RFO & SUPPLIER_NONE & NO_SNOOP_NEEDED", 394 "Counter": "0,1,2,3", 395 "CounterHTOff": "0,1,2,3", 396 "EventCode": "0xB7, 0xBB", 397 "EventName": "OCR.ALL_RFO.SUPPLIER_NONE.NO_SNOOP_NEEDED", 398 "MSRIndex": "0x1a6,0x1a7", 399 "MSRValue": "0x0100020122", 400 "Offcore": "1", 401 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 402 "SampleAfterValue": "100003", 403 "UMask": "0x1" 404 }, 405 { 406 "BriefDescription": "ALL_DATA_RD & L3_HIT_F & HITM_OTHER_CORE", 407 "Counter": "0,1,2,3", 408 "CounterHTOff": "0,1,2,3", 409 "EventCode": "0xB7, 0xBB", 410 "EventName": "OCR.ALL_DATA_RD.L3_HIT_F.HITM_OTHER_CORE", 411 "MSRIndex": "0x1a6,0x1a7", 412 "MSRValue": "0x1000200491", 413 "Offcore": "1", 414 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 415 "SampleAfterValue": "100003", 416 "UMask": "0x1" 417 }, 418 { 419 "BriefDescription": "Counts any other requests OTHER & PMM_HIT_LOCAL_PMM & ANY_SNOOP", 420 "Counter": "0,1,2,3", 421 "CounterHTOff": "0,1,2,3", 422 "EventCode": "0xB7, 0xBB", 423 "EventName": "OCR.OTHER.PMM_HIT_LOCAL_PMM.ANY_SNOOP", 424 "MSRIndex": "0x1a6,0x1a7", 425 "MSRValue": "0x3F80408000", 426 "Offcore": "1", 427 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 428 "SampleAfterValue": "100003", 429 "UMask": "0x1" 430 }, 431 { 432 "BriefDescription": "ALL_PF_DATA_RD & SUPPLIER_NONE & HITM_OTHER_CORE", 433 "Counter": "0,1,2,3", 434 "CounterHTOff": "0,1,2,3", 435 "EventCode": "0xB7, 0xBB", 436 "EventName": "OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.HITM_OTHER_CORE", 437 "MSRIndex": "0x1a6,0x1a7", 438 "MSRValue": "0x1000020490", 439 "Offcore": "1", 440 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 441 "SampleAfterValue": "100003", 442 "UMask": "0x1" 443 }, 444 { 445 "BriefDescription": "ALL_READS & PMM_HIT_LOCAL_PMM & ANY_SNOOP", 446 "Counter": "0,1,2,3", 447 "CounterHTOff": "0,1,2,3", 448 "EventCode": "0xB7, 0xBB", 449 "EventName": "OCR.ALL_READS.PMM_HIT_LOCAL_PMM.ANY_SNOOP", 450 "MSRIndex": "0x1a6,0x1a7", 451 "MSRValue": "0x3F804007F7", 452 "Offcore": "1", 453 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 454 "SampleAfterValue": "100003", 455 "UMask": "0x1" 456 }, 457 { 458 "BriefDescription": "Counts number of cache lines that are dropped and not written back to L3 as they are deemed to be less likely to be reused shortly", 459 "Counter": "0,1,2,3", 460 "CounterHTOff": "0,1,2,3,4,5,6,7", 461 "EventCode": "0xFE", 462 "EventName": "IDI_MISC.WB_DOWNGRADE", 463 "PublicDescription": "Counts number of cache lines that are dropped and not written back to L3 as they are deemed to be less likely to be reused shortly.", 464 "SampleAfterValue": "100003", 465 "UMask": "0x4" 466 }, 467 { 468 "BriefDescription": "Counts all demand data writes (RFOs)", 469 "Counter": "0,1,2,3", 470 "CounterHTOff": "0,1,2,3", 471 "EventCode": "0xB7, 0xBB", 472 "EventName": "OCR.DEMAND_RFO.L3_HIT_E.SNOOP_NONE", 473 "MSRIndex": "0x1a6,0x1a7", 474 "MSRValue": "0x0080080002", 475 "Offcore": "1", 476 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 477 "SampleAfterValue": "100003", 478 "UMask": "0x1" 479 }, 480 { 481 "BriefDescription": "Counts all demand code reads DEMAND_CODE_RD & L3_HIT & HITM_OTHER_CORE", 482 "Counter": "0,1,2,3", 483 "CounterHTOff": "0,1,2,3", 484 "EventCode": "0xB7, 0xBB", 485 "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.HITM_OTHER_CORE", 486 "MSRIndex": "0x1a6,0x1a7", 487 "MSRValue": "0x10003C0004", 488 "Offcore": "1", 489 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 490 "SampleAfterValue": "100003", 491 "UMask": "0x1" 492 }, 493 { 494 "BriefDescription": "ALL_PF_RFO & L3_HIT_E & HIT_OTHER_CORE_NO_FWD", 495 "Counter": "0,1,2,3", 496 "CounterHTOff": "0,1,2,3", 497 "EventCode": "0xB7, 0xBB", 498 "EventName": "OCR.ALL_PF_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", 499 "MSRIndex": "0x1a6,0x1a7", 500 "MSRValue": "0x0400080120", 501 "Offcore": "1", 502 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 503 "SampleAfterValue": "100003", 504 "UMask": "0x1" 505 }, 506 { 507 "BriefDescription": "Counts demand data reads", 508 "Counter": "0,1,2,3", 509 "CounterHTOff": "0,1,2,3", 510 "EventCode": "0xB7, 0xBB", 511 "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_F.SNOOP_MISS", 512 "MSRIndex": "0x1a6,0x1a7", 513 "MSRValue": "0x0200200001", 514 "Offcore": "1", 515 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 516 "SampleAfterValue": "100003", 517 "UMask": "0x1" 518 }, 519 { 520 "BriefDescription": "Counts all demand code reads DEMAND_CODE_RD & L3_HIT_M & ANY_SNOOP", 521 "Counter": "0,1,2,3", 522 "CounterHTOff": "0,1,2,3", 523 "EventCode": "0xB7, 0xBB", 524 "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_M.ANY_SNOOP", 525 "MSRIndex": "0x1a6,0x1a7", 526 "MSRValue": "0x3F80040004", 527 "Offcore": "1", 528 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 529 "SampleAfterValue": "100003", 530 "UMask": "0x1" 531 }, 532 { 533 "BriefDescription": "Counts any other requests OTHER & L3_HIT_S & ANY_SNOOP", 534 "Counter": "0,1,2,3", 535 "CounterHTOff": "0,1,2,3", 536 "EventCode": "0xB7, 0xBB", 537 "EventName": "OCR.OTHER.L3_HIT_S.ANY_SNOOP", 538 "MSRIndex": "0x1a6,0x1a7", 539 "MSRValue": "0x3F80108000", 540 "Offcore": "1", 541 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 542 "SampleAfterValue": "100003", 543 "UMask": "0x1" 544 }, 545 { 546 "BriefDescription": "Counts any other requests OTHER & L3_HIT & HIT_OTHER_CORE_NO_FWD", 547 "Counter": "0,1,2,3", 548 "CounterHTOff": "0,1,2,3", 549 "EventCode": "0xB7, 0xBB", 550 "EventName": "OCR.OTHER.L3_HIT.HIT_OTHER_CORE_NO_FWD", 551 "MSRIndex": "0x1a6,0x1a7", 552 "MSRValue": "0x04003C8000", 553 "Offcore": "1", 554 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 555 "SampleAfterValue": "100003", 556 "UMask": "0x1" 557 }, 558 { 559 "BriefDescription": "ALL_DATA_RD & PMM_HIT_LOCAL_PMM & ANY_SNOOP", 560 "Counter": "0,1,2,3", 561 "CounterHTOff": "0,1,2,3", 562 "EventCode": "0xB7, 0xBB", 563 "EventName": "OCR.ALL_DATA_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOP", 564 "MSRIndex": "0x1a6,0x1a7", 565 "MSRValue": "0x3F80400491", 566 "Offcore": "1", 567 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 568 "SampleAfterValue": "100003", 569 "UMask": "0x1" 570 }, 571 { 572 "BriefDescription": "Counts prefetch (that bring data to L2) data reads", 573 "Counter": "0,1,2,3", 574 "CounterHTOff": "0,1,2,3", 575 "EventCode": "0xB7, 0xBB", 576 "EventName": "OCR.PF_L2_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD", 577 "MSRIndex": "0x1a6,0x1a7", 578 "MSRValue": "0x08007C0010", 579 "Offcore": "1", 580 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 581 "SampleAfterValue": "100003", 582 "UMask": "0x1" 583 }, 584 { 585 "BriefDescription": "Counts any other requests OTHER & L3_HIT_S & NO_SNOOP_NEEDED", 586 "Counter": "0,1,2,3", 587 "CounterHTOff": "0,1,2,3", 588 "EventCode": "0xB7, 0xBB", 589 "EventName": "OCR.OTHER.L3_HIT_S.NO_SNOOP_NEEDED", 590 "MSRIndex": "0x1a6,0x1a7", 591 "MSRValue": "0x0100108000", 592 "Offcore": "1", 593 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 594 "SampleAfterValue": "100003", 595 "UMask": "0x1" 596 }, 597 { 598 "BriefDescription": "ALL_READS & L3_HIT_F & SNOOP_MISS", 599 "Counter": "0,1,2,3", 600 "CounterHTOff": "0,1,2,3", 601 "EventCode": "0xB7, 0xBB", 602 "EventName": "OCR.ALL_READS.L3_HIT_F.SNOOP_MISS", 603 "MSRIndex": "0x1a6,0x1a7", 604 "MSRValue": "0x02002007F7", 605 "Offcore": "1", 606 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 607 "SampleAfterValue": "100003", 608 "UMask": "0x1" 609 }, 610 { 611 "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests", 612 "Counter": "0,1,2,3", 613 "CounterHTOff": "0,1,2,3", 614 "EventCode": "0xB7, 0xBB", 615 "EventName": "OCR.PF_L1D_AND_SW.L3_HIT.SNOOP_HIT_WITH_FWD", 616 "MSRIndex": "0x1a6,0x1a7", 617 "MSRValue": "0x08007C0400", 618 "Offcore": "1", 619 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 620 "SampleAfterValue": "100003", 621 "UMask": "0x1" 622 }, 623 { 624 "BriefDescription": "ALL_PF_DATA_RD & L3_HIT_M & HIT_OTHER_CORE_NO_FWD", 625 "Counter": "0,1,2,3", 626 "CounterHTOff": "0,1,2,3", 627 "EventCode": "0xB7, 0xBB", 628 "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", 629 "MSRIndex": "0x1a6,0x1a7", 630 "MSRValue": "0x0400040490", 631 "Offcore": "1", 632 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 633 "SampleAfterValue": "100003", 634 "UMask": "0x1" 635 }, 636 { 637 "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs PF_L2_RFO & L3_HIT_E & HITM_OTHER_CORE", 638 "Counter": "0,1,2,3", 639 "CounterHTOff": "0,1,2,3", 640 "EventCode": "0xB7, 0xBB", 641 "EventName": "OCR.PF_L2_RFO.L3_HIT_E.HITM_OTHER_CORE", 642 "MSRIndex": "0x1a6,0x1a7", 643 "MSRValue": "0x1000080020", 644 "Offcore": "1", 645 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 646 "SampleAfterValue": "100003", 647 "UMask": "0x1" 648 }, 649 { 650 "BriefDescription": "Counts all demand code reads", 651 "Counter": "0,1,2,3", 652 "CounterHTOff": "0,1,2,3", 653 "EventCode": "0xB7, 0xBB", 654 "EventName": "OCR.DEMAND_CODE_RD.SUPPLIER_NONE.SNOOP_NONE", 655 "MSRIndex": "0x1a6,0x1a7", 656 "MSRValue": "0x0080020004", 657 "Offcore": "1", 658 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 659 "SampleAfterValue": "100003", 660 "UMask": "0x1" 661 }, 662 { 663 "BriefDescription": "ALL_PF_RFO & L3_HIT_E & HIT_OTHER_CORE_FWD", 664 "Counter": "0,1,2,3", 665 "CounterHTOff": "0,1,2,3", 666 "EventCode": "0xB7, 0xBB", 667 "EventName": "OCR.ALL_PF_RFO.L3_HIT_E.HIT_OTHER_CORE_FWD", 668 "MSRIndex": "0x1a6,0x1a7", 669 "MSRValue": "0x0800080120", 670 "Offcore": "1", 671 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 672 "SampleAfterValue": "100003", 673 "UMask": "0x1" 674 }, 675 { 676 "BriefDescription": "ALL_RFO & L3_HIT_S & HIT_OTHER_CORE_NO_FWD", 677 "Counter": "0,1,2,3", 678 "CounterHTOff": "0,1,2,3", 679 "EventCode": "0xB7, 0xBB", 680 "EventName": "OCR.ALL_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", 681 "MSRIndex": "0x1a6,0x1a7", 682 "MSRValue": "0x0400100122", 683 "Offcore": "1", 684 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 685 "SampleAfterValue": "100003", 686 "UMask": "0x1" 687 }, 688 { 689 "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs", 690 "Counter": "0,1,2,3", 691 "CounterHTOff": "0,1,2,3", 692 "EventCode": "0xB7, 0xBB", 693 "EventName": "OCR.PF_L3_RFO.L3_HIT.SNOOP_HIT_WITH_FWD", 694 "MSRIndex": "0x1a6,0x1a7", 695 "MSRValue": "0x08007C0100", 696 "Offcore": "1", 697 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 698 "SampleAfterValue": "100003", 699 "UMask": "0x1" 700 }, 701 { 702 "BriefDescription": "ALL_PF_DATA_RD & L3_HIT_S & HIT_OTHER_CORE_FWD", 703 "Counter": "0,1,2,3", 704 "CounterHTOff": "0,1,2,3", 705 "EventCode": "0xB7, 0xBB", 706 "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWD", 707 "MSRIndex": "0x1a6,0x1a7", 708 "MSRValue": "0x0800100490", 709 "Offcore": "1", 710 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 711 "SampleAfterValue": "100003", 712 "UMask": "0x1" 713 }, 714 { 715 "BriefDescription": "Counts any other requests OTHER & L3_HIT & SNOOP_MISS", 716 "Counter": "0,1,2,3", 717 "CounterHTOff": "0,1,2,3", 718 "EventCode": "0xB7, 0xBB", 719 "EventName": "OCR.OTHER.L3_HIT.SNOOP_MISS", 720 "MSRIndex": "0x1a6,0x1a7", 721 "MSRValue": "0x02003C8000", 722 "Offcore": "1", 723 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 724 "SampleAfterValue": "100003", 725 "UMask": "0x1" 726 }, 727 { 728 "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests", 729 "Counter": "0,1,2,3", 730 "CounterHTOff": "0,1,2,3", 731 "EventCode": "0xB7, 0xBB", 732 "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_E.SNOOP_MISS", 733 "MSRIndex": "0x1a6,0x1a7", 734 "MSRValue": "0x0200080400", 735 "Offcore": "1", 736 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 737 "SampleAfterValue": "100003", 738 "UMask": "0x1" 739 }, 740 { 741 "BriefDescription": "Counts demand data reads DEMAND_DATA_RD & L3_HIT_S & HIT_OTHER_CORE_FWD", 742 "Counter": "0,1,2,3", 743 "CounterHTOff": "0,1,2,3", 744 "EventCode": "0xB7, 0xBB", 745 "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWD", 746 "MSRIndex": "0x1a6,0x1a7", 747 "MSRValue": "0x0800100001", 748 "Offcore": "1", 749 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 750 "SampleAfterValue": "100003", 751 "UMask": "0x1" 752 }, 753 { 754 "BriefDescription": "ALL_RFO & L3_HIT & SNOOP_MISS", 755 "Counter": "0,1,2,3", 756 "CounterHTOff": "0,1,2,3", 757 "EventCode": "0xB7, 0xBB", 758 "EventName": "OCR.ALL_RFO.L3_HIT.SNOOP_MISS", 759 "MSRIndex": "0x1a6,0x1a7", 760 "MSRValue": "0x02003C0122", 761 "Offcore": "1", 762 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 763 "SampleAfterValue": "100003", 764 "UMask": "0x1" 765 }, 766 { 767 "BriefDescription": "Counts all demand data writes (RFOs) DEMAND_RFO & L3_HIT_M & HITM_OTHER_CORE", 768 "Counter": "0,1,2,3", 769 "CounterHTOff": "0,1,2,3", 770 "EventCode": "0xB7, 0xBB", 771 "EventName": "OCR.DEMAND_RFO.L3_HIT_M.HITM_OTHER_CORE", 772 "MSRIndex": "0x1a6,0x1a7", 773 "MSRValue": "0x1000040002", 774 "Offcore": "1", 775 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 776 "SampleAfterValue": "100003", 777 "UMask": "0x1" 778 }, 779 { 780 "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads PF_L3_DATA_RD & L3_HIT_S & ANY_SNOOP", 781 "Counter": "0,1,2,3", 782 "CounterHTOff": "0,1,2,3", 783 "EventCode": "0xB7, 0xBB", 784 "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_S.ANY_SNOOP", 785 "MSRIndex": "0x1a6,0x1a7", 786 "MSRValue": "0x3F80100080", 787 "Offcore": "1", 788 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 789 "SampleAfterValue": "100003", 790 "UMask": "0x1" 791 }, 792 { 793 "BriefDescription": "ALL_RFO & L3_HIT_F & HITM_OTHER_CORE", 794 "Counter": "0,1,2,3", 795 "CounterHTOff": "0,1,2,3", 796 "EventCode": "0xB7, 0xBB", 797 "EventName": "OCR.ALL_RFO.L3_HIT_F.HITM_OTHER_CORE", 798 "MSRIndex": "0x1a6,0x1a7", 799 "MSRValue": "0x1000200122", 800 "Offcore": "1", 801 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 802 "SampleAfterValue": "100003", 803 "UMask": "0x1" 804 }, 805 { 806 "BriefDescription": "Counts any other requests OTHER & L3_HIT_E & HIT_OTHER_CORE_FWD", 807 "Counter": "0,1,2,3", 808 "CounterHTOff": "0,1,2,3", 809 "EventCode": "0xB7, 0xBB", 810 "EventName": "OCR.OTHER.L3_HIT_E.HIT_OTHER_CORE_FWD", 811 "MSRIndex": "0x1a6,0x1a7", 812 "MSRValue": "0x0800088000", 813 "Offcore": "1", 814 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 815 "SampleAfterValue": "100003", 816 "UMask": "0x1" 817 }, 818 { 819 "BriefDescription": "ALL_DATA_RD & SUPPLIER_NONE & SNOOP_MISS", 820 "Counter": "0,1,2,3", 821 "CounterHTOff": "0,1,2,3", 822 "EventCode": "0xB7, 0xBB", 823 "EventName": "OCR.ALL_DATA_RD.SUPPLIER_NONE.SNOOP_MISS", 824 "MSRIndex": "0x1a6,0x1a7", 825 "MSRValue": "0x0200020491", 826 "Offcore": "1", 827 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 828 "SampleAfterValue": "100003", 829 "UMask": "0x1" 830 }, 831 { 832 "BriefDescription": "Counts prefetch (that bring data to L2) data reads PF_L2_DATA_RD & L3_HIT_E & HIT_OTHER_CORE_NO_FWD", 833 "Counter": "0,1,2,3", 834 "CounterHTOff": "0,1,2,3", 835 "EventCode": "0xB7, 0xBB", 836 "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", 837 "MSRIndex": "0x1a6,0x1a7", 838 "MSRValue": "0x0400080010", 839 "Offcore": "1", 840 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 841 "SampleAfterValue": "100003", 842 "UMask": "0x1" 843 }, 844 { 845 "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests PF_L1D_AND_SW & L3_HIT & SNOOP_NONE", 846 "Counter": "0,1,2,3", 847 "CounterHTOff": "0,1,2,3", 848 "EventCode": "0xB7, 0xBB", 849 "EventName": "OCR.PF_L1D_AND_SW.L3_HIT.SNOOP_NONE", 850 "MSRIndex": "0x1a6,0x1a7", 851 "MSRValue": "0x00803C0400", 852 "Offcore": "1", 853 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 854 "SampleAfterValue": "100003", 855 "UMask": "0x1" 856 }, 857 { 858 "BriefDescription": "Counts all demand data writes (RFOs) DEMAND_RFO & L3_HIT_E & ANY_SNOOP", 859 "Counter": "0,1,2,3", 860 "CounterHTOff": "0,1,2,3", 861 "EventCode": "0xB7, 0xBB", 862 "EventName": "OCR.DEMAND_RFO.L3_HIT_E.ANY_SNOOP", 863 "MSRIndex": "0x1a6,0x1a7", 864 "MSRValue": "0x3F80080002", 865 "Offcore": "1", 866 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 867 "SampleAfterValue": "100003", 868 "UMask": "0x1" 869 }, 870 { 871 "BriefDescription": "ALL_RFO & L3_HIT_M & SNOOP_MISS", 872 "Counter": "0,1,2,3", 873 "CounterHTOff": "0,1,2,3", 874 "EventCode": "0xB7, 0xBB", 875 "EventName": "OCR.ALL_RFO.L3_HIT_M.SNOOP_MISS", 876 "MSRIndex": "0x1a6,0x1a7", 877 "MSRValue": "0x0200040122", 878 "Offcore": "1", 879 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 880 "SampleAfterValue": "100003", 881 "UMask": "0x1" 882 }, 883 { 884 "BriefDescription": "ALL_RFO & L3_HIT & HITM_OTHER_CORE", 885 "Counter": "0,1,2,3", 886 "CounterHTOff": "0,1,2,3", 887 "EventCode": "0xB7, 0xBB", 888 "EventName": "OCR.ALL_RFO.L3_HIT.HITM_OTHER_CORE", 889 "MSRIndex": "0x1a6,0x1a7", 890 "MSRValue": "0x10003C0122", 891 "Offcore": "1", 892 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 893 "SampleAfterValue": "100003", 894 "UMask": "0x1" 895 }, 896 { 897 "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads PF_L3_DATA_RD & L3_HIT & SNOOP_NONE", 898 "Counter": "0,1,2,3", 899 "CounterHTOff": "0,1,2,3", 900 "EventCode": "0xB7, 0xBB", 901 "EventName": "OCR.PF_L3_DATA_RD.L3_HIT.SNOOP_NONE", 902 "MSRIndex": "0x1a6,0x1a7", 903 "MSRValue": "0x00803C0080", 904 "Offcore": "1", 905 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 906 "SampleAfterValue": "100003", 907 "UMask": "0x1" 908 }, 909 { 910 "BriefDescription": "Counts demand data reads", 911 "Counter": "0,1,2,3", 912 "CounterHTOff": "0,1,2,3", 913 "EventCode": "0xB7, 0xBB", 914 "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_E.SNOOP_NONE", 915 "MSRIndex": "0x1a6,0x1a7", 916 "MSRValue": "0x0080080001", 917 "Offcore": "1", 918 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 919 "SampleAfterValue": "100003", 920 "UMask": "0x1" 921 }, 922 { 923 "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests", 924 "Counter": "0,1,2,3", 925 "CounterHTOff": "0,1,2,3", 926 "EventCode": "0xB7, 0xBB", 927 "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_M.SNOOP_MISS", 928 "MSRIndex": "0x1a6,0x1a7", 929 "MSRValue": "0x0200040400", 930 "Offcore": "1", 931 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 932 "SampleAfterValue": "100003", 933 "UMask": "0x1" 934 }, 935 { 936 "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs have any response type.", 937 "Counter": "0,1,2,3", 938 "CounterHTOff": "0,1,2,3", 939 "EventCode": "0xB7, 0xBB", 940 "EventName": "OCR.PF_L2_RFO.ANY_RESPONSE", 941 "MSRIndex": "0x1a6,0x1a7", 942 "MSRValue": "0x0000010020", 943 "Offcore": "1", 944 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 945 "SampleAfterValue": "100003", 946 "UMask": "0x1" 947 }, 948 { 949 "BriefDescription": "Counts all demand data writes (RFOs) DEMAND_RFO & SUPPLIER_NONE & HIT_OTHER_CORE_FWD", 950 "Counter": "0,1,2,3", 951 "CounterHTOff": "0,1,2,3", 952 "EventCode": "0xB7, 0xBB", 953 "EventName": "OCR.DEMAND_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", 954 "MSRIndex": "0x1a6,0x1a7", 955 "MSRValue": "0x0800020002", 956 "Offcore": "1", 957 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 958 "SampleAfterValue": "100003", 959 "UMask": "0x1" 960 }, 961 { 962 "BriefDescription": "Counts all demand code reads", 963 "Counter": "0,1,2,3", 964 "CounterHTOff": "0,1,2,3", 965 "EventCode": "0xB7, 0xBB", 966 "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_F.SNOOP_MISS", 967 "MSRIndex": "0x1a6,0x1a7", 968 "MSRValue": "0x0200200004", 969 "Offcore": "1", 970 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 971 "SampleAfterValue": "100003", 972 "UMask": "0x1" 973 }, 974 { 975 "BriefDescription": "Counts any other requests", 976 "Counter": "0,1,2,3", 977 "CounterHTOff": "0,1,2,3", 978 "EventCode": "0xB7, 0xBB", 979 "EventName": "OCR.OTHER.SUPPLIER_NONE.SNOOP_MISS", 980 "MSRIndex": "0x1a6,0x1a7", 981 "MSRValue": "0x0200028000", 982 "Offcore": "1", 983 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 984 "SampleAfterValue": "100003", 985 "UMask": "0x1" 986 }, 987 { 988 "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs PF_L3_RFO & L3_HIT_E & NO_SNOOP_NEEDED", 989 "Counter": "0,1,2,3", 990 "CounterHTOff": "0,1,2,3", 991 "EventCode": "0xB7, 0xBB", 992 "EventName": "OCR.PF_L3_RFO.L3_HIT_E.NO_SNOOP_NEEDED", 993 "MSRIndex": "0x1a6,0x1a7", 994 "MSRValue": "0x0100080100", 995 "Offcore": "1", 996 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 997 "SampleAfterValue": "100003", 998 "UMask": "0x1" 999 }, 1000 { 1001 "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads PF_L3_DATA_RD & PMM_HIT_LOCAL_PMM & SNOOP_NOT_NEEDED", 1002 "Counter": "0,1,2,3", 1003 "CounterHTOff": "0,1,2,3", 1004 "EventCode": "0xB7, 0xBB", 1005 "EventName": "OCR.PF_L3_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", 1006 "MSRIndex": "0x1a6,0x1a7", 1007 "MSRValue": "0x0100400080", 1008 "Offcore": "1", 1009 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1010 "SampleAfterValue": "100003", 1011 "UMask": "0x1" 1012 }, 1013 { 1014 "BriefDescription": "ALL_READS & L3_HIT_E & HIT_OTHER_CORE_FWD", 1015 "Counter": "0,1,2,3", 1016 "CounterHTOff": "0,1,2,3", 1017 "EventCode": "0xB7, 0xBB", 1018 "EventName": "OCR.ALL_READS.L3_HIT_E.HIT_OTHER_CORE_FWD", 1019 "MSRIndex": "0x1a6,0x1a7", 1020 "MSRValue": "0x08000807F7", 1021 "Offcore": "1", 1022 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1023 "SampleAfterValue": "100003", 1024 "UMask": "0x1" 1025 }, 1026 { 1027 "BriefDescription": "ALL_RFO & L3_HIT_F & HIT_OTHER_CORE_NO_FWD", 1028 "Counter": "0,1,2,3", 1029 "CounterHTOff": "0,1,2,3", 1030 "EventCode": "0xB7, 0xBB", 1031 "EventName": "OCR.ALL_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", 1032 "MSRIndex": "0x1a6,0x1a7", 1033 "MSRValue": "0x0400200122", 1034 "Offcore": "1", 1035 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1036 "SampleAfterValue": "100003", 1037 "UMask": "0x1" 1038 }, 1039 { 1040 "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs", 1041 "Counter": "0,1,2,3", 1042 "CounterHTOff": "0,1,2,3", 1043 "EventCode": "0xB7, 0xBB", 1044 "EventName": "OCR.PF_L2_RFO.L3_HIT_M.SNOOP_NONE", 1045 "MSRIndex": "0x1a6,0x1a7", 1046 "MSRValue": "0x0080040020", 1047 "Offcore": "1", 1048 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1049 "SampleAfterValue": "100003", 1050 "UMask": "0x1" 1051 }, 1052 { 1053 "BriefDescription": "Counts demand data reads DEMAND_DATA_RD & L3_HIT_F & ANY_SNOOP", 1054 "Counter": "0,1,2,3", 1055 "CounterHTOff": "0,1,2,3", 1056 "EventCode": "0xB7, 0xBB", 1057 "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_F.ANY_SNOOP", 1058 "MSRIndex": "0x1a6,0x1a7", 1059 "MSRValue": "0x3F80200001", 1060 "Offcore": "1", 1061 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1062 "SampleAfterValue": "100003", 1063 "UMask": "0x1" 1064 }, 1065 { 1066 "BriefDescription": "Counts demand data reads DEMAND_DATA_RD & L3_HIT_M & HIT_OTHER_CORE_FWD", 1067 "Counter": "0,1,2,3", 1068 "CounterHTOff": "0,1,2,3", 1069 "EventCode": "0xB7, 0xBB", 1070 "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWD", 1071 "MSRIndex": "0x1a6,0x1a7", 1072 "MSRValue": "0x0800040001", 1073 "Offcore": "1", 1074 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1075 "SampleAfterValue": "100003", 1076 "UMask": "0x1" 1077 }, 1078 { 1079 "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests PF_L1D_AND_SW & PMM_HIT_LOCAL_PMM & SNOOP_NONE", 1080 "Counter": "0,1,2,3", 1081 "CounterHTOff": "0,1,2,3", 1082 "EventCode": "0xB7, 0xBB", 1083 "EventName": "OCR.PF_L1D_AND_SW.PMM_HIT_LOCAL_PMM.SNOOP_NONE", 1084 "MSRIndex": "0x1a6,0x1a7", 1085 "MSRValue": "0x0080400400", 1086 "Offcore": "1", 1087 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1088 "SampleAfterValue": "100003", 1089 "UMask": "0x1" 1090 }, 1091 { 1092 "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs PF_L3_RFO & L3_HIT & HITM_OTHER_CORE", 1093 "Counter": "0,1,2,3", 1094 "CounterHTOff": "0,1,2,3", 1095 "EventCode": "0xB7, 0xBB", 1096 "EventName": "OCR.PF_L3_RFO.L3_HIT.HITM_OTHER_CORE", 1097 "MSRIndex": "0x1a6,0x1a7", 1098 "MSRValue": "0x10003C0100", 1099 "Offcore": "1", 1100 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1101 "SampleAfterValue": "100003", 1102 "UMask": "0x1" 1103 }, 1104 { 1105 "BriefDescription": "Counts prefetch (that bring data to L2) data reads PF_L2_DATA_RD & L3_HIT_M & NO_SNOOP_NEEDED", 1106 "Counter": "0,1,2,3", 1107 "CounterHTOff": "0,1,2,3", 1108 "EventCode": "0xB7, 0xBB", 1109 "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDED", 1110 "MSRIndex": "0x1a6,0x1a7", 1111 "MSRValue": "0x0100040010", 1112 "Offcore": "1", 1113 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1114 "SampleAfterValue": "100003", 1115 "UMask": "0x1" 1116 }, 1117 { 1118 "BriefDescription": "Counts any other requests OTHER & L3_HIT_M & HIT_OTHER_CORE_FWD", 1119 "Counter": "0,1,2,3", 1120 "CounterHTOff": "0,1,2,3", 1121 "EventCode": "0xB7, 0xBB", 1122 "EventName": "OCR.OTHER.L3_HIT_M.HIT_OTHER_CORE_FWD", 1123 "MSRIndex": "0x1a6,0x1a7", 1124 "MSRValue": "0x0800048000", 1125 "Offcore": "1", 1126 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1127 "SampleAfterValue": "100003", 1128 "UMask": "0x1" 1129 }, 1130 { 1131 "BriefDescription": "Counts demand data reads DEMAND_DATA_RD & L3_HIT_E & HITM_OTHER_CORE", 1132 "Counter": "0,1,2,3", 1133 "CounterHTOff": "0,1,2,3", 1134 "EventCode": "0xB7, 0xBB", 1135 "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_E.HITM_OTHER_CORE", 1136 "MSRIndex": "0x1a6,0x1a7", 1137 "MSRValue": "0x1000080001", 1138 "Offcore": "1", 1139 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1140 "SampleAfterValue": "100003", 1141 "UMask": "0x1" 1142 }, 1143 { 1144 "BriefDescription": "ALL_DATA_RD & L3_HIT_E & NO_SNOOP_NEEDED", 1145 "Counter": "0,1,2,3", 1146 "CounterHTOff": "0,1,2,3", 1147 "EventCode": "0xB7, 0xBB", 1148 "EventName": "OCR.ALL_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDED", 1149 "MSRIndex": "0x1a6,0x1a7", 1150 "MSRValue": "0x0100080491", 1151 "Offcore": "1", 1152 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1153 "SampleAfterValue": "100003", 1154 "UMask": "0x1" 1155 }, 1156 { 1157 "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs", 1158 "Counter": "0,1,2,3", 1159 "CounterHTOff": "0,1,2,3", 1160 "EventCode": "0xB7, 0xBB", 1161 "EventName": "OCR.PF_L2_RFO.L3_HIT_S.SNOOP_NONE", 1162 "MSRIndex": "0x1a6,0x1a7", 1163 "MSRValue": "0x0080100020", 1164 "Offcore": "1", 1165 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1166 "SampleAfterValue": "100003", 1167 "UMask": "0x1" 1168 }, 1169 { 1170 "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs PF_L2_RFO & L3_HIT_E & NO_SNOOP_NEEDED", 1171 "Counter": "0,1,2,3", 1172 "CounterHTOff": "0,1,2,3", 1173 "EventCode": "0xB7, 0xBB", 1174 "EventName": "OCR.PF_L2_RFO.L3_HIT_E.NO_SNOOP_NEEDED", 1175 "MSRIndex": "0x1a6,0x1a7", 1176 "MSRValue": "0x0100080020", 1177 "Offcore": "1", 1178 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1179 "SampleAfterValue": "100003", 1180 "UMask": "0x1" 1181 }, 1182 { 1183 "BriefDescription": "Counts all demand data writes (RFOs) DEMAND_RFO & L3_HIT & ANY_SNOOP", 1184 "Counter": "0,1,2,3", 1185 "CounterHTOff": "0,1,2,3", 1186 "EventCode": "0xB7, 0xBB", 1187 "EventName": "OCR.DEMAND_RFO.L3_HIT.ANY_SNOOP", 1188 "MSRIndex": "0x1a6,0x1a7", 1189 "MSRValue": "0x3F803C0002", 1190 "Offcore": "1", 1191 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1192 "SampleAfterValue": "100003", 1193 "UMask": "0x1" 1194 }, 1195 { 1196 "BriefDescription": "ALL_DATA_RD & SUPPLIER_NONE & HIT_OTHER_CORE_NO_FWD", 1197 "Counter": "0,1,2,3", 1198 "CounterHTOff": "0,1,2,3", 1199 "EventCode": "0xB7, 0xBB", 1200 "EventName": "OCR.ALL_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", 1201 "MSRIndex": "0x1a6,0x1a7", 1202 "MSRValue": "0x0400020491", 1203 "Offcore": "1", 1204 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1205 "SampleAfterValue": "100003", 1206 "UMask": "0x1" 1207 }, 1208 { 1209 "BriefDescription": "Counts prefetch (that bring data to L2) data reads PF_L2_DATA_RD & SUPPLIER_NONE & NO_SNOOP_NEEDED", 1210 "Counter": "0,1,2,3", 1211 "CounterHTOff": "0,1,2,3", 1212 "EventCode": "0xB7, 0xBB", 1213 "EventName": "OCR.PF_L2_DATA_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED", 1214 "MSRIndex": "0x1a6,0x1a7", 1215 "MSRValue": "0x0100020010", 1216 "Offcore": "1", 1217 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1218 "SampleAfterValue": "100003", 1219 "UMask": "0x1" 1220 }, 1221 { 1222 "BriefDescription": "ALL_PF_DATA_RD & SUPPLIER_NONE & HIT_OTHER_CORE_FWD", 1223 "Counter": "0,1,2,3", 1224 "CounterHTOff": "0,1,2,3", 1225 "EventCode": "0xB7, 0xBB", 1226 "EventName": "OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", 1227 "MSRIndex": "0x1a6,0x1a7", 1228 "MSRValue": "0x0800020490", 1229 "Offcore": "1", 1230 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1231 "SampleAfterValue": "100003", 1232 "UMask": "0x1" 1233 }, 1234 { 1235 "BriefDescription": "ALL_RFO & L3_HIT & NO_SNOOP_NEEDED", 1236 "Counter": "0,1,2,3", 1237 "CounterHTOff": "0,1,2,3", 1238 "EventCode": "0xB7, 0xBB", 1239 "EventName": "OCR.ALL_RFO.L3_HIT.NO_SNOOP_NEEDED", 1240 "MSRIndex": "0x1a6,0x1a7", 1241 "MSRValue": "0x01003C0122", 1242 "Offcore": "1", 1243 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1244 "SampleAfterValue": "100003", 1245 "UMask": "0x1" 1246 }, 1247 { 1248 "BriefDescription": "Counts demand data reads DEMAND_DATA_RD & SUPPLIER_NONE & NO_SNOOP_NEEDED", 1249 "Counter": "0,1,2,3", 1250 "CounterHTOff": "0,1,2,3", 1251 "EventCode": "0xB7, 0xBB", 1252 "EventName": "OCR.DEMAND_DATA_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED", 1253 "MSRIndex": "0x1a6,0x1a7", 1254 "MSRValue": "0x0100020001", 1255 "Offcore": "1", 1256 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1257 "SampleAfterValue": "100003", 1258 "UMask": "0x1" 1259 }, 1260 { 1261 "BriefDescription": "Counts demand data reads DEMAND_DATA_RD & L3_HIT & SNOOP_NONE", 1262 "Counter": "0,1,2,3", 1263 "CounterHTOff": "0,1,2,3", 1264 "EventCode": "0xB7, 0xBB", 1265 "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_NONE", 1266 "MSRIndex": "0x1a6,0x1a7", 1267 "MSRValue": "0x00803C0001", 1268 "Offcore": "1", 1269 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1270 "SampleAfterValue": "100003", 1271 "UMask": "0x1" 1272 }, 1273 { 1274 "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs", 1275 "Counter": "0,1,2,3", 1276 "CounterHTOff": "0,1,2,3", 1277 "EventCode": "0xB7, 0xBB", 1278 "EventName": "OCR.PF_L3_RFO.SUPPLIER_NONE.SNOOP_MISS", 1279 "MSRIndex": "0x1a6,0x1a7", 1280 "MSRValue": "0x0200020100", 1281 "Offcore": "1", 1282 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1283 "SampleAfterValue": "100003", 1284 "UMask": "0x1" 1285 }, 1286 { 1287 "BriefDescription": "Counts prefetch (that bring data to L2) data reads", 1288 "Counter": "0,1,2,3", 1289 "CounterHTOff": "0,1,2,3", 1290 "EventCode": "0xB7, 0xBB", 1291 "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_F.SNOOP_MISS", 1292 "MSRIndex": "0x1a6,0x1a7", 1293 "MSRValue": "0x0200200010", 1294 "Offcore": "1", 1295 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1296 "SampleAfterValue": "100003", 1297 "UMask": "0x1" 1298 }, 1299 { 1300 "BriefDescription": "ALL_PF_DATA_RD & L3_HIT_S & HIT_OTHER_CORE_NO_FWD", 1301 "Counter": "0,1,2,3", 1302 "CounterHTOff": "0,1,2,3", 1303 "EventCode": "0xB7, 0xBB", 1304 "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", 1305 "MSRIndex": "0x1a6,0x1a7", 1306 "MSRValue": "0x0400100490", 1307 "Offcore": "1", 1308 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1309 "SampleAfterValue": "100003", 1310 "UMask": "0x1" 1311 }, 1312 { 1313 "BriefDescription": "ALL_PF_DATA_RD & ANY_RESPONSE have any response type.", 1314 "Counter": "0,1,2,3", 1315 "CounterHTOff": "0,1,2,3", 1316 "EventCode": "0xB7, 0xBB", 1317 "EventName": "OCR.ALL_PF_DATA_RD.ANY_RESPONSE", 1318 "MSRIndex": "0x1a6,0x1a7", 1319 "MSRValue": "0x0000010490", 1320 "Offcore": "1", 1321 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1322 "SampleAfterValue": "100003", 1323 "UMask": "0x1" 1324 }, 1325 { 1326 "BriefDescription": "Counts any other requests OTHER & L3_HIT_S & HIT_OTHER_CORE_FWD", 1327 "Counter": "0,1,2,3", 1328 "CounterHTOff": "0,1,2,3", 1329 "EventCode": "0xB7, 0xBB", 1330 "EventName": "OCR.OTHER.L3_HIT_S.HIT_OTHER_CORE_FWD", 1331 "MSRIndex": "0x1a6,0x1a7", 1332 "MSRValue": "0x0800108000", 1333 "Offcore": "1", 1334 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1335 "SampleAfterValue": "100003", 1336 "UMask": "0x1" 1337 }, 1338 { 1339 "BriefDescription": "ALL_PF_RFO & L3_HIT & SNOOP_MISS", 1340 "Counter": "0,1,2,3", 1341 "CounterHTOff": "0,1,2,3", 1342 "EventCode": "0xB7, 0xBB", 1343 "EventName": "OCR.ALL_PF_RFO.L3_HIT.SNOOP_MISS", 1344 "MSRIndex": "0x1a6,0x1a7", 1345 "MSRValue": "0x02003C0120", 1346 "Offcore": "1", 1347 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1348 "SampleAfterValue": "100003", 1349 "UMask": "0x1" 1350 }, 1351 { 1352 "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests PF_L1D_AND_SW & L3_HIT_M & HIT_OTHER_CORE_NO_FWD", 1353 "Counter": "0,1,2,3", 1354 "CounterHTOff": "0,1,2,3", 1355 "EventCode": "0xB7, 0xBB", 1356 "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", 1357 "MSRIndex": "0x1a6,0x1a7", 1358 "MSRValue": "0x0400040400", 1359 "Offcore": "1", 1360 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1361 "SampleAfterValue": "100003", 1362 "UMask": "0x1" 1363 }, 1364 { 1365 "BriefDescription": "Counts prefetch (that bring data to L2) data reads PF_L2_DATA_RD & SUPPLIER_NONE & HIT_OTHER_CORE_NO_FWD", 1366 "Counter": "0,1,2,3", 1367 "CounterHTOff": "0,1,2,3", 1368 "EventCode": "0xB7, 0xBB", 1369 "EventName": "OCR.PF_L2_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", 1370 "MSRIndex": "0x1a6,0x1a7", 1371 "MSRValue": "0x0400020010", 1372 "Offcore": "1", 1373 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1374 "SampleAfterValue": "100003", 1375 "UMask": "0x1" 1376 }, 1377 { 1378 "BriefDescription": "Counts any other requests", 1379 "Counter": "0,1,2,3", 1380 "CounterHTOff": "0,1,2,3", 1381 "EventCode": "0xB7, 0xBB", 1382 "EventName": "OCR.OTHER.L3_HIT_M.SNOOP_MISS", 1383 "MSRIndex": "0x1a6,0x1a7", 1384 "MSRValue": "0x0200048000", 1385 "Offcore": "1", 1386 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1387 "SampleAfterValue": "100003", 1388 "UMask": "0x1" 1389 }, 1390 { 1391 "BriefDescription": "ALL_DATA_RD & L3_HIT_S & SNOOP_MISS", 1392 "Counter": "0,1,2,3", 1393 "CounterHTOff": "0,1,2,3", 1394 "EventCode": "0xB7, 0xBB", 1395 "EventName": "OCR.ALL_DATA_RD.L3_HIT_S.SNOOP_MISS", 1396 "MSRIndex": "0x1a6,0x1a7", 1397 "MSRValue": "0x0200100491", 1398 "Offcore": "1", 1399 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1400 "SampleAfterValue": "100003", 1401 "UMask": "0x1" 1402 }, 1403 { 1404 "BriefDescription": "ALL_RFO & L3_HIT_M & ANY_SNOOP", 1405 "Counter": "0,1,2,3", 1406 "CounterHTOff": "0,1,2,3", 1407 "EventCode": "0xB7, 0xBB", 1408 "EventName": "OCR.ALL_RFO.L3_HIT_M.ANY_SNOOP", 1409 "MSRIndex": "0x1a6,0x1a7", 1410 "MSRValue": "0x3F80040122", 1411 "Offcore": "1", 1412 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1413 "SampleAfterValue": "100003", 1414 "UMask": "0x1" 1415 }, 1416 { 1417 "BriefDescription": "Counts all demand data writes (RFOs) DEMAND_RFO & L3_HIT_F & HIT_OTHER_CORE_FWD", 1418 "Counter": "0,1,2,3", 1419 "CounterHTOff": "0,1,2,3", 1420 "EventCode": "0xB7, 0xBB", 1421 "EventName": "OCR.DEMAND_RFO.L3_HIT_F.HIT_OTHER_CORE_FWD", 1422 "MSRIndex": "0x1a6,0x1a7", 1423 "MSRValue": "0x0800200002", 1424 "Offcore": "1", 1425 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1426 "SampleAfterValue": "100003", 1427 "UMask": "0x1" 1428 }, 1429 { 1430 "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs PF_L3_RFO & SUPPLIER_NONE & HITM_OTHER_CORE", 1431 "Counter": "0,1,2,3", 1432 "CounterHTOff": "0,1,2,3", 1433 "EventCode": "0xB7, 0xBB", 1434 "EventName": "OCR.PF_L3_RFO.SUPPLIER_NONE.HITM_OTHER_CORE", 1435 "MSRIndex": "0x1a6,0x1a7", 1436 "MSRValue": "0x1000020100", 1437 "Offcore": "1", 1438 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1439 "SampleAfterValue": "100003", 1440 "UMask": "0x1" 1441 }, 1442 { 1443 "BriefDescription": "ALL_READS & L3_HIT_E & ANY_SNOOP", 1444 "Counter": "0,1,2,3", 1445 "CounterHTOff": "0,1,2,3", 1446 "EventCode": "0xB7, 0xBB", 1447 "EventName": "OCR.ALL_READS.L3_HIT_E.ANY_SNOOP", 1448 "MSRIndex": "0x1a6,0x1a7", 1449 "MSRValue": "0x3F800807F7", 1450 "Offcore": "1", 1451 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1452 "SampleAfterValue": "100003", 1453 "UMask": "0x1" 1454 }, 1455 { 1456 "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests PF_L1D_AND_SW & L3_HIT_E & NO_SNOOP_NEEDED", 1457 "Counter": "0,1,2,3", 1458 "CounterHTOff": "0,1,2,3", 1459 "EventCode": "0xB7, 0xBB", 1460 "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_E.NO_SNOOP_NEEDED", 1461 "MSRIndex": "0x1a6,0x1a7", 1462 "MSRValue": "0x0100080400", 1463 "Offcore": "1", 1464 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1465 "SampleAfterValue": "100003", 1466 "UMask": "0x1" 1467 }, 1468 { 1469 "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs PF_L3_RFO & SUPPLIER_NONE & ANY_SNOOP", 1470 "Counter": "0,1,2,3", 1471 "CounterHTOff": "0,1,2,3", 1472 "EventCode": "0xB7, 0xBB", 1473 "EventName": "OCR.PF_L3_RFO.SUPPLIER_NONE.ANY_SNOOP", 1474 "MSRIndex": "0x1a6,0x1a7", 1475 "MSRValue": "0x3F80020100", 1476 "Offcore": "1", 1477 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1478 "SampleAfterValue": "100003", 1479 "UMask": "0x1" 1480 }, 1481 { 1482 "BriefDescription": "ALL_PF_DATA_RD & L3_HIT_F & HITM_OTHER_CORE", 1483 "Counter": "0,1,2,3", 1484 "CounterHTOff": "0,1,2,3", 1485 "EventCode": "0xB7, 0xBB", 1486 "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_F.HITM_OTHER_CORE", 1487 "MSRIndex": "0x1a6,0x1a7", 1488 "MSRValue": "0x1000200490", 1489 "Offcore": "1", 1490 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1491 "SampleAfterValue": "100003", 1492 "UMask": "0x1" 1493 }, 1494 { 1495 "BriefDescription": "ALL_READS & SUPPLIER_NONE & HIT_OTHER_CORE_FWD", 1496 "Counter": "0,1,2,3", 1497 "CounterHTOff": "0,1,2,3", 1498 "EventCode": "0xB7, 0xBB", 1499 "EventName": "OCR.ALL_READS.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", 1500 "MSRIndex": "0x1a6,0x1a7", 1501 "MSRValue": "0x08000207F7", 1502 "Offcore": "1", 1503 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1504 "SampleAfterValue": "100003", 1505 "UMask": "0x1" 1506 }, 1507 { 1508 "BriefDescription": "ALL_READS & SUPPLIER_NONE & HIT_OTHER_CORE_NO_FWD", 1509 "Counter": "0,1,2,3", 1510 "CounterHTOff": "0,1,2,3", 1511 "EventCode": "0xB7, 0xBB", 1512 "EventName": "OCR.ALL_READS.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", 1513 "MSRIndex": "0x1a6,0x1a7", 1514 "MSRValue": "0x04000207F7", 1515 "Offcore": "1", 1516 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1517 "SampleAfterValue": "100003", 1518 "UMask": "0x1" 1519 }, 1520 { 1521 "BriefDescription": "ALL_PF_DATA_RD & L3_HIT_E & SNOOP_MISS", 1522 "Counter": "0,1,2,3", 1523 "CounterHTOff": "0,1,2,3", 1524 "EventCode": "0xB7, 0xBB", 1525 "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_E.SNOOP_MISS", 1526 "MSRIndex": "0x1a6,0x1a7", 1527 "MSRValue": "0x0200080490", 1528 "Offcore": "1", 1529 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1530 "SampleAfterValue": "100003", 1531 "UMask": "0x1" 1532 }, 1533 { 1534 "BriefDescription": "ALL_DATA_RD & L3_HIT_F & HIT_OTHER_CORE_NO_FWD", 1535 "Counter": "0,1,2,3", 1536 "CounterHTOff": "0,1,2,3", 1537 "EventCode": "0xB7, 0xBB", 1538 "EventName": "OCR.ALL_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", 1539 "MSRIndex": "0x1a6,0x1a7", 1540 "MSRValue": "0x0400200491", 1541 "Offcore": "1", 1542 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1543 "SampleAfterValue": "100003", 1544 "UMask": "0x1" 1545 }, 1546 { 1547 "BriefDescription": "ALL_PF_RFO & L3_HIT_E & NO_SNOOP_NEEDED", 1548 "Counter": "0,1,2,3", 1549 "CounterHTOff": "0,1,2,3", 1550 "EventCode": "0xB7, 0xBB", 1551 "EventName": "OCR.ALL_PF_RFO.L3_HIT_E.NO_SNOOP_NEEDED", 1552 "MSRIndex": "0x1a6,0x1a7", 1553 "MSRValue": "0x0100080120", 1554 "Offcore": "1", 1555 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1556 "SampleAfterValue": "100003", 1557 "UMask": "0x1" 1558 }, 1559 { 1560 "BriefDescription": "ALL_RFO & L3_HIT_E & HIT_OTHER_CORE_FWD", 1561 "Counter": "0,1,2,3", 1562 "CounterHTOff": "0,1,2,3", 1563 "EventCode": "0xB7, 0xBB", 1564 "EventName": "OCR.ALL_RFO.L3_HIT_E.HIT_OTHER_CORE_FWD", 1565 "MSRIndex": "0x1a6,0x1a7", 1566 "MSRValue": "0x0800080122", 1567 "Offcore": "1", 1568 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1569 "SampleAfterValue": "100003", 1570 "UMask": "0x1" 1571 }, 1572 { 1573 "BriefDescription": "ALL_DATA_RD & L3_HIT_F & ANY_SNOOP", 1574 "Counter": "0,1,2,3", 1575 "CounterHTOff": "0,1,2,3", 1576 "EventCode": "0xB7, 0xBB", 1577 "EventName": "OCR.ALL_DATA_RD.L3_HIT_F.ANY_SNOOP", 1578 "MSRIndex": "0x1a6,0x1a7", 1579 "MSRValue": "0x3F80200491", 1580 "Offcore": "1", 1581 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1582 "SampleAfterValue": "100003", 1583 "UMask": "0x1" 1584 }, 1585 { 1586 "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs PF_L3_RFO & L3_HIT & SNOOP_NONE", 1587 "Counter": "0,1,2,3", 1588 "CounterHTOff": "0,1,2,3", 1589 "EventCode": "0xB7, 0xBB", 1590 "EventName": "OCR.PF_L3_RFO.L3_HIT.SNOOP_NONE", 1591 "MSRIndex": "0x1a6,0x1a7", 1592 "MSRValue": "0x00803C0100", 1593 "Offcore": "1", 1594 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1595 "SampleAfterValue": "100003", 1596 "UMask": "0x1" 1597 }, 1598 { 1599 "BriefDescription": "Counts demand data reads DEMAND_DATA_RD & L3_HIT_E & HIT_OTHER_CORE_FWD", 1600 "Counter": "0,1,2,3", 1601 "CounterHTOff": "0,1,2,3", 1602 "EventCode": "0xB7, 0xBB", 1603 "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWD", 1604 "MSRIndex": "0x1a6,0x1a7", 1605 "MSRValue": "0x0800080001", 1606 "Offcore": "1", 1607 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1608 "SampleAfterValue": "100003", 1609 "UMask": "0x1" 1610 }, 1611 { 1612 "BriefDescription": "Counts demand data reads DEMAND_DATA_RD & L3_HIT_E & NO_SNOOP_NEEDED", 1613 "Counter": "0,1,2,3", 1614 "CounterHTOff": "0,1,2,3", 1615 "EventCode": "0xB7, 0xBB", 1616 "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDED", 1617 "MSRIndex": "0x1a6,0x1a7", 1618 "MSRValue": "0x0100080001", 1619 "Offcore": "1", 1620 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1621 "SampleAfterValue": "100003", 1622 "UMask": "0x1" 1623 }, 1624 { 1625 "BriefDescription": "Counts any other requests OTHER & L3_HIT_E & HIT_OTHER_CORE_NO_FWD", 1626 "Counter": "0,1,2,3", 1627 "CounterHTOff": "0,1,2,3", 1628 "EventCode": "0xB7, 0xBB", 1629 "EventName": "OCR.OTHER.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", 1630 "MSRIndex": "0x1a6,0x1a7", 1631 "MSRValue": "0x0400088000", 1632 "Offcore": "1", 1633 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1634 "SampleAfterValue": "100003", 1635 "UMask": "0x1" 1636 }, 1637 { 1638 "BriefDescription": "ALL_RFO & L3_HIT_M & HITM_OTHER_CORE", 1639 "Counter": "0,1,2,3", 1640 "CounterHTOff": "0,1,2,3", 1641 "EventCode": "0xB7, 0xBB", 1642 "EventName": "OCR.ALL_RFO.L3_HIT_M.HITM_OTHER_CORE", 1643 "MSRIndex": "0x1a6,0x1a7", 1644 "MSRValue": "0x1000040122", 1645 "Offcore": "1", 1646 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1647 "SampleAfterValue": "100003", 1648 "UMask": "0x1" 1649 }, 1650 { 1651 "BriefDescription": "Counts demand data reads", 1652 "Counter": "0,1,2,3", 1653 "CounterHTOff": "0,1,2,3", 1654 "EventCode": "0xB7, 0xBB", 1655 "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_M.SNOOP_MISS", 1656 "MSRIndex": "0x1a6,0x1a7", 1657 "MSRValue": "0x0200040001", 1658 "Offcore": "1", 1659 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1660 "SampleAfterValue": "100003", 1661 "UMask": "0x1" 1662 }, 1663 { 1664 "BriefDescription": "ALL_RFO & ANY_RESPONSE have any response type.", 1665 "Counter": "0,1,2,3", 1666 "CounterHTOff": "0,1,2,3", 1667 "EventCode": "0xB7, 0xBB", 1668 "EventName": "OCR.ALL_RFO.ANY_RESPONSE", 1669 "MSRIndex": "0x1a6,0x1a7", 1670 "MSRValue": "0x0000010122", 1671 "Offcore": "1", 1672 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1673 "SampleAfterValue": "100003", 1674 "UMask": "0x1" 1675 }, 1676 { 1677 "BriefDescription": "Counts all demand code reads have any response type.", 1678 "Counter": "0,1,2,3", 1679 "CounterHTOff": "0,1,2,3", 1680 "EventCode": "0xB7, 0xBB", 1681 "EventName": "OCR.DEMAND_CODE_RD.ANY_RESPONSE", 1682 "MSRIndex": "0x1a6,0x1a7", 1683 "MSRValue": "0x0000010004", 1684 "Offcore": "1", 1685 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1686 "SampleAfterValue": "100003", 1687 "UMask": "0x1" 1688 }, 1689 { 1690 "BriefDescription": "Counts all demand code reads", 1691 "Counter": "0,1,2,3", 1692 "CounterHTOff": "0,1,2,3", 1693 "EventCode": "0xB7, 0xBB", 1694 "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_E.SNOOP_MISS", 1695 "MSRIndex": "0x1a6,0x1a7", 1696 "MSRValue": "0x0200080004", 1697 "Offcore": "1", 1698 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1699 "SampleAfterValue": "100003", 1700 "UMask": "0x1" 1701 }, 1702 { 1703 "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs", 1704 "Counter": "0,1,2,3", 1705 "CounterHTOff": "0,1,2,3", 1706 "EventCode": "0xB7, 0xBB", 1707 "EventName": "OCR.PF_L3_RFO.L3_HIT_M.SNOOP_MISS", 1708 "MSRIndex": "0x1a6,0x1a7", 1709 "MSRValue": "0x0200040100", 1710 "Offcore": "1", 1711 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1712 "SampleAfterValue": "100003", 1713 "UMask": "0x1" 1714 }, 1715 { 1716 "BriefDescription": "Counts all demand data writes (RFOs)", 1717 "Counter": "0,1,2,3", 1718 "CounterHTOff": "0,1,2,3", 1719 "EventCode": "0xB7, 0xBB", 1720 "EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_HIT_WITH_FWD", 1721 "MSRIndex": "0x1a6,0x1a7", 1722 "MSRValue": "0x08007C0002", 1723 "Offcore": "1", 1724 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1725 "SampleAfterValue": "100003", 1726 "UMask": "0x1" 1727 }, 1728 { 1729 "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests PF_L1D_AND_SW & PMM_HIT_LOCAL_PMM & ANY_SNOOP", 1730 "Counter": "0,1,2,3", 1731 "CounterHTOff": "0,1,2,3", 1732 "EventCode": "0xB7, 0xBB", 1733 "EventName": "OCR.PF_L1D_AND_SW.PMM_HIT_LOCAL_PMM.ANY_SNOOP", 1734 "MSRIndex": "0x1a6,0x1a7", 1735 "MSRValue": "0x3F80400400", 1736 "Offcore": "1", 1737 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1738 "SampleAfterValue": "100003", 1739 "UMask": "0x1" 1740 }, 1741 { 1742 "BriefDescription": "Counts demand data reads DEMAND_DATA_RD & L3_HIT & HIT_OTHER_CORE_FWD", 1743 "Counter": "0,1,2,3", 1744 "CounterHTOff": "0,1,2,3", 1745 "EventCode": "0xB7, 0xBB", 1746 "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD", 1747 "MSRIndex": "0x1a6,0x1a7", 1748 "MSRValue": "0x08003C0001", 1749 "Offcore": "1", 1750 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1751 "SampleAfterValue": "100003", 1752 "UMask": "0x1" 1753 }, 1754 { 1755 "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs PF_L2_RFO & L3_HIT & ANY_SNOOP", 1756 "Counter": "0,1,2,3", 1757 "CounterHTOff": "0,1,2,3", 1758 "EventCode": "0xB7, 0xBB", 1759 "EventName": "OCR.PF_L2_RFO.L3_HIT.ANY_SNOOP", 1760 "MSRIndex": "0x1a6,0x1a7", 1761 "MSRValue": "0x3F803C0020", 1762 "Offcore": "1", 1763 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1764 "SampleAfterValue": "100003", 1765 "UMask": "0x1" 1766 }, 1767 { 1768 "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs PF_L2_RFO & L3_HIT_E & HIT_OTHER_CORE_NO_FWD", 1769 "Counter": "0,1,2,3", 1770 "CounterHTOff": "0,1,2,3", 1771 "EventCode": "0xB7, 0xBB", 1772 "EventName": "OCR.PF_L2_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", 1773 "MSRIndex": "0x1a6,0x1a7", 1774 "MSRValue": "0x0400080020", 1775 "Offcore": "1", 1776 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1777 "SampleAfterValue": "100003", 1778 "UMask": "0x1" 1779 }, 1780 { 1781 "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs PF_L2_RFO & PMM_HIT_LOCAL_PMM & SNOOP_NOT_NEEDED", 1782 "Counter": "0,1,2,3", 1783 "CounterHTOff": "0,1,2,3", 1784 "EventCode": "0xB7, 0xBB", 1785 "EventName": "OCR.PF_L2_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", 1786 "MSRIndex": "0x1a6,0x1a7", 1787 "MSRValue": "0x0100400020", 1788 "Offcore": "1", 1789 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1790 "SampleAfterValue": "100003", 1791 "UMask": "0x1" 1792 }, 1793 { 1794 "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs PF_L2_RFO & L3_HIT_F & ANY_SNOOP", 1795 "Counter": "0,1,2,3", 1796 "CounterHTOff": "0,1,2,3", 1797 "EventCode": "0xB7, 0xBB", 1798 "EventName": "OCR.PF_L2_RFO.L3_HIT_F.ANY_SNOOP", 1799 "MSRIndex": "0x1a6,0x1a7", 1800 "MSRValue": "0x3F80200020", 1801 "Offcore": "1", 1802 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1803 "SampleAfterValue": "100003", 1804 "UMask": "0x1" 1805 }, 1806 { 1807 "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads PF_L3_DATA_RD & SUPPLIER_NONE & HITM_OTHER_CORE", 1808 "Counter": "0,1,2,3", 1809 "CounterHTOff": "0,1,2,3", 1810 "EventCode": "0xB7, 0xBB", 1811 "EventName": "OCR.PF_L3_DATA_RD.SUPPLIER_NONE.HITM_OTHER_CORE", 1812 "MSRIndex": "0x1a6,0x1a7", 1813 "MSRValue": "0x1000020080", 1814 "Offcore": "1", 1815 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1816 "SampleAfterValue": "100003", 1817 "UMask": "0x1" 1818 }, 1819 { 1820 "BriefDescription": "ALL_READS & L3_HIT & SNOOP_MISS", 1821 "Counter": "0,1,2,3", 1822 "CounterHTOff": "0,1,2,3", 1823 "EventCode": "0xB7, 0xBB", 1824 "EventName": "OCR.ALL_READS.L3_HIT.SNOOP_MISS", 1825 "MSRIndex": "0x1a6,0x1a7", 1826 "MSRValue": "0x02003C07F7", 1827 "Offcore": "1", 1828 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1829 "SampleAfterValue": "100003", 1830 "UMask": "0x1" 1831 }, 1832 { 1833 "BriefDescription": "ALL_PF_DATA_RD & SUPPLIER_NONE & SNOOP_MISS", 1834 "Counter": "0,1,2,3", 1835 "CounterHTOff": "0,1,2,3", 1836 "EventCode": "0xB7, 0xBB", 1837 "EventName": "OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.SNOOP_MISS", 1838 "MSRIndex": "0x1a6,0x1a7", 1839 "MSRValue": "0x0200020490", 1840 "Offcore": "1", 1841 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1842 "SampleAfterValue": "100003", 1843 "UMask": "0x1" 1844 }, 1845 { 1846 "BriefDescription": "Counts demand data reads DEMAND_DATA_RD & L3_HIT_F & HIT_OTHER_CORE_NO_FWD", 1847 "Counter": "0,1,2,3", 1848 "CounterHTOff": "0,1,2,3", 1849 "EventCode": "0xB7, 0xBB", 1850 "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", 1851 "MSRIndex": "0x1a6,0x1a7", 1852 "MSRValue": "0x0400200001", 1853 "Offcore": "1", 1854 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1855 "SampleAfterValue": "100003", 1856 "UMask": "0x1" 1857 }, 1858 { 1859 "BriefDescription": "Counts prefetch (that bring data to L2) data reads PF_L2_DATA_RD & PMM_HIT_LOCAL_PMM & SNOOP_NONE", 1860 "Counter": "0,1,2,3", 1861 "CounterHTOff": "0,1,2,3", 1862 "EventCode": "0xB7, 0xBB", 1863 "EventName": "OCR.PF_L2_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE", 1864 "MSRIndex": "0x1a6,0x1a7", 1865 "MSRValue": "0x0080400010", 1866 "Offcore": "1", 1867 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1868 "SampleAfterValue": "100003", 1869 "UMask": "0x1" 1870 }, 1871 { 1872 "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs", 1873 "Counter": "0,1,2,3", 1874 "CounterHTOff": "0,1,2,3", 1875 "EventCode": "0xB7, 0xBB", 1876 "EventName": "OCR.PF_L3_RFO.L3_HIT_E.SNOOP_MISS", 1877 "MSRIndex": "0x1a6,0x1a7", 1878 "MSRValue": "0x0200080100", 1879 "Offcore": "1", 1880 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1881 "SampleAfterValue": "100003", 1882 "UMask": "0x1" 1883 }, 1884 { 1885 "BriefDescription": "Counts all demand data writes (RFOs)", 1886 "Counter": "0,1,2,3", 1887 "CounterHTOff": "0,1,2,3", 1888 "EventCode": "0xB7, 0xBB", 1889 "EventName": "OCR.DEMAND_RFO.L3_HIT_F.SNOOP_NONE", 1890 "MSRIndex": "0x1a6,0x1a7", 1891 "MSRValue": "0x0080200002", 1892 "Offcore": "1", 1893 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1894 "SampleAfterValue": "100003", 1895 "UMask": "0x1" 1896 }, 1897 { 1898 "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs", 1899 "Counter": "0,1,2,3", 1900 "CounterHTOff": "0,1,2,3", 1901 "EventCode": "0xB7, 0xBB", 1902 "EventName": "OCR.PF_L2_RFO.SUPPLIER_NONE.SNOOP_NONE", 1903 "MSRIndex": "0x1a6,0x1a7", 1904 "MSRValue": "0x0080020020", 1905 "Offcore": "1", 1906 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1907 "SampleAfterValue": "100003", 1908 "UMask": "0x1" 1909 }, 1910 { 1911 "BriefDescription": "Counts any other requests OTHER & L3_HIT_E & NO_SNOOP_NEEDED", 1912 "Counter": "0,1,2,3", 1913 "CounterHTOff": "0,1,2,3", 1914 "EventCode": "0xB7, 0xBB", 1915 "EventName": "OCR.OTHER.L3_HIT_E.NO_SNOOP_NEEDED", 1916 "MSRIndex": "0x1a6,0x1a7", 1917 "MSRValue": "0x0100088000", 1918 "Offcore": "1", 1919 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1920 "SampleAfterValue": "100003", 1921 "UMask": "0x1" 1922 }, 1923 { 1924 "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs PF_L3_RFO & L3_HIT_F & HIT_OTHER_CORE_NO_FWD", 1925 "Counter": "0,1,2,3", 1926 "CounterHTOff": "0,1,2,3", 1927 "EventCode": "0xB7, 0xBB", 1928 "EventName": "OCR.PF_L3_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", 1929 "MSRIndex": "0x1a6,0x1a7", 1930 "MSRValue": "0x0400200100", 1931 "Offcore": "1", 1932 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1933 "SampleAfterValue": "100003", 1934 "UMask": "0x1" 1935 }, 1936 { 1937 "BriefDescription": "ALL_PF_DATA_RD & L3_HIT_F & ANY_SNOOP", 1938 "Counter": "0,1,2,3", 1939 "CounterHTOff": "0,1,2,3", 1940 "EventCode": "0xB7, 0xBB", 1941 "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_F.ANY_SNOOP", 1942 "MSRIndex": "0x1a6,0x1a7", 1943 "MSRValue": "0x3F80200490", 1944 "Offcore": "1", 1945 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1946 "SampleAfterValue": "100003", 1947 "UMask": "0x1" 1948 }, 1949 { 1950 "BriefDescription": "ALL_PF_RFO & L3_HIT_M & HIT_OTHER_CORE_FWD", 1951 "Counter": "0,1,2,3", 1952 "CounterHTOff": "0,1,2,3", 1953 "EventCode": "0xB7, 0xBB", 1954 "EventName": "OCR.ALL_PF_RFO.L3_HIT_M.HIT_OTHER_CORE_FWD", 1955 "MSRIndex": "0x1a6,0x1a7", 1956 "MSRValue": "0x0800040120", 1957 "Offcore": "1", 1958 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1959 "SampleAfterValue": "100003", 1960 "UMask": "0x1" 1961 }, 1962 { 1963 "BriefDescription": "ALL_READS & SUPPLIER_NONE & ANY_SNOOP", 1964 "Counter": "0,1,2,3", 1965 "CounterHTOff": "0,1,2,3", 1966 "EventCode": "0xB7, 0xBB", 1967 "EventName": "OCR.ALL_READS.SUPPLIER_NONE.ANY_SNOOP", 1968 "MSRIndex": "0x1a6,0x1a7", 1969 "MSRValue": "0x3F800207F7", 1970 "Offcore": "1", 1971 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1972 "SampleAfterValue": "100003", 1973 "UMask": "0x1" 1974 }, 1975 { 1976 "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads PF_L3_DATA_RD & L3_HIT_F & ANY_SNOOP", 1977 "Counter": "0,1,2,3", 1978 "CounterHTOff": "0,1,2,3", 1979 "EventCode": "0xB7, 0xBB", 1980 "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_F.ANY_SNOOP", 1981 "MSRIndex": "0x1a6,0x1a7", 1982 "MSRValue": "0x3F80200080", 1983 "Offcore": "1", 1984 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1985 "SampleAfterValue": "100003", 1986 "UMask": "0x1" 1987 }, 1988 { 1989 "BriefDescription": "Counts prefetch (that bring data to L2) data reads PF_L2_DATA_RD & L3_HIT & SNOOP_NONE", 1990 "Counter": "0,1,2,3", 1991 "CounterHTOff": "0,1,2,3", 1992 "EventCode": "0xB7, 0xBB", 1993 "EventName": "OCR.PF_L2_DATA_RD.L3_HIT.SNOOP_NONE", 1994 "MSRIndex": "0x1a6,0x1a7", 1995 "MSRValue": "0x00803C0010", 1996 "Offcore": "1", 1997 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1998 "SampleAfterValue": "100003", 1999 "UMask": "0x1" 2000 }, 2001 { 2002 "BriefDescription": "ALL_DATA_RD & L3_HIT_S & NO_SNOOP_NEEDED", 2003 "Counter": "0,1,2,3", 2004 "CounterHTOff": "0,1,2,3", 2005 "EventCode": "0xB7, 0xBB", 2006 "EventName": "OCR.ALL_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDED", 2007 "MSRIndex": "0x1a6,0x1a7", 2008 "MSRValue": "0x0100100491", 2009 "Offcore": "1", 2010 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2011 "SampleAfterValue": "100003", 2012 "UMask": "0x1" 2013 }, 2014 { 2015 "BriefDescription": "ALL_PF_RFO & SUPPLIER_NONE & SNOOP_MISS", 2016 "Counter": "0,1,2,3", 2017 "CounterHTOff": "0,1,2,3", 2018 "EventCode": "0xB7, 0xBB", 2019 "EventName": "OCR.ALL_PF_RFO.SUPPLIER_NONE.SNOOP_MISS", 2020 "MSRIndex": "0x1a6,0x1a7", 2021 "MSRValue": "0x0200020120", 2022 "Offcore": "1", 2023 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2024 "SampleAfterValue": "100003", 2025 "UMask": "0x1" 2026 }, 2027 { 2028 "BriefDescription": "ALL_RFO & L3_HIT_M & HIT_OTHER_CORE_NO_FWD", 2029 "Counter": "0,1,2,3", 2030 "CounterHTOff": "0,1,2,3", 2031 "EventCode": "0xB7, 0xBB", 2032 "EventName": "OCR.ALL_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", 2033 "MSRIndex": "0x1a6,0x1a7", 2034 "MSRValue": "0x0400040122", 2035 "Offcore": "1", 2036 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2037 "SampleAfterValue": "100003", 2038 "UMask": "0x1" 2039 }, 2040 { 2041 "BriefDescription": "ALL_READS & SUPPLIER_NONE & SNOOP_NONE", 2042 "Counter": "0,1,2,3", 2043 "CounterHTOff": "0,1,2,3", 2044 "EventCode": "0xB7, 0xBB", 2045 "EventName": "OCR.ALL_READS.SUPPLIER_NONE.SNOOP_NONE", 2046 "MSRIndex": "0x1a6,0x1a7", 2047 "MSRValue": "0x00800207F7", 2048 "Offcore": "1", 2049 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2050 "SampleAfterValue": "100003", 2051 "UMask": "0x1" 2052 }, 2053 { 2054 "BriefDescription": "ALL_DATA_RD & L3_HIT_S & HIT_OTHER_CORE_FWD", 2055 "Counter": "0,1,2,3", 2056 "CounterHTOff": "0,1,2,3", 2057 "EventCode": "0xB7, 0xBB", 2058 "EventName": "OCR.ALL_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWD", 2059 "MSRIndex": "0x1a6,0x1a7", 2060 "MSRValue": "0x0800100491", 2061 "Offcore": "1", 2062 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2063 "SampleAfterValue": "100003", 2064 "UMask": "0x1" 2065 }, 2066 { 2067 "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests", 2068 "Counter": "0,1,2,3", 2069 "CounterHTOff": "0,1,2,3", 2070 "EventCode": "0xB7, 0xBB", 2071 "EventName": "OCR.PF_L1D_AND_SW.SUPPLIER_NONE.SNOOP_MISS", 2072 "MSRIndex": "0x1a6,0x1a7", 2073 "MSRValue": "0x0200020400", 2074 "Offcore": "1", 2075 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2076 "SampleAfterValue": "100003", 2077 "UMask": "0x1" 2078 }, 2079 { 2080 "BriefDescription": "ALL_RFO & PMM_HIT_LOCAL_PMM & SNOOP_NONE", 2081 "Counter": "0,1,2,3", 2082 "CounterHTOff": "0,1,2,3", 2083 "EventCode": "0xB7, 0xBB", 2084 "EventName": "OCR.ALL_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NONE", 2085 "MSRIndex": "0x1a6,0x1a7", 2086 "MSRValue": "0x0080400122", 2087 "Offcore": "1", 2088 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2089 "SampleAfterValue": "100003", 2090 "UMask": "0x1" 2091 }, 2092 { 2093 "BriefDescription": "ALL_PF_DATA_RD & SUPPLIER_NONE & SNOOP_NONE", 2094 "Counter": "0,1,2,3", 2095 "CounterHTOff": "0,1,2,3", 2096 "EventCode": "0xB7, 0xBB", 2097 "EventName": "OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.SNOOP_NONE", 2098 "MSRIndex": "0x1a6,0x1a7", 2099 "MSRValue": "0x0080020490", 2100 "Offcore": "1", 2101 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2102 "SampleAfterValue": "100003", 2103 "UMask": "0x1" 2104 }, 2105 { 2106 "BriefDescription": "ALL_READS & L3_HIT_E & SNOOP_MISS", 2107 "Counter": "0,1,2,3", 2108 "CounterHTOff": "0,1,2,3", 2109 "EventCode": "0xB7, 0xBB", 2110 "EventName": "OCR.ALL_READS.L3_HIT_E.SNOOP_MISS", 2111 "MSRIndex": "0x1a6,0x1a7", 2112 "MSRValue": "0x02000807F7", 2113 "Offcore": "1", 2114 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2115 "SampleAfterValue": "100003", 2116 "UMask": "0x1" 2117 }, 2118 { 2119 "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs PF_L3_RFO & PMM_HIT_LOCAL_PMM & SNOOP_NOT_NEEDED", 2120 "Counter": "0,1,2,3", 2121 "CounterHTOff": "0,1,2,3", 2122 "EventCode": "0xB7, 0xBB", 2123 "EventName": "OCR.PF_L3_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", 2124 "MSRIndex": "0x1a6,0x1a7", 2125 "MSRValue": "0x0100400100", 2126 "Offcore": "1", 2127 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2128 "SampleAfterValue": "100003", 2129 "UMask": "0x1" 2130 }, 2131 { 2132 "BriefDescription": "ALL_DATA_RD & L3_HIT_M & SNOOP_NONE", 2133 "Counter": "0,1,2,3", 2134 "CounterHTOff": "0,1,2,3", 2135 "EventCode": "0xB7, 0xBB", 2136 "EventName": "OCR.ALL_DATA_RD.L3_HIT_M.SNOOP_NONE", 2137 "MSRIndex": "0x1a6,0x1a7", 2138 "MSRValue": "0x0080040491", 2139 "Offcore": "1", 2140 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2141 "SampleAfterValue": "100003", 2142 "UMask": "0x1" 2143 }, 2144 { 2145 "BriefDescription": "ALL_RFO & PMM_HIT_LOCAL_PMM & ANY_SNOOP", 2146 "Counter": "0,1,2,3", 2147 "CounterHTOff": "0,1,2,3", 2148 "EventCode": "0xB7, 0xBB", 2149 "EventName": "OCR.ALL_RFO.PMM_HIT_LOCAL_PMM.ANY_SNOOP", 2150 "MSRIndex": "0x1a6,0x1a7", 2151 "MSRValue": "0x3F80400122", 2152 "Offcore": "1", 2153 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2154 "SampleAfterValue": "100003", 2155 "UMask": "0x1" 2156 }, 2157 { 2158 "BriefDescription": "ALL_RFO & L3_HIT_M & HIT_OTHER_CORE_FWD", 2159 "Counter": "0,1,2,3", 2160 "CounterHTOff": "0,1,2,3", 2161 "EventCode": "0xB7, 0xBB", 2162 "EventName": "OCR.ALL_RFO.L3_HIT_M.HIT_OTHER_CORE_FWD", 2163 "MSRIndex": "0x1a6,0x1a7", 2164 "MSRValue": "0x0800040122", 2165 "Offcore": "1", 2166 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2167 "SampleAfterValue": "100003", 2168 "UMask": "0x1" 2169 }, 2170 { 2171 "BriefDescription": "Counts all demand code reads DEMAND_CODE_RD & L3_HIT_M & HIT_OTHER_CORE_NO_FWD", 2172 "Counter": "0,1,2,3", 2173 "CounterHTOff": "0,1,2,3", 2174 "EventCode": "0xB7, 0xBB", 2175 "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", 2176 "MSRIndex": "0x1a6,0x1a7", 2177 "MSRValue": "0x0400040004", 2178 "Offcore": "1", 2179 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2180 "SampleAfterValue": "100003", 2181 "UMask": "0x1" 2182 }, 2183 { 2184 "BriefDescription": "Counts prefetch (that bring data to L2) data reads", 2185 "Counter": "0,1,2,3", 2186 "CounterHTOff": "0,1,2,3", 2187 "EventCode": "0xB7, 0xBB", 2188 "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_F.SNOOP_NONE", 2189 "MSRIndex": "0x1a6,0x1a7", 2190 "MSRValue": "0x0080200010", 2191 "Offcore": "1", 2192 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2193 "SampleAfterValue": "100003", 2194 "UMask": "0x1" 2195 }, 2196 { 2197 "BriefDescription": "Counts prefetch (that bring data to L2) data reads PF_L2_DATA_RD & L3_HIT_M & HIT_OTHER_CORE_NO_FWD", 2198 "Counter": "0,1,2,3", 2199 "CounterHTOff": "0,1,2,3", 2200 "EventCode": "0xB7, 0xBB", 2201 "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", 2202 "MSRIndex": "0x1a6,0x1a7", 2203 "MSRValue": "0x0400040010", 2204 "Offcore": "1", 2205 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2206 "SampleAfterValue": "100003", 2207 "UMask": "0x1" 2208 }, 2209 { 2210 "BriefDescription": "Counts demand data reads DEMAND_DATA_RD & L3_HIT & HIT_OTHER_CORE_NO_FWD", 2211 "Counter": "0,1,2,3", 2212 "CounterHTOff": "0,1,2,3", 2213 "EventCode": "0xB7, 0xBB", 2214 "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD", 2215 "MSRIndex": "0x1a6,0x1a7", 2216 "MSRValue": "0x04003C0001", 2217 "Offcore": "1", 2218 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2219 "SampleAfterValue": "100003", 2220 "UMask": "0x1" 2221 }, 2222 { 2223 "BriefDescription": "ALL_PF_RFO & L3_HIT & HIT_OTHER_CORE_FWD", 2224 "Counter": "0,1,2,3", 2225 "CounterHTOff": "0,1,2,3", 2226 "EventCode": "0xB7, 0xBB", 2227 "EventName": "OCR.ALL_PF_RFO.L3_HIT.HIT_OTHER_CORE_FWD", 2228 "MSRIndex": "0x1a6,0x1a7", 2229 "MSRValue": "0x08003C0120", 2230 "Offcore": "1", 2231 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2232 "SampleAfterValue": "100003", 2233 "UMask": "0x1" 2234 }, 2235 { 2236 "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs PF_L3_RFO & L3_HIT_F & HIT_OTHER_CORE_FWD", 2237 "Counter": "0,1,2,3", 2238 "CounterHTOff": "0,1,2,3", 2239 "EventCode": "0xB7, 0xBB", 2240 "EventName": "OCR.PF_L3_RFO.L3_HIT_F.HIT_OTHER_CORE_FWD", 2241 "MSRIndex": "0x1a6,0x1a7", 2242 "MSRValue": "0x0800200100", 2243 "Offcore": "1", 2244 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2245 "SampleAfterValue": "100003", 2246 "UMask": "0x1" 2247 }, 2248 { 2249 "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads PF_L3_DATA_RD & L3_HIT_S & HIT_OTHER_CORE_NO_FWD", 2250 "Counter": "0,1,2,3", 2251 "CounterHTOff": "0,1,2,3", 2252 "EventCode": "0xB7, 0xBB", 2253 "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", 2254 "MSRIndex": "0x1a6,0x1a7", 2255 "MSRValue": "0x0400100080", 2256 "Offcore": "1", 2257 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2258 "SampleAfterValue": "100003", 2259 "UMask": "0x1" 2260 }, 2261 { 2262 "BriefDescription": "Counts demand data reads DEMAND_DATA_RD & L3_HIT_E & ANY_SNOOP", 2263 "Counter": "0,1,2,3", 2264 "CounterHTOff": "0,1,2,3", 2265 "EventCode": "0xB7, 0xBB", 2266 "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_E.ANY_SNOOP", 2267 "MSRIndex": "0x1a6,0x1a7", 2268 "MSRValue": "0x3F80080001", 2269 "Offcore": "1", 2270 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2271 "SampleAfterValue": "100003", 2272 "UMask": "0x1" 2273 }, 2274 { 2275 "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests PF_L1D_AND_SW & L3_HIT_F & NO_SNOOP_NEEDED", 2276 "Counter": "0,1,2,3", 2277 "CounterHTOff": "0,1,2,3", 2278 "EventCode": "0xB7, 0xBB", 2279 "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_F.NO_SNOOP_NEEDED", 2280 "MSRIndex": "0x1a6,0x1a7", 2281 "MSRValue": "0x0100200400", 2282 "Offcore": "1", 2283 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2284 "SampleAfterValue": "100003", 2285 "UMask": "0x1" 2286 }, 2287 { 2288 "BriefDescription": "Counts prefetch (that bring data to L2) data reads PF_L2_DATA_RD & L3_HIT_S & ANY_SNOOP", 2289 "Counter": "0,1,2,3", 2290 "CounterHTOff": "0,1,2,3", 2291 "EventCode": "0xB7, 0xBB", 2292 "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_S.ANY_SNOOP", 2293 "MSRIndex": "0x1a6,0x1a7", 2294 "MSRValue": "0x3F80100010", 2295 "Offcore": "1", 2296 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2297 "SampleAfterValue": "100003", 2298 "UMask": "0x1" 2299 }, 2300 { 2301 "BriefDescription": "Counts demand data reads", 2302 "Counter": "0,1,2,3", 2303 "CounterHTOff": "0,1,2,3", 2304 "EventCode": "0xB7, 0xBB", 2305 "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_F.SNOOP_NONE", 2306 "MSRIndex": "0x1a6,0x1a7", 2307 "MSRValue": "0x0080200001", 2308 "Offcore": "1", 2309 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2310 "SampleAfterValue": "100003", 2311 "UMask": "0x1" 2312 }, 2313 { 2314 "BriefDescription": "Counts all demand code reads", 2315 "Counter": "0,1,2,3", 2316 "CounterHTOff": "0,1,2,3", 2317 "EventCode": "0xB7, 0xBB", 2318 "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_E.SNOOP_NONE", 2319 "MSRIndex": "0x1a6,0x1a7", 2320 "MSRValue": "0x0080080004", 2321 "Offcore": "1", 2322 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2323 "SampleAfterValue": "100003", 2324 "UMask": "0x1" 2325 }, 2326 { 2327 "BriefDescription": "Counts prefetch (that bring data to L2) data reads", 2328 "Counter": "0,1,2,3", 2329 "CounterHTOff": "0,1,2,3", 2330 "EventCode": "0xB7, 0xBB", 2331 "EventName": "OCR.PF_L2_DATA_RD.SUPPLIER_NONE.SNOOP_MISS", 2332 "MSRIndex": "0x1a6,0x1a7", 2333 "MSRValue": "0x0200020010", 2334 "Offcore": "1", 2335 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2336 "SampleAfterValue": "100003", 2337 "UMask": "0x1" 2338 }, 2339 { 2340 "BriefDescription": "ALL_PF_DATA_RD & L3_HIT_F & SNOOP_MISS", 2341 "Counter": "0,1,2,3", 2342 "CounterHTOff": "0,1,2,3", 2343 "EventCode": "0xB7, 0xBB", 2344 "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_F.SNOOP_MISS", 2345 "MSRIndex": "0x1a6,0x1a7", 2346 "MSRValue": "0x0200200490", 2347 "Offcore": "1", 2348 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2349 "SampleAfterValue": "100003", 2350 "UMask": "0x1" 2351 }, 2352 { 2353 "BriefDescription": "ALL_PF_DATA_RD & L3_HIT_M & ANY_SNOOP", 2354 "Counter": "0,1,2,3", 2355 "CounterHTOff": "0,1,2,3", 2356 "EventCode": "0xB7, 0xBB", 2357 "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_M.ANY_SNOOP", 2358 "MSRIndex": "0x1a6,0x1a7", 2359 "MSRValue": "0x3F80040490", 2360 "Offcore": "1", 2361 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2362 "SampleAfterValue": "100003", 2363 "UMask": "0x1" 2364 }, 2365 { 2366 "BriefDescription": "Counts all demand code reads DEMAND_CODE_RD & SUPPLIER_NONE & HITM_OTHER_CORE", 2367 "Counter": "0,1,2,3", 2368 "CounterHTOff": "0,1,2,3", 2369 "EventCode": "0xB7, 0xBB", 2370 "EventName": "OCR.DEMAND_CODE_RD.SUPPLIER_NONE.HITM_OTHER_CORE", 2371 "MSRIndex": "0x1a6,0x1a7", 2372 "MSRValue": "0x1000020004", 2373 "Offcore": "1", 2374 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2375 "SampleAfterValue": "100003", 2376 "UMask": "0x1" 2377 }, 2378 { 2379 "BriefDescription": "Counts all demand code reads DEMAND_CODE_RD & L3_HIT & HIT_OTHER_CORE_FWD", 2380 "Counter": "0,1,2,3", 2381 "CounterHTOff": "0,1,2,3", 2382 "EventCode": "0xB7, 0xBB", 2383 "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.HIT_OTHER_CORE_FWD", 2384 "MSRIndex": "0x1a6,0x1a7", 2385 "MSRValue": "0x08003C0004", 2386 "Offcore": "1", 2387 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2388 "SampleAfterValue": "100003", 2389 "UMask": "0x1" 2390 }, 2391 { 2392 "BriefDescription": "Counts all demand code reads DEMAND_CODE_RD & SUPPLIER_NONE & HIT_OTHER_CORE_NO_FWD", 2393 "Counter": "0,1,2,3", 2394 "CounterHTOff": "0,1,2,3", 2395 "EventCode": "0xB7, 0xBB", 2396 "EventName": "OCR.DEMAND_CODE_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", 2397 "MSRIndex": "0x1a6,0x1a7", 2398 "MSRValue": "0x0400020004", 2399 "Offcore": "1", 2400 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2401 "SampleAfterValue": "100003", 2402 "UMask": "0x1" 2403 }, 2404 { 2405 "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs PF_L2_RFO & L3_HIT_S & HITM_OTHER_CORE", 2406 "Counter": "0,1,2,3", 2407 "CounterHTOff": "0,1,2,3", 2408 "EventCode": "0xB7, 0xBB", 2409 "EventName": "OCR.PF_L2_RFO.L3_HIT_S.HITM_OTHER_CORE", 2410 "MSRIndex": "0x1a6,0x1a7", 2411 "MSRValue": "0x1000100020", 2412 "Offcore": "1", 2413 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2414 "SampleAfterValue": "100003", 2415 "UMask": "0x1" 2416 }, 2417 { 2418 "BriefDescription": "Counts all demand data writes (RFOs)", 2419 "Counter": "0,1,2,3", 2420 "CounterHTOff": "0,1,2,3", 2421 "EventCode": "0xB7, 0xBB", 2422 "EventName": "OCR.DEMAND_RFO.L3_HIT_M.SNOOP_MISS", 2423 "MSRIndex": "0x1a6,0x1a7", 2424 "MSRValue": "0x0200040002", 2425 "Offcore": "1", 2426 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2427 "SampleAfterValue": "100003", 2428 "UMask": "0x1" 2429 }, 2430 { 2431 "BriefDescription": "ALL_RFO & L3_HIT_F & HIT_OTHER_CORE_FWD", 2432 "Counter": "0,1,2,3", 2433 "CounterHTOff": "0,1,2,3", 2434 "EventCode": "0xB7, 0xBB", 2435 "EventName": "OCR.ALL_RFO.L3_HIT_F.HIT_OTHER_CORE_FWD", 2436 "MSRIndex": "0x1a6,0x1a7", 2437 "MSRValue": "0x0800200122", 2438 "Offcore": "1", 2439 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2440 "SampleAfterValue": "100003", 2441 "UMask": "0x1" 2442 }, 2443 { 2444 "BriefDescription": "ALL_RFO & L3_HIT_E & HIT_OTHER_CORE_NO_FWD", 2445 "Counter": "0,1,2,3", 2446 "CounterHTOff": "0,1,2,3", 2447 "EventCode": "0xB7, 0xBB", 2448 "EventName": "OCR.ALL_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", 2449 "MSRIndex": "0x1a6,0x1a7", 2450 "MSRValue": "0x0400080122", 2451 "Offcore": "1", 2452 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2453 "SampleAfterValue": "100003", 2454 "UMask": "0x1" 2455 }, 2456 { 2457 "BriefDescription": "Counts all demand data writes (RFOs) DEMAND_RFO & SUPPLIER_NONE & HITM_OTHER_CORE", 2458 "Counter": "0,1,2,3", 2459 "CounterHTOff": "0,1,2,3", 2460 "EventCode": "0xB7, 0xBB", 2461 "EventName": "OCR.DEMAND_RFO.SUPPLIER_NONE.HITM_OTHER_CORE", 2462 "MSRIndex": "0x1a6,0x1a7", 2463 "MSRValue": "0x1000020002", 2464 "Offcore": "1", 2465 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2466 "SampleAfterValue": "100003", 2467 "UMask": "0x1" 2468 }, 2469 { 2470 "BriefDescription": "Core cycles where the core was running in a manner where Turbo may be clipped to the Non-AVX turbo schedule.", 2471 "Counter": "0,1,2,3", 2472 "CounterHTOff": "0,1,2,3,4,5,6,7", 2473 "EventCode": "0x28", 2474 "EventName": "CORE_POWER.LVL0_TURBO_LICENSE", 2475 "PublicDescription": "Core cycles where the core was running with power-delivery for baseline license level 0. This includes non-AVX codes, SSE, AVX 128-bit, and low-current AVX 256-bit codes.", 2476 "SampleAfterValue": "200003", 2477 "UMask": "0x7" 2478 }, 2479 { 2480 "BriefDescription": "Counts any other requests", 2481 "Counter": "0,1,2,3", 2482 "CounterHTOff": "0,1,2,3", 2483 "EventCode": "0xB7, 0xBB", 2484 "EventName": "OCR.OTHER.SUPPLIER_NONE.SNOOP_NONE", 2485 "MSRIndex": "0x1a6,0x1a7", 2486 "MSRValue": "0x0080028000", 2487 "Offcore": "1", 2488 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2489 "SampleAfterValue": "100003", 2490 "UMask": "0x1" 2491 }, 2492 { 2493 "BriefDescription": "ALL_PF_DATA_RD & PMM_HIT_LOCAL_PMM & SNOOP_NONE", 2494 "Counter": "0,1,2,3", 2495 "CounterHTOff": "0,1,2,3", 2496 "EventCode": "0xB7, 0xBB", 2497 "EventName": "OCR.ALL_PF_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE", 2498 "MSRIndex": "0x1a6,0x1a7", 2499 "MSRValue": "0x0080400490", 2500 "Offcore": "1", 2501 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2502 "SampleAfterValue": "100003", 2503 "UMask": "0x1" 2504 }, 2505 { 2506 "BriefDescription": "Counts all demand data writes (RFOs) DEMAND_RFO & L3_HIT_M & HIT_OTHER_CORE_FWD", 2507 "Counter": "0,1,2,3", 2508 "CounterHTOff": "0,1,2,3", 2509 "EventCode": "0xB7, 0xBB", 2510 "EventName": "OCR.DEMAND_RFO.L3_HIT_M.HIT_OTHER_CORE_FWD", 2511 "MSRIndex": "0x1a6,0x1a7", 2512 "MSRValue": "0x0800040002", 2513 "Offcore": "1", 2514 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2515 "SampleAfterValue": "100003", 2516 "UMask": "0x1" 2517 }, 2518 { 2519 "BriefDescription": "Counts all demand data writes (RFOs) DEMAND_RFO & L3_HIT_F & NO_SNOOP_NEEDED", 2520 "Counter": "0,1,2,3", 2521 "CounterHTOff": "0,1,2,3", 2522 "EventCode": "0xB7, 0xBB", 2523 "EventName": "OCR.DEMAND_RFO.L3_HIT_F.NO_SNOOP_NEEDED", 2524 "MSRIndex": "0x1a6,0x1a7", 2525 "MSRValue": "0x0100200002", 2526 "Offcore": "1", 2527 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2528 "SampleAfterValue": "100003", 2529 "UMask": "0x1" 2530 }, 2531 { 2532 "BriefDescription": "ALL_RFO & SUPPLIER_NONE & SNOOP_NONE", 2533 "Counter": "0,1,2,3", 2534 "CounterHTOff": "0,1,2,3", 2535 "EventCode": "0xB7, 0xBB", 2536 "EventName": "OCR.ALL_RFO.SUPPLIER_NONE.SNOOP_NONE", 2537 "MSRIndex": "0x1a6,0x1a7", 2538 "MSRValue": "0x0080020122", 2539 "Offcore": "1", 2540 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2541 "SampleAfterValue": "100003", 2542 "UMask": "0x1" 2543 }, 2544 { 2545 "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs PF_L2_RFO & PMM_HIT_LOCAL_PMM & SNOOP_NONE", 2546 "Counter": "0,1,2,3", 2547 "CounterHTOff": "0,1,2,3", 2548 "EventCode": "0xB7, 0xBB", 2549 "EventName": "OCR.PF_L2_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NONE", 2550 "MSRIndex": "0x1a6,0x1a7", 2551 "MSRValue": "0x0080400020", 2552 "Offcore": "1", 2553 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2554 "SampleAfterValue": "100003", 2555 "UMask": "0x1" 2556 }, 2557 { 2558 "BriefDescription": "Counts all demand code reads DEMAND_CODE_RD & L3_HIT_E & HITM_OTHER_CORE", 2559 "Counter": "0,1,2,3", 2560 "CounterHTOff": "0,1,2,3", 2561 "EventCode": "0xB7, 0xBB", 2562 "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_E.HITM_OTHER_CORE", 2563 "MSRIndex": "0x1a6,0x1a7", 2564 "MSRValue": "0x1000080004", 2565 "Offcore": "1", 2566 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2567 "SampleAfterValue": "100003", 2568 "UMask": "0x1" 2569 }, 2570 { 2571 "BriefDescription": "ALL_DATA_RD & L3_HIT_S & ANY_SNOOP", 2572 "Counter": "0,1,2,3", 2573 "CounterHTOff": "0,1,2,3", 2574 "EventCode": "0xB7, 0xBB", 2575 "EventName": "OCR.ALL_DATA_RD.L3_HIT_S.ANY_SNOOP", 2576 "MSRIndex": "0x1a6,0x1a7", 2577 "MSRValue": "0x3F80100491", 2578 "Offcore": "1", 2579 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2580 "SampleAfterValue": "100003", 2581 "UMask": "0x1" 2582 }, 2583 { 2584 "BriefDescription": "ALL_READS & L3_HIT_F & HIT_OTHER_CORE_FWD", 2585 "Counter": "0,1,2,3", 2586 "CounterHTOff": "0,1,2,3", 2587 "EventCode": "0xB7, 0xBB", 2588 "EventName": "OCR.ALL_READS.L3_HIT_F.HIT_OTHER_CORE_FWD", 2589 "MSRIndex": "0x1a6,0x1a7", 2590 "MSRValue": "0x08002007F7", 2591 "Offcore": "1", 2592 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2593 "SampleAfterValue": "100003", 2594 "UMask": "0x1" 2595 }, 2596 { 2597 "BriefDescription": "ALL_DATA_RD & L3_HIT_F & SNOOP_MISS", 2598 "Counter": "0,1,2,3", 2599 "CounterHTOff": "0,1,2,3", 2600 "EventCode": "0xB7, 0xBB", 2601 "EventName": "OCR.ALL_DATA_RD.L3_HIT_F.SNOOP_MISS", 2602 "MSRIndex": "0x1a6,0x1a7", 2603 "MSRValue": "0x0200200491", 2604 "Offcore": "1", 2605 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2606 "SampleAfterValue": "100003", 2607 "UMask": "0x1" 2608 }, 2609 { 2610 "BriefDescription": "ALL_PF_RFO & SUPPLIER_NONE & SNOOP_NONE", 2611 "Counter": "0,1,2,3", 2612 "CounterHTOff": "0,1,2,3", 2613 "EventCode": "0xB7, 0xBB", 2614 "EventName": "OCR.ALL_PF_RFO.SUPPLIER_NONE.SNOOP_NONE", 2615 "MSRIndex": "0x1a6,0x1a7", 2616 "MSRValue": "0x0080020120", 2617 "Offcore": "1", 2618 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2619 "SampleAfterValue": "100003", 2620 "UMask": "0x1" 2621 }, 2622 { 2623 "BriefDescription": "ALL_PF_RFO & ANY_RESPONSE have any response type.", 2624 "Counter": "0,1,2,3", 2625 "CounterHTOff": "0,1,2,3", 2626 "EventCode": "0xB7, 0xBB", 2627 "EventName": "OCR.ALL_PF_RFO.ANY_RESPONSE", 2628 "MSRIndex": "0x1a6,0x1a7", 2629 "MSRValue": "0x0000010120", 2630 "Offcore": "1", 2631 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2632 "SampleAfterValue": "100003", 2633 "UMask": "0x1" 2634 }, 2635 { 2636 "BriefDescription": "ALL_RFO & L3_HIT & HIT_OTHER_CORE_NO_FWD", 2637 "Counter": "0,1,2,3", 2638 "CounterHTOff": "0,1,2,3", 2639 "EventCode": "0xB7, 0xBB", 2640 "EventName": "OCR.ALL_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD", 2641 "MSRIndex": "0x1a6,0x1a7", 2642 "MSRValue": "0x04003C0122", 2643 "Offcore": "1", 2644 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2645 "SampleAfterValue": "100003", 2646 "UMask": "0x1" 2647 }, 2648 { 2649 "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs PF_L3_RFO & L3_HIT_M & HITM_OTHER_CORE", 2650 "Counter": "0,1,2,3", 2651 "CounterHTOff": "0,1,2,3", 2652 "EventCode": "0xB7, 0xBB", 2653 "EventName": "OCR.PF_L3_RFO.L3_HIT_M.HITM_OTHER_CORE", 2654 "MSRIndex": "0x1a6,0x1a7", 2655 "MSRValue": "0x1000040100", 2656 "Offcore": "1", 2657 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2658 "SampleAfterValue": "100003", 2659 "UMask": "0x1" 2660 }, 2661 { 2662 "BriefDescription": "Counts all demand code reads DEMAND_CODE_RD & L3_HIT_F & ANY_SNOOP", 2663 "Counter": "0,1,2,3", 2664 "CounterHTOff": "0,1,2,3", 2665 "EventCode": "0xB7, 0xBB", 2666 "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_F.ANY_SNOOP", 2667 "MSRIndex": "0x1a6,0x1a7", 2668 "MSRValue": "0x3F80200004", 2669 "Offcore": "1", 2670 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2671 "SampleAfterValue": "100003", 2672 "UMask": "0x1" 2673 }, 2674 { 2675 "BriefDescription": "Counts prefetch (that bring data to L2) data reads PF_L2_DATA_RD & L3_HIT_E & ANY_SNOOP", 2676 "Counter": "0,1,2,3", 2677 "CounterHTOff": "0,1,2,3", 2678 "EventCode": "0xB7, 0xBB", 2679 "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_E.ANY_SNOOP", 2680 "MSRIndex": "0x1a6,0x1a7", 2681 "MSRValue": "0x3F80080010", 2682 "Offcore": "1", 2683 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2684 "SampleAfterValue": "100003", 2685 "UMask": "0x1" 2686 }, 2687 { 2688 "BriefDescription": "ALL_READS & L3_HIT_M & SNOOP_MISS", 2689 "Counter": "0,1,2,3", 2690 "CounterHTOff": "0,1,2,3", 2691 "EventCode": "0xB7, 0xBB", 2692 "EventName": "OCR.ALL_READS.L3_HIT_M.SNOOP_MISS", 2693 "MSRIndex": "0x1a6,0x1a7", 2694 "MSRValue": "0x02000407F7", 2695 "Offcore": "1", 2696 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2697 "SampleAfterValue": "100003", 2698 "UMask": "0x1" 2699 }, 2700 { 2701 "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs PF_L2_RFO & L3_HIT & SNOOP_MISS", 2702 "Counter": "0,1,2,3", 2703 "CounterHTOff": "0,1,2,3", 2704 "EventCode": "0xB7, 0xBB", 2705 "EventName": "OCR.PF_L2_RFO.L3_HIT.SNOOP_MISS", 2706 "MSRIndex": "0x1a6,0x1a7", 2707 "MSRValue": "0x02003C0020", 2708 "Offcore": "1", 2709 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2710 "SampleAfterValue": "100003", 2711 "UMask": "0x1" 2712 }, 2713 { 2714 "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads PF_L3_DATA_RD & L3_HIT_M & NO_SNOOP_NEEDED", 2715 "Counter": "0,1,2,3", 2716 "CounterHTOff": "0,1,2,3", 2717 "EventCode": "0xB7, 0xBB", 2718 "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDED", 2719 "MSRIndex": "0x1a6,0x1a7", 2720 "MSRValue": "0x0100040080", 2721 "Offcore": "1", 2722 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2723 "SampleAfterValue": "100003", 2724 "UMask": "0x1" 2725 }, 2726 { 2727 "BriefDescription": "Counts all demand data writes (RFOs) DEMAND_RFO & L3_HIT & SNOOP_MISS", 2728 "Counter": "0,1,2,3", 2729 "CounterHTOff": "0,1,2,3", 2730 "EventCode": "0xB7, 0xBB", 2731 "EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_MISS", 2732 "MSRIndex": "0x1a6,0x1a7", 2733 "MSRValue": "0x02003C0002", 2734 "Offcore": "1", 2735 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2736 "SampleAfterValue": "100003", 2737 "UMask": "0x1" 2738 }, 2739 { 2740 "BriefDescription": "Core cycles the core was throttled due to a pending power level request.", 2741 "Counter": "0,1,2,3", 2742 "CounterHTOff": "0,1,2,3,4,5,6,7", 2743 "EventCode": "0x28", 2744 "EventName": "CORE_POWER.THROTTLE", 2745 "PublicDescription": "Core cycles the out-of-order engine was throttled due to a pending power level request.", 2746 "SampleAfterValue": "200003", 2747 "UMask": "0x40" 2748 }, 2749 { 2750 "BriefDescription": "Counts all demand data writes (RFOs) DEMAND_RFO & L3_HIT & HITM_OTHER_CORE", 2751 "Counter": "0,1,2,3", 2752 "CounterHTOff": "0,1,2,3", 2753 "EventCode": "0xB7, 0xBB", 2754 "EventName": "OCR.DEMAND_RFO.L3_HIT.HITM_OTHER_CORE", 2755 "MSRIndex": "0x1a6,0x1a7", 2756 "MSRValue": "0x10003C0002", 2757 "Offcore": "1", 2758 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2759 "SampleAfterValue": "100003", 2760 "UMask": "0x1" 2761 }, 2762 { 2763 "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs", 2764 "Counter": "0,1,2,3", 2765 "CounterHTOff": "0,1,2,3", 2766 "EventCode": "0xB7, 0xBB", 2767 "EventName": "OCR.PF_L2_RFO.L3_HIT_F.SNOOP_MISS", 2768 "MSRIndex": "0x1a6,0x1a7", 2769 "MSRValue": "0x0200200020", 2770 "Offcore": "1", 2771 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2772 "SampleAfterValue": "100003", 2773 "UMask": "0x1" 2774 }, 2775 { 2776 "BriefDescription": "Counts all demand code reads DEMAND_CODE_RD & L3_HIT_E & HIT_OTHER_CORE_FWD", 2777 "Counter": "0,1,2,3", 2778 "CounterHTOff": "0,1,2,3", 2779 "EventCode": "0xB7, 0xBB", 2780 "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_E.HIT_OTHER_CORE_FWD", 2781 "MSRIndex": "0x1a6,0x1a7", 2782 "MSRValue": "0x0800080004", 2783 "Offcore": "1", 2784 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2785 "SampleAfterValue": "100003", 2786 "UMask": "0x1" 2787 }, 2788 { 2789 "BriefDescription": "Counts all demand code reads", 2790 "Counter": "0,1,2,3", 2791 "CounterHTOff": "0,1,2,3", 2792 "EventCode": "0xB7, 0xBB", 2793 "EventName": "OCR.DEMAND_CODE_RD.SUPPLIER_NONE.SNOOP_MISS", 2794 "MSRIndex": "0x1a6,0x1a7", 2795 "MSRValue": "0x0200020004", 2796 "Offcore": "1", 2797 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2798 "SampleAfterValue": "100003", 2799 "UMask": "0x1" 2800 }, 2801 { 2802 "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests PF_L1D_AND_SW & L3_HIT_M & ANY_SNOOP", 2803 "Counter": "0,1,2,3", 2804 "CounterHTOff": "0,1,2,3", 2805 "EventCode": "0xB7, 0xBB", 2806 "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_M.ANY_SNOOP", 2807 "MSRIndex": "0x1a6,0x1a7", 2808 "MSRValue": "0x3F80040400", 2809 "Offcore": "1", 2810 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2811 "SampleAfterValue": "100003", 2812 "UMask": "0x1" 2813 }, 2814 { 2815 "BriefDescription": "ALL_PF_RFO & L3_HIT_M & SNOOP_NONE", 2816 "Counter": "0,1,2,3", 2817 "CounterHTOff": "0,1,2,3", 2818 "EventCode": "0xB7, 0xBB", 2819 "EventName": "OCR.ALL_PF_RFO.L3_HIT_M.SNOOP_NONE", 2820 "MSRIndex": "0x1a6,0x1a7", 2821 "MSRValue": "0x0080040120", 2822 "Offcore": "1", 2823 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2824 "SampleAfterValue": "100003", 2825 "UMask": "0x1" 2826 }, 2827 { 2828 "BriefDescription": "Counts demand data reads DEMAND_DATA_RD & L3_HIT_S & HITM_OTHER_CORE", 2829 "Counter": "0,1,2,3", 2830 "CounterHTOff": "0,1,2,3", 2831 "EventCode": "0xB7, 0xBB", 2832 "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_S.HITM_OTHER_CORE", 2833 "MSRIndex": "0x1a6,0x1a7", 2834 "MSRValue": "0x1000100001", 2835 "Offcore": "1", 2836 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2837 "SampleAfterValue": "100003", 2838 "UMask": "0x1" 2839 }, 2840 { 2841 "BriefDescription": "Counts all demand data writes (RFOs) DEMAND_RFO & L3_HIT_M & ANY_SNOOP", 2842 "Counter": "0,1,2,3", 2843 "CounterHTOff": "0,1,2,3", 2844 "EventCode": "0xB7, 0xBB", 2845 "EventName": "OCR.DEMAND_RFO.L3_HIT_M.ANY_SNOOP", 2846 "MSRIndex": "0x1a6,0x1a7", 2847 "MSRValue": "0x3F80040002", 2848 "Offcore": "1", 2849 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2850 "SampleAfterValue": "100003", 2851 "UMask": "0x1" 2852 }, 2853 { 2854 "BriefDescription": "Counts demand data reads hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.", 2855 "Counter": "0,1,2,3", 2856 "CounterHTOff": "0,1,2,3", 2857 "EventCode": "0xB7, 0xBB", 2858 "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.NO_SNOOP_NEEDED", 2859 "MSRIndex": "0x1a6,0x1a7", 2860 "MSRValue": "0x01003C0001", 2861 "Offcore": "1", 2862 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2863 "SampleAfterValue": "100003", 2864 "UMask": "0x1" 2865 }, 2866 { 2867 "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests", 2868 "Counter": "0,1,2,3", 2869 "CounterHTOff": "0,1,2,3", 2870 "EventCode": "0xB7, 0xBB", 2871 "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_M.SNOOP_NONE", 2872 "MSRIndex": "0x1a6,0x1a7", 2873 "MSRValue": "0x0080040400", 2874 "Offcore": "1", 2875 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2876 "SampleAfterValue": "100003", 2877 "UMask": "0x1" 2878 }, 2879 { 2880 "BriefDescription": "Counts prefetch (that bring data to L2) data reads PF_L2_DATA_RD & L3_HIT_S & HITM_OTHER_CORE", 2881 "Counter": "0,1,2,3", 2882 "CounterHTOff": "0,1,2,3", 2883 "EventCode": "0xB7, 0xBB", 2884 "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_S.HITM_OTHER_CORE", 2885 "MSRIndex": "0x1a6,0x1a7", 2886 "MSRValue": "0x1000100010", 2887 "Offcore": "1", 2888 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2889 "SampleAfterValue": "100003", 2890 "UMask": "0x1" 2891 }, 2892 { 2893 "BriefDescription": "ALL_RFO & SUPPLIER_NONE & HIT_OTHER_CORE_FWD", 2894 "Counter": "0,1,2,3", 2895 "CounterHTOff": "0,1,2,3", 2896 "EventCode": "0xB7, 0xBB", 2897 "EventName": "OCR.ALL_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", 2898 "MSRIndex": "0x1a6,0x1a7", 2899 "MSRValue": "0x0800020122", 2900 "Offcore": "1", 2901 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2902 "SampleAfterValue": "100003", 2903 "UMask": "0x1" 2904 }, 2905 { 2906 "BriefDescription": "Counts any other requests have any response type.", 2907 "Counter": "0,1,2,3", 2908 "CounterHTOff": "0,1,2,3", 2909 "EventCode": "0xB7, 0xBB", 2910 "EventName": "OCR.OTHER.ANY_RESPONSE", 2911 "MSRIndex": "0x1a6,0x1a7", 2912 "MSRValue": "0x0000018000", 2913 "Offcore": "1", 2914 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2915 "SampleAfterValue": "100003", 2916 "UMask": "0x1" 2917 }, 2918 { 2919 "BriefDescription": "Counts all demand code reads DEMAND_CODE_RD & L3_HIT_S & HIT_OTHER_CORE_NO_FWD", 2920 "Counter": "0,1,2,3", 2921 "CounterHTOff": "0,1,2,3", 2922 "EventCode": "0xB7, 0xBB", 2923 "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", 2924 "MSRIndex": "0x1a6,0x1a7", 2925 "MSRValue": "0x0400100004", 2926 "Offcore": "1", 2927 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2928 "SampleAfterValue": "100003", 2929 "UMask": "0x1" 2930 }, 2931 { 2932 "BriefDescription": "Counts all demand code reads DEMAND_CODE_RD & SUPPLIER_NONE & HIT_OTHER_CORE_FWD", 2933 "Counter": "0,1,2,3", 2934 "CounterHTOff": "0,1,2,3", 2935 "EventCode": "0xB7, 0xBB", 2936 "EventName": "OCR.DEMAND_CODE_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", 2937 "MSRIndex": "0x1a6,0x1a7", 2938 "MSRValue": "0x0800020004", 2939 "Offcore": "1", 2940 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2941 "SampleAfterValue": "100003", 2942 "UMask": "0x1" 2943 }, 2944 { 2945 "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs PF_L2_RFO & L3_HIT_E & ANY_SNOOP", 2946 "Counter": "0,1,2,3", 2947 "CounterHTOff": "0,1,2,3", 2948 "EventCode": "0xB7, 0xBB", 2949 "EventName": "OCR.PF_L2_RFO.L3_HIT_E.ANY_SNOOP", 2950 "MSRIndex": "0x1a6,0x1a7", 2951 "MSRValue": "0x3F80080020", 2952 "Offcore": "1", 2953 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2954 "SampleAfterValue": "100003", 2955 "UMask": "0x1" 2956 }, 2957 { 2958 "BriefDescription": "Counts prefetch (that bring data to L2) data reads PF_L2_DATA_RD & SUPPLIER_NONE & ANY_SNOOP", 2959 "Counter": "0,1,2,3", 2960 "CounterHTOff": "0,1,2,3", 2961 "EventCode": "0xB7, 0xBB", 2962 "EventName": "OCR.PF_L2_DATA_RD.SUPPLIER_NONE.ANY_SNOOP", 2963 "MSRIndex": "0x1a6,0x1a7", 2964 "MSRValue": "0x3F80020010", 2965 "Offcore": "1", 2966 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2967 "SampleAfterValue": "100003", 2968 "UMask": "0x1" 2969 }, 2970 { 2971 "BriefDescription": "Counts all demand data writes (RFOs) DEMAND_RFO & SUPPLIER_NONE & NO_SNOOP_NEEDED", 2972 "Counter": "0,1,2,3", 2973 "CounterHTOff": "0,1,2,3", 2974 "EventCode": "0xB7, 0xBB", 2975 "EventName": "OCR.DEMAND_RFO.SUPPLIER_NONE.NO_SNOOP_NEEDED", 2976 "MSRIndex": "0x1a6,0x1a7", 2977 "MSRValue": "0x0100020002", 2978 "Offcore": "1", 2979 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2980 "SampleAfterValue": "100003", 2981 "UMask": "0x1" 2982 }, 2983 { 2984 "BriefDescription": "Counts prefetch (that bring data to L2) data reads", 2985 "Counter": "0,1,2,3", 2986 "CounterHTOff": "0,1,2,3", 2987 "EventCode": "0xB7, 0xBB", 2988 "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_E.SNOOP_NONE", 2989 "MSRIndex": "0x1a6,0x1a7", 2990 "MSRValue": "0x0080080010", 2991 "Offcore": "1", 2992 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2993 "SampleAfterValue": "100003", 2994 "UMask": "0x1" 2995 }, 2996 { 2997 "BriefDescription": "ALL_PF_RFO & L3_HIT & NO_SNOOP_NEEDED", 2998 "Counter": "0,1,2,3", 2999 "CounterHTOff": "0,1,2,3", 3000 "EventCode": "0xB7, 0xBB", 3001 "EventName": "OCR.ALL_PF_RFO.L3_HIT.NO_SNOOP_NEEDED", 3002 "MSRIndex": "0x1a6,0x1a7", 3003 "MSRValue": "0x01003C0120", 3004 "Offcore": "1", 3005 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3006 "SampleAfterValue": "100003", 3007 "UMask": "0x1" 3008 }, 3009 { 3010 "BriefDescription": "Counts demand data reads have any response type.", 3011 "Counter": "0,1,2,3", 3012 "CounterHTOff": "0,1,2,3", 3013 "EventCode": "0xB7, 0xBB", 3014 "EventName": "OCR.DEMAND_DATA_RD.ANY_RESPONSE", 3015 "MSRIndex": "0x1a6,0x1a7", 3016 "MSRValue": "0x0000010001", 3017 "Offcore": "1", 3018 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3019 "SampleAfterValue": "100003", 3020 "UMask": "0x1" 3021 }, 3022 { 3023 "BriefDescription": "Counts all demand code reads DEMAND_CODE_RD & L3_HIT & SNOOP_MISS", 3024 "Counter": "0,1,2,3", 3025 "CounterHTOff": "0,1,2,3", 3026 "EventCode": "0xB7, 0xBB", 3027 "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_MISS", 3028 "MSRIndex": "0x1a6,0x1a7", 3029 "MSRValue": "0x02003C0004", 3030 "Offcore": "1", 3031 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3032 "SampleAfterValue": "100003", 3033 "UMask": "0x1" 3034 }, 3035 { 3036 "BriefDescription": "Counts any other requests", 3037 "Counter": "0,1,2,3", 3038 "CounterHTOff": "0,1,2,3", 3039 "EventCode": "0xB7, 0xBB", 3040 "EventName": "OCR.OTHER.L3_HIT_F.SNOOP_NONE", 3041 "MSRIndex": "0x1a6,0x1a7", 3042 "MSRValue": "0x0080208000", 3043 "Offcore": "1", 3044 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3045 "SampleAfterValue": "100003", 3046 "UMask": "0x1" 3047 }, 3048 { 3049 "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs PF_L2_RFO & SUPPLIER_NONE & ANY_SNOOP", 3050 "Counter": "0,1,2,3", 3051 "CounterHTOff": "0,1,2,3", 3052 "EventCode": "0xB7, 0xBB", 3053 "EventName": "OCR.PF_L2_RFO.SUPPLIER_NONE.ANY_SNOOP", 3054 "MSRIndex": "0x1a6,0x1a7", 3055 "MSRValue": "0x3F80020020", 3056 "Offcore": "1", 3057 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3058 "SampleAfterValue": "100003", 3059 "UMask": "0x1" 3060 }, 3061 { 3062 "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads PF_L3_DATA_RD & L3_HIT_S & HITM_OTHER_CORE", 3063 "Counter": "0,1,2,3", 3064 "CounterHTOff": "0,1,2,3", 3065 "EventCode": "0xB7, 0xBB", 3066 "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_S.HITM_OTHER_CORE", 3067 "MSRIndex": "0x1a6,0x1a7", 3068 "MSRValue": "0x1000100080", 3069 "Offcore": "1", 3070 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3071 "SampleAfterValue": "100003", 3072 "UMask": "0x1" 3073 }, 3074 { 3075 "BriefDescription": "Counts all demand data writes (RFOs) DEMAND_RFO & PMM_HIT_LOCAL_PMM & SNOOP_NONE", 3076 "Counter": "0,1,2,3", 3077 "CounterHTOff": "0,1,2,3", 3078 "EventCode": "0xB7, 0xBB", 3079 "EventName": "OCR.DEMAND_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NONE", 3080 "MSRIndex": "0x1a6,0x1a7", 3081 "MSRValue": "0x0080400002", 3082 "Offcore": "1", 3083 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3084 "SampleAfterValue": "100003", 3085 "UMask": "0x1" 3086 }, 3087 { 3088 "BriefDescription": "Counts all demand data writes (RFOs) DEMAND_RFO & L3_HIT_S & NO_SNOOP_NEEDED", 3089 "Counter": "0,1,2,3", 3090 "CounterHTOff": "0,1,2,3", 3091 "EventCode": "0xB7, 0xBB", 3092 "EventName": "OCR.DEMAND_RFO.L3_HIT_S.NO_SNOOP_NEEDED", 3093 "MSRIndex": "0x1a6,0x1a7", 3094 "MSRValue": "0x0100100002", 3095 "Offcore": "1", 3096 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3097 "SampleAfterValue": "100003", 3098 "UMask": "0x1" 3099 }, 3100 { 3101 "BriefDescription": "ALL_PF_RFO & L3_HIT_M & NO_SNOOP_NEEDED", 3102 "Counter": "0,1,2,3", 3103 "CounterHTOff": "0,1,2,3", 3104 "EventCode": "0xB7, 0xBB", 3105 "EventName": "OCR.ALL_PF_RFO.L3_HIT_M.NO_SNOOP_NEEDED", 3106 "MSRIndex": "0x1a6,0x1a7", 3107 "MSRValue": "0x0100040120", 3108 "Offcore": "1", 3109 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3110 "SampleAfterValue": "100003", 3111 "UMask": "0x1" 3112 }, 3113 { 3114 "BriefDescription": "ALL_PF_RFO & L3_HIT_E & SNOOP_MISS", 3115 "Counter": "0,1,2,3", 3116 "CounterHTOff": "0,1,2,3", 3117 "EventCode": "0xB7, 0xBB", 3118 "EventName": "OCR.ALL_PF_RFO.L3_HIT_E.SNOOP_MISS", 3119 "MSRIndex": "0x1a6,0x1a7", 3120 "MSRValue": "0x0200080120", 3121 "Offcore": "1", 3122 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3123 "SampleAfterValue": "100003", 3124 "UMask": "0x1" 3125 }, 3126 { 3127 "BriefDescription": "Counts demand data reads DEMAND_DATA_RD & SUPPLIER_NONE & ANY_SNOOP", 3128 "Counter": "0,1,2,3", 3129 "CounterHTOff": "0,1,2,3", 3130 "EventCode": "0xB7, 0xBB", 3131 "EventName": "OCR.DEMAND_DATA_RD.SUPPLIER_NONE.ANY_SNOOP", 3132 "MSRIndex": "0x1a6,0x1a7", 3133 "MSRValue": "0x3F80020001", 3134 "Offcore": "1", 3135 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3136 "SampleAfterValue": "100003", 3137 "UMask": "0x1" 3138 }, 3139 { 3140 "BriefDescription": "ALL_DATA_RD & ANY_RESPONSE have any response type.", 3141 "Counter": "0,1,2,3", 3142 "CounterHTOff": "0,1,2,3", 3143 "EventCode": "0xB7, 0xBB", 3144 "EventName": "OCR.ALL_DATA_RD.ANY_RESPONSE", 3145 "MSRIndex": "0x1a6,0x1a7", 3146 "MSRValue": "0x0000010491", 3147 "Offcore": "1", 3148 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3149 "SampleAfterValue": "100003", 3150 "UMask": "0x1" 3151 }, 3152 { 3153 "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs PF_L3_RFO & L3_HIT_E & HITM_OTHER_CORE", 3154 "Counter": "0,1,2,3", 3155 "CounterHTOff": "0,1,2,3", 3156 "EventCode": "0xB7, 0xBB", 3157 "EventName": "OCR.PF_L3_RFO.L3_HIT_E.HITM_OTHER_CORE", 3158 "MSRIndex": "0x1a6,0x1a7", 3159 "MSRValue": "0x1000080100", 3160 "Offcore": "1", 3161 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3162 "SampleAfterValue": "100003", 3163 "UMask": "0x1" 3164 }, 3165 { 3166 "BriefDescription": "ALL_RFO & L3_HIT_S & SNOOP_NONE", 3167 "Counter": "0,1,2,3", 3168 "CounterHTOff": "0,1,2,3", 3169 "EventCode": "0xB7, 0xBB", 3170 "EventName": "OCR.ALL_RFO.L3_HIT_S.SNOOP_NONE", 3171 "MSRIndex": "0x1a6,0x1a7", 3172 "MSRValue": "0x0080100122", 3173 "Offcore": "1", 3174 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3175 "SampleAfterValue": "100003", 3176 "UMask": "0x1" 3177 }, 3178 { 3179 "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs", 3180 "Counter": "0,1,2,3", 3181 "CounterHTOff": "0,1,2,3", 3182 "EventCode": "0xB7, 0xBB", 3183 "EventName": "OCR.PF_L2_RFO.L3_HIT_E.SNOOP_NONE", 3184 "MSRIndex": "0x1a6,0x1a7", 3185 "MSRValue": "0x0080080020", 3186 "Offcore": "1", 3187 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3188 "SampleAfterValue": "100003", 3189 "UMask": "0x1" 3190 }, 3191 { 3192 "BriefDescription": "Counts all demand code reads DEMAND_CODE_RD & L3_HIT_F & HIT_OTHER_CORE_FWD", 3193 "Counter": "0,1,2,3", 3194 "CounterHTOff": "0,1,2,3", 3195 "EventCode": "0xB7, 0xBB", 3196 "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_F.HIT_OTHER_CORE_FWD", 3197 "MSRIndex": "0x1a6,0x1a7", 3198 "MSRValue": "0x0800200004", 3199 "Offcore": "1", 3200 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3201 "SampleAfterValue": "100003", 3202 "UMask": "0x1" 3203 }, 3204 { 3205 "BriefDescription": "ALL_PF_RFO & PMM_HIT_LOCAL_PMM & SNOOP_NONE", 3206 "Counter": "0,1,2,3", 3207 "CounterHTOff": "0,1,2,3", 3208 "EventCode": "0xB7, 0xBB", 3209 "EventName": "OCR.ALL_PF_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NONE", 3210 "MSRIndex": "0x1a6,0x1a7", 3211 "MSRValue": "0x0080400120", 3212 "Offcore": "1", 3213 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3214 "SampleAfterValue": "100003", 3215 "UMask": "0x1" 3216 }, 3217 { 3218 "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads PF_L3_DATA_RD & SUPPLIER_NONE & HIT_OTHER_CORE_NO_FWD", 3219 "Counter": "0,1,2,3", 3220 "CounterHTOff": "0,1,2,3", 3221 "EventCode": "0xB7, 0xBB", 3222 "EventName": "OCR.PF_L3_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", 3223 "MSRIndex": "0x1a6,0x1a7", 3224 "MSRValue": "0x0400020080", 3225 "Offcore": "1", 3226 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3227 "SampleAfterValue": "100003", 3228 "UMask": "0x1" 3229 }, 3230 { 3231 "BriefDescription": "Counts all demand data writes (RFOs)", 3232 "Counter": "0,1,2,3", 3233 "CounterHTOff": "0,1,2,3", 3234 "EventCode": "0xB7, 0xBB", 3235 "EventName": "OCR.DEMAND_RFO.L3_HIT_M.SNOOP_NONE", 3236 "MSRIndex": "0x1a6,0x1a7", 3237 "MSRValue": "0x0080040002", 3238 "Offcore": "1", 3239 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3240 "SampleAfterValue": "100003", 3241 "UMask": "0x1" 3242 }, 3243 { 3244 "BriefDescription": "ALL_PF_RFO & L3_HIT_F & SNOOP_NONE", 3245 "Counter": "0,1,2,3", 3246 "CounterHTOff": "0,1,2,3", 3247 "EventCode": "0xB7, 0xBB", 3248 "EventName": "OCR.ALL_PF_RFO.L3_HIT_F.SNOOP_NONE", 3249 "MSRIndex": "0x1a6,0x1a7", 3250 "MSRValue": "0x0080200120", 3251 "Offcore": "1", 3252 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3253 "SampleAfterValue": "100003", 3254 "UMask": "0x1" 3255 }, 3256 { 3257 "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs PF_L3_RFO & L3_HIT_F & NO_SNOOP_NEEDED", 3258 "Counter": "0,1,2,3", 3259 "CounterHTOff": "0,1,2,3", 3260 "EventCode": "0xB7, 0xBB", 3261 "EventName": "OCR.PF_L3_RFO.L3_HIT_F.NO_SNOOP_NEEDED", 3262 "MSRIndex": "0x1a6,0x1a7", 3263 "MSRValue": "0x0100200100", 3264 "Offcore": "1", 3265 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3266 "SampleAfterValue": "100003", 3267 "UMask": "0x1" 3268 }, 3269 { 3270 "BriefDescription": "ALL_PF_RFO & L3_HIT_E & ANY_SNOOP", 3271 "Counter": "0,1,2,3", 3272 "CounterHTOff": "0,1,2,3", 3273 "EventCode": "0xB7, 0xBB", 3274 "EventName": "OCR.ALL_PF_RFO.L3_HIT_E.ANY_SNOOP", 3275 "MSRIndex": "0x1a6,0x1a7", 3276 "MSRValue": "0x3F80080120", 3277 "Offcore": "1", 3278 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3279 "SampleAfterValue": "100003", 3280 "UMask": "0x1" 3281 }, 3282 { 3283 "BriefDescription": "Counts any other requests OTHER & L3_HIT & HIT_OTHER_CORE_FWD", 3284 "Counter": "0,1,2,3", 3285 "CounterHTOff": "0,1,2,3", 3286 "EventCode": "0xB7, 0xBB", 3287 "EventName": "OCR.OTHER.L3_HIT.HIT_OTHER_CORE_FWD", 3288 "MSRIndex": "0x1a6,0x1a7", 3289 "MSRValue": "0x08003C8000", 3290 "Offcore": "1", 3291 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3292 "SampleAfterValue": "100003", 3293 "UMask": "0x1" 3294 }, 3295 { 3296 "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs", 3297 "Counter": "0,1,2,3", 3298 "CounterHTOff": "0,1,2,3", 3299 "EventCode": "0xB7, 0xBB", 3300 "EventName": "OCR.PF_L3_RFO.L3_HIT_M.SNOOP_NONE", 3301 "MSRIndex": "0x1a6,0x1a7", 3302 "MSRValue": "0x0080040100", 3303 "Offcore": "1", 3304 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3305 "SampleAfterValue": "100003", 3306 "UMask": "0x1" 3307 }, 3308 { 3309 "BriefDescription": "ALL_PF_DATA_RD & L3_HIT_M & HIT_OTHER_CORE_FWD", 3310 "Counter": "0,1,2,3", 3311 "CounterHTOff": "0,1,2,3", 3312 "EventCode": "0xB7, 0xBB", 3313 "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWD", 3314 "MSRIndex": "0x1a6,0x1a7", 3315 "MSRValue": "0x0800040490", 3316 "Offcore": "1", 3317 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3318 "SampleAfterValue": "100003", 3319 "UMask": "0x1" 3320 }, 3321 { 3322 "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs PF_L3_RFO & SUPPLIER_NONE & HIT_OTHER_CORE_FWD", 3323 "Counter": "0,1,2,3", 3324 "CounterHTOff": "0,1,2,3", 3325 "EventCode": "0xB7, 0xBB", 3326 "EventName": "OCR.PF_L3_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", 3327 "MSRIndex": "0x1a6,0x1a7", 3328 "MSRValue": "0x0800020100", 3329 "Offcore": "1", 3330 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3331 "SampleAfterValue": "100003", 3332 "UMask": "0x1" 3333 }, 3334 { 3335 "BriefDescription": "ALL_PF_DATA_RD & L3_HIT_E & HITM_OTHER_CORE", 3336 "Counter": "0,1,2,3", 3337 "CounterHTOff": "0,1,2,3", 3338 "EventCode": "0xB7, 0xBB", 3339 "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_E.HITM_OTHER_CORE", 3340 "MSRIndex": "0x1a6,0x1a7", 3341 "MSRValue": "0x1000080490", 3342 "Offcore": "1", 3343 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3344 "SampleAfterValue": "100003", 3345 "UMask": "0x1" 3346 }, 3347 { 3348 "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs PF_L2_RFO & L3_HIT_F & HITM_OTHER_CORE", 3349 "Counter": "0,1,2,3", 3350 "CounterHTOff": "0,1,2,3", 3351 "EventCode": "0xB7, 0xBB", 3352 "EventName": "OCR.PF_L2_RFO.L3_HIT_F.HITM_OTHER_CORE", 3353 "MSRIndex": "0x1a6,0x1a7", 3354 "MSRValue": "0x1000200020", 3355 "Offcore": "1", 3356 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3357 "SampleAfterValue": "100003", 3358 "UMask": "0x1" 3359 }, 3360 { 3361 "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests PF_L1D_AND_SW & SUPPLIER_NONE & NO_SNOOP_NEEDED", 3362 "Counter": "0,1,2,3", 3363 "CounterHTOff": "0,1,2,3", 3364 "EventCode": "0xB7, 0xBB", 3365 "EventName": "OCR.PF_L1D_AND_SW.SUPPLIER_NONE.NO_SNOOP_NEEDED", 3366 "MSRIndex": "0x1a6,0x1a7", 3367 "MSRValue": "0x0100020400", 3368 "Offcore": "1", 3369 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3370 "SampleAfterValue": "100003", 3371 "UMask": "0x1" 3372 }, 3373 { 3374 "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs PF_L3_RFO & L3_HIT_M & HIT_OTHER_CORE_NO_FWD", 3375 "Counter": "0,1,2,3", 3376 "CounterHTOff": "0,1,2,3", 3377 "EventCode": "0xB7, 0xBB", 3378 "EventName": "OCR.PF_L3_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", 3379 "MSRIndex": "0x1a6,0x1a7", 3380 "MSRValue": "0x0400040100", 3381 "Offcore": "1", 3382 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3383 "SampleAfterValue": "100003", 3384 "UMask": "0x1" 3385 }, 3386 { 3387 "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs PF_L3_RFO & L3_HIT_F & HITM_OTHER_CORE", 3388 "Counter": "0,1,2,3", 3389 "CounterHTOff": "0,1,2,3", 3390 "EventCode": "0xB7, 0xBB", 3391 "EventName": "OCR.PF_L3_RFO.L3_HIT_F.HITM_OTHER_CORE", 3392 "MSRIndex": "0x1a6,0x1a7", 3393 "MSRValue": "0x1000200100", 3394 "Offcore": "1", 3395 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3396 "SampleAfterValue": "100003", 3397 "UMask": "0x1" 3398 }, 3399 { 3400 "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs PF_L3_RFO & SUPPLIER_NONE & NO_SNOOP_NEEDED", 3401 "Counter": "0,1,2,3", 3402 "CounterHTOff": "0,1,2,3", 3403 "EventCode": "0xB7, 0xBB", 3404 "EventName": "OCR.PF_L3_RFO.SUPPLIER_NONE.NO_SNOOP_NEEDED", 3405 "MSRIndex": "0x1a6,0x1a7", 3406 "MSRValue": "0x0100020100", 3407 "Offcore": "1", 3408 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3409 "SampleAfterValue": "100003", 3410 "UMask": "0x1" 3411 }, 3412 { 3413 "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs", 3414 "Counter": "0,1,2,3", 3415 "CounterHTOff": "0,1,2,3", 3416 "EventCode": "0xB7, 0xBB", 3417 "EventName": "OCR.PF_L3_RFO.L3_HIT_S.SNOOP_NONE", 3418 "MSRIndex": "0x1a6,0x1a7", 3419 "MSRValue": "0x0080100100", 3420 "Offcore": "1", 3421 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3422 "SampleAfterValue": "100003", 3423 "UMask": "0x1" 3424 }, 3425 { 3426 "BriefDescription": "ALL_DATA_RD & L3_HIT & NO_SNOOP_NEEDED", 3427 "Counter": "0,1,2,3", 3428 "CounterHTOff": "0,1,2,3", 3429 "EventCode": "0xB7, 0xBB", 3430 "EventName": "OCR.ALL_DATA_RD.L3_HIT.NO_SNOOP_NEEDED", 3431 "MSRIndex": "0x1a6,0x1a7", 3432 "MSRValue": "0x01003C0491", 3433 "Offcore": "1", 3434 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3435 "SampleAfterValue": "100003", 3436 "UMask": "0x1" 3437 }, 3438 { 3439 "BriefDescription": "ALL_READS & L3_HIT & HIT_OTHER_CORE_FWD", 3440 "Counter": "0,1,2,3", 3441 "CounterHTOff": "0,1,2,3", 3442 "EventCode": "0xB7, 0xBB", 3443 "EventName": "OCR.ALL_READS.L3_HIT.HIT_OTHER_CORE_FWD", 3444 "MSRIndex": "0x1a6,0x1a7", 3445 "MSRValue": "0x08003C07F7", 3446 "Offcore": "1", 3447 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3448 "SampleAfterValue": "100003", 3449 "UMask": "0x1" 3450 }, 3451 { 3452 "BriefDescription": "Counts all demand code reads DEMAND_CODE_RD & L3_HIT & SNOOP_NONE", 3453 "Counter": "0,1,2,3", 3454 "CounterHTOff": "0,1,2,3", 3455 "EventCode": "0xB7, 0xBB", 3456 "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_NONE", 3457 "MSRIndex": "0x1a6,0x1a7", 3458 "MSRValue": "0x00803C0004", 3459 "Offcore": "1", 3460 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3461 "SampleAfterValue": "100003", 3462 "UMask": "0x1" 3463 }, 3464 { 3465 "BriefDescription": "ALL_DATA_RD & PMM_HIT_LOCAL_PMM & SNOOP_NONE", 3466 "Counter": "0,1,2,3", 3467 "CounterHTOff": "0,1,2,3", 3468 "EventCode": "0xB7, 0xBB", 3469 "EventName": "OCR.ALL_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE", 3470 "MSRIndex": "0x1a6,0x1a7", 3471 "MSRValue": "0x0080400491", 3472 "Offcore": "1", 3473 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3474 "SampleAfterValue": "100003", 3475 "UMask": "0x1" 3476 }, 3477 { 3478 "BriefDescription": "ALL_DATA_RD & SUPPLIER_NONE & SNOOP_NONE", 3479 "Counter": "0,1,2,3", 3480 "CounterHTOff": "0,1,2,3", 3481 "EventCode": "0xB7, 0xBB", 3482 "EventName": "OCR.ALL_DATA_RD.SUPPLIER_NONE.SNOOP_NONE", 3483 "MSRIndex": "0x1a6,0x1a7", 3484 "MSRValue": "0x0080020491", 3485 "Offcore": "1", 3486 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3487 "SampleAfterValue": "100003", 3488 "UMask": "0x1" 3489 }, 3490 { 3491 "BriefDescription": "Counts all demand data writes (RFOs) DEMAND_RFO & PMM_HIT_LOCAL_PMM & SNOOP_NOT_NEEDED", 3492 "Counter": "0,1,2,3", 3493 "CounterHTOff": "0,1,2,3", 3494 "EventCode": "0xB7, 0xBB", 3495 "EventName": "OCR.DEMAND_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", 3496 "MSRIndex": "0x1a6,0x1a7", 3497 "MSRValue": "0x0100400002", 3498 "Offcore": "1", 3499 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3500 "SampleAfterValue": "100003", 3501 "UMask": "0x1" 3502 }, 3503 { 3504 "BriefDescription": "ALL_PF_DATA_RD & L3_HIT & HIT_OTHER_CORE_FWD", 3505 "Counter": "0,1,2,3", 3506 "CounterHTOff": "0,1,2,3", 3507 "EventCode": "0xB7, 0xBB", 3508 "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD", 3509 "MSRIndex": "0x1a6,0x1a7", 3510 "MSRValue": "0x08003C0490", 3511 "Offcore": "1", 3512 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3513 "SampleAfterValue": "100003", 3514 "UMask": "0x1" 3515 }, 3516 { 3517 "BriefDescription": "ALL_DATA_RD & L3_HIT & HITM_OTHER_CORE", 3518 "Counter": "0,1,2,3", 3519 "CounterHTOff": "0,1,2,3", 3520 "EventCode": "0xB7, 0xBB", 3521 "EventName": "OCR.ALL_DATA_RD.L3_HIT.HITM_OTHER_CORE", 3522 "MSRIndex": "0x1a6,0x1a7", 3523 "MSRValue": "0x10003C0491", 3524 "Offcore": "1", 3525 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3526 "SampleAfterValue": "100003", 3527 "UMask": "0x1" 3528 }, 3529 { 3530 "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests PF_L1D_AND_SW & L3_HIT_M & HIT_OTHER_CORE_FWD", 3531 "Counter": "0,1,2,3", 3532 "CounterHTOff": "0,1,2,3", 3533 "EventCode": "0xB7, 0xBB", 3534 "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_M.HIT_OTHER_CORE_FWD", 3535 "MSRIndex": "0x1a6,0x1a7", 3536 "MSRValue": "0x0800040400", 3537 "Offcore": "1", 3538 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3539 "SampleAfterValue": "100003", 3540 "UMask": "0x1" 3541 }, 3542 { 3543 "BriefDescription": "Counts demand data reads DEMAND_DATA_RD & L3_HIT_M & ANY_SNOOP", 3544 "Counter": "0,1,2,3", 3545 "CounterHTOff": "0,1,2,3", 3546 "EventCode": "0xB7, 0xBB", 3547 "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_M.ANY_SNOOP", 3548 "MSRIndex": "0x1a6,0x1a7", 3549 "MSRValue": "0x3F80040001", 3550 "Offcore": "1", 3551 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3552 "SampleAfterValue": "100003", 3553 "UMask": "0x1" 3554 }, 3555 { 3556 "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests PF_L1D_AND_SW & L3_HIT_F & HIT_OTHER_CORE_FWD", 3557 "Counter": "0,1,2,3", 3558 "CounterHTOff": "0,1,2,3", 3559 "EventCode": "0xB7, 0xBB", 3560 "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_F.HIT_OTHER_CORE_FWD", 3561 "MSRIndex": "0x1a6,0x1a7", 3562 "MSRValue": "0x0800200400", 3563 "Offcore": "1", 3564 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3565 "SampleAfterValue": "100003", 3566 "UMask": "0x1" 3567 }, 3568 { 3569 "BriefDescription": "ALL_DATA_RD & L3_HIT & HIT_OTHER_CORE_NO_FWD", 3570 "Counter": "0,1,2,3", 3571 "CounterHTOff": "0,1,2,3", 3572 "EventCode": "0xB7, 0xBB", 3573 "EventName": "OCR.ALL_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD", 3574 "MSRIndex": "0x1a6,0x1a7", 3575 "MSRValue": "0x04003C0491", 3576 "Offcore": "1", 3577 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3578 "SampleAfterValue": "100003", 3579 "UMask": "0x1" 3580 }, 3581 { 3582 "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs PF_L3_RFO & L3_HIT & SNOOP_MISS", 3583 "Counter": "0,1,2,3", 3584 "CounterHTOff": "0,1,2,3", 3585 "EventCode": "0xB7, 0xBB", 3586 "EventName": "OCR.PF_L3_RFO.L3_HIT.SNOOP_MISS", 3587 "MSRIndex": "0x1a6,0x1a7", 3588 "MSRValue": "0x02003C0100", 3589 "Offcore": "1", 3590 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3591 "SampleAfterValue": "100003", 3592 "UMask": "0x1" 3593 }, 3594 { 3595 "BriefDescription": "Counts prefetch (that bring data to L2) data reads PF_L2_DATA_RD & L3_HIT_S & NO_SNOOP_NEEDED", 3596 "Counter": "0,1,2,3", 3597 "CounterHTOff": "0,1,2,3", 3598 "EventCode": "0xB7, 0xBB", 3599 "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDED", 3600 "MSRIndex": "0x1a6,0x1a7", 3601 "MSRValue": "0x0100100010", 3602 "Offcore": "1", 3603 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3604 "SampleAfterValue": "100003", 3605 "UMask": "0x1" 3606 }, 3607 { 3608 "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs PF_L3_RFO & L3_HIT_S & HITM_OTHER_CORE", 3609 "Counter": "0,1,2,3", 3610 "CounterHTOff": "0,1,2,3", 3611 "EventCode": "0xB7, 0xBB", 3612 "EventName": "OCR.PF_L3_RFO.L3_HIT_S.HITM_OTHER_CORE", 3613 "MSRIndex": "0x1a6,0x1a7", 3614 "MSRValue": "0x1000100100", 3615 "Offcore": "1", 3616 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3617 "SampleAfterValue": "100003", 3618 "UMask": "0x1" 3619 }, 3620 { 3621 "BriefDescription": "ALL_DATA_RD & L3_HIT_E & ANY_SNOOP", 3622 "Counter": "0,1,2,3", 3623 "CounterHTOff": "0,1,2,3", 3624 "EventCode": "0xB7, 0xBB", 3625 "EventName": "OCR.ALL_DATA_RD.L3_HIT_E.ANY_SNOOP", 3626 "MSRIndex": "0x1a6,0x1a7", 3627 "MSRValue": "0x3F80080491", 3628 "Offcore": "1", 3629 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3630 "SampleAfterValue": "100003", 3631 "UMask": "0x1" 3632 }, 3633 { 3634 "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs PF_L3_RFO & PMM_HIT_LOCAL_PMM & ANY_SNOOP", 3635 "Counter": "0,1,2,3", 3636 "CounterHTOff": "0,1,2,3", 3637 "EventCode": "0xB7, 0xBB", 3638 "EventName": "OCR.PF_L3_RFO.PMM_HIT_LOCAL_PMM.ANY_SNOOP", 3639 "MSRIndex": "0x1a6,0x1a7", 3640 "MSRValue": "0x3F80400100", 3641 "Offcore": "1", 3642 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3643 "SampleAfterValue": "100003", 3644 "UMask": "0x1" 3645 }, 3646 { 3647 "BriefDescription": "ALL_READS & L3_HIT_F & HITM_OTHER_CORE", 3648 "Counter": "0,1,2,3", 3649 "CounterHTOff": "0,1,2,3", 3650 "EventCode": "0xB7, 0xBB", 3651 "EventName": "OCR.ALL_READS.L3_HIT_F.HITM_OTHER_CORE", 3652 "MSRIndex": "0x1a6,0x1a7", 3653 "MSRValue": "0x10002007F7", 3654 "Offcore": "1", 3655 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3656 "SampleAfterValue": "100003", 3657 "UMask": "0x1" 3658 }, 3659 { 3660 "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests PF_L1D_AND_SW & L3_HIT & HIT_OTHER_CORE_NO_FWD", 3661 "Counter": "0,1,2,3", 3662 "CounterHTOff": "0,1,2,3", 3663 "EventCode": "0xB7, 0xBB", 3664 "EventName": "OCR.PF_L1D_AND_SW.L3_HIT.HIT_OTHER_CORE_NO_FWD", 3665 "MSRIndex": "0x1a6,0x1a7", 3666 "MSRValue": "0x04003C0400", 3667 "Offcore": "1", 3668 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3669 "SampleAfterValue": "100003", 3670 "UMask": "0x1" 3671 }, 3672 { 3673 "BriefDescription": "ALL_PF_RFO & L3_HIT & HITM_OTHER_CORE", 3674 "Counter": "0,1,2,3", 3675 "CounterHTOff": "0,1,2,3", 3676 "EventCode": "0xB7, 0xBB", 3677 "EventName": "OCR.ALL_PF_RFO.L3_HIT.HITM_OTHER_CORE", 3678 "MSRIndex": "0x1a6,0x1a7", 3679 "MSRValue": "0x10003C0120", 3680 "Offcore": "1", 3681 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3682 "SampleAfterValue": "100003", 3683 "UMask": "0x1" 3684 }, 3685 { 3686 "BriefDescription": "Counts any other requests", 3687 "Counter": "0,1,2,3", 3688 "CounterHTOff": "0,1,2,3", 3689 "EventCode": "0xB7, 0xBB", 3690 "EventName": "OCR.OTHER.L3_HIT_S.SNOOP_MISS", 3691 "MSRIndex": "0x1a6,0x1a7", 3692 "MSRValue": "0x0200108000", 3693 "Offcore": "1", 3694 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3695 "SampleAfterValue": "100003", 3696 "UMask": "0x1" 3697 }, 3698 { 3699 "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs PF_L3_RFO & L3_HIT & HIT_OTHER_CORE_FWD", 3700 "Counter": "0,1,2,3", 3701 "CounterHTOff": "0,1,2,3", 3702 "EventCode": "0xB7, 0xBB", 3703 "EventName": "OCR.PF_L3_RFO.L3_HIT.HIT_OTHER_CORE_FWD", 3704 "MSRIndex": "0x1a6,0x1a7", 3705 "MSRValue": "0x08003C0100", 3706 "Offcore": "1", 3707 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3708 "SampleAfterValue": "100003", 3709 "UMask": "0x1" 3710 }, 3711 { 3712 "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests PF_L1D_AND_SW & SUPPLIER_NONE & ANY_SNOOP", 3713 "Counter": "0,1,2,3", 3714 "CounterHTOff": "0,1,2,3", 3715 "EventCode": "0xB7, 0xBB", 3716 "EventName": "OCR.PF_L1D_AND_SW.SUPPLIER_NONE.ANY_SNOOP", 3717 "MSRIndex": "0x1a6,0x1a7", 3718 "MSRValue": "0x3F80020400", 3719 "Offcore": "1", 3720 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3721 "SampleAfterValue": "100003", 3722 "UMask": "0x1" 3723 }, 3724 { 3725 "BriefDescription": "Counts prefetch (that bring data to L2) data reads have any response type.", 3726 "Counter": "0,1,2,3", 3727 "CounterHTOff": "0,1,2,3", 3728 "EventCode": "0xB7, 0xBB", 3729 "EventName": "OCR.PF_L2_DATA_RD.ANY_RESPONSE", 3730 "MSRIndex": "0x1a6,0x1a7", 3731 "MSRValue": "0x0000010010", 3732 "Offcore": "1", 3733 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3734 "SampleAfterValue": "100003", 3735 "UMask": "0x1" 3736 }, 3737 { 3738 "BriefDescription": "Counts all demand data writes (RFOs) DEMAND_RFO & L3_HIT_S & HIT_OTHER_CORE_NO_FWD", 3739 "Counter": "0,1,2,3", 3740 "CounterHTOff": "0,1,2,3", 3741 "EventCode": "0xB7, 0xBB", 3742 "EventName": "OCR.DEMAND_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", 3743 "MSRIndex": "0x1a6,0x1a7", 3744 "MSRValue": "0x0400100002", 3745 "Offcore": "1", 3746 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3747 "SampleAfterValue": "100003", 3748 "UMask": "0x1" 3749 }, 3750 { 3751 "BriefDescription": "ALL_DATA_RD & L3_HIT_M & HITM_OTHER_CORE", 3752 "Counter": "0,1,2,3", 3753 "CounterHTOff": "0,1,2,3", 3754 "EventCode": "0xB7, 0xBB", 3755 "EventName": "OCR.ALL_DATA_RD.L3_HIT_M.HITM_OTHER_CORE", 3756 "MSRIndex": "0x1a6,0x1a7", 3757 "MSRValue": "0x1000040491", 3758 "Offcore": "1", 3759 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3760 "SampleAfterValue": "100003", 3761 "UMask": "0x1" 3762 }, 3763 { 3764 "BriefDescription": "Counts number of cache lines that are allocated and written back to L3 with the intention that they are more likely to be reused shortly", 3765 "Counter": "0,1,2,3", 3766 "CounterHTOff": "0,1,2,3,4,5,6,7", 3767 "EventCode": "0xFE", 3768 "EventName": "IDI_MISC.WB_UPGRADE", 3769 "PublicDescription": "Counts number of cache lines that are allocated and written back to L3 with the intention that they are more likely to be reused shortly.", 3770 "SampleAfterValue": "100003", 3771 "UMask": "0x2" 3772 }, 3773 { 3774 "BriefDescription": "Counts prefetch (that bring data to L2) data reads PF_L2_DATA_RD & L3_HIT_F & HIT_OTHER_CORE_FWD", 3775 "Counter": "0,1,2,3", 3776 "CounterHTOff": "0,1,2,3", 3777 "EventCode": "0xB7, 0xBB", 3778 "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWD", 3779 "MSRIndex": "0x1a6,0x1a7", 3780 "MSRValue": "0x0800200010", 3781 "Offcore": "1", 3782 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3783 "SampleAfterValue": "100003", 3784 "UMask": "0x1" 3785 }, 3786 { 3787 "BriefDescription": "Counts all demand code reads", 3788 "Counter": "0,1,2,3", 3789 "CounterHTOff": "0,1,2,3", 3790 "EventCode": "0xB7, 0xBB", 3791 "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_HIT_WITH_FWD", 3792 "MSRIndex": "0x1a6,0x1a7", 3793 "MSRValue": "0x08007C0004", 3794 "Offcore": "1", 3795 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3796 "SampleAfterValue": "100003", 3797 "UMask": "0x1" 3798 }, 3799 { 3800 "BriefDescription": "Counts any other requests OTHER & L3_HIT_M & NO_SNOOP_NEEDED", 3801 "Counter": "0,1,2,3", 3802 "CounterHTOff": "0,1,2,3", 3803 "EventCode": "0xB7, 0xBB", 3804 "EventName": "OCR.OTHER.L3_HIT_M.NO_SNOOP_NEEDED", 3805 "MSRIndex": "0x1a6,0x1a7", 3806 "MSRValue": "0x0100048000", 3807 "Offcore": "1", 3808 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3809 "SampleAfterValue": "100003", 3810 "UMask": "0x1" 3811 }, 3812 { 3813 "BriefDescription": "ALL_PF_DATA_RD & L3_HIT & SNOOP_HIT_WITH_FWD", 3814 "Counter": "0,1,2,3", 3815 "CounterHTOff": "0,1,2,3", 3816 "EventCode": "0xB7, 0xBB", 3817 "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD", 3818 "MSRIndex": "0x1a6,0x1a7", 3819 "MSRValue": "0x08007C0490", 3820 "Offcore": "1", 3821 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3822 "SampleAfterValue": "100003", 3823 "UMask": "0x1" 3824 }, 3825 { 3826 "BriefDescription": "ALL_PF_DATA_RD & L3_HIT_M & NO_SNOOP_NEEDED", 3827 "Counter": "0,1,2,3", 3828 "CounterHTOff": "0,1,2,3", 3829 "EventCode": "0xB7, 0xBB", 3830 "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDED", 3831 "MSRIndex": "0x1a6,0x1a7", 3832 "MSRValue": "0x0100040490", 3833 "Offcore": "1", 3834 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3835 "SampleAfterValue": "100003", 3836 "UMask": "0x1" 3837 }, 3838 { 3839 "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests PF_L1D_AND_SW & L3_HIT_F & ANY_SNOOP", 3840 "Counter": "0,1,2,3", 3841 "CounterHTOff": "0,1,2,3", 3842 "EventCode": "0xB7, 0xBB", 3843 "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_F.ANY_SNOOP", 3844 "MSRIndex": "0x1a6,0x1a7", 3845 "MSRValue": "0x3F80200400", 3846 "Offcore": "1", 3847 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3848 "SampleAfterValue": "100003", 3849 "UMask": "0x1" 3850 }, 3851 { 3852 "BriefDescription": "ALL_DATA_RD & L3_HIT_F & SNOOP_NONE", 3853 "Counter": "0,1,2,3", 3854 "CounterHTOff": "0,1,2,3", 3855 "EventCode": "0xB7, 0xBB", 3856 "EventName": "OCR.ALL_DATA_RD.L3_HIT_F.SNOOP_NONE", 3857 "MSRIndex": "0x1a6,0x1a7", 3858 "MSRValue": "0x0080200491", 3859 "Offcore": "1", 3860 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3861 "SampleAfterValue": "100003", 3862 "UMask": "0x1" 3863 }, 3864 { 3865 "BriefDescription": "Counts prefetch (that bring data to L2) data reads", 3866 "Counter": "0,1,2,3", 3867 "CounterHTOff": "0,1,2,3", 3868 "EventCode": "0xB7, 0xBB", 3869 "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_S.SNOOP_MISS", 3870 "MSRIndex": "0x1a6,0x1a7", 3871 "MSRValue": "0x0200100010", 3872 "Offcore": "1", 3873 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3874 "SampleAfterValue": "100003", 3875 "UMask": "0x1" 3876 }, 3877 { 3878 "BriefDescription": "ALL_PF_RFO & L3_HIT_F & NO_SNOOP_NEEDED", 3879 "Counter": "0,1,2,3", 3880 "CounterHTOff": "0,1,2,3", 3881 "EventCode": "0xB7, 0xBB", 3882 "EventName": "OCR.ALL_PF_RFO.L3_HIT_F.NO_SNOOP_NEEDED", 3883 "MSRIndex": "0x1a6,0x1a7", 3884 "MSRValue": "0x0100200120", 3885 "Offcore": "1", 3886 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3887 "SampleAfterValue": "100003", 3888 "UMask": "0x1" 3889 }, 3890 { 3891 "BriefDescription": "Counts all demand code reads DEMAND_CODE_RD & L3_HIT_S & NO_SNOOP_NEEDED", 3892 "Counter": "0,1,2,3", 3893 "CounterHTOff": "0,1,2,3", 3894 "EventCode": "0xB7, 0xBB", 3895 "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_S.NO_SNOOP_NEEDED", 3896 "MSRIndex": "0x1a6,0x1a7", 3897 "MSRValue": "0x0100100004", 3898 "Offcore": "1", 3899 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3900 "SampleAfterValue": "100003", 3901 "UMask": "0x1" 3902 }, 3903 { 3904 "BriefDescription": "Counts prefetch (that bring data to L2) data reads", 3905 "Counter": "0,1,2,3", 3906 "CounterHTOff": "0,1,2,3", 3907 "EventCode": "0xB7, 0xBB", 3908 "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_M.SNOOP_NONE", 3909 "MSRIndex": "0x1a6,0x1a7", 3910 "MSRValue": "0x0080040010", 3911 "Offcore": "1", 3912 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3913 "SampleAfterValue": "100003", 3914 "UMask": "0x1" 3915 }, 3916 { 3917 "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs PF_L2_RFO & L3_HIT & HIT_OTHER_CORE_NO_FWD", 3918 "Counter": "0,1,2,3", 3919 "CounterHTOff": "0,1,2,3", 3920 "EventCode": "0xB7, 0xBB", 3921 "EventName": "OCR.PF_L2_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD", 3922 "MSRIndex": "0x1a6,0x1a7", 3923 "MSRValue": "0x04003C0020", 3924 "Offcore": "1", 3925 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3926 "SampleAfterValue": "100003", 3927 "UMask": "0x1" 3928 }, 3929 { 3930 "BriefDescription": "Counts prefetch (that bring data to L2) data reads PF_L2_DATA_RD & L3_HIT & SNOOP_MISS", 3931 "Counter": "0,1,2,3", 3932 "CounterHTOff": "0,1,2,3", 3933 "EventCode": "0xB7, 0xBB", 3934 "EventName": "OCR.PF_L2_DATA_RD.L3_HIT.SNOOP_MISS", 3935 "MSRIndex": "0x1a6,0x1a7", 3936 "MSRValue": "0x02003C0010", 3937 "Offcore": "1", 3938 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3939 "SampleAfterValue": "100003", 3940 "UMask": "0x1" 3941 }, 3942 { 3943 "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests PF_L1D_AND_SW & PMM_HIT_LOCAL_PMM & SNOOP_NOT_NEEDED", 3944 "Counter": "0,1,2,3", 3945 "CounterHTOff": "0,1,2,3", 3946 "EventCode": "0xB7, 0xBB", 3947 "EventName": "OCR.PF_L1D_AND_SW.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", 3948 "MSRIndex": "0x1a6,0x1a7", 3949 "MSRValue": "0x0100400400", 3950 "Offcore": "1", 3951 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3952 "SampleAfterValue": "100003", 3953 "UMask": "0x1" 3954 }, 3955 { 3956 "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs PF_L2_RFO & PMM_HIT_LOCAL_PMM & ANY_SNOOP", 3957 "Counter": "0,1,2,3", 3958 "CounterHTOff": "0,1,2,3", 3959 "EventCode": "0xB7, 0xBB", 3960 "EventName": "OCR.PF_L2_RFO.PMM_HIT_LOCAL_PMM.ANY_SNOOP", 3961 "MSRIndex": "0x1a6,0x1a7", 3962 "MSRValue": "0x3F80400020", 3963 "Offcore": "1", 3964 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3965 "SampleAfterValue": "100003", 3966 "UMask": "0x1" 3967 }, 3968 { 3969 "BriefDescription": "ALL_READS & L3_HIT & HITM_OTHER_CORE", 3970 "Counter": "0,1,2,3", 3971 "CounterHTOff": "0,1,2,3", 3972 "EventCode": "0xB7, 0xBB", 3973 "EventName": "OCR.ALL_READS.L3_HIT.HITM_OTHER_CORE", 3974 "MSRIndex": "0x1a6,0x1a7", 3975 "MSRValue": "0x10003C07F7", 3976 "Offcore": "1", 3977 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3978 "SampleAfterValue": "100003", 3979 "UMask": "0x1" 3980 }, 3981 { 3982 "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests PF_L1D_AND_SW & L3_HIT_S & NO_SNOOP_NEEDED", 3983 "Counter": "0,1,2,3", 3984 "CounterHTOff": "0,1,2,3", 3985 "EventCode": "0xB7, 0xBB", 3986 "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_S.NO_SNOOP_NEEDED", 3987 "MSRIndex": "0x1a6,0x1a7", 3988 "MSRValue": "0x0100100400", 3989 "Offcore": "1", 3990 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3991 "SampleAfterValue": "100003", 3992 "UMask": "0x1" 3993 }, 3994 { 3995 "BriefDescription": "Counts all demand code reads DEMAND_CODE_RD & L3_HIT_M & NO_SNOOP_NEEDED", 3996 "Counter": "0,1,2,3", 3997 "CounterHTOff": "0,1,2,3", 3998 "EventCode": "0xB7, 0xBB", 3999 "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_M.NO_SNOOP_NEEDED", 4000 "MSRIndex": "0x1a6,0x1a7", 4001 "MSRValue": "0x0100040004", 4002 "Offcore": "1", 4003 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4004 "SampleAfterValue": "100003", 4005 "UMask": "0x1" 4006 }, 4007 { 4008 "BriefDescription": "ALL_READS & L3_HIT & HIT_OTHER_CORE_NO_FWD", 4009 "Counter": "0,1,2,3", 4010 "CounterHTOff": "0,1,2,3", 4011 "EventCode": "0xB7, 0xBB", 4012 "EventName": "OCR.ALL_READS.L3_HIT.HIT_OTHER_CORE_NO_FWD", 4013 "MSRIndex": "0x1a6,0x1a7", 4014 "MSRValue": "0x04003C07F7", 4015 "Offcore": "1", 4016 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4017 "SampleAfterValue": "100003", 4018 "UMask": "0x1" 4019 }, 4020 { 4021 "BriefDescription": "ALL_PF_DATA_RD & L3_HIT_F & NO_SNOOP_NEEDED", 4022 "Counter": "0,1,2,3", 4023 "CounterHTOff": "0,1,2,3", 4024 "EventCode": "0xB7, 0xBB", 4025 "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDED", 4026 "MSRIndex": "0x1a6,0x1a7", 4027 "MSRValue": "0x0100200490", 4028 "Offcore": "1", 4029 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4030 "SampleAfterValue": "100003", 4031 "UMask": "0x1" 4032 }, 4033 { 4034 "BriefDescription": "Counts any other requests OTHER & SUPPLIER_NONE & NO_SNOOP_NEEDED", 4035 "Counter": "0,1,2,3", 4036 "CounterHTOff": "0,1,2,3", 4037 "EventCode": "0xB7, 0xBB", 4038 "EventName": "OCR.OTHER.SUPPLIER_NONE.NO_SNOOP_NEEDED", 4039 "MSRIndex": "0x1a6,0x1a7", 4040 "MSRValue": "0x0100028000", 4041 "Offcore": "1", 4042 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4043 "SampleAfterValue": "100003", 4044 "UMask": "0x1" 4045 }, 4046 { 4047 "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads PF_L3_DATA_RD & L3_HIT_E & ANY_SNOOP", 4048 "Counter": "0,1,2,3", 4049 "CounterHTOff": "0,1,2,3", 4050 "EventCode": "0xB7, 0xBB", 4051 "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_E.ANY_SNOOP", 4052 "MSRIndex": "0x1a6,0x1a7", 4053 "MSRValue": "0x3F80080080", 4054 "Offcore": "1", 4055 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4056 "SampleAfterValue": "100003", 4057 "UMask": "0x1" 4058 }, 4059 { 4060 "BriefDescription": "Counts any other requests OTHER & PMM_HIT_LOCAL_PMM & SNOOP_NONE", 4061 "Counter": "0,1,2,3", 4062 "CounterHTOff": "0,1,2,3", 4063 "EventCode": "0xB7, 0xBB", 4064 "EventName": "OCR.OTHER.PMM_HIT_LOCAL_PMM.SNOOP_NONE", 4065 "MSRIndex": "0x1a6,0x1a7", 4066 "MSRValue": "0x0080408000", 4067 "Offcore": "1", 4068 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4069 "SampleAfterValue": "100003", 4070 "UMask": "0x1" 4071 }, 4072 { 4073 "BriefDescription": "ALL_READS & L3_HIT_S & HIT_OTHER_CORE_FWD", 4074 "Counter": "0,1,2,3", 4075 "CounterHTOff": "0,1,2,3", 4076 "EventCode": "0xB7, 0xBB", 4077 "EventName": "OCR.ALL_READS.L3_HIT_S.HIT_OTHER_CORE_FWD", 4078 "MSRIndex": "0x1a6,0x1a7", 4079 "MSRValue": "0x08001007F7", 4080 "Offcore": "1", 4081 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4082 "SampleAfterValue": "100003", 4083 "UMask": "0x1" 4084 }, 4085 { 4086 "BriefDescription": "Number of PREFETCHT1 or PREFETCHT2 instructions executed.", 4087 "Counter": "0,1,2,3", 4088 "CounterHTOff": "0,1,2,3,4,5,6,7", 4089 "EventCode": "0x32", 4090 "EventName": "SW_PREFETCH_ACCESS.T1_T2", 4091 "SampleAfterValue": "2000003", 4092 "UMask": "0x4" 4093 }, 4094 { 4095 "BriefDescription": "Counts prefetch (that bring data to L2) data reads PF_L2_DATA_RD & PMM_HIT_LOCAL_PMM & SNOOP_NOT_NEEDED", 4096 "Counter": "0,1,2,3", 4097 "CounterHTOff": "0,1,2,3", 4098 "EventCode": "0xB7, 0xBB", 4099 "EventName": "OCR.PF_L2_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", 4100 "MSRIndex": "0x1a6,0x1a7", 4101 "MSRValue": "0x0100400010", 4102 "Offcore": "1", 4103 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4104 "SampleAfterValue": "100003", 4105 "UMask": "0x1" 4106 }, 4107 { 4108 "BriefDescription": "Counts demand data reads", 4109 "Counter": "0,1,2,3", 4110 "CounterHTOff": "0,1,2,3", 4111 "EventCode": "0xB7, 0xBB", 4112 "EventName": "OCR.DEMAND_DATA_RD.SUPPLIER_NONE.SNOOP_NONE", 4113 "MSRIndex": "0x1a6,0x1a7", 4114 "MSRValue": "0x0080020001", 4115 "Offcore": "1", 4116 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4117 "SampleAfterValue": "100003", 4118 "UMask": "0x1" 4119 }, 4120 { 4121 "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs PF_L2_RFO & L3_HIT_M & ANY_SNOOP", 4122 "Counter": "0,1,2,3", 4123 "CounterHTOff": "0,1,2,3", 4124 "EventCode": "0xB7, 0xBB", 4125 "EventName": "OCR.PF_L2_RFO.L3_HIT_M.ANY_SNOOP", 4126 "MSRIndex": "0x1a6,0x1a7", 4127 "MSRValue": "0x3F80040020", 4128 "Offcore": "1", 4129 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4130 "SampleAfterValue": "100003", 4131 "UMask": "0x1" 4132 }, 4133 { 4134 "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs PF_L2_RFO & SUPPLIER_NONE & HITM_OTHER_CORE", 4135 "Counter": "0,1,2,3", 4136 "CounterHTOff": "0,1,2,3", 4137 "EventCode": "0xB7, 0xBB", 4138 "EventName": "OCR.PF_L2_RFO.SUPPLIER_NONE.HITM_OTHER_CORE", 4139 "MSRIndex": "0x1a6,0x1a7", 4140 "MSRValue": "0x1000020020", 4141 "Offcore": "1", 4142 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4143 "SampleAfterValue": "100003", 4144 "UMask": "0x1" 4145 }, 4146 { 4147 "BriefDescription": "ALL_DATA_RD & L3_HIT_M & HIT_OTHER_CORE_FWD", 4148 "Counter": "0,1,2,3", 4149 "CounterHTOff": "0,1,2,3", 4150 "EventCode": "0xB7, 0xBB", 4151 "EventName": "OCR.ALL_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWD", 4152 "MSRIndex": "0x1a6,0x1a7", 4153 "MSRValue": "0x0800040491", 4154 "Offcore": "1", 4155 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4156 "SampleAfterValue": "100003", 4157 "UMask": "0x1" 4158 }, 4159 { 4160 "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs PF_L2_RFO & L3_HIT_F & NO_SNOOP_NEEDED", 4161 "Counter": "0,1,2,3", 4162 "CounterHTOff": "0,1,2,3", 4163 "EventCode": "0xB7, 0xBB", 4164 "EventName": "OCR.PF_L2_RFO.L3_HIT_F.NO_SNOOP_NEEDED", 4165 "MSRIndex": "0x1a6,0x1a7", 4166 "MSRValue": "0x0100200020", 4167 "Offcore": "1", 4168 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4169 "SampleAfterValue": "100003", 4170 "UMask": "0x1" 4171 }, 4172 { 4173 "BriefDescription": "ALL_RFO & L3_HIT_F & SNOOP_MISS", 4174 "Counter": "0,1,2,3", 4175 "CounterHTOff": "0,1,2,3", 4176 "EventCode": "0xB7, 0xBB", 4177 "EventName": "OCR.ALL_RFO.L3_HIT_F.SNOOP_MISS", 4178 "MSRIndex": "0x1a6,0x1a7", 4179 "MSRValue": "0x0200200122", 4180 "Offcore": "1", 4181 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4182 "SampleAfterValue": "100003", 4183 "UMask": "0x1" 4184 }, 4185 { 4186 "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs", 4187 "Counter": "0,1,2,3", 4188 "CounterHTOff": "0,1,2,3", 4189 "EventCode": "0xB7, 0xBB", 4190 "EventName": "OCR.PF_L2_RFO.L3_HIT_F.SNOOP_NONE", 4191 "MSRIndex": "0x1a6,0x1a7", 4192 "MSRValue": "0x0080200020", 4193 "Offcore": "1", 4194 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4195 "SampleAfterValue": "100003", 4196 "UMask": "0x1" 4197 }, 4198 { 4199 "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests PF_L1D_AND_SW & SUPPLIER_NONE & HITM_OTHER_CORE", 4200 "Counter": "0,1,2,3", 4201 "CounterHTOff": "0,1,2,3", 4202 "EventCode": "0xB7, 0xBB", 4203 "EventName": "OCR.PF_L1D_AND_SW.SUPPLIER_NONE.HITM_OTHER_CORE", 4204 "MSRIndex": "0x1a6,0x1a7", 4205 "MSRValue": "0x1000020400", 4206 "Offcore": "1", 4207 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4208 "SampleAfterValue": "100003", 4209 "UMask": "0x1" 4210 }, 4211 { 4212 "BriefDescription": "ALL_PF_RFO & L3_HIT & HIT_OTHER_CORE_NO_FWD", 4213 "Counter": "0,1,2,3", 4214 "CounterHTOff": "0,1,2,3", 4215 "EventCode": "0xB7, 0xBB", 4216 "EventName": "OCR.ALL_PF_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD", 4217 "MSRIndex": "0x1a6,0x1a7", 4218 "MSRValue": "0x04003C0120", 4219 "Offcore": "1", 4220 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4221 "SampleAfterValue": "100003", 4222 "UMask": "0x1" 4223 }, 4224 { 4225 "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads have any response type.", 4226 "Counter": "0,1,2,3", 4227 "CounterHTOff": "0,1,2,3", 4228 "EventCode": "0xB7, 0xBB", 4229 "EventName": "OCR.PF_L3_DATA_RD.ANY_RESPONSE", 4230 "MSRIndex": "0x1a6,0x1a7", 4231 "MSRValue": "0x0000010080", 4232 "Offcore": "1", 4233 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4234 "SampleAfterValue": "100003", 4235 "UMask": "0x1" 4236 }, 4237 { 4238 "BriefDescription": "ALL_PF_DATA_RD & SUPPLIER_NONE & ANY_SNOOP", 4239 "Counter": "0,1,2,3", 4240 "CounterHTOff": "0,1,2,3", 4241 "EventCode": "0xB7, 0xBB", 4242 "EventName": "OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.ANY_SNOOP", 4243 "MSRIndex": "0x1a6,0x1a7", 4244 "MSRValue": "0x3F80020490", 4245 "Offcore": "1", 4246 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4247 "SampleAfterValue": "100003", 4248 "UMask": "0x1" 4249 }, 4250 { 4251 "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs PF_L3_RFO & L3_HIT_M & ANY_SNOOP", 4252 "Counter": "0,1,2,3", 4253 "CounterHTOff": "0,1,2,3", 4254 "EventCode": "0xB7, 0xBB", 4255 "EventName": "OCR.PF_L3_RFO.L3_HIT_M.ANY_SNOOP", 4256 "MSRIndex": "0x1a6,0x1a7", 4257 "MSRValue": "0x3F80040100", 4258 "Offcore": "1", 4259 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4260 "SampleAfterValue": "100003", 4261 "UMask": "0x1" 4262 }, 4263 { 4264 "BriefDescription": "ALL_RFO & SUPPLIER_NONE & HITM_OTHER_CORE", 4265 "Counter": "0,1,2,3", 4266 "CounterHTOff": "0,1,2,3", 4267 "EventCode": "0xB7, 0xBB", 4268 "EventName": "OCR.ALL_RFO.SUPPLIER_NONE.HITM_OTHER_CORE", 4269 "MSRIndex": "0x1a6,0x1a7", 4270 "MSRValue": "0x1000020122", 4271 "Offcore": "1", 4272 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4273 "SampleAfterValue": "100003", 4274 "UMask": "0x1" 4275 }, 4276 { 4277 "BriefDescription": "Counts prefetch (that bring data to L2) data reads PF_L2_DATA_RD & L3_HIT & HIT_OTHER_CORE_NO_FWD", 4278 "Counter": "0,1,2,3", 4279 "CounterHTOff": "0,1,2,3", 4280 "EventCode": "0xB7, 0xBB", 4281 "EventName": "OCR.PF_L2_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD", 4282 "MSRIndex": "0x1a6,0x1a7", 4283 "MSRValue": "0x04003C0010", 4284 "Offcore": "1", 4285 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4286 "SampleAfterValue": "100003", 4287 "UMask": "0x1" 4288 }, 4289 { 4290 "BriefDescription": "ALL_RFO & L3_HIT_F & ANY_SNOOP", 4291 "Counter": "0,1,2,3", 4292 "CounterHTOff": "0,1,2,3", 4293 "EventCode": "0xB7, 0xBB", 4294 "EventName": "OCR.ALL_RFO.L3_HIT_F.ANY_SNOOP", 4295 "MSRIndex": "0x1a6,0x1a7", 4296 "MSRValue": "0x3F80200122", 4297 "Offcore": "1", 4298 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4299 "SampleAfterValue": "100003", 4300 "UMask": "0x1" 4301 }, 4302 { 4303 "BriefDescription": "ALL_PF_DATA_RD & L3_HIT_S & HITM_OTHER_CORE", 4304 "Counter": "0,1,2,3", 4305 "CounterHTOff": "0,1,2,3", 4306 "EventCode": "0xB7, 0xBB", 4307 "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_S.HITM_OTHER_CORE", 4308 "MSRIndex": "0x1a6,0x1a7", 4309 "MSRValue": "0x1000100490", 4310 "Offcore": "1", 4311 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4312 "SampleAfterValue": "100003", 4313 "UMask": "0x1" 4314 }, 4315 { 4316 "BriefDescription": "ALL_RFO & L3_HIT_S & ANY_SNOOP", 4317 "Counter": "0,1,2,3", 4318 "CounterHTOff": "0,1,2,3", 4319 "EventCode": "0xB7, 0xBB", 4320 "EventName": "OCR.ALL_RFO.L3_HIT_S.ANY_SNOOP", 4321 "MSRIndex": "0x1a6,0x1a7", 4322 "MSRValue": "0x3F80100122", 4323 "Offcore": "1", 4324 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4325 "SampleAfterValue": "100003", 4326 "UMask": "0x1" 4327 }, 4328 { 4329 "BriefDescription": "Counts any other requests OTHER & PMM_HIT_LOCAL_PMM & SNOOP_NOT_NEEDED", 4330 "Counter": "0,1,2,3", 4331 "CounterHTOff": "0,1,2,3", 4332 "EventCode": "0xB7, 0xBB", 4333 "EventName": "OCR.OTHER.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", 4334 "MSRIndex": "0x1a6,0x1a7", 4335 "MSRValue": "0x0100408000", 4336 "Offcore": "1", 4337 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4338 "SampleAfterValue": "100003", 4339 "UMask": "0x1" 4340 }, 4341 { 4342 "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs PF_L2_RFO & L3_HIT & SNOOP_NONE", 4343 "Counter": "0,1,2,3", 4344 "CounterHTOff": "0,1,2,3", 4345 "EventCode": "0xB7, 0xBB", 4346 "EventName": "OCR.PF_L2_RFO.L3_HIT.SNOOP_NONE", 4347 "MSRIndex": "0x1a6,0x1a7", 4348 "MSRValue": "0x00803C0020", 4349 "Offcore": "1", 4350 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4351 "SampleAfterValue": "100003", 4352 "UMask": "0x1" 4353 }, 4354 { 4355 "BriefDescription": "Counts all demand data writes (RFOs) hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.", 4356 "Counter": "0,1,2,3", 4357 "CounterHTOff": "0,1,2,3", 4358 "EventCode": "0xB7, 0xBB", 4359 "EventName": "OCR.DEMAND_RFO.L3_HIT.NO_SNOOP_NEEDED", 4360 "MSRIndex": "0x1a6,0x1a7", 4361 "MSRValue": "0x01003C0002", 4362 "Offcore": "1", 4363 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4364 "SampleAfterValue": "100003", 4365 "UMask": "0x1" 4366 }, 4367 { 4368 "BriefDescription": "ALL_READS & L3_HIT_S & HIT_OTHER_CORE_NO_FWD", 4369 "Counter": "0,1,2,3", 4370 "CounterHTOff": "0,1,2,3", 4371 "EventCode": "0xB7, 0xBB", 4372 "EventName": "OCR.ALL_READS.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", 4373 "MSRIndex": "0x1a6,0x1a7", 4374 "MSRValue": "0x04001007F7", 4375 "Offcore": "1", 4376 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4377 "SampleAfterValue": "100003", 4378 "UMask": "0x1" 4379 }, 4380 { 4381 "BriefDescription": "Counts any other requests OTHER & L3_HIT_M & ANY_SNOOP", 4382 "Counter": "0,1,2,3", 4383 "CounterHTOff": "0,1,2,3", 4384 "EventCode": "0xB7, 0xBB", 4385 "EventName": "OCR.OTHER.L3_HIT_M.ANY_SNOOP", 4386 "MSRIndex": "0x1a6,0x1a7", 4387 "MSRValue": "0x3F80048000", 4388 "Offcore": "1", 4389 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4390 "SampleAfterValue": "100003", 4391 "UMask": "0x1" 4392 }, 4393 { 4394 "BriefDescription": "ALL_PF_DATA_RD & L3_HIT_S & ANY_SNOOP", 4395 "Counter": "0,1,2,3", 4396 "CounterHTOff": "0,1,2,3", 4397 "EventCode": "0xB7, 0xBB", 4398 "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_S.ANY_SNOOP", 4399 "MSRIndex": "0x1a6,0x1a7", 4400 "MSRValue": "0x3F80100490", 4401 "Offcore": "1", 4402 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4403 "SampleAfterValue": "100003", 4404 "UMask": "0x1" 4405 }, 4406 { 4407 "BriefDescription": "Counts all demand data writes (RFOs) DEMAND_RFO & L3_HIT_F & HITM_OTHER_CORE", 4408 "Counter": "0,1,2,3", 4409 "CounterHTOff": "0,1,2,3", 4410 "EventCode": "0xB7, 0xBB", 4411 "EventName": "OCR.DEMAND_RFO.L3_HIT_F.HITM_OTHER_CORE", 4412 "MSRIndex": "0x1a6,0x1a7", 4413 "MSRValue": "0x1000200002", 4414 "Offcore": "1", 4415 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4416 "SampleAfterValue": "100003", 4417 "UMask": "0x1" 4418 }, 4419 { 4420 "BriefDescription": "ALL_DATA_RD & L3_HIT_E & HITM_OTHER_CORE", 4421 "Counter": "0,1,2,3", 4422 "CounterHTOff": "0,1,2,3", 4423 "EventCode": "0xB7, 0xBB", 4424 "EventName": "OCR.ALL_DATA_RD.L3_HIT_E.HITM_OTHER_CORE", 4425 "MSRIndex": "0x1a6,0x1a7", 4426 "MSRValue": "0x1000080491", 4427 "Offcore": "1", 4428 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4429 "SampleAfterValue": "100003", 4430 "UMask": "0x1" 4431 }, 4432 { 4433 "BriefDescription": "ALL_READS & L3_HIT_E & NO_SNOOP_NEEDED", 4434 "Counter": "0,1,2,3", 4435 "CounterHTOff": "0,1,2,3", 4436 "EventCode": "0xB7, 0xBB", 4437 "EventName": "OCR.ALL_READS.L3_HIT_E.NO_SNOOP_NEEDED", 4438 "MSRIndex": "0x1a6,0x1a7", 4439 "MSRValue": "0x01000807F7", 4440 "Offcore": "1", 4441 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4442 "SampleAfterValue": "100003", 4443 "UMask": "0x1" 4444 }, 4445 { 4446 "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests PF_L1D_AND_SW & L3_HIT_S & HIT_OTHER_CORE_NO_FWD", 4447 "Counter": "0,1,2,3", 4448 "CounterHTOff": "0,1,2,3", 4449 "EventCode": "0xB7, 0xBB", 4450 "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", 4451 "MSRIndex": "0x1a6,0x1a7", 4452 "MSRValue": "0x0400100400", 4453 "Offcore": "1", 4454 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4455 "SampleAfterValue": "100003", 4456 "UMask": "0x1" 4457 }, 4458 { 4459 "BriefDescription": "Counts all demand data writes (RFOs)", 4460 "Counter": "0,1,2,3", 4461 "CounterHTOff": "0,1,2,3", 4462 "EventCode": "0xB7, 0xBB", 4463 "EventName": "OCR.DEMAND_RFO.L3_HIT_F.SNOOP_MISS", 4464 "MSRIndex": "0x1a6,0x1a7", 4465 "MSRValue": "0x0200200002", 4466 "Offcore": "1", 4467 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4468 "SampleAfterValue": "100003", 4469 "UMask": "0x1" 4470 }, 4471 { 4472 "BriefDescription": "Counts all demand code reads DEMAND_CODE_RD & L3_HIT_S & ANY_SNOOP", 4473 "Counter": "0,1,2,3", 4474 "CounterHTOff": "0,1,2,3", 4475 "EventCode": "0xB7, 0xBB", 4476 "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_S.ANY_SNOOP", 4477 "MSRIndex": "0x1a6,0x1a7", 4478 "MSRValue": "0x3F80100004", 4479 "Offcore": "1", 4480 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4481 "SampleAfterValue": "100003", 4482 "UMask": "0x1" 4483 }, 4484 { 4485 "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests have any response type.", 4486 "Counter": "0,1,2,3", 4487 "CounterHTOff": "0,1,2,3", 4488 "EventCode": "0xB7, 0xBB", 4489 "EventName": "OCR.PF_L1D_AND_SW.ANY_RESPONSE", 4490 "MSRIndex": "0x1a6,0x1a7", 4491 "MSRValue": "0x0000010400", 4492 "Offcore": "1", 4493 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4494 "SampleAfterValue": "100003", 4495 "UMask": "0x1" 4496 }, 4497 { 4498 "BriefDescription": "Counts demand data reads DEMAND_DATA_RD & L3_HIT_F & NO_SNOOP_NEEDED", 4499 "Counter": "0,1,2,3", 4500 "CounterHTOff": "0,1,2,3", 4501 "EventCode": "0xB7, 0xBB", 4502 "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDED", 4503 "MSRIndex": "0x1a6,0x1a7", 4504 "MSRValue": "0x0100200001", 4505 "Offcore": "1", 4506 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4507 "SampleAfterValue": "100003", 4508 "UMask": "0x1" 4509 }, 4510 { 4511 "BriefDescription": "Counts any other requests", 4512 "Counter": "0,1,2,3", 4513 "CounterHTOff": "0,1,2,3", 4514 "EventCode": "0xB7, 0xBB", 4515 "EventName": "OCR.OTHER.L3_HIT.SNOOP_HIT_WITH_FWD", 4516 "MSRIndex": "0x1a6,0x1a7", 4517 "MSRValue": "0x08007C8000", 4518 "Offcore": "1", 4519 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4520 "SampleAfterValue": "100003", 4521 "UMask": "0x1" 4522 }, 4523 { 4524 "BriefDescription": "ALL_PF_RFO & L3_HIT_S & NO_SNOOP_NEEDED", 4525 "Counter": "0,1,2,3", 4526 "CounterHTOff": "0,1,2,3", 4527 "EventCode": "0xB7, 0xBB", 4528 "EventName": "OCR.ALL_PF_RFO.L3_HIT_S.NO_SNOOP_NEEDED", 4529 "MSRIndex": "0x1a6,0x1a7", 4530 "MSRValue": "0x0100100120", 4531 "Offcore": "1", 4532 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4533 "SampleAfterValue": "100003", 4534 "UMask": "0x1" 4535 }, 4536 { 4537 "BriefDescription": "Counts prefetch (that bring data to L2) data reads PF_L2_DATA_RD & L3_HIT_M & HIT_OTHER_CORE_FWD", 4538 "Counter": "0,1,2,3", 4539 "CounterHTOff": "0,1,2,3", 4540 "EventCode": "0xB7, 0xBB", 4541 "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWD", 4542 "MSRIndex": "0x1a6,0x1a7", 4543 "MSRValue": "0x0800040010", 4544 "Offcore": "1", 4545 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4546 "SampleAfterValue": "100003", 4547 "UMask": "0x1" 4548 }, 4549 { 4550 "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads", 4551 "Counter": "0,1,2,3", 4552 "CounterHTOff": "0,1,2,3", 4553 "EventCode": "0xB7, 0xBB", 4554 "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_S.SNOOP_NONE", 4555 "MSRIndex": "0x1a6,0x1a7", 4556 "MSRValue": "0x0080100080", 4557 "Offcore": "1", 4558 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4559 "SampleAfterValue": "100003", 4560 "UMask": "0x1" 4561 }, 4562 { 4563 "BriefDescription": "ALL_RFO & SUPPLIER_NONE & HIT_OTHER_CORE_NO_FWD", 4564 "Counter": "0,1,2,3", 4565 "CounterHTOff": "0,1,2,3", 4566 "EventCode": "0xB7, 0xBB", 4567 "EventName": "OCR.ALL_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", 4568 "MSRIndex": "0x1a6,0x1a7", 4569 "MSRValue": "0x0400020122", 4570 "Offcore": "1", 4571 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4572 "SampleAfterValue": "100003", 4573 "UMask": "0x1" 4574 }, 4575 { 4576 "BriefDescription": "Counts any other requests OTHER & L3_HIT_E & HITM_OTHER_CORE", 4577 "Counter": "0,1,2,3", 4578 "CounterHTOff": "0,1,2,3", 4579 "EventCode": "0xB7, 0xBB", 4580 "EventName": "OCR.OTHER.L3_HIT_E.HITM_OTHER_CORE", 4581 "MSRIndex": "0x1a6,0x1a7", 4582 "MSRValue": "0x1000088000", 4583 "Offcore": "1", 4584 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4585 "SampleAfterValue": "100003", 4586 "UMask": "0x1" 4587 }, 4588 { 4589 "BriefDescription": "ALL_READS & L3_HIT & ANY_SNOOP", 4590 "Counter": "0,1,2,3", 4591 "CounterHTOff": "0,1,2,3", 4592 "EventCode": "0xB7, 0xBB", 4593 "EventName": "OCR.ALL_READS.L3_HIT.ANY_SNOOP", 4594 "MSRIndex": "0x1a6,0x1a7", 4595 "MSRValue": "0x3F803C07F7", 4596 "Offcore": "1", 4597 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4598 "SampleAfterValue": "100003", 4599 "UMask": "0x1" 4600 }, 4601 { 4602 "BriefDescription": "ALL_READS & PMM_HIT_LOCAL_PMM & SNOOP_NONE", 4603 "Counter": "0,1,2,3", 4604 "CounterHTOff": "0,1,2,3", 4605 "EventCode": "0xB7, 0xBB", 4606 "EventName": "OCR.ALL_READS.PMM_HIT_LOCAL_PMM.SNOOP_NONE", 4607 "MSRIndex": "0x1a6,0x1a7", 4608 "MSRValue": "0x00804007F7", 4609 "Offcore": "1", 4610 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4611 "SampleAfterValue": "100003", 4612 "UMask": "0x1" 4613 }, 4614 { 4615 "BriefDescription": "Counts any other requests OTHER & SUPPLIER_NONE & HIT_OTHER_CORE_NO_FWD", 4616 "Counter": "0,1,2,3", 4617 "CounterHTOff": "0,1,2,3", 4618 "EventCode": "0xB7, 0xBB", 4619 "EventName": "OCR.OTHER.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", 4620 "MSRIndex": "0x1a6,0x1a7", 4621 "MSRValue": "0x0400028000", 4622 "Offcore": "1", 4623 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4624 "SampleAfterValue": "100003", 4625 "UMask": "0x1" 4626 }, 4627 { 4628 "BriefDescription": "ALL_PF_DATA_RD & L3_HIT & ANY_SNOOP", 4629 "Counter": "0,1,2,3", 4630 "CounterHTOff": "0,1,2,3", 4631 "EventCode": "0xB7, 0xBB", 4632 "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT.ANY_SNOOP", 4633 "MSRIndex": "0x1a6,0x1a7", 4634 "MSRValue": "0x3F803C0490", 4635 "Offcore": "1", 4636 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4637 "SampleAfterValue": "100003", 4638 "UMask": "0x1" 4639 }, 4640 { 4641 "BriefDescription": "Counts all demand code reads DEMAND_CODE_RD & PMM_HIT_LOCAL_PMM & SNOOP_NOT_NEEDED", 4642 "Counter": "0,1,2,3", 4643 "CounterHTOff": "0,1,2,3", 4644 "EventCode": "0xB7, 0xBB", 4645 "EventName": "OCR.DEMAND_CODE_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", 4646 "MSRIndex": "0x1a6,0x1a7", 4647 "MSRValue": "0x0100400004", 4648 "Offcore": "1", 4649 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4650 "SampleAfterValue": "100003", 4651 "UMask": "0x1" 4652 }, 4653 { 4654 "BriefDescription": "Counts demand data reads DEMAND_DATA_RD & L3_HIT & HITM_OTHER_CORE", 4655 "Counter": "0,1,2,3", 4656 "CounterHTOff": "0,1,2,3", 4657 "EventCode": "0xB7, 0xBB", 4658 "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.HITM_OTHER_CORE", 4659 "MSRIndex": "0x1a6,0x1a7", 4660 "MSRValue": "0x10003C0001", 4661 "Offcore": "1", 4662 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4663 "SampleAfterValue": "100003", 4664 "UMask": "0x1" 4665 }, 4666 { 4667 "BriefDescription": "Counts all demand data writes (RFOs)", 4668 "Counter": "0,1,2,3", 4669 "CounterHTOff": "0,1,2,3", 4670 "EventCode": "0xB7, 0xBB", 4671 "EventName": "OCR.DEMAND_RFO.SUPPLIER_NONE.SNOOP_MISS", 4672 "MSRIndex": "0x1a6,0x1a7", 4673 "MSRValue": "0x0200020002", 4674 "Offcore": "1", 4675 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4676 "SampleAfterValue": "100003", 4677 "UMask": "0x1" 4678 }, 4679 { 4680 "BriefDescription": "ALL_READS & L3_HIT & SNOOP_HIT_WITH_FWD", 4681 "Counter": "0,1,2,3", 4682 "CounterHTOff": "0,1,2,3", 4683 "EventCode": "0xB7, 0xBB", 4684 "EventName": "OCR.ALL_READS.L3_HIT.SNOOP_HIT_WITH_FWD", 4685 "MSRIndex": "0x1a6,0x1a7", 4686 "MSRValue": "0x08007C07F7", 4687 "Offcore": "1", 4688 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4689 "SampleAfterValue": "100003", 4690 "UMask": "0x1" 4691 }, 4692 { 4693 "BriefDescription": "Counts all demand code reads DEMAND_CODE_RD & PMM_HIT_LOCAL_PMM & SNOOP_NONE", 4694 "Counter": "0,1,2,3", 4695 "CounterHTOff": "0,1,2,3", 4696 "EventCode": "0xB7, 0xBB", 4697 "EventName": "OCR.DEMAND_CODE_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE", 4698 "MSRIndex": "0x1a6,0x1a7", 4699 "MSRValue": "0x0080400004", 4700 "Offcore": "1", 4701 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4702 "SampleAfterValue": "100003", 4703 "UMask": "0x1" 4704 }, 4705 { 4706 "BriefDescription": "Counts demand data reads", 4707 "Counter": "0,1,2,3", 4708 "CounterHTOff": "0,1,2,3", 4709 "EventCode": "0xB7, 0xBB", 4710 "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_S.SNOOP_MISS", 4711 "MSRIndex": "0x1a6,0x1a7", 4712 "MSRValue": "0x0200100001", 4713 "Offcore": "1", 4714 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4715 "SampleAfterValue": "100003", 4716 "UMask": "0x1" 4717 }, 4718 { 4719 "BriefDescription": "ALL_READS & L3_HIT & SNOOP_NONE", 4720 "Counter": "0,1,2,3", 4721 "CounterHTOff": "0,1,2,3", 4722 "EventCode": "0xB7, 0xBB", 4723 "EventName": "OCR.ALL_READS.L3_HIT.SNOOP_NONE", 4724 "MSRIndex": "0x1a6,0x1a7", 4725 "MSRValue": "0x00803C07F7", 4726 "Offcore": "1", 4727 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4728 "SampleAfterValue": "100003", 4729 "UMask": "0x1" 4730 }, 4731 { 4732 "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads PF_L3_DATA_RD & L3_HIT_E & HITM_OTHER_CORE", 4733 "Counter": "0,1,2,3", 4734 "CounterHTOff": "0,1,2,3", 4735 "EventCode": "0xB7, 0xBB", 4736 "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_E.HITM_OTHER_CORE", 4737 "MSRIndex": "0x1a6,0x1a7", 4738 "MSRValue": "0x1000080080", 4739 "Offcore": "1", 4740 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4741 "SampleAfterValue": "100003", 4742 "UMask": "0x1" 4743 }, 4744 { 4745 "BriefDescription": "ALL_PF_DATA_RD & SUPPLIER_NONE & NO_SNOOP_NEEDED", 4746 "Counter": "0,1,2,3", 4747 "CounterHTOff": "0,1,2,3", 4748 "EventCode": "0xB7, 0xBB", 4749 "EventName": "OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED", 4750 "MSRIndex": "0x1a6,0x1a7", 4751 "MSRValue": "0x0100020490", 4752 "Offcore": "1", 4753 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4754 "SampleAfterValue": "100003", 4755 "UMask": "0x1" 4756 }, 4757 { 4758 "BriefDescription": "Counts any other requests OTHER & SUPPLIER_NONE & ANY_SNOOP", 4759 "Counter": "0,1,2,3", 4760 "CounterHTOff": "0,1,2,3", 4761 "EventCode": "0xB7, 0xBB", 4762 "EventName": "OCR.OTHER.SUPPLIER_NONE.ANY_SNOOP", 4763 "MSRIndex": "0x1a6,0x1a7", 4764 "MSRValue": "0x3F80028000", 4765 "Offcore": "1", 4766 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4767 "SampleAfterValue": "100003", 4768 "UMask": "0x1" 4769 }, 4770 { 4771 "BriefDescription": "ALL_PF_DATA_RD & L3_HIT & NO_SNOOP_NEEDED", 4772 "Counter": "0,1,2,3", 4773 "CounterHTOff": "0,1,2,3", 4774 "EventCode": "0xB7, 0xBB", 4775 "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT.NO_SNOOP_NEEDED", 4776 "MSRIndex": "0x1a6,0x1a7", 4777 "MSRValue": "0x01003C0490", 4778 "Offcore": "1", 4779 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4780 "SampleAfterValue": "100003", 4781 "UMask": "0x1" 4782 }, 4783 { 4784 "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs PF_L2_RFO & L3_HIT_F & HIT_OTHER_CORE_FWD", 4785 "Counter": "0,1,2,3", 4786 "CounterHTOff": "0,1,2,3", 4787 "EventCode": "0xB7, 0xBB", 4788 "EventName": "OCR.PF_L2_RFO.L3_HIT_F.HIT_OTHER_CORE_FWD", 4789 "MSRIndex": "0x1a6,0x1a7", 4790 "MSRValue": "0x0800200020", 4791 "Offcore": "1", 4792 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4793 "SampleAfterValue": "100003", 4794 "UMask": "0x1" 4795 }, 4796 { 4797 "BriefDescription": "ALL_READS & L3_HIT_S & NO_SNOOP_NEEDED", 4798 "Counter": "0,1,2,3", 4799 "CounterHTOff": "0,1,2,3", 4800 "EventCode": "0xB7, 0xBB", 4801 "EventName": "OCR.ALL_READS.L3_HIT_S.NO_SNOOP_NEEDED", 4802 "MSRIndex": "0x1a6,0x1a7", 4803 "MSRValue": "0x01001007F7", 4804 "Offcore": "1", 4805 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4806 "SampleAfterValue": "100003", 4807 "UMask": "0x1" 4808 }, 4809 { 4810 "BriefDescription": "ALL_RFO & L3_HIT_S & HITM_OTHER_CORE", 4811 "Counter": "0,1,2,3", 4812 "CounterHTOff": "0,1,2,3", 4813 "EventCode": "0xB7, 0xBB", 4814 "EventName": "OCR.ALL_RFO.L3_HIT_S.HITM_OTHER_CORE", 4815 "MSRIndex": "0x1a6,0x1a7", 4816 "MSRValue": "0x1000100122", 4817 "Offcore": "1", 4818 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4819 "SampleAfterValue": "100003", 4820 "UMask": "0x1" 4821 }, 4822 { 4823 "BriefDescription": "ALL_RFO & L3_HIT & SNOOP_HIT_WITH_FWD", 4824 "Counter": "0,1,2,3", 4825 "CounterHTOff": "0,1,2,3", 4826 "EventCode": "0xB7, 0xBB", 4827 "EventName": "OCR.ALL_RFO.L3_HIT.SNOOP_HIT_WITH_FWD", 4828 "MSRIndex": "0x1a6,0x1a7", 4829 "MSRValue": "0x08007C0122", 4830 "Offcore": "1", 4831 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4832 "SampleAfterValue": "100003", 4833 "UMask": "0x1" 4834 }, 4835 { 4836 "BriefDescription": "ALL_READS & L3_HIT_M & ANY_SNOOP", 4837 "Counter": "0,1,2,3", 4838 "CounterHTOff": "0,1,2,3", 4839 "EventCode": "0xB7, 0xBB", 4840 "EventName": "OCR.ALL_READS.L3_HIT_M.ANY_SNOOP", 4841 "MSRIndex": "0x1a6,0x1a7", 4842 "MSRValue": "0x3F800407F7", 4843 "Offcore": "1", 4844 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4845 "SampleAfterValue": "100003", 4846 "UMask": "0x1" 4847 }, 4848 { 4849 "BriefDescription": "ALL_READS & L3_HIT & NO_SNOOP_NEEDED", 4850 "Counter": "0,1,2,3", 4851 "CounterHTOff": "0,1,2,3", 4852 "EventCode": "0xB7, 0xBB", 4853 "EventName": "OCR.ALL_READS.L3_HIT.NO_SNOOP_NEEDED", 4854 "MSRIndex": "0x1a6,0x1a7", 4855 "MSRValue": "0x01003C07F7", 4856 "Offcore": "1", 4857 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4858 "SampleAfterValue": "100003", 4859 "UMask": "0x1" 4860 }, 4861 { 4862 "BriefDescription": "ALL_READS & ANY_RESPONSE have any response type.", 4863 "Counter": "0,1,2,3", 4864 "CounterHTOff": "0,1,2,3", 4865 "EventCode": "0xB7, 0xBB", 4866 "EventName": "OCR.ALL_READS.ANY_RESPONSE", 4867 "MSRIndex": "0x1a6,0x1a7", 4868 "MSRValue": "0x00000107F7", 4869 "Offcore": "1", 4870 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4871 "SampleAfterValue": "100003", 4872 "UMask": "0x1" 4873 }, 4874 { 4875 "BriefDescription": "ALL_DATA_RD & L3_HIT & HIT_OTHER_CORE_FWD", 4876 "Counter": "0,1,2,3", 4877 "CounterHTOff": "0,1,2,3", 4878 "EventCode": "0xB7, 0xBB", 4879 "EventName": "OCR.ALL_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD", 4880 "MSRIndex": "0x1a6,0x1a7", 4881 "MSRValue": "0x08003C0491", 4882 "Offcore": "1", 4883 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4884 "SampleAfterValue": "100003", 4885 "UMask": "0x1" 4886 }, 4887 { 4888 "BriefDescription": "ALL_DATA_RD & L3_HIT_M & NO_SNOOP_NEEDED", 4889 "Counter": "0,1,2,3", 4890 "CounterHTOff": "0,1,2,3", 4891 "EventCode": "0xB7, 0xBB", 4892 "EventName": "OCR.ALL_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDED", 4893 "MSRIndex": "0x1a6,0x1a7", 4894 "MSRValue": "0x0100040491", 4895 "Offcore": "1", 4896 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4897 "SampleAfterValue": "100003", 4898 "UMask": "0x1" 4899 }, 4900 { 4901 "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads PF_L3_DATA_RD & SUPPLIER_NONE & ANY_SNOOP", 4902 "Counter": "0,1,2,3", 4903 "CounterHTOff": "0,1,2,3", 4904 "EventCode": "0xB7, 0xBB", 4905 "EventName": "OCR.PF_L3_DATA_RD.SUPPLIER_NONE.ANY_SNOOP", 4906 "MSRIndex": "0x1a6,0x1a7", 4907 "MSRValue": "0x3F80020080", 4908 "Offcore": "1", 4909 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4910 "SampleAfterValue": "100003", 4911 "UMask": "0x1" 4912 }, 4913 { 4914 "BriefDescription": "Counts any other requests OTHER & L3_HIT_F & HITM_OTHER_CORE", 4915 "Counter": "0,1,2,3", 4916 "CounterHTOff": "0,1,2,3", 4917 "EventCode": "0xB7, 0xBB", 4918 "EventName": "OCR.OTHER.L3_HIT_F.HITM_OTHER_CORE", 4919 "MSRIndex": "0x1a6,0x1a7", 4920 "MSRValue": "0x1000208000", 4921 "Offcore": "1", 4922 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4923 "SampleAfterValue": "100003", 4924 "UMask": "0x1" 4925 }, 4926 { 4927 "BriefDescription": "ALL_DATA_RD & L3_HIT & ANY_SNOOP", 4928 "Counter": "0,1,2,3", 4929 "CounterHTOff": "0,1,2,3", 4930 "EventCode": "0xB7, 0xBB", 4931 "EventName": "OCR.ALL_DATA_RD.L3_HIT.ANY_SNOOP", 4932 "MSRIndex": "0x1a6,0x1a7", 4933 "MSRValue": "0x3F803C0491", 4934 "Offcore": "1", 4935 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4936 "SampleAfterValue": "100003", 4937 "UMask": "0x1" 4938 }, 4939 { 4940 "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests PF_L1D_AND_SW & L3_HIT_M & HITM_OTHER_CORE", 4941 "Counter": "0,1,2,3", 4942 "CounterHTOff": "0,1,2,3", 4943 "EventCode": "0xB7, 0xBB", 4944 "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_M.HITM_OTHER_CORE", 4945 "MSRIndex": "0x1a6,0x1a7", 4946 "MSRValue": "0x1000040400", 4947 "Offcore": "1", 4948 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4949 "SampleAfterValue": "100003", 4950 "UMask": "0x1" 4951 }, 4952 { 4953 "BriefDescription": "Counts prefetch (that bring data to L2) data reads PF_L2_DATA_RD & L3_HIT_E & HIT_OTHER_CORE_FWD", 4954 "Counter": "0,1,2,3", 4955 "CounterHTOff": "0,1,2,3", 4956 "EventCode": "0xB7, 0xBB", 4957 "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWD", 4958 "MSRIndex": "0x1a6,0x1a7", 4959 "MSRValue": "0x0800080010", 4960 "Offcore": "1", 4961 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4962 "SampleAfterValue": "100003", 4963 "UMask": "0x1" 4964 }, 4965 { 4966 "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs PF_L3_RFO & PMM_HIT_LOCAL_PMM & SNOOP_NONE", 4967 "Counter": "0,1,2,3", 4968 "CounterHTOff": "0,1,2,3", 4969 "EventCode": "0xB7, 0xBB", 4970 "EventName": "OCR.PF_L3_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NONE", 4971 "MSRIndex": "0x1a6,0x1a7", 4972 "MSRValue": "0x0080400100", 4973 "Offcore": "1", 4974 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4975 "SampleAfterValue": "100003", 4976 "UMask": "0x1" 4977 }, 4978 { 4979 "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads PF_L3_DATA_RD & L3_HIT_S & HIT_OTHER_CORE_FWD", 4980 "Counter": "0,1,2,3", 4981 "CounterHTOff": "0,1,2,3", 4982 "EventCode": "0xB7, 0xBB", 4983 "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWD", 4984 "MSRIndex": "0x1a6,0x1a7", 4985 "MSRValue": "0x0800100080", 4986 "Offcore": "1", 4987 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4988 "SampleAfterValue": "100003", 4989 "UMask": "0x1" 4990 }, 4991 { 4992 "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs", 4993 "Counter": "0,1,2,3", 4994 "CounterHTOff": "0,1,2,3", 4995 "EventCode": "0xB7, 0xBB", 4996 "EventName": "OCR.PF_L3_RFO.L3_HIT_E.SNOOP_NONE", 4997 "MSRIndex": "0x1a6,0x1a7", 4998 "MSRValue": "0x0080080100", 4999 "Offcore": "1", 5000 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5001 "SampleAfterValue": "100003", 5002 "UMask": "0x1" 5003 }, 5004 { 5005 "BriefDescription": "Counts prefetch (that bring data to L2) data reads", 5006 "Counter": "0,1,2,3", 5007 "CounterHTOff": "0,1,2,3", 5008 "EventCode": "0xB7, 0xBB", 5009 "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_E.SNOOP_MISS", 5010 "MSRIndex": "0x1a6,0x1a7", 5011 "MSRValue": "0x0200080010", 5012 "Offcore": "1", 5013 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5014 "SampleAfterValue": "100003", 5015 "UMask": "0x1" 5016 }, 5017 { 5018 "BriefDescription": "ALL_PF_RFO & PMM_HIT_LOCAL_PMM & ANY_SNOOP", 5019 "Counter": "0,1,2,3", 5020 "CounterHTOff": "0,1,2,3", 5021 "EventCode": "0xB7, 0xBB", 5022 "EventName": "OCR.ALL_PF_RFO.PMM_HIT_LOCAL_PMM.ANY_SNOOP", 5023 "MSRIndex": "0x1a6,0x1a7", 5024 "MSRValue": "0x3F80400120", 5025 "Offcore": "1", 5026 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5027 "SampleAfterValue": "100003", 5028 "UMask": "0x1" 5029 }, 5030 { 5031 "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests", 5032 "Counter": "0,1,2,3", 5033 "CounterHTOff": "0,1,2,3", 5034 "EventCode": "0xB7, 0xBB", 5035 "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_E.SNOOP_NONE", 5036 "MSRIndex": "0x1a6,0x1a7", 5037 "MSRValue": "0x0080080400", 5038 "Offcore": "1", 5039 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5040 "SampleAfterValue": "100003", 5041 "UMask": "0x1" 5042 }, 5043 { 5044 "BriefDescription": "ALL_PF_DATA_RD & L3_HIT & SNOOP_MISS", 5045 "Counter": "0,1,2,3", 5046 "CounterHTOff": "0,1,2,3", 5047 "EventCode": "0xB7, 0xBB", 5048 "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT.SNOOP_MISS", 5049 "MSRIndex": "0x1a6,0x1a7", 5050 "MSRValue": "0x02003C0490", 5051 "Offcore": "1", 5052 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5053 "SampleAfterValue": "100003", 5054 "UMask": "0x1" 5055 }, 5056 { 5057 "BriefDescription": "Counts any other requests OTHER & L3_HIT & SNOOP_NONE", 5058 "Counter": "0,1,2,3", 5059 "CounterHTOff": "0,1,2,3", 5060 "EventCode": "0xB7, 0xBB", 5061 "EventName": "OCR.OTHER.L3_HIT.SNOOP_NONE", 5062 "MSRIndex": "0x1a6,0x1a7", 5063 "MSRValue": "0x00803C8000", 5064 "Offcore": "1", 5065 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5066 "SampleAfterValue": "100003", 5067 "UMask": "0x1" 5068 }, 5069 { 5070 "BriefDescription": "Counts any other requests OTHER & SUPPLIER_NONE & HIT_OTHER_CORE_FWD", 5071 "Counter": "0,1,2,3", 5072 "CounterHTOff": "0,1,2,3", 5073 "EventCode": "0xB7, 0xBB", 5074 "EventName": "OCR.OTHER.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", 5075 "MSRIndex": "0x1a6,0x1a7", 5076 "MSRValue": "0x0800028000", 5077 "Offcore": "1", 5078 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5079 "SampleAfterValue": "100003", 5080 "UMask": "0x1" 5081 }, 5082 { 5083 "BriefDescription": "ALL_DATA_RD & L3_HIT_E & SNOOP_NONE", 5084 "Counter": "0,1,2,3", 5085 "CounterHTOff": "0,1,2,3", 5086 "EventCode": "0xB7, 0xBB", 5087 "EventName": "OCR.ALL_DATA_RD.L3_HIT_E.SNOOP_NONE", 5088 "MSRIndex": "0x1a6,0x1a7", 5089 "MSRValue": "0x0080080491", 5090 "Offcore": "1", 5091 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5092 "SampleAfterValue": "100003", 5093 "UMask": "0x1" 5094 }, 5095 { 5096 "BriefDescription": "Counts all demand data writes (RFOs) DEMAND_RFO & L3_HIT_S & HITM_OTHER_CORE", 5097 "Counter": "0,1,2,3", 5098 "CounterHTOff": "0,1,2,3", 5099 "EventCode": "0xB7, 0xBB", 5100 "EventName": "OCR.DEMAND_RFO.L3_HIT_S.HITM_OTHER_CORE", 5101 "MSRIndex": "0x1a6,0x1a7", 5102 "MSRValue": "0x1000100002", 5103 "Offcore": "1", 5104 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5105 "SampleAfterValue": "100003", 5106 "UMask": "0x1" 5107 }, 5108 { 5109 "BriefDescription": "ALL_READS & L3_HIT_S & HITM_OTHER_CORE", 5110 "Counter": "0,1,2,3", 5111 "CounterHTOff": "0,1,2,3", 5112 "EventCode": "0xB7, 0xBB", 5113 "EventName": "OCR.ALL_READS.L3_HIT_S.HITM_OTHER_CORE", 5114 "MSRIndex": "0x1a6,0x1a7", 5115 "MSRValue": "0x10001007F7", 5116 "Offcore": "1", 5117 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5118 "SampleAfterValue": "100003", 5119 "UMask": "0x1" 5120 }, 5121 { 5122 "BriefDescription": "ALL_READS & L3_HIT_F & ANY_SNOOP", 5123 "Counter": "0,1,2,3", 5124 "CounterHTOff": "0,1,2,3", 5125 "EventCode": "0xB7, 0xBB", 5126 "EventName": "OCR.ALL_READS.L3_HIT_F.ANY_SNOOP", 5127 "MSRIndex": "0x1a6,0x1a7", 5128 "MSRValue": "0x3F802007F7", 5129 "Offcore": "1", 5130 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5131 "SampleAfterValue": "100003", 5132 "UMask": "0x1" 5133 }, 5134 { 5135 "BriefDescription": "ALL_READS & L3_HIT_M & HIT_OTHER_CORE_NO_FWD", 5136 "Counter": "0,1,2,3", 5137 "CounterHTOff": "0,1,2,3", 5138 "EventCode": "0xB7, 0xBB", 5139 "EventName": "OCR.ALL_READS.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", 5140 "MSRIndex": "0x1a6,0x1a7", 5141 "MSRValue": "0x04000407F7", 5142 "Offcore": "1", 5143 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5144 "SampleAfterValue": "100003", 5145 "UMask": "0x1" 5146 }, 5147 { 5148 "BriefDescription": "ALL_READS & L3_HIT_S & SNOOP_NONE", 5149 "Counter": "0,1,2,3", 5150 "CounterHTOff": "0,1,2,3", 5151 "EventCode": "0xB7, 0xBB", 5152 "EventName": "OCR.ALL_READS.L3_HIT_S.SNOOP_NONE", 5153 "MSRIndex": "0x1a6,0x1a7", 5154 "MSRValue": "0x00801007F7", 5155 "Offcore": "1", 5156 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5157 "SampleAfterValue": "100003", 5158 "UMask": "0x1" 5159 }, 5160 { 5161 "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads PF_L3_DATA_RD & L3_HIT & SNOOP_MISS", 5162 "Counter": "0,1,2,3", 5163 "CounterHTOff": "0,1,2,3", 5164 "EventCode": "0xB7, 0xBB", 5165 "EventName": "OCR.PF_L3_DATA_RD.L3_HIT.SNOOP_MISS", 5166 "MSRIndex": "0x1a6,0x1a7", 5167 "MSRValue": "0x02003C0080", 5168 "Offcore": "1", 5169 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5170 "SampleAfterValue": "100003", 5171 "UMask": "0x1" 5172 }, 5173 { 5174 "BriefDescription": "ALL_PF_DATA_RD & L3_HIT_E & SNOOP_NONE", 5175 "Counter": "0,1,2,3", 5176 "CounterHTOff": "0,1,2,3", 5177 "EventCode": "0xB7, 0xBB", 5178 "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_E.SNOOP_NONE", 5179 "MSRIndex": "0x1a6,0x1a7", 5180 "MSRValue": "0x0080080490", 5181 "Offcore": "1", 5182 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5183 "SampleAfterValue": "100003", 5184 "UMask": "0x1" 5185 }, 5186 { 5187 "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests PF_L1D_AND_SW & SUPPLIER_NONE & HIT_OTHER_CORE_NO_FWD", 5188 "Counter": "0,1,2,3", 5189 "CounterHTOff": "0,1,2,3", 5190 "EventCode": "0xB7, 0xBB", 5191 "EventName": "OCR.PF_L1D_AND_SW.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", 5192 "MSRIndex": "0x1a6,0x1a7", 5193 "MSRValue": "0x0400020400", 5194 "Offcore": "1", 5195 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5196 "SampleAfterValue": "100003", 5197 "UMask": "0x1" 5198 }, 5199 { 5200 "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests PF_L1D_AND_SW & L3_HIT_S & HIT_OTHER_CORE_FWD", 5201 "Counter": "0,1,2,3", 5202 "CounterHTOff": "0,1,2,3", 5203 "EventCode": "0xB7, 0xBB", 5204 "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_S.HIT_OTHER_CORE_FWD", 5205 "MSRIndex": "0x1a6,0x1a7", 5206 "MSRValue": "0x0800100400", 5207 "Offcore": "1", 5208 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5209 "SampleAfterValue": "100003", 5210 "UMask": "0x1" 5211 }, 5212 { 5213 "BriefDescription": "ALL_READS & L3_HIT_E & HIT_OTHER_CORE_NO_FWD", 5214 "Counter": "0,1,2,3", 5215 "CounterHTOff": "0,1,2,3", 5216 "EventCode": "0xB7, 0xBB", 5217 "EventName": "OCR.ALL_READS.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", 5218 "MSRIndex": "0x1a6,0x1a7", 5219 "MSRValue": "0x04000807F7", 5220 "Offcore": "1", 5221 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5222 "SampleAfterValue": "100003", 5223 "UMask": "0x1" 5224 }, 5225 { 5226 "BriefDescription": "Counts all demand code reads", 5227 "Counter": "0,1,2,3", 5228 "CounterHTOff": "0,1,2,3", 5229 "EventCode": "0xB7, 0xBB", 5230 "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_S.SNOOP_MISS", 5231 "MSRIndex": "0x1a6,0x1a7", 5232 "MSRValue": "0x0200100004", 5233 "Offcore": "1", 5234 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5235 "SampleAfterValue": "100003", 5236 "UMask": "0x1" 5237 }, 5238 { 5239 "BriefDescription": "ALL_DATA_RD & L3_HIT_S & SNOOP_NONE", 5240 "Counter": "0,1,2,3", 5241 "CounterHTOff": "0,1,2,3", 5242 "EventCode": "0xB7, 0xBB", 5243 "EventName": "OCR.ALL_DATA_RD.L3_HIT_S.SNOOP_NONE", 5244 "MSRIndex": "0x1a6,0x1a7", 5245 "MSRValue": "0x0080100491", 5246 "Offcore": "1", 5247 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5248 "SampleAfterValue": "100003", 5249 "UMask": "0x1" 5250 }, 5251 { 5252 "BriefDescription": "Counts all demand data writes (RFOs) DEMAND_RFO & SUPPLIER_NONE & ANY_SNOOP", 5253 "Counter": "0,1,2,3", 5254 "CounterHTOff": "0,1,2,3", 5255 "EventCode": "0xB7, 0xBB", 5256 "EventName": "OCR.DEMAND_RFO.SUPPLIER_NONE.ANY_SNOOP", 5257 "MSRIndex": "0x1a6,0x1a7", 5258 "MSRValue": "0x3F80020002", 5259 "Offcore": "1", 5260 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5261 "SampleAfterValue": "100003", 5262 "UMask": "0x1" 5263 }, 5264 { 5265 "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads PF_L3_DATA_RD & L3_HIT & ANY_SNOOP", 5266 "Counter": "0,1,2,3", 5267 "CounterHTOff": "0,1,2,3", 5268 "EventCode": "0xB7, 0xBB", 5269 "EventName": "OCR.PF_L3_DATA_RD.L3_HIT.ANY_SNOOP", 5270 "MSRIndex": "0x1a6,0x1a7", 5271 "MSRValue": "0x3F803C0080", 5272 "Offcore": "1", 5273 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5274 "SampleAfterValue": "100003", 5275 "UMask": "0x1" 5276 }, 5277 { 5278 "BriefDescription": "ALL_RFO & L3_HIT & SNOOP_NONE", 5279 "Counter": "0,1,2,3", 5280 "CounterHTOff": "0,1,2,3", 5281 "EventCode": "0xB7, 0xBB", 5282 "EventName": "OCR.ALL_RFO.L3_HIT.SNOOP_NONE", 5283 "MSRIndex": "0x1a6,0x1a7", 5284 "MSRValue": "0x00803C0122", 5285 "Offcore": "1", 5286 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5287 "SampleAfterValue": "100003", 5288 "UMask": "0x1" 5289 }, 5290 { 5291 "BriefDescription": "ALL_PF_DATA_RD & L3_HIT_M & SNOOP_NONE", 5292 "Counter": "0,1,2,3", 5293 "CounterHTOff": "0,1,2,3", 5294 "EventCode": "0xB7, 0xBB", 5295 "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_M.SNOOP_NONE", 5296 "MSRIndex": "0x1a6,0x1a7", 5297 "MSRValue": "0x0080040490", 5298 "Offcore": "1", 5299 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5300 "SampleAfterValue": "100003", 5301 "UMask": "0x1" 5302 }, 5303 { 5304 "BriefDescription": "Counts all demand data writes (RFOs) DEMAND_RFO & L3_HIT & HIT_OTHER_CORE_NO_FWD", 5305 "Counter": "0,1,2,3", 5306 "CounterHTOff": "0,1,2,3", 5307 "EventCode": "0xB7, 0xBB", 5308 "EventName": "OCR.DEMAND_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD", 5309 "MSRIndex": "0x1a6,0x1a7", 5310 "MSRValue": "0x04003C0002", 5311 "Offcore": "1", 5312 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5313 "SampleAfterValue": "100003", 5314 "UMask": "0x1" 5315 }, 5316 { 5317 "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs PF_L3_RFO & SUPPLIER_NONE & HIT_OTHER_CORE_NO_FWD", 5318 "Counter": "0,1,2,3", 5319 "CounterHTOff": "0,1,2,3", 5320 "EventCode": "0xB7, 0xBB", 5321 "EventName": "OCR.PF_L3_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", 5322 "MSRIndex": "0x1a6,0x1a7", 5323 "MSRValue": "0x0400020100", 5324 "Offcore": "1", 5325 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5326 "SampleAfterValue": "100003", 5327 "UMask": "0x1" 5328 }, 5329 { 5330 "BriefDescription": "ALL_PF_RFO & L3_HIT_M & HIT_OTHER_CORE_NO_FWD", 5331 "Counter": "0,1,2,3", 5332 "CounterHTOff": "0,1,2,3", 5333 "EventCode": "0xB7, 0xBB", 5334 "EventName": "OCR.ALL_PF_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", 5335 "MSRIndex": "0x1a6,0x1a7", 5336 "MSRValue": "0x0400040120", 5337 "Offcore": "1", 5338 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5339 "SampleAfterValue": "100003", 5340 "UMask": "0x1" 5341 }, 5342 { 5343 "BriefDescription": "ALL_READS & L3_HIT_E & SNOOP_NONE", 5344 "Counter": "0,1,2,3", 5345 "CounterHTOff": "0,1,2,3", 5346 "EventCode": "0xB7, 0xBB", 5347 "EventName": "OCR.ALL_READS.L3_HIT_E.SNOOP_NONE", 5348 "MSRIndex": "0x1a6,0x1a7", 5349 "MSRValue": "0x00800807F7", 5350 "Offcore": "1", 5351 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5352 "SampleAfterValue": "100003", 5353 "UMask": "0x1" 5354 }, 5355 { 5356 "BriefDescription": "Counts demand data reads DEMAND_DATA_RD & SUPPLIER_NONE & HITM_OTHER_CORE", 5357 "Counter": "0,1,2,3", 5358 "CounterHTOff": "0,1,2,3", 5359 "EventCode": "0xB7, 0xBB", 5360 "EventName": "OCR.DEMAND_DATA_RD.SUPPLIER_NONE.HITM_OTHER_CORE", 5361 "MSRIndex": "0x1a6,0x1a7", 5362 "MSRValue": "0x1000020001", 5363 "Offcore": "1", 5364 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5365 "SampleAfterValue": "100003", 5366 "UMask": "0x1" 5367 }, 5368 { 5369 "BriefDescription": "ALL_READS & SUPPLIER_NONE & SNOOP_MISS", 5370 "Counter": "0,1,2,3", 5371 "CounterHTOff": "0,1,2,3", 5372 "EventCode": "0xB7, 0xBB", 5373 "EventName": "OCR.ALL_READS.SUPPLIER_NONE.SNOOP_MISS", 5374 "MSRIndex": "0x1a6,0x1a7", 5375 "MSRValue": "0x02000207F7", 5376 "Offcore": "1", 5377 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5378 "SampleAfterValue": "100003", 5379 "UMask": "0x1" 5380 }, 5381 { 5382 "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads PF_L3_DATA_RD & L3_HIT_F & HITM_OTHER_CORE", 5383 "Counter": "0,1,2,3", 5384 "CounterHTOff": "0,1,2,3", 5385 "EventCode": "0xB7, 0xBB", 5386 "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_F.HITM_OTHER_CORE", 5387 "MSRIndex": "0x1a6,0x1a7", 5388 "MSRValue": "0x1000200080", 5389 "Offcore": "1", 5390 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5391 "SampleAfterValue": "100003", 5392 "UMask": "0x1" 5393 }, 5394 { 5395 "BriefDescription": "Number of PREFETCHT0 instructions executed.", 5396 "Counter": "0,1,2,3", 5397 "CounterHTOff": "0,1,2,3,4,5,6,7", 5398 "EventCode": "0x32", 5399 "EventName": "SW_PREFETCH_ACCESS.T0", 5400 "SampleAfterValue": "2000003", 5401 "UMask": "0x2" 5402 }, 5403 { 5404 "BriefDescription": "ALL_RFO & L3_HIT & HIT_OTHER_CORE_FWD", 5405 "Counter": "0,1,2,3", 5406 "CounterHTOff": "0,1,2,3", 5407 "EventCode": "0xB7, 0xBB", 5408 "EventName": "OCR.ALL_RFO.L3_HIT.HIT_OTHER_CORE_FWD", 5409 "MSRIndex": "0x1a6,0x1a7", 5410 "MSRValue": "0x08003C0122", 5411 "Offcore": "1", 5412 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5413 "SampleAfterValue": "100003", 5414 "UMask": "0x1" 5415 }, 5416 { 5417 "BriefDescription": "Counts demand data reads DEMAND_DATA_RD & L3_HIT_F & HIT_OTHER_CORE_FWD", 5418 "Counter": "0,1,2,3", 5419 "CounterHTOff": "0,1,2,3", 5420 "EventCode": "0xB7, 0xBB", 5421 "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWD", 5422 "MSRIndex": "0x1a6,0x1a7", 5423 "MSRValue": "0x0800200001", 5424 "Offcore": "1", 5425 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5426 "SampleAfterValue": "100003", 5427 "UMask": "0x1" 5428 }, 5429 { 5430 "BriefDescription": "ALL_DATA_RD & L3_HIT_S & HIT_OTHER_CORE_NO_FWD", 5431 "Counter": "0,1,2,3", 5432 "CounterHTOff": "0,1,2,3", 5433 "EventCode": "0xB7, 0xBB", 5434 "EventName": "OCR.ALL_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", 5435 "MSRIndex": "0x1a6,0x1a7", 5436 "MSRValue": "0x0400100491", 5437 "Offcore": "1", 5438 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5439 "SampleAfterValue": "100003", 5440 "UMask": "0x1" 5441 }, 5442 { 5443 "BriefDescription": "ALL_READS & L3_HIT_M & SNOOP_NONE", 5444 "Counter": "0,1,2,3", 5445 "CounterHTOff": "0,1,2,3", 5446 "EventCode": "0xB7, 0xBB", 5447 "EventName": "OCR.ALL_READS.L3_HIT_M.SNOOP_NONE", 5448 "MSRIndex": "0x1a6,0x1a7", 5449 "MSRValue": "0x00800407F7", 5450 "Offcore": "1", 5451 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5452 "SampleAfterValue": "100003", 5453 "UMask": "0x1" 5454 }, 5455 { 5456 "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs", 5457 "Counter": "0,1,2,3", 5458 "CounterHTOff": "0,1,2,3", 5459 "EventCode": "0xB7, 0xBB", 5460 "EventName": "OCR.PF_L2_RFO.L3_HIT_S.SNOOP_MISS", 5461 "MSRIndex": "0x1a6,0x1a7", 5462 "MSRValue": "0x0200100020", 5463 "Offcore": "1", 5464 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5465 "SampleAfterValue": "100003", 5466 "UMask": "0x1" 5467 }, 5468 { 5469 "BriefDescription": "Core cycles where the core was running in a manner where Turbo may be clipped to the AVX512 turbo schedule.", 5470 "Counter": "0,1,2,3", 5471 "CounterHTOff": "0,1,2,3,4,5,6,7", 5472 "EventCode": "0x28", 5473 "EventName": "CORE_POWER.LVL2_TURBO_LICENSE", 5474 "PublicDescription": "Core cycles where the core was running with power-delivery for license level 2 (introduced in Skylake Server michroarchtecture). This includes high current AVX 512-bit instructions.", 5475 "SampleAfterValue": "200003", 5476 "UMask": "0x20" 5477 }, 5478 { 5479 "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests PF_L1D_AND_SW & L3_HIT & HITM_OTHER_CORE", 5480 "Counter": "0,1,2,3", 5481 "CounterHTOff": "0,1,2,3", 5482 "EventCode": "0xB7, 0xBB", 5483 "EventName": "OCR.PF_L1D_AND_SW.L3_HIT.HITM_OTHER_CORE", 5484 "MSRIndex": "0x1a6,0x1a7", 5485 "MSRValue": "0x10003C0400", 5486 "Offcore": "1", 5487 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5488 "SampleAfterValue": "100003", 5489 "UMask": "0x1" 5490 }, 5491 { 5492 "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.", 5493 "Counter": "0,1,2,3", 5494 "CounterHTOff": "0,1,2,3", 5495 "EventCode": "0xB7, 0xBB", 5496 "EventName": "OCR.PF_L2_RFO.L3_HIT.NO_SNOOP_NEEDED", 5497 "MSRIndex": "0x1a6,0x1a7", 5498 "MSRValue": "0x01003C0020", 5499 "Offcore": "1", 5500 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5501 "SampleAfterValue": "100003", 5502 "UMask": "0x1" 5503 }, 5504 { 5505 "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests PF_L1D_AND_SW & L3_HIT_E & HITM_OTHER_CORE", 5506 "Counter": "0,1,2,3", 5507 "CounterHTOff": "0,1,2,3", 5508 "EventCode": "0xB7, 0xBB", 5509 "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_E.HITM_OTHER_CORE", 5510 "MSRIndex": "0x1a6,0x1a7", 5511 "MSRValue": "0x1000080400", 5512 "Offcore": "1", 5513 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5514 "SampleAfterValue": "100003", 5515 "UMask": "0x1" 5516 }, 5517 { 5518 "BriefDescription": "ALL_PF_RFO & L3_HIT_F & HIT_OTHER_CORE_NO_FWD", 5519 "Counter": "0,1,2,3", 5520 "CounterHTOff": "0,1,2,3", 5521 "EventCode": "0xB7, 0xBB", 5522 "EventName": "OCR.ALL_PF_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", 5523 "MSRIndex": "0x1a6,0x1a7", 5524 "MSRValue": "0x0400200120", 5525 "Offcore": "1", 5526 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5527 "SampleAfterValue": "100003", 5528 "UMask": "0x1" 5529 }, 5530 { 5531 "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads PF_L3_DATA_RD & PMM_HIT_LOCAL_PMM & ANY_SNOOP", 5532 "Counter": "0,1,2,3", 5533 "CounterHTOff": "0,1,2,3", 5534 "EventCode": "0xB7, 0xBB", 5535 "EventName": "OCR.PF_L3_DATA_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOP", 5536 "MSRIndex": "0x1a6,0x1a7", 5537 "MSRValue": "0x3F80400080", 5538 "Offcore": "1", 5539 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5540 "SampleAfterValue": "100003", 5541 "UMask": "0x1" 5542 }, 5543 { 5544 "BriefDescription": "Counts all demand code reads DEMAND_CODE_RD & SUPPLIER_NONE & ANY_SNOOP", 5545 "Counter": "0,1,2,3", 5546 "CounterHTOff": "0,1,2,3", 5547 "EventCode": "0xB7, 0xBB", 5548 "EventName": "OCR.DEMAND_CODE_RD.SUPPLIER_NONE.ANY_SNOOP", 5549 "MSRIndex": "0x1a6,0x1a7", 5550 "MSRValue": "0x3F80020004", 5551 "Offcore": "1", 5552 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5553 "SampleAfterValue": "100003", 5554 "UMask": "0x1" 5555 }, 5556 { 5557 "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests PF_L1D_AND_SW & L3_HIT_S & ANY_SNOOP", 5558 "Counter": "0,1,2,3", 5559 "CounterHTOff": "0,1,2,3", 5560 "EventCode": "0xB7, 0xBB", 5561 "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_S.ANY_SNOOP", 5562 "MSRIndex": "0x1a6,0x1a7", 5563 "MSRValue": "0x3F80100400", 5564 "Offcore": "1", 5565 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5566 "SampleAfterValue": "100003", 5567 "UMask": "0x1" 5568 }, 5569 { 5570 "BriefDescription": "Counts all demand data writes (RFOs) DEMAND_RFO & L3_HIT_E & HIT_OTHER_CORE_FWD", 5571 "Counter": "0,1,2,3", 5572 "CounterHTOff": "0,1,2,3", 5573 "EventCode": "0xB7, 0xBB", 5574 "EventName": "OCR.DEMAND_RFO.L3_HIT_E.HIT_OTHER_CORE_FWD", 5575 "MSRIndex": "0x1a6,0x1a7", 5576 "MSRValue": "0x0800080002", 5577 "Offcore": "1", 5578 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5579 "SampleAfterValue": "100003", 5580 "UMask": "0x1" 5581 }, 5582 { 5583 "BriefDescription": "ALL_PF_RFO & L3_HIT_F & SNOOP_MISS", 5584 "Counter": "0,1,2,3", 5585 "CounterHTOff": "0,1,2,3", 5586 "EventCode": "0xB7, 0xBB", 5587 "EventName": "OCR.ALL_PF_RFO.L3_HIT_F.SNOOP_MISS", 5588 "MSRIndex": "0x1a6,0x1a7", 5589 "MSRValue": "0x0200200120", 5590 "Offcore": "1", 5591 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5592 "SampleAfterValue": "100003", 5593 "UMask": "0x1" 5594 }, 5595 { 5596 "BriefDescription": "Counts all demand code reads DEMAND_CODE_RD & L3_HIT & HIT_OTHER_CORE_NO_FWD", 5597 "Counter": "0,1,2,3", 5598 "CounterHTOff": "0,1,2,3", 5599 "EventCode": "0xB7, 0xBB", 5600 "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD", 5601 "MSRIndex": "0x1a6,0x1a7", 5602 "MSRValue": "0x04003C0004", 5603 "Offcore": "1", 5604 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5605 "SampleAfterValue": "100003", 5606 "UMask": "0x1" 5607 }, 5608 { 5609 "BriefDescription": "ALL_PF_DATA_RD & L3_HIT_F & HIT_OTHER_CORE_NO_FWD", 5610 "Counter": "0,1,2,3", 5611 "CounterHTOff": "0,1,2,3", 5612 "EventCode": "0xB7, 0xBB", 5613 "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", 5614 "MSRIndex": "0x1a6,0x1a7", 5615 "MSRValue": "0x0400200490", 5616 "Offcore": "1", 5617 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5618 "SampleAfterValue": "100003", 5619 "UMask": "0x1" 5620 }, 5621 { 5622 "BriefDescription": "Counts any other requests OTHER & L3_HIT_F & ANY_SNOOP", 5623 "Counter": "0,1,2,3", 5624 "CounterHTOff": "0,1,2,3", 5625 "EventCode": "0xB7, 0xBB", 5626 "EventName": "OCR.OTHER.L3_HIT_F.ANY_SNOOP", 5627 "MSRIndex": "0x1a6,0x1a7", 5628 "MSRValue": "0x3F80208000", 5629 "Offcore": "1", 5630 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5631 "SampleAfterValue": "100003", 5632 "UMask": "0x1" 5633 }, 5634 { 5635 "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests", 5636 "Counter": "0,1,2,3", 5637 "CounterHTOff": "0,1,2,3", 5638 "EventCode": "0xB7, 0xBB", 5639 "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_S.SNOOP_NONE", 5640 "MSRIndex": "0x1a6,0x1a7", 5641 "MSRValue": "0x0080100400", 5642 "Offcore": "1", 5643 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5644 "SampleAfterValue": "100003", 5645 "UMask": "0x1" 5646 }, 5647 { 5648 "BriefDescription": "ALL_READS & SUPPLIER_NONE & NO_SNOOP_NEEDED", 5649 "Counter": "0,1,2,3", 5650 "CounterHTOff": "0,1,2,3", 5651 "EventCode": "0xB7, 0xBB", 5652 "EventName": "OCR.ALL_READS.SUPPLIER_NONE.NO_SNOOP_NEEDED", 5653 "MSRIndex": "0x1a6,0x1a7", 5654 "MSRValue": "0x01000207F7", 5655 "Offcore": "1", 5656 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5657 "SampleAfterValue": "100003", 5658 "UMask": "0x1" 5659 }, 5660 { 5661 "BriefDescription": "ALL_PF_DATA_RD & L3_HIT_F & SNOOP_NONE", 5662 "Counter": "0,1,2,3", 5663 "CounterHTOff": "0,1,2,3", 5664 "EventCode": "0xB7, 0xBB", 5665 "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_F.SNOOP_NONE", 5666 "MSRIndex": "0x1a6,0x1a7", 5667 "MSRValue": "0x0080200490", 5668 "Offcore": "1", 5669 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5670 "SampleAfterValue": "100003", 5671 "UMask": "0x1" 5672 }, 5673 { 5674 "BriefDescription": "Counts all demand data writes (RFOs) DEMAND_RFO & L3_HIT_S & HIT_OTHER_CORE_FWD", 5675 "Counter": "0,1,2,3", 5676 "CounterHTOff": "0,1,2,3", 5677 "EventCode": "0xB7, 0xBB", 5678 "EventName": "OCR.DEMAND_RFO.L3_HIT_S.HIT_OTHER_CORE_FWD", 5679 "MSRIndex": "0x1a6,0x1a7", 5680 "MSRValue": "0x0800100002", 5681 "Offcore": "1", 5682 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5683 "SampleAfterValue": "100003", 5684 "UMask": "0x1" 5685 }, 5686 { 5687 "BriefDescription": "ALL_READS & L3_HIT_F & SNOOP_NONE", 5688 "Counter": "0,1,2,3", 5689 "CounterHTOff": "0,1,2,3", 5690 "EventCode": "0xB7, 0xBB", 5691 "EventName": "OCR.ALL_READS.L3_HIT_F.SNOOP_NONE", 5692 "MSRIndex": "0x1a6,0x1a7", 5693 "MSRValue": "0x00802007F7", 5694 "Offcore": "1", 5695 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5696 "SampleAfterValue": "100003", 5697 "UMask": "0x1" 5698 }, 5699 { 5700 "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests PF_L1D_AND_SW & L3_HIT & ANY_SNOOP", 5701 "Counter": "0,1,2,3", 5702 "CounterHTOff": "0,1,2,3", 5703 "EventCode": "0xB7, 0xBB", 5704 "EventName": "OCR.PF_L1D_AND_SW.L3_HIT.ANY_SNOOP", 5705 "MSRIndex": "0x1a6,0x1a7", 5706 "MSRValue": "0x3F803C0400", 5707 "Offcore": "1", 5708 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5709 "SampleAfterValue": "100003", 5710 "UMask": "0x1" 5711 }, 5712 { 5713 "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads PF_L3_DATA_RD & L3_HIT & HITM_OTHER_CORE", 5714 "Counter": "0,1,2,3", 5715 "CounterHTOff": "0,1,2,3", 5716 "EventCode": "0xB7, 0xBB", 5717 "EventName": "OCR.PF_L3_DATA_RD.L3_HIT.HITM_OTHER_CORE", 5718 "MSRIndex": "0x1a6,0x1a7", 5719 "MSRValue": "0x10003C0080", 5720 "Offcore": "1", 5721 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5722 "SampleAfterValue": "100003", 5723 "UMask": "0x1" 5724 }, 5725 { 5726 "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs PF_L3_RFO & L3_HIT_S & HIT_OTHER_CORE_NO_FWD", 5727 "Counter": "0,1,2,3", 5728 "CounterHTOff": "0,1,2,3", 5729 "EventCode": "0xB7, 0xBB", 5730 "EventName": "OCR.PF_L3_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", 5731 "MSRIndex": "0x1a6,0x1a7", 5732 "MSRValue": "0x0400100100", 5733 "Offcore": "1", 5734 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5735 "SampleAfterValue": "100003", 5736 "UMask": "0x1" 5737 }, 5738 { 5739 "BriefDescription": "Counts prefetch (that bring data to L2) data reads PF_L2_DATA_RD & L3_HIT_F & NO_SNOOP_NEEDED", 5740 "Counter": "0,1,2,3", 5741 "CounterHTOff": "0,1,2,3", 5742 "EventCode": "0xB7, 0xBB", 5743 "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDED", 5744 "MSRIndex": "0x1a6,0x1a7", 5745 "MSRValue": "0x0100200010", 5746 "Offcore": "1", 5747 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5748 "SampleAfterValue": "100003", 5749 "UMask": "0x1" 5750 }, 5751 { 5752 "BriefDescription": "ALL_PF_RFO & L3_HIT_M & HITM_OTHER_CORE", 5753 "Counter": "0,1,2,3", 5754 "CounterHTOff": "0,1,2,3", 5755 "EventCode": "0xB7, 0xBB", 5756 "EventName": "OCR.ALL_PF_RFO.L3_HIT_M.HITM_OTHER_CORE", 5757 "MSRIndex": "0x1a6,0x1a7", 5758 "MSRValue": "0x1000040120", 5759 "Offcore": "1", 5760 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5761 "SampleAfterValue": "100003", 5762 "UMask": "0x1" 5763 }, 5764 { 5765 "BriefDescription": "Counts all demand code reads DEMAND_CODE_RD & L3_HIT_F & HITM_OTHER_CORE", 5766 "Counter": "0,1,2,3", 5767 "CounterHTOff": "0,1,2,3", 5768 "EventCode": "0xB7, 0xBB", 5769 "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_F.HITM_OTHER_CORE", 5770 "MSRIndex": "0x1a6,0x1a7", 5771 "MSRValue": "0x1000200004", 5772 "Offcore": "1", 5773 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5774 "SampleAfterValue": "100003", 5775 "UMask": "0x1" 5776 }, 5777 { 5778 "BriefDescription": "Counts all demand data writes (RFOs) DEMAND_RFO & L3_HIT & HIT_OTHER_CORE_FWD", 5779 "Counter": "0,1,2,3", 5780 "CounterHTOff": "0,1,2,3", 5781 "EventCode": "0xB7, 0xBB", 5782 "EventName": "OCR.DEMAND_RFO.L3_HIT.HIT_OTHER_CORE_FWD", 5783 "MSRIndex": "0x1a6,0x1a7", 5784 "MSRValue": "0x08003C0002", 5785 "Offcore": "1", 5786 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5787 "SampleAfterValue": "100003", 5788 "UMask": "0x1" 5789 }, 5790 { 5791 "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads PF_L3_DATA_RD & L3_HIT_F & HIT_OTHER_CORE_FWD", 5792 "Counter": "0,1,2,3", 5793 "CounterHTOff": "0,1,2,3", 5794 "EventCode": "0xB7, 0xBB", 5795 "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWD", 5796 "MSRIndex": "0x1a6,0x1a7", 5797 "MSRValue": "0x0800200080", 5798 "Offcore": "1", 5799 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5800 "SampleAfterValue": "100003", 5801 "UMask": "0x1" 5802 }, 5803 { 5804 "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads PF_L3_DATA_RD & L3_HIT_M & HIT_OTHER_CORE_FWD", 5805 "Counter": "0,1,2,3", 5806 "CounterHTOff": "0,1,2,3", 5807 "EventCode": "0xB7, 0xBB", 5808 "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWD", 5809 "MSRIndex": "0x1a6,0x1a7", 5810 "MSRValue": "0x0800040080", 5811 "Offcore": "1", 5812 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5813 "SampleAfterValue": "100003", 5814 "UMask": "0x1" 5815 }, 5816 { 5817 "BriefDescription": "ALL_PF_DATA_RD & PMM_HIT_LOCAL_PMM & ANY_SNOOP", 5818 "Counter": "0,1,2,3", 5819 "CounterHTOff": "0,1,2,3", 5820 "EventCode": "0xB7, 0xBB", 5821 "EventName": "OCR.ALL_PF_DATA_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOP", 5822 "MSRIndex": "0x1a6,0x1a7", 5823 "MSRValue": "0x3F80400490", 5824 "Offcore": "1", 5825 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5826 "SampleAfterValue": "100003", 5827 "UMask": "0x1" 5828 }, 5829 { 5830 "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests PF_L1D_AND_SW & SUPPLIER_NONE & HIT_OTHER_CORE_FWD", 5831 "Counter": "0,1,2,3", 5832 "CounterHTOff": "0,1,2,3", 5833 "EventCode": "0xB7, 0xBB", 5834 "EventName": "OCR.PF_L1D_AND_SW.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", 5835 "MSRIndex": "0x1a6,0x1a7", 5836 "MSRValue": "0x0800020400", 5837 "Offcore": "1", 5838 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5839 "SampleAfterValue": "100003", 5840 "UMask": "0x1" 5841 }, 5842 { 5843 "BriefDescription": "ALL_DATA_RD & L3_HIT & SNOOP_NONE", 5844 "Counter": "0,1,2,3", 5845 "CounterHTOff": "0,1,2,3", 5846 "EventCode": "0xB7, 0xBB", 5847 "EventName": "OCR.ALL_DATA_RD.L3_HIT.SNOOP_NONE", 5848 "MSRIndex": "0x1a6,0x1a7", 5849 "MSRValue": "0x00803C0491", 5850 "Offcore": "1", 5851 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5852 "SampleAfterValue": "100003", 5853 "UMask": "0x1" 5854 }, 5855 { 5856 "BriefDescription": "Counts all demand data writes (RFOs) DEMAND_RFO & L3_HIT_S & ANY_SNOOP", 5857 "Counter": "0,1,2,3", 5858 "CounterHTOff": "0,1,2,3", 5859 "EventCode": "0xB7, 0xBB", 5860 "EventName": "OCR.DEMAND_RFO.L3_HIT_S.ANY_SNOOP", 5861 "MSRIndex": "0x1a6,0x1a7", 5862 "MSRValue": "0x3F80100002", 5863 "Offcore": "1", 5864 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5865 "SampleAfterValue": "100003", 5866 "UMask": "0x1" 5867 }, 5868 { 5869 "BriefDescription": "ALL_RFO & L3_HIT_S & SNOOP_MISS", 5870 "Counter": "0,1,2,3", 5871 "CounterHTOff": "0,1,2,3", 5872 "EventCode": "0xB7, 0xBB", 5873 "EventName": "OCR.ALL_RFO.L3_HIT_S.SNOOP_MISS", 5874 "MSRIndex": "0x1a6,0x1a7", 5875 "MSRValue": "0x0200100122", 5876 "Offcore": "1", 5877 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5878 "SampleAfterValue": "100003", 5879 "UMask": "0x1" 5880 }, 5881 { 5882 "BriefDescription": "ALL_PF_DATA_RD & L3_HIT_E & ANY_SNOOP", 5883 "Counter": "0,1,2,3", 5884 "CounterHTOff": "0,1,2,3", 5885 "EventCode": "0xB7, 0xBB", 5886 "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_E.ANY_SNOOP", 5887 "MSRIndex": "0x1a6,0x1a7", 5888 "MSRValue": "0x3F80080490", 5889 "Offcore": "1", 5890 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5891 "SampleAfterValue": "100003", 5892 "UMask": "0x1" 5893 }, 5894 { 5895 "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads", 5896 "Counter": "0,1,2,3", 5897 "CounterHTOff": "0,1,2,3", 5898 "EventCode": "0xB7, 0xBB", 5899 "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_E.SNOOP_MISS", 5900 "MSRIndex": "0x1a6,0x1a7", 5901 "MSRValue": "0x0200080080", 5902 "Offcore": "1", 5903 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5904 "SampleAfterValue": "100003", 5905 "UMask": "0x1" 5906 }, 5907 { 5908 "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs PF_L2_RFO & L3_HIT_M & HIT_OTHER_CORE_NO_FWD", 5909 "Counter": "0,1,2,3", 5910 "CounterHTOff": "0,1,2,3", 5911 "EventCode": "0xB7, 0xBB", 5912 "EventName": "OCR.PF_L2_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", 5913 "MSRIndex": "0x1a6,0x1a7", 5914 "MSRValue": "0x0400040020", 5915 "Offcore": "1", 5916 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5917 "SampleAfterValue": "100003", 5918 "UMask": "0x1" 5919 }, 5920 { 5921 "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs PF_L3_RFO & L3_HIT & ANY_SNOOP", 5922 "Counter": "0,1,2,3", 5923 "CounterHTOff": "0,1,2,3", 5924 "EventCode": "0xB7, 0xBB", 5925 "EventName": "OCR.PF_L3_RFO.L3_HIT.ANY_SNOOP", 5926 "MSRIndex": "0x1a6,0x1a7", 5927 "MSRValue": "0x3F803C0100", 5928 "Offcore": "1", 5929 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5930 "SampleAfterValue": "100003", 5931 "UMask": "0x1" 5932 }, 5933 { 5934 "BriefDescription": "ALL_DATA_RD & L3_HIT_M & SNOOP_MISS", 5935 "Counter": "0,1,2,3", 5936 "CounterHTOff": "0,1,2,3", 5937 "EventCode": "0xB7, 0xBB", 5938 "EventName": "OCR.ALL_DATA_RD.L3_HIT_M.SNOOP_MISS", 5939 "MSRIndex": "0x1a6,0x1a7", 5940 "MSRValue": "0x0200040491", 5941 "Offcore": "1", 5942 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5943 "SampleAfterValue": "100003", 5944 "UMask": "0x1" 5945 }, 5946 { 5947 "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads", 5948 "Counter": "0,1,2,3", 5949 "CounterHTOff": "0,1,2,3", 5950 "EventCode": "0xB7, 0xBB", 5951 "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_M.SNOOP_NONE", 5952 "MSRIndex": "0x1a6,0x1a7", 5953 "MSRValue": "0x0080040080", 5954 "Offcore": "1", 5955 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5956 "SampleAfterValue": "100003", 5957 "UMask": "0x1" 5958 }, 5959 { 5960 "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.", 5961 "Counter": "0,1,2,3", 5962 "CounterHTOff": "0,1,2,3", 5963 "EventCode": "0xB7, 0xBB", 5964 "EventName": "OCR.PF_L3_RFO.L3_HIT.NO_SNOOP_NEEDED", 5965 "MSRIndex": "0x1a6,0x1a7", 5966 "MSRValue": "0x01003C0100", 5967 "Offcore": "1", 5968 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5969 "SampleAfterValue": "100003", 5970 "UMask": "0x1" 5971 }, 5972 { 5973 "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads PF_L3_DATA_RD & PMM_HIT_LOCAL_PMM & SNOOP_NONE", 5974 "Counter": "0,1,2,3", 5975 "CounterHTOff": "0,1,2,3", 5976 "EventCode": "0xB7, 0xBB", 5977 "EventName": "OCR.PF_L3_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE", 5978 "MSRIndex": "0x1a6,0x1a7", 5979 "MSRValue": "0x0080400080", 5980 "Offcore": "1", 5981 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5982 "SampleAfterValue": "100003", 5983 "UMask": "0x1" 5984 }, 5985 { 5986 "BriefDescription": "ALL_PF_RFO & L3_HIT_F & HIT_OTHER_CORE_FWD", 5987 "Counter": "0,1,2,3", 5988 "CounterHTOff": "0,1,2,3", 5989 "EventCode": "0xB7, 0xBB", 5990 "EventName": "OCR.ALL_PF_RFO.L3_HIT_F.HIT_OTHER_CORE_FWD", 5991 "MSRIndex": "0x1a6,0x1a7", 5992 "MSRValue": "0x0800200120", 5993 "Offcore": "1", 5994 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5995 "SampleAfterValue": "100003", 5996 "UMask": "0x1" 5997 }, 5998 { 5999 "BriefDescription": "ALL_PF_RFO & L3_HIT_E & SNOOP_NONE", 6000 "Counter": "0,1,2,3", 6001 "CounterHTOff": "0,1,2,3", 6002 "EventCode": "0xB7, 0xBB", 6003 "EventName": "OCR.ALL_PF_RFO.L3_HIT_E.SNOOP_NONE", 6004 "MSRIndex": "0x1a6,0x1a7", 6005 "MSRValue": "0x0080080120", 6006 "Offcore": "1", 6007 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6008 "SampleAfterValue": "100003", 6009 "UMask": "0x1" 6010 }, 6011 { 6012 "BriefDescription": "Counts all demand data writes (RFOs) DEMAND_RFO & L3_HIT_E & HITM_OTHER_CORE", 6013 "Counter": "0,1,2,3", 6014 "CounterHTOff": "0,1,2,3", 6015 "EventCode": "0xB7, 0xBB", 6016 "EventName": "OCR.DEMAND_RFO.L3_HIT_E.HITM_OTHER_CORE", 6017 "MSRIndex": "0x1a6,0x1a7", 6018 "MSRValue": "0x1000080002", 6019 "Offcore": "1", 6020 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6021 "SampleAfterValue": "100003", 6022 "UMask": "0x1" 6023 }, 6024 { 6025 "BriefDescription": "ALL_PF_DATA_RD & L3_HIT_M & SNOOP_MISS", 6026 "Counter": "0,1,2,3", 6027 "CounterHTOff": "0,1,2,3", 6028 "EventCode": "0xB7, 0xBB", 6029 "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_M.SNOOP_MISS", 6030 "MSRIndex": "0x1a6,0x1a7", 6031 "MSRValue": "0x0200040490", 6032 "Offcore": "1", 6033 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6034 "SampleAfterValue": "100003", 6035 "UMask": "0x1" 6036 }, 6037 { 6038 "BriefDescription": "Counts all demand data writes (RFOs) DEMAND_RFO & L3_HIT_E & NO_SNOOP_NEEDED", 6039 "Counter": "0,1,2,3", 6040 "CounterHTOff": "0,1,2,3", 6041 "EventCode": "0xB7, 0xBB", 6042 "EventName": "OCR.DEMAND_RFO.L3_HIT_E.NO_SNOOP_NEEDED", 6043 "MSRIndex": "0x1a6,0x1a7", 6044 "MSRValue": "0x0100080002", 6045 "Offcore": "1", 6046 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6047 "SampleAfterValue": "100003", 6048 "UMask": "0x1" 6049 }, 6050 { 6051 "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs PF_L2_RFO & SUPPLIER_NONE & HIT_OTHER_CORE_FWD", 6052 "Counter": "0,1,2,3", 6053 "CounterHTOff": "0,1,2,3", 6054 "EventCode": "0xB7, 0xBB", 6055 "EventName": "OCR.PF_L2_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", 6056 "MSRIndex": "0x1a6,0x1a7", 6057 "MSRValue": "0x0800020020", 6058 "Offcore": "1", 6059 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6060 "SampleAfterValue": "100003", 6061 "UMask": "0x1" 6062 }, 6063 { 6064 "BriefDescription": "Counts any other requests", 6065 "Counter": "0,1,2,3", 6066 "CounterHTOff": "0,1,2,3", 6067 "EventCode": "0xB7, 0xBB", 6068 "EventName": "OCR.OTHER.L3_HIT_M.SNOOP_NONE", 6069 "MSRIndex": "0x1a6,0x1a7", 6070 "MSRValue": "0x0080048000", 6071 "Offcore": "1", 6072 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6073 "SampleAfterValue": "100003", 6074 "UMask": "0x1" 6075 }, 6076 { 6077 "BriefDescription": "Counts all demand data writes (RFOs) DEMAND_RFO & L3_HIT_E & HIT_OTHER_CORE_NO_FWD", 6078 "Counter": "0,1,2,3", 6079 "CounterHTOff": "0,1,2,3", 6080 "EventCode": "0xB7, 0xBB", 6081 "EventName": "OCR.DEMAND_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", 6082 "MSRIndex": "0x1a6,0x1a7", 6083 "MSRValue": "0x0400080002", 6084 "Offcore": "1", 6085 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6086 "SampleAfterValue": "100003", 6087 "UMask": "0x1" 6088 }, 6089 { 6090 "BriefDescription": "Counts demand data reads", 6091 "Counter": "0,1,2,3", 6092 "CounterHTOff": "0,1,2,3", 6093 "EventCode": "0xB7, 0xBB", 6094 "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_E.SNOOP_MISS", 6095 "MSRIndex": "0x1a6,0x1a7", 6096 "MSRValue": "0x0200080001", 6097 "Offcore": "1", 6098 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6099 "SampleAfterValue": "100003", 6100 "UMask": "0x1" 6101 }, 6102 { 6103 "BriefDescription": "ALL_RFO & L3_HIT_F & NO_SNOOP_NEEDED", 6104 "Counter": "0,1,2,3", 6105 "CounterHTOff": "0,1,2,3", 6106 "EventCode": "0xB7, 0xBB", 6107 "EventName": "OCR.ALL_RFO.L3_HIT_F.NO_SNOOP_NEEDED", 6108 "MSRIndex": "0x1a6,0x1a7", 6109 "MSRValue": "0x0100200122", 6110 "Offcore": "1", 6111 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6112 "SampleAfterValue": "100003", 6113 "UMask": "0x1" 6114 }, 6115 { 6116 "BriefDescription": "ALL_PF_DATA_RD & L3_HIT_E & NO_SNOOP_NEEDED", 6117 "Counter": "0,1,2,3", 6118 "CounterHTOff": "0,1,2,3", 6119 "EventCode": "0xB7, 0xBB", 6120 "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDED", 6121 "MSRIndex": "0x1a6,0x1a7", 6122 "MSRValue": "0x0100080490", 6123 "Offcore": "1", 6124 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6125 "SampleAfterValue": "100003", 6126 "UMask": "0x1" 6127 }, 6128 { 6129 "BriefDescription": "Counts all demand code reads", 6130 "Counter": "0,1,2,3", 6131 "CounterHTOff": "0,1,2,3", 6132 "EventCode": "0xB7, 0xBB", 6133 "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_M.SNOOP_MISS", 6134 "MSRIndex": "0x1a6,0x1a7", 6135 "MSRValue": "0x0200040004", 6136 "Offcore": "1", 6137 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6138 "SampleAfterValue": "100003", 6139 "UMask": "0x1" 6140 }, 6141 { 6142 "BriefDescription": "Counts all demand data writes (RFOs) DEMAND_RFO & L3_HIT_M & HIT_OTHER_CORE_NO_FWD", 6143 "Counter": "0,1,2,3", 6144 "CounterHTOff": "0,1,2,3", 6145 "EventCode": "0xB7, 0xBB", 6146 "EventName": "OCR.DEMAND_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", 6147 "MSRIndex": "0x1a6,0x1a7", 6148 "MSRValue": "0x0400040002", 6149 "Offcore": "1", 6150 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6151 "SampleAfterValue": "100003", 6152 "UMask": "0x1" 6153 }, 6154 { 6155 "BriefDescription": "Counts demand data reads DEMAND_DATA_RD & L3_HIT_M & HITM_OTHER_CORE", 6156 "Counter": "0,1,2,3", 6157 "CounterHTOff": "0,1,2,3", 6158 "EventCode": "0xB7, 0xBB", 6159 "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_M.HITM_OTHER_CORE", 6160 "MSRIndex": "0x1a6,0x1a7", 6161 "MSRValue": "0x1000040001", 6162 "Offcore": "1", 6163 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6164 "SampleAfterValue": "100003", 6165 "UMask": "0x1" 6166 }, 6167 { 6168 "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests PF_L1D_AND_SW & L3_HIT_F & HITM_OTHER_CORE", 6169 "Counter": "0,1,2,3", 6170 "CounterHTOff": "0,1,2,3", 6171 "EventCode": "0xB7, 0xBB", 6172 "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_F.HITM_OTHER_CORE", 6173 "MSRIndex": "0x1a6,0x1a7", 6174 "MSRValue": "0x1000200400", 6175 "Offcore": "1", 6176 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6177 "SampleAfterValue": "100003", 6178 "UMask": "0x1" 6179 }, 6180 { 6181 "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests", 6182 "Counter": "0,1,2,3", 6183 "CounterHTOff": "0,1,2,3", 6184 "EventCode": "0xB7, 0xBB", 6185 "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_S.SNOOP_MISS", 6186 "MSRIndex": "0x1a6,0x1a7", 6187 "MSRValue": "0x0200100400", 6188 "Offcore": "1", 6189 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6190 "SampleAfterValue": "100003", 6191 "UMask": "0x1" 6192 }, 6193 { 6194 "BriefDescription": "Counts demand data reads DEMAND_DATA_RD & PMM_HIT_LOCAL_PMM & SNOOP_NOT_NEEDED", 6195 "Counter": "0,1,2,3", 6196 "CounterHTOff": "0,1,2,3", 6197 "EventCode": "0xB7, 0xBB", 6198 "EventName": "OCR.DEMAND_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", 6199 "MSRIndex": "0x1a6,0x1a7", 6200 "MSRValue": "0x0100400001", 6201 "Offcore": "1", 6202 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6203 "SampleAfterValue": "100003", 6204 "UMask": "0x1" 6205 }, 6206 { 6207 "BriefDescription": "ALL_RFO & L3_HIT_M & NO_SNOOP_NEEDED", 6208 "Counter": "0,1,2,3", 6209 "CounterHTOff": "0,1,2,3", 6210 "EventCode": "0xB7, 0xBB", 6211 "EventName": "OCR.ALL_RFO.L3_HIT_M.NO_SNOOP_NEEDED", 6212 "MSRIndex": "0x1a6,0x1a7", 6213 "MSRValue": "0x0100040122", 6214 "Offcore": "1", 6215 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6216 "SampleAfterValue": "100003", 6217 "UMask": "0x1" 6218 }, 6219 { 6220 "BriefDescription": "Counts demand data reads DEMAND_DATA_RD & PMM_HIT_LOCAL_PMM & ANY_SNOOP", 6221 "Counter": "0,1,2,3", 6222 "CounterHTOff": "0,1,2,3", 6223 "EventCode": "0xB7, 0xBB", 6224 "EventName": "OCR.DEMAND_DATA_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOP", 6225 "MSRIndex": "0x1a6,0x1a7", 6226 "MSRValue": "0x3F80400001", 6227 "Offcore": "1", 6228 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6229 "SampleAfterValue": "100003", 6230 "UMask": "0x1" 6231 }, 6232 { 6233 "BriefDescription": "ALL_DATA_RD & L3_HIT_F & NO_SNOOP_NEEDED", 6234 "Counter": "0,1,2,3", 6235 "CounterHTOff": "0,1,2,3", 6236 "EventCode": "0xB7, 0xBB", 6237 "EventName": "OCR.ALL_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDED", 6238 "MSRIndex": "0x1a6,0x1a7", 6239 "MSRValue": "0x0100200491", 6240 "Offcore": "1", 6241 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6242 "SampleAfterValue": "100003", 6243 "UMask": "0x1" 6244 }, 6245 { 6246 "BriefDescription": "Counts all demand data writes (RFOs) DEMAND_RFO & PMM_HIT_LOCAL_PMM & ANY_SNOOP", 6247 "Counter": "0,1,2,3", 6248 "CounterHTOff": "0,1,2,3", 6249 "EventCode": "0xB7, 0xBB", 6250 "EventName": "OCR.DEMAND_RFO.PMM_HIT_LOCAL_PMM.ANY_SNOOP", 6251 "MSRIndex": "0x1a6,0x1a7", 6252 "MSRValue": "0x3F80400002", 6253 "Offcore": "1", 6254 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6255 "SampleAfterValue": "100003", 6256 "UMask": "0x1" 6257 }, 6258 { 6259 "BriefDescription": "Counts prefetch (that bring data to L2) data reads PF_L2_DATA_RD & PMM_HIT_LOCAL_PMM & ANY_SNOOP", 6260 "Counter": "0,1,2,3", 6261 "CounterHTOff": "0,1,2,3", 6262 "EventCode": "0xB7, 0xBB", 6263 "EventName": "OCR.PF_L2_DATA_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOP", 6264 "MSRIndex": "0x1a6,0x1a7", 6265 "MSRValue": "0x3F80400010", 6266 "Offcore": "1", 6267 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6268 "SampleAfterValue": "100003", 6269 "UMask": "0x1" 6270 }, 6271 { 6272 "BriefDescription": "Counts any other requests OTHER & L3_HIT & ANY_SNOOP", 6273 "Counter": "0,1,2,3", 6274 "CounterHTOff": "0,1,2,3", 6275 "EventCode": "0xB7, 0xBB", 6276 "EventName": "OCR.OTHER.L3_HIT.ANY_SNOOP", 6277 "MSRIndex": "0x1a6,0x1a7", 6278 "MSRValue": "0x3F803C8000", 6279 "Offcore": "1", 6280 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6281 "SampleAfterValue": "100003", 6282 "UMask": "0x1" 6283 }, 6284 { 6285 "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads PF_L3_DATA_RD & L3_HIT_F & NO_SNOOP_NEEDED", 6286 "Counter": "0,1,2,3", 6287 "CounterHTOff": "0,1,2,3", 6288 "EventCode": "0xB7, 0xBB", 6289 "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDED", 6290 "MSRIndex": "0x1a6,0x1a7", 6291 "MSRValue": "0x0100200080", 6292 "Offcore": "1", 6293 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6294 "SampleAfterValue": "100003", 6295 "UMask": "0x1" 6296 }, 6297 { 6298 "BriefDescription": "ALL_PF_RFO & L3_HIT_S & SNOOP_MISS", 6299 "Counter": "0,1,2,3", 6300 "CounterHTOff": "0,1,2,3", 6301 "EventCode": "0xB7, 0xBB", 6302 "EventName": "OCR.ALL_PF_RFO.L3_HIT_S.SNOOP_MISS", 6303 "MSRIndex": "0x1a6,0x1a7", 6304 "MSRValue": "0x0200100120", 6305 "Offcore": "1", 6306 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6307 "SampleAfterValue": "100003", 6308 "UMask": "0x1" 6309 }, 6310 { 6311 "BriefDescription": "Counts prefetch (that bring data to L2) data reads PF_L2_DATA_RD & L3_HIT & HITM_OTHER_CORE", 6312 "Counter": "0,1,2,3", 6313 "CounterHTOff": "0,1,2,3", 6314 "EventCode": "0xB7, 0xBB", 6315 "EventName": "OCR.PF_L2_DATA_RD.L3_HIT.HITM_OTHER_CORE", 6316 "MSRIndex": "0x1a6,0x1a7", 6317 "MSRValue": "0x10003C0010", 6318 "Offcore": "1", 6319 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6320 "SampleAfterValue": "100003", 6321 "UMask": "0x1" 6322 }, 6323 { 6324 "BriefDescription": "ALL_READS & L3_HIT_E & HITM_OTHER_CORE", 6325 "Counter": "0,1,2,3", 6326 "CounterHTOff": "0,1,2,3", 6327 "EventCode": "0xB7, 0xBB", 6328 "EventName": "OCR.ALL_READS.L3_HIT_E.HITM_OTHER_CORE", 6329 "MSRIndex": "0x1a6,0x1a7", 6330 "MSRValue": "0x10000807F7", 6331 "Offcore": "1", 6332 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6333 "SampleAfterValue": "100003", 6334 "UMask": "0x1" 6335 }, 6336 { 6337 "BriefDescription": "Counts prefetch (that bring data to L2) data reads", 6338 "Counter": "0,1,2,3", 6339 "CounterHTOff": "0,1,2,3", 6340 "EventCode": "0xB7, 0xBB", 6341 "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_S.SNOOP_NONE", 6342 "MSRIndex": "0x1a6,0x1a7", 6343 "MSRValue": "0x0080100010", 6344 "Offcore": "1", 6345 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6346 "SampleAfterValue": "100003", 6347 "UMask": "0x1" 6348 }, 6349 { 6350 "BriefDescription": "Counts all demand code reads DEMAND_CODE_RD & PMM_HIT_LOCAL_PMM & ANY_SNOOP", 6351 "Counter": "0,1,2,3", 6352 "CounterHTOff": "0,1,2,3", 6353 "EventCode": "0xB7, 0xBB", 6354 "EventName": "OCR.DEMAND_CODE_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOP", 6355 "MSRIndex": "0x1a6,0x1a7", 6356 "MSRValue": "0x3F80400004", 6357 "Offcore": "1", 6358 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6359 "SampleAfterValue": "100003", 6360 "UMask": "0x1" 6361 }, 6362 { 6363 "BriefDescription": "ALL_DATA_RD & L3_HIT_E & HIT_OTHER_CORE_NO_FWD", 6364 "Counter": "0,1,2,3", 6365 "CounterHTOff": "0,1,2,3", 6366 "EventCode": "0xB7, 0xBB", 6367 "EventName": "OCR.ALL_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", 6368 "MSRIndex": "0x1a6,0x1a7", 6369 "MSRValue": "0x0400080491", 6370 "Offcore": "1", 6371 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6372 "SampleAfterValue": "100003", 6373 "UMask": "0x1" 6374 }, 6375 { 6376 "BriefDescription": "Counts demand data reads DEMAND_DATA_RD & SUPPLIER_NONE & HIT_OTHER_CORE_FWD", 6377 "Counter": "0,1,2,3", 6378 "CounterHTOff": "0,1,2,3", 6379 "EventCode": "0xB7, 0xBB", 6380 "EventName": "OCR.DEMAND_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", 6381 "MSRIndex": "0x1a6,0x1a7", 6382 "MSRValue": "0x0800020001", 6383 "Offcore": "1", 6384 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6385 "SampleAfterValue": "100003", 6386 "UMask": "0x1" 6387 }, 6388 { 6389 "BriefDescription": "Counts any other requests OTHER & L3_HIT_F & HIT_OTHER_CORE_FWD", 6390 "Counter": "0,1,2,3", 6391 "CounterHTOff": "0,1,2,3", 6392 "EventCode": "0xB7, 0xBB", 6393 "EventName": "OCR.OTHER.L3_HIT_F.HIT_OTHER_CORE_FWD", 6394 "MSRIndex": "0x1a6,0x1a7", 6395 "MSRValue": "0x0800208000", 6396 "Offcore": "1", 6397 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6398 "SampleAfterValue": "100003", 6399 "UMask": "0x1" 6400 }, 6401 { 6402 "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs", 6403 "Counter": "0,1,2,3", 6404 "CounterHTOff": "0,1,2,3", 6405 "EventCode": "0xB7, 0xBB", 6406 "EventName": "OCR.PF_L3_RFO.SUPPLIER_NONE.SNOOP_NONE", 6407 "MSRIndex": "0x1a6,0x1a7", 6408 "MSRValue": "0x0080020100", 6409 "Offcore": "1", 6410 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6411 "SampleAfterValue": "100003", 6412 "UMask": "0x1" 6413 }, 6414 { 6415 "BriefDescription": "Counts demand data reads DEMAND_DATA_RD & L3_HIT & ANY_SNOOP", 6416 "Counter": "0,1,2,3", 6417 "CounterHTOff": "0,1,2,3", 6418 "EventCode": "0xB7, 0xBB", 6419 "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.ANY_SNOOP", 6420 "MSRIndex": "0x1a6,0x1a7", 6421 "MSRValue": "0x3F803C0001", 6422 "Offcore": "1", 6423 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6424 "SampleAfterValue": "100003", 6425 "UMask": "0x1" 6426 }, 6427 { 6428 "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads", 6429 "Counter": "0,1,2,3", 6430 "CounterHTOff": "0,1,2,3", 6431 "EventCode": "0xB7, 0xBB", 6432 "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_M.SNOOP_MISS", 6433 "MSRIndex": "0x1a6,0x1a7", 6434 "MSRValue": "0x0200040080", 6435 "Offcore": "1", 6436 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6437 "SampleAfterValue": "100003", 6438 "UMask": "0x1" 6439 }, 6440 { 6441 "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests PF_L1D_AND_SW & L3_HIT & SNOOP_MISS", 6442 "Counter": "0,1,2,3", 6443 "CounterHTOff": "0,1,2,3", 6444 "EventCode": "0xB7, 0xBB", 6445 "EventName": "OCR.PF_L1D_AND_SW.L3_HIT.SNOOP_MISS", 6446 "MSRIndex": "0x1a6,0x1a7", 6447 "MSRValue": "0x02003C0400", 6448 "Offcore": "1", 6449 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6450 "SampleAfterValue": "100003", 6451 "UMask": "0x1" 6452 }, 6453 { 6454 "BriefDescription": "ALL_PF_RFO & L3_HIT & SNOOP_HIT_WITH_FWD", 6455 "Counter": "0,1,2,3", 6456 "CounterHTOff": "0,1,2,3", 6457 "EventCode": "0xB7, 0xBB", 6458 "EventName": "OCR.ALL_PF_RFO.L3_HIT.SNOOP_HIT_WITH_FWD", 6459 "MSRIndex": "0x1a6,0x1a7", 6460 "MSRValue": "0x08007C0120", 6461 "Offcore": "1", 6462 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6463 "SampleAfterValue": "100003", 6464 "UMask": "0x1" 6465 }, 6466 { 6467 "BriefDescription": "ALL_PF_RFO & SUPPLIER_NONE & HITM_OTHER_CORE", 6468 "Counter": "0,1,2,3", 6469 "CounterHTOff": "0,1,2,3", 6470 "EventCode": "0xB7, 0xBB", 6471 "EventName": "OCR.ALL_PF_RFO.SUPPLIER_NONE.HITM_OTHER_CORE", 6472 "MSRIndex": "0x1a6,0x1a7", 6473 "MSRValue": "0x1000020120", 6474 "Offcore": "1", 6475 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6476 "SampleAfterValue": "100003", 6477 "UMask": "0x1" 6478 }, 6479 { 6480 "BriefDescription": "Counts any other requests OTHER & L3_HIT_S & HIT_OTHER_CORE_NO_FWD", 6481 "Counter": "0,1,2,3", 6482 "CounterHTOff": "0,1,2,3", 6483 "EventCode": "0xB7, 0xBB", 6484 "EventName": "OCR.OTHER.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", 6485 "MSRIndex": "0x1a6,0x1a7", 6486 "MSRValue": "0x0400108000", 6487 "Offcore": "1", 6488 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6489 "SampleAfterValue": "100003", 6490 "UMask": "0x1" 6491 }, 6492 { 6493 "BriefDescription": "ALL_PF_DATA_RD & L3_HIT & HIT_OTHER_CORE_NO_FWD", 6494 "Counter": "0,1,2,3", 6495 "CounterHTOff": "0,1,2,3", 6496 "EventCode": "0xB7, 0xBB", 6497 "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD", 6498 "MSRIndex": "0x1a6,0x1a7", 6499 "MSRValue": "0x04003C0490", 6500 "Offcore": "1", 6501 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6502 "SampleAfterValue": "100003", 6503 "UMask": "0x1" 6504 }, 6505 { 6506 "BriefDescription": "Counts any other requests", 6507 "Counter": "0,1,2,3", 6508 "CounterHTOff": "0,1,2,3", 6509 "EventCode": "0xB7, 0xBB", 6510 "EventName": "OCR.OTHER.L3_HIT_S.SNOOP_NONE", 6511 "MSRIndex": "0x1a6,0x1a7", 6512 "MSRValue": "0x0080108000", 6513 "Offcore": "1", 6514 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6515 "SampleAfterValue": "100003", 6516 "UMask": "0x1" 6517 }, 6518 { 6519 "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads", 6520 "Counter": "0,1,2,3", 6521 "CounterHTOff": "0,1,2,3", 6522 "EventCode": "0xB7, 0xBB", 6523 "EventName": "OCR.PF_L3_DATA_RD.SUPPLIER_NONE.SNOOP_MISS", 6524 "MSRIndex": "0x1a6,0x1a7", 6525 "MSRValue": "0x0200020080", 6526 "Offcore": "1", 6527 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6528 "SampleAfterValue": "100003", 6529 "UMask": "0x1" 6530 }, 6531 { 6532 "BriefDescription": "ALL_READS & PMM_HIT_LOCAL_PMM & SNOOP_NOT_NEEDED", 6533 "Counter": "0,1,2,3", 6534 "CounterHTOff": "0,1,2,3", 6535 "EventCode": "0xB7, 0xBB", 6536 "EventName": "OCR.ALL_READS.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", 6537 "MSRIndex": "0x1a6,0x1a7", 6538 "MSRValue": "0x01004007F7", 6539 "Offcore": "1", 6540 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6541 "SampleAfterValue": "100003", 6542 "UMask": "0x1" 6543 }, 6544 { 6545 "BriefDescription": "Counts prefetch (that bring data to L2) data reads PF_L2_DATA_RD & L3_HIT_M & ANY_SNOOP", 6546 "Counter": "0,1,2,3", 6547 "CounterHTOff": "0,1,2,3", 6548 "EventCode": "0xB7, 0xBB", 6549 "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_M.ANY_SNOOP", 6550 "MSRIndex": "0x1a6,0x1a7", 6551 "MSRValue": "0x3F80040010", 6552 "Offcore": "1", 6553 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6554 "SampleAfterValue": "100003", 6555 "UMask": "0x1" 6556 }, 6557 { 6558 "BriefDescription": "Counts prefetch (that bring data to L2) data reads PF_L2_DATA_RD & L3_HIT_F & ANY_SNOOP", 6559 "Counter": "0,1,2,3", 6560 "CounterHTOff": "0,1,2,3", 6561 "EventCode": "0xB7, 0xBB", 6562 "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_F.ANY_SNOOP", 6563 "MSRIndex": "0x1a6,0x1a7", 6564 "MSRValue": "0x3F80200010", 6565 "Offcore": "1", 6566 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6567 "SampleAfterValue": "100003", 6568 "UMask": "0x1" 6569 }, 6570 { 6571 "BriefDescription": "Counts all demand code reads hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.", 6572 "Counter": "0,1,2,3", 6573 "CounterHTOff": "0,1,2,3", 6574 "EventCode": "0xB7, 0xBB", 6575 "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.NO_SNOOP_NEEDED", 6576 "MSRIndex": "0x1a6,0x1a7", 6577 "MSRValue": "0x01003C0004", 6578 "Offcore": "1", 6579 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6580 "SampleAfterValue": "100003", 6581 "UMask": "0x1" 6582 }, 6583 { 6584 "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs", 6585 "Counter": "0,1,2,3", 6586 "CounterHTOff": "0,1,2,3", 6587 "EventCode": "0xB7, 0xBB", 6588 "EventName": "OCR.PF_L3_RFO.L3_HIT_F.SNOOP_MISS", 6589 "MSRIndex": "0x1a6,0x1a7", 6590 "MSRValue": "0x0200200100", 6591 "Offcore": "1", 6592 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6593 "SampleAfterValue": "100003", 6594 "UMask": "0x1" 6595 }, 6596 { 6597 "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads", 6598 "Counter": "0,1,2,3", 6599 "CounterHTOff": "0,1,2,3", 6600 "EventCode": "0xB7, 0xBB", 6601 "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_F.SNOOP_NONE", 6602 "MSRIndex": "0x1a6,0x1a7", 6603 "MSRValue": "0x0080200080", 6604 "Offcore": "1", 6605 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6606 "SampleAfterValue": "100003", 6607 "UMask": "0x1" 6608 }, 6609 { 6610 "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs", 6611 "Counter": "0,1,2,3", 6612 "CounterHTOff": "0,1,2,3", 6613 "EventCode": "0xB7, 0xBB", 6614 "EventName": "OCR.PF_L2_RFO.L3_HIT_M.SNOOP_MISS", 6615 "MSRIndex": "0x1a6,0x1a7", 6616 "MSRValue": "0x0200040020", 6617 "Offcore": "1", 6618 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6619 "SampleAfterValue": "100003", 6620 "UMask": "0x1" 6621 }, 6622 { 6623 "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads PF_L3_DATA_RD & SUPPLIER_NONE & NO_SNOOP_NEEDED", 6624 "Counter": "0,1,2,3", 6625 "CounterHTOff": "0,1,2,3", 6626 "EventCode": "0xB7, 0xBB", 6627 "EventName": "OCR.PF_L3_DATA_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED", 6628 "MSRIndex": "0x1a6,0x1a7", 6629 "MSRValue": "0x0100020080", 6630 "Offcore": "1", 6631 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6632 "SampleAfterValue": "100003", 6633 "UMask": "0x1" 6634 }, 6635 { 6636 "BriefDescription": "ALL_READS & L3_HIT_M & HITM_OTHER_CORE", 6637 "Counter": "0,1,2,3", 6638 "CounterHTOff": "0,1,2,3", 6639 "EventCode": "0xB7, 0xBB", 6640 "EventName": "OCR.ALL_READS.L3_HIT_M.HITM_OTHER_CORE", 6641 "MSRIndex": "0x1a6,0x1a7", 6642 "MSRValue": "0x10000407F7", 6643 "Offcore": "1", 6644 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6645 "SampleAfterValue": "100003", 6646 "UMask": "0x1" 6647 }, 6648 { 6649 "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads", 6650 "Counter": "0,1,2,3", 6651 "CounterHTOff": "0,1,2,3", 6652 "EventCode": "0xB7, 0xBB", 6653 "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_S.SNOOP_MISS", 6654 "MSRIndex": "0x1a6,0x1a7", 6655 "MSRValue": "0x0200100080", 6656 "Offcore": "1", 6657 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6658 "SampleAfterValue": "100003", 6659 "UMask": "0x1" 6660 }, 6661 { 6662 "BriefDescription": "ALL_READS & SUPPLIER_NONE & HITM_OTHER_CORE", 6663 "Counter": "0,1,2,3", 6664 "CounterHTOff": "0,1,2,3", 6665 "EventCode": "0xB7, 0xBB", 6666 "EventName": "OCR.ALL_READS.SUPPLIER_NONE.HITM_OTHER_CORE", 6667 "MSRIndex": "0x1a6,0x1a7", 6668 "MSRValue": "0x10000207F7", 6669 "Offcore": "1", 6670 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6671 "SampleAfterValue": "100003", 6672 "UMask": "0x1" 6673 }, 6674 { 6675 "BriefDescription": "ALL_DATA_RD & L3_HIT_M & ANY_SNOOP", 6676 "Counter": "0,1,2,3", 6677 "CounterHTOff": "0,1,2,3", 6678 "EventCode": "0xB7, 0xBB", 6679 "EventName": "OCR.ALL_DATA_RD.L3_HIT_M.ANY_SNOOP", 6680 "MSRIndex": "0x1a6,0x1a7", 6681 "MSRValue": "0x3F80040491", 6682 "Offcore": "1", 6683 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6684 "SampleAfterValue": "100003", 6685 "UMask": "0x1" 6686 }, 6687 { 6688 "BriefDescription": "ALL_RFO & L3_HIT_E & NO_SNOOP_NEEDED", 6689 "Counter": "0,1,2,3", 6690 "CounterHTOff": "0,1,2,3", 6691 "EventCode": "0xB7, 0xBB", 6692 "EventName": "OCR.ALL_RFO.L3_HIT_E.NO_SNOOP_NEEDED", 6693 "MSRIndex": "0x1a6,0x1a7", 6694 "MSRValue": "0x0100080122", 6695 "Offcore": "1", 6696 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6697 "SampleAfterValue": "100003", 6698 "UMask": "0x1" 6699 }, 6700 { 6701 "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests PF_L1D_AND_SW & L3_HIT_F & HIT_OTHER_CORE_NO_FWD", 6702 "Counter": "0,1,2,3", 6703 "CounterHTOff": "0,1,2,3", 6704 "EventCode": "0xB7, 0xBB", 6705 "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", 6706 "MSRIndex": "0x1a6,0x1a7", 6707 "MSRValue": "0x0400200400", 6708 "Offcore": "1", 6709 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6710 "SampleAfterValue": "100003", 6711 "UMask": "0x1" 6712 }, 6713 { 6714 "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs PF_L3_RFO & L3_HIT_F & ANY_SNOOP", 6715 "Counter": "0,1,2,3", 6716 "CounterHTOff": "0,1,2,3", 6717 "EventCode": "0xB7, 0xBB", 6718 "EventName": "OCR.PF_L3_RFO.L3_HIT_F.ANY_SNOOP", 6719 "MSRIndex": "0x1a6,0x1a7", 6720 "MSRValue": "0x3F80200100", 6721 "Offcore": "1", 6722 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6723 "SampleAfterValue": "100003", 6724 "UMask": "0x1" 6725 }, 6726 { 6727 "BriefDescription": "Counts prefetch (that bring data to L2) data reads", 6728 "Counter": "0,1,2,3", 6729 "CounterHTOff": "0,1,2,3", 6730 "EventCode": "0xB7, 0xBB", 6731 "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_M.SNOOP_MISS", 6732 "MSRIndex": "0x1a6,0x1a7", 6733 "MSRValue": "0x0200040010", 6734 "Offcore": "1", 6735 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6736 "SampleAfterValue": "100003", 6737 "UMask": "0x1" 6738 }, 6739 { 6740 "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads", 6741 "Counter": "0,1,2,3", 6742 "CounterHTOff": "0,1,2,3", 6743 "EventCode": "0xB7, 0xBB", 6744 "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_E.SNOOP_NONE", 6745 "MSRIndex": "0x1a6,0x1a7", 6746 "MSRValue": "0x0080080080", 6747 "Offcore": "1", 6748 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6749 "SampleAfterValue": "100003", 6750 "UMask": "0x1" 6751 }, 6752 { 6753 "BriefDescription": "Counts all demand code reads", 6754 "Counter": "0,1,2,3", 6755 "CounterHTOff": "0,1,2,3", 6756 "EventCode": "0xB7, 0xBB", 6757 "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_F.SNOOP_NONE", 6758 "MSRIndex": "0x1a6,0x1a7", 6759 "MSRValue": "0x0080200004", 6760 "Offcore": "1", 6761 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6762 "SampleAfterValue": "100003", 6763 "UMask": "0x1" 6764 }, 6765 { 6766 "BriefDescription": "Counts any other requests hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.", 6767 "Counter": "0,1,2,3", 6768 "CounterHTOff": "0,1,2,3", 6769 "EventCode": "0xB7, 0xBB", 6770 "EventName": "OCR.OTHER.L3_HIT.NO_SNOOP_NEEDED", 6771 "MSRIndex": "0x1a6,0x1a7", 6772 "MSRValue": "0x01003C8000", 6773 "Offcore": "1", 6774 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6775 "SampleAfterValue": "100003", 6776 "UMask": "0x1" 6777 }, 6778 { 6779 "BriefDescription": "ALL_PF_RFO & L3_HIT_F & HITM_OTHER_CORE", 6780 "Counter": "0,1,2,3", 6781 "CounterHTOff": "0,1,2,3", 6782 "EventCode": "0xB7, 0xBB", 6783 "EventName": "OCR.ALL_PF_RFO.L3_HIT_F.HITM_OTHER_CORE", 6784 "MSRIndex": "0x1a6,0x1a7", 6785 "MSRValue": "0x1000200120", 6786 "Offcore": "1", 6787 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6788 "SampleAfterValue": "100003", 6789 "UMask": "0x1" 6790 }, 6791 { 6792 "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs PF_L3_RFO & L3_HIT_S & NO_SNOOP_NEEDED", 6793 "Counter": "0,1,2,3", 6794 "CounterHTOff": "0,1,2,3", 6795 "EventCode": "0xB7, 0xBB", 6796 "EventName": "OCR.PF_L3_RFO.L3_HIT_S.NO_SNOOP_NEEDED", 6797 "MSRIndex": "0x1a6,0x1a7", 6798 "MSRValue": "0x0100100100", 6799 "Offcore": "1", 6800 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6801 "SampleAfterValue": "100003", 6802 "UMask": "0x1" 6803 }, 6804 { 6805 "BriefDescription": "Counts demand data reads", 6806 "Counter": "0,1,2,3", 6807 "CounterHTOff": "0,1,2,3", 6808 "EventCode": "0xB7, 0xBB", 6809 "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD", 6810 "MSRIndex": "0x1a6,0x1a7", 6811 "MSRValue": "0x08007C0001", 6812 "Offcore": "1", 6813 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6814 "SampleAfterValue": "100003", 6815 "UMask": "0x1" 6816 }, 6817 { 6818 "BriefDescription": "ALL_RFO & L3_HIT & ANY_SNOOP", 6819 "Counter": "0,1,2,3", 6820 "CounterHTOff": "0,1,2,3", 6821 "EventCode": "0xB7, 0xBB", 6822 "EventName": "OCR.ALL_RFO.L3_HIT.ANY_SNOOP", 6823 "MSRIndex": "0x1a6,0x1a7", 6824 "MSRValue": "0x3F803C0122", 6825 "Offcore": "1", 6826 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6827 "SampleAfterValue": "100003", 6828 "UMask": "0x1" 6829 }, 6830 { 6831 "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs PF_L3_RFO & L3_HIT & HIT_OTHER_CORE_NO_FWD", 6832 "Counter": "0,1,2,3", 6833 "CounterHTOff": "0,1,2,3", 6834 "EventCode": "0xB7, 0xBB", 6835 "EventName": "OCR.PF_L3_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD", 6836 "MSRIndex": "0x1a6,0x1a7", 6837 "MSRValue": "0x04003C0100", 6838 "Offcore": "1", 6839 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6840 "SampleAfterValue": "100003", 6841 "UMask": "0x1" 6842 }, 6843 { 6844 "BriefDescription": "Counts prefetch (that bring data to L2) data reads PF_L2_DATA_RD & L3_HIT_E & NO_SNOOP_NEEDED", 6845 "Counter": "0,1,2,3", 6846 "CounterHTOff": "0,1,2,3", 6847 "EventCode": "0xB7, 0xBB", 6848 "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDED", 6849 "MSRIndex": "0x1a6,0x1a7", 6850 "MSRValue": "0x0100080010", 6851 "Offcore": "1", 6852 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6853 "SampleAfterValue": "100003", 6854 "UMask": "0x1" 6855 }, 6856 { 6857 "BriefDescription": "Counts any other requests", 6858 "Counter": "0,1,2,3", 6859 "CounterHTOff": "0,1,2,3", 6860 "EventCode": "0xB7, 0xBB", 6861 "EventName": "OCR.OTHER.L3_HIT_E.SNOOP_MISS", 6862 "MSRIndex": "0x1a6,0x1a7", 6863 "MSRValue": "0x0200088000", 6864 "Offcore": "1", 6865 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6866 "SampleAfterValue": "100003", 6867 "UMask": "0x1" 6868 }, 6869 { 6870 "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests PF_L1D_AND_SW & L3_HIT_E & ANY_SNOOP", 6871 "Counter": "0,1,2,3", 6872 "CounterHTOff": "0,1,2,3", 6873 "EventCode": "0xB7, 0xBB", 6874 "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_E.ANY_SNOOP", 6875 "MSRIndex": "0x1a6,0x1a7", 6876 "MSRValue": "0x3F80080400", 6877 "Offcore": "1", 6878 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6879 "SampleAfterValue": "100003", 6880 "UMask": "0x1" 6881 }, 6882 { 6883 "BriefDescription": "ALL_DATA_RD & SUPPLIER_NONE & ANY_SNOOP", 6884 "Counter": "0,1,2,3", 6885 "CounterHTOff": "0,1,2,3", 6886 "EventCode": "0xB7, 0xBB", 6887 "EventName": "OCR.ALL_DATA_RD.SUPPLIER_NONE.ANY_SNOOP", 6888 "MSRIndex": "0x1a6,0x1a7", 6889 "MSRValue": "0x3F80020491", 6890 "Offcore": "1", 6891 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6892 "SampleAfterValue": "100003", 6893 "UMask": "0x1" 6894 }, 6895 { 6896 "BriefDescription": "ALL_RFO & L3_HIT_M & SNOOP_NONE", 6897 "Counter": "0,1,2,3", 6898 "CounterHTOff": "0,1,2,3", 6899 "EventCode": "0xB7, 0xBB", 6900 "EventName": "OCR.ALL_RFO.L3_HIT_M.SNOOP_NONE", 6901 "MSRIndex": "0x1a6,0x1a7", 6902 "MSRValue": "0x0080040122", 6903 "Offcore": "1", 6904 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6905 "SampleAfterValue": "100003", 6906 "UMask": "0x1" 6907 }, 6908 { 6909 "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs PF_L2_RFO & SUPPLIER_NONE & NO_SNOOP_NEEDED", 6910 "Counter": "0,1,2,3", 6911 "CounterHTOff": "0,1,2,3", 6912 "EventCode": "0xB7, 0xBB", 6913 "EventName": "OCR.PF_L2_RFO.SUPPLIER_NONE.NO_SNOOP_NEEDED", 6914 "MSRIndex": "0x1a6,0x1a7", 6915 "MSRValue": "0x0100020020", 6916 "Offcore": "1", 6917 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6918 "SampleAfterValue": "100003", 6919 "UMask": "0x1" 6920 }, 6921 { 6922 "BriefDescription": "ALL_PF_DATA_RD & PMM_HIT_LOCAL_PMM & SNOOP_NOT_NEEDED", 6923 "Counter": "0,1,2,3", 6924 "CounterHTOff": "0,1,2,3", 6925 "EventCode": "0xB7, 0xBB", 6926 "EventName": "OCR.ALL_PF_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", 6927 "MSRIndex": "0x1a6,0x1a7", 6928 "MSRValue": "0x0100400490", 6929 "Offcore": "1", 6930 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6931 "SampleAfterValue": "100003", 6932 "UMask": "0x1" 6933 }, 6934 { 6935 "BriefDescription": "Counts all demand data writes (RFOs)", 6936 "Counter": "0,1,2,3", 6937 "CounterHTOff": "0,1,2,3", 6938 "EventCode": "0xB7, 0xBB", 6939 "EventName": "OCR.DEMAND_RFO.SUPPLIER_NONE.SNOOP_NONE", 6940 "MSRIndex": "0x1a6,0x1a7", 6941 "MSRValue": "0x0080020002", 6942 "Offcore": "1", 6943 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6944 "SampleAfterValue": "100003", 6945 "UMask": "0x1" 6946 }, 6947 { 6948 "BriefDescription": "Counts all demand data writes (RFOs)", 6949 "Counter": "0,1,2,3", 6950 "CounterHTOff": "0,1,2,3", 6951 "EventCode": "0xB7, 0xBB", 6952 "EventName": "OCR.DEMAND_RFO.L3_HIT_S.SNOOP_MISS", 6953 "MSRIndex": "0x1a6,0x1a7", 6954 "MSRValue": "0x0200100002", 6955 "Offcore": "1", 6956 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6957 "SampleAfterValue": "100003", 6958 "UMask": "0x1" 6959 }, 6960 { 6961 "BriefDescription": "ALL_RFO & SUPPLIER_NONE & ANY_SNOOP", 6962 "Counter": "0,1,2,3", 6963 "CounterHTOff": "0,1,2,3", 6964 "EventCode": "0xB7, 0xBB", 6965 "EventName": "OCR.ALL_RFO.SUPPLIER_NONE.ANY_SNOOP", 6966 "MSRIndex": "0x1a6,0x1a7", 6967 "MSRValue": "0x3F80020122", 6968 "Offcore": "1", 6969 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6970 "SampleAfterValue": "100003", 6971 "UMask": "0x1" 6972 }, 6973 { 6974 "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads PF_L3_DATA_RD & SUPPLIER_NONE & HIT_OTHER_CORE_FWD", 6975 "Counter": "0,1,2,3", 6976 "CounterHTOff": "0,1,2,3", 6977 "EventCode": "0xB7, 0xBB", 6978 "EventName": "OCR.PF_L3_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", 6979 "MSRIndex": "0x1a6,0x1a7", 6980 "MSRValue": "0x0800020080", 6981 "Offcore": "1", 6982 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6983 "SampleAfterValue": "100003", 6984 "UMask": "0x1" 6985 }, 6986 { 6987 "BriefDescription": "Counts demand data reads DEMAND_DATA_RD & SUPPLIER_NONE & HIT_OTHER_CORE_NO_FWD", 6988 "Counter": "0,1,2,3", 6989 "CounterHTOff": "0,1,2,3", 6990 "EventCode": "0xB7, 0xBB", 6991 "EventName": "OCR.DEMAND_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", 6992 "MSRIndex": "0x1a6,0x1a7", 6993 "MSRValue": "0x0400020001", 6994 "Offcore": "1", 6995 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6996 "SampleAfterValue": "100003", 6997 "UMask": "0x1" 6998 }, 6999 { 7000 "BriefDescription": "ALL_PF_DATA_RD & L3_HIT_M & HITM_OTHER_CORE", 7001 "Counter": "0,1,2,3", 7002 "CounterHTOff": "0,1,2,3", 7003 "EventCode": "0xB7, 0xBB", 7004 "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_M.HITM_OTHER_CORE", 7005 "MSRIndex": "0x1a6,0x1a7", 7006 "MSRValue": "0x1000040490", 7007 "Offcore": "1", 7008 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7009 "SampleAfterValue": "100003", 7010 "UMask": "0x1" 7011 }, 7012 { 7013 "BriefDescription": "Number of PREFETCHW instructions executed.", 7014 "Counter": "0,1,2,3", 7015 "CounterHTOff": "0,1,2,3,4,5,6,7", 7016 "EventCode": "0x32", 7017 "EventName": "SW_PREFETCH_ACCESS.PREFETCHW", 7018 "SampleAfterValue": "2000003", 7019 "UMask": "0x8" 7020 }, 7021 { 7022 "BriefDescription": "ALL_PF_DATA_RD & L3_HIT_S & SNOOP_MISS", 7023 "Counter": "0,1,2,3", 7024 "CounterHTOff": "0,1,2,3", 7025 "EventCode": "0xB7, 0xBB", 7026 "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_S.SNOOP_MISS", 7027 "MSRIndex": "0x1a6,0x1a7", 7028 "MSRValue": "0x0200100490", 7029 "Offcore": "1", 7030 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7031 "SampleAfterValue": "100003", 7032 "UMask": "0x1" 7033 }, 7034 { 7035 "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs PF_L2_RFO & L3_HIT_S & HIT_OTHER_CORE_FWD", 7036 "Counter": "0,1,2,3", 7037 "CounterHTOff": "0,1,2,3", 7038 "EventCode": "0xB7, 0xBB", 7039 "EventName": "OCR.PF_L2_RFO.L3_HIT_S.HIT_OTHER_CORE_FWD", 7040 "MSRIndex": "0x1a6,0x1a7", 7041 "MSRValue": "0x0800100020", 7042 "Offcore": "1", 7043 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7044 "SampleAfterValue": "100003", 7045 "UMask": "0x1" 7046 }, 7047 { 7048 "BriefDescription": "ALL_DATA_RD & L3_HIT_E & HIT_OTHER_CORE_FWD", 7049 "Counter": "0,1,2,3", 7050 "CounterHTOff": "0,1,2,3", 7051 "EventCode": "0xB7, 0xBB", 7052 "EventName": "OCR.ALL_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWD", 7053 "MSRIndex": "0x1a6,0x1a7", 7054 "MSRValue": "0x0800080491", 7055 "Offcore": "1", 7056 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7057 "SampleAfterValue": "100003", 7058 "UMask": "0x1" 7059 }, 7060 { 7061 "BriefDescription": "ALL_PF_RFO & L3_HIT_M & ANY_SNOOP", 7062 "Counter": "0,1,2,3", 7063 "CounterHTOff": "0,1,2,3", 7064 "EventCode": "0xB7, 0xBB", 7065 "EventName": "OCR.ALL_PF_RFO.L3_HIT_M.ANY_SNOOP", 7066 "MSRIndex": "0x1a6,0x1a7", 7067 "MSRValue": "0x3F80040120", 7068 "Offcore": "1", 7069 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7070 "SampleAfterValue": "100003", 7071 "UMask": "0x1" 7072 }, 7073 { 7074 "BriefDescription": "ALL_PF_RFO & L3_HIT_M & SNOOP_MISS", 7075 "Counter": "0,1,2,3", 7076 "CounterHTOff": "0,1,2,3", 7077 "EventCode": "0xB7, 0xBB", 7078 "EventName": "OCR.ALL_PF_RFO.L3_HIT_M.SNOOP_MISS", 7079 "MSRIndex": "0x1a6,0x1a7", 7080 "MSRValue": "0x0200040120", 7081 "Offcore": "1", 7082 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7083 "SampleAfterValue": "100003", 7084 "UMask": "0x1" 7085 }, 7086 { 7087 "BriefDescription": "Counts prefetch (that bring data to L2) data reads PF_L2_DATA_RD & SUPPLIER_NONE & HITM_OTHER_CORE", 7088 "Counter": "0,1,2,3", 7089 "CounterHTOff": "0,1,2,3", 7090 "EventCode": "0xB7, 0xBB", 7091 "EventName": "OCR.PF_L2_DATA_RD.SUPPLIER_NONE.HITM_OTHER_CORE", 7092 "MSRIndex": "0x1a6,0x1a7", 7093 "MSRValue": "0x1000020010", 7094 "Offcore": "1", 7095 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7096 "SampleAfterValue": "100003", 7097 "UMask": "0x1" 7098 }, 7099 { 7100 "BriefDescription": "ALL_PF_DATA_RD & SUPPLIER_NONE & HIT_OTHER_CORE_NO_FWD", 7101 "Counter": "0,1,2,3", 7102 "CounterHTOff": "0,1,2,3", 7103 "EventCode": "0xB7, 0xBB", 7104 "EventName": "OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", 7105 "MSRIndex": "0x1a6,0x1a7", 7106 "MSRValue": "0x0400020490", 7107 "Offcore": "1", 7108 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7109 "SampleAfterValue": "100003", 7110 "UMask": "0x1" 7111 }, 7112 { 7113 "BriefDescription": "Counts all demand code reads DEMAND_CODE_RD & L3_HIT & ANY_SNOOP", 7114 "Counter": "0,1,2,3", 7115 "CounterHTOff": "0,1,2,3", 7116 "EventCode": "0xB7, 0xBB", 7117 "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.ANY_SNOOP", 7118 "MSRIndex": "0x1a6,0x1a7", 7119 "MSRValue": "0x3F803C0004", 7120 "Offcore": "1", 7121 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7122 "SampleAfterValue": "100003", 7123 "UMask": "0x1" 7124 }, 7125 { 7126 "BriefDescription": "ALL_PF_DATA_RD & L3_HIT_F & HIT_OTHER_CORE_FWD", 7127 "Counter": "0,1,2,3", 7128 "CounterHTOff": "0,1,2,3", 7129 "EventCode": "0xB7, 0xBB", 7130 "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWD", 7131 "MSRIndex": "0x1a6,0x1a7", 7132 "MSRValue": "0x0800200490", 7133 "Offcore": "1", 7134 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7135 "SampleAfterValue": "100003", 7136 "UMask": "0x1" 7137 }, 7138 { 7139 "BriefDescription": "ALL_RFO & L3_HIT_E & SNOOP_MISS", 7140 "Counter": "0,1,2,3", 7141 "CounterHTOff": "0,1,2,3", 7142 "EventCode": "0xB7, 0xBB", 7143 "EventName": "OCR.ALL_RFO.L3_HIT_E.SNOOP_MISS", 7144 "MSRIndex": "0x1a6,0x1a7", 7145 "MSRValue": "0x0200080122", 7146 "Offcore": "1", 7147 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7148 "SampleAfterValue": "100003", 7149 "UMask": "0x1" 7150 }, 7151 { 7152 "BriefDescription": "Counts demand data reads DEMAND_DATA_RD & L3_HIT_M & HIT_OTHER_CORE_NO_FWD", 7153 "Counter": "0,1,2,3", 7154 "CounterHTOff": "0,1,2,3", 7155 "EventCode": "0xB7, 0xBB", 7156 "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", 7157 "MSRIndex": "0x1a6,0x1a7", 7158 "MSRValue": "0x0400040001", 7159 "Offcore": "1", 7160 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7161 "SampleAfterValue": "100003", 7162 "UMask": "0x1" 7163 }, 7164 { 7165 "BriefDescription": "Counts prefetch (that bring data to L2) data reads PF_L2_DATA_RD & L3_HIT & HIT_OTHER_CORE_FWD", 7166 "Counter": "0,1,2,3", 7167 "CounterHTOff": "0,1,2,3", 7168 "EventCode": "0xB7, 0xBB", 7169 "EventName": "OCR.PF_L2_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD", 7170 "MSRIndex": "0x1a6,0x1a7", 7171 "MSRValue": "0x08003C0010", 7172 "Offcore": "1", 7173 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7174 "SampleAfterValue": "100003", 7175 "UMask": "0x1" 7176 }, 7177 { 7178 "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs PF_L3_RFO & L3_HIT_S & HIT_OTHER_CORE_FWD", 7179 "Counter": "0,1,2,3", 7180 "CounterHTOff": "0,1,2,3", 7181 "EventCode": "0xB7, 0xBB", 7182 "EventName": "OCR.PF_L3_RFO.L3_HIT_S.HIT_OTHER_CORE_FWD", 7183 "MSRIndex": "0x1a6,0x1a7", 7184 "MSRValue": "0x0800100100", 7185 "Offcore": "1", 7186 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7187 "SampleAfterValue": "100003", 7188 "UMask": "0x1" 7189 }, 7190 { 7191 "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.", 7192 "Counter": "0,1,2,3", 7193 "CounterHTOff": "0,1,2,3", 7194 "EventCode": "0xB7, 0xBB", 7195 "EventName": "OCR.PF_L3_DATA_RD.L3_HIT.NO_SNOOP_NEEDED", 7196 "MSRIndex": "0x1a6,0x1a7", 7197 "MSRValue": "0x01003C0080", 7198 "Offcore": "1", 7199 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7200 "SampleAfterValue": "100003", 7201 "UMask": "0x1" 7202 }, 7203 { 7204 "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads PF_L3_DATA_RD & L3_HIT_M & HITM_OTHER_CORE", 7205 "Counter": "0,1,2,3", 7206 "CounterHTOff": "0,1,2,3", 7207 "EventCode": "0xB7, 0xBB", 7208 "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_M.HITM_OTHER_CORE", 7209 "MSRIndex": "0x1a6,0x1a7", 7210 "MSRValue": "0x1000040080", 7211 "Offcore": "1", 7212 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7213 "SampleAfterValue": "100003", 7214 "UMask": "0x1" 7215 }, 7216 { 7217 "BriefDescription": "Counts prefetch (that bring data to L2) data reads PF_L2_DATA_RD & L3_HIT_E & HITM_OTHER_CORE", 7218 "Counter": "0,1,2,3", 7219 "CounterHTOff": "0,1,2,3", 7220 "EventCode": "0xB7, 0xBB", 7221 "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_E.HITM_OTHER_CORE", 7222 "MSRIndex": "0x1a6,0x1a7", 7223 "MSRValue": "0x1000080010", 7224 "Offcore": "1", 7225 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7226 "SampleAfterValue": "100003", 7227 "UMask": "0x1" 7228 }, 7229 { 7230 "BriefDescription": "ALL_PF_RFO & SUPPLIER_NONE & NO_SNOOP_NEEDED", 7231 "Counter": "0,1,2,3", 7232 "CounterHTOff": "0,1,2,3", 7233 "EventCode": "0xB7, 0xBB", 7234 "EventName": "OCR.ALL_PF_RFO.SUPPLIER_NONE.NO_SNOOP_NEEDED", 7235 "MSRIndex": "0x1a6,0x1a7", 7236 "MSRValue": "0x0100020120", 7237 "Offcore": "1", 7238 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7239 "SampleAfterValue": "100003", 7240 "UMask": "0x1" 7241 }, 7242 { 7243 "BriefDescription": "ALL_RFO & L3_HIT_S & HIT_OTHER_CORE_FWD", 7244 "Counter": "0,1,2,3", 7245 "CounterHTOff": "0,1,2,3", 7246 "EventCode": "0xB7, 0xBB", 7247 "EventName": "OCR.ALL_RFO.L3_HIT_S.HIT_OTHER_CORE_FWD", 7248 "MSRIndex": "0x1a6,0x1a7", 7249 "MSRValue": "0x0800100122", 7250 "Offcore": "1", 7251 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7252 "SampleAfterValue": "100003", 7253 "UMask": "0x1" 7254 }, 7255 { 7256 "BriefDescription": "ALL_PF_RFO & SUPPLIER_NONE & HIT_OTHER_CORE_NO_FWD", 7257 "Counter": "0,1,2,3", 7258 "CounterHTOff": "0,1,2,3", 7259 "EventCode": "0xB7, 0xBB", 7260 "EventName": "OCR.ALL_PF_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", 7261 "MSRIndex": "0x1a6,0x1a7", 7262 "MSRValue": "0x0400020120", 7263 "Offcore": "1", 7264 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7265 "SampleAfterValue": "100003", 7266 "UMask": "0x1" 7267 }, 7268 { 7269 "BriefDescription": "Core cycles where the core was running in a manner where Turbo may be clipped to the AVX2 turbo schedule.", 7270 "Counter": "0,1,2,3", 7271 "CounterHTOff": "0,1,2,3,4,5,6,7", 7272 "EventCode": "0x28", 7273 "EventName": "CORE_POWER.LVL1_TURBO_LICENSE", 7274 "PublicDescription": "Core cycles where the core was running with power-delivery for license level 1. This includes high current AVX 256-bit instructions as well as low current AVX 512-bit instructions.", 7275 "SampleAfterValue": "200003", 7276 "UMask": "0x18" 7277 }, 7278 { 7279 "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs PF_L2_RFO & L3_HIT_M & HIT_OTHER_CORE_FWD", 7280 "Counter": "0,1,2,3", 7281 "CounterHTOff": "0,1,2,3", 7282 "EventCode": "0xB7, 0xBB", 7283 "EventName": "OCR.PF_L2_RFO.L3_HIT_M.HIT_OTHER_CORE_FWD", 7284 "MSRIndex": "0x1a6,0x1a7", 7285 "MSRValue": "0x0800040020", 7286 "Offcore": "1", 7287 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7288 "SampleAfterValue": "100003", 7289 "UMask": "0x1" 7290 }, 7291 { 7292 "BriefDescription": "Counts all demand code reads DEMAND_CODE_RD & L3_HIT_F & HIT_OTHER_CORE_NO_FWD", 7293 "Counter": "0,1,2,3", 7294 "CounterHTOff": "0,1,2,3", 7295 "EventCode": "0xB7, 0xBB", 7296 "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", 7297 "MSRIndex": "0x1a6,0x1a7", 7298 "MSRValue": "0x0400200004", 7299 "Offcore": "1", 7300 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7301 "SampleAfterValue": "100003", 7302 "UMask": "0x1" 7303 }, 7304 { 7305 "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads", 7306 "Counter": "0,1,2,3", 7307 "CounterHTOff": "0,1,2,3", 7308 "EventCode": "0xB7, 0xBB", 7309 "EventName": "OCR.PF_L3_DATA_RD.SUPPLIER_NONE.SNOOP_NONE", 7310 "MSRIndex": "0x1a6,0x1a7", 7311 "MSRValue": "0x0080020080", 7312 "Offcore": "1", 7313 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7314 "SampleAfterValue": "100003", 7315 "UMask": "0x1" 7316 }, 7317 { 7318 "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs PF_L2_RFO & L3_HIT_M & HITM_OTHER_CORE", 7319 "Counter": "0,1,2,3", 7320 "CounterHTOff": "0,1,2,3", 7321 "EventCode": "0xB7, 0xBB", 7322 "EventName": "OCR.PF_L2_RFO.L3_HIT_M.HITM_OTHER_CORE", 7323 "MSRIndex": "0x1a6,0x1a7", 7324 "MSRValue": "0x1000040020", 7325 "Offcore": "1", 7326 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7327 "SampleAfterValue": "100003", 7328 "UMask": "0x1" 7329 }, 7330 { 7331 "BriefDescription": "Counts demand data reads DEMAND_DATA_RD & PMM_HIT_LOCAL_PMM & SNOOP_NONE", 7332 "Counter": "0,1,2,3", 7333 "CounterHTOff": "0,1,2,3", 7334 "EventCode": "0xB7, 0xBB", 7335 "EventName": "OCR.DEMAND_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE", 7336 "MSRIndex": "0x1a6,0x1a7", 7337 "MSRValue": "0x0080400001", 7338 "Offcore": "1", 7339 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7340 "SampleAfterValue": "100003", 7341 "UMask": "0x1" 7342 }, 7343 { 7344 "BriefDescription": "Counts all demand code reads DEMAND_CODE_RD & L3_HIT_E & NO_SNOOP_NEEDED", 7345 "Counter": "0,1,2,3", 7346 "CounterHTOff": "0,1,2,3", 7347 "EventCode": "0xB7, 0xBB", 7348 "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_E.NO_SNOOP_NEEDED", 7349 "MSRIndex": "0x1a6,0x1a7", 7350 "MSRValue": "0x0100080004", 7351 "Offcore": "1", 7352 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7353 "SampleAfterValue": "100003", 7354 "UMask": "0x1" 7355 }, 7356 { 7357 "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs PF_L3_RFO & L3_HIT_E & ANY_SNOOP", 7358 "Counter": "0,1,2,3", 7359 "CounterHTOff": "0,1,2,3", 7360 "EventCode": "0xB7, 0xBB", 7361 "EventName": "OCR.PF_L3_RFO.L3_HIT_E.ANY_SNOOP", 7362 "MSRIndex": "0x1a6,0x1a7", 7363 "MSRValue": "0x3F80080100", 7364 "Offcore": "1", 7365 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7366 "SampleAfterValue": "100003", 7367 "UMask": "0x1" 7368 }, 7369 { 7370 "BriefDescription": "ALL_PF_DATA_RD & L3_HIT_S & SNOOP_NONE", 7371 "Counter": "0,1,2,3", 7372 "CounterHTOff": "0,1,2,3", 7373 "EventCode": "0xB7, 0xBB", 7374 "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_S.SNOOP_NONE", 7375 "MSRIndex": "0x1a6,0x1a7", 7376 "MSRValue": "0x0080100490", 7377 "Offcore": "1", 7378 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7379 "SampleAfterValue": "100003", 7380 "UMask": "0x1" 7381 }, 7382 { 7383 "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs PF_L2_RFO & L3_HIT_S & HIT_OTHER_CORE_NO_FWD", 7384 "Counter": "0,1,2,3", 7385 "CounterHTOff": "0,1,2,3", 7386 "EventCode": "0xB7, 0xBB", 7387 "EventName": "OCR.PF_L2_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", 7388 "MSRIndex": "0x1a6,0x1a7", 7389 "MSRValue": "0x0400100020", 7390 "Offcore": "1", 7391 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7392 "SampleAfterValue": "100003", 7393 "UMask": "0x1" 7394 }, 7395 { 7396 "BriefDescription": "ALL_RFO & L3_HIT_E & ANY_SNOOP", 7397 "Counter": "0,1,2,3", 7398 "CounterHTOff": "0,1,2,3", 7399 "EventCode": "0xB7, 0xBB", 7400 "EventName": "OCR.ALL_RFO.L3_HIT_E.ANY_SNOOP", 7401 "MSRIndex": "0x1a6,0x1a7", 7402 "MSRValue": "0x3F80080122", 7403 "Offcore": "1", 7404 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7405 "SampleAfterValue": "100003", 7406 "UMask": "0x1" 7407 }, 7408 { 7409 "BriefDescription": "ALL_PF_RFO & L3_HIT_S & HIT_OTHER_CORE_NO_FWD", 7410 "Counter": "0,1,2,3", 7411 "CounterHTOff": "0,1,2,3", 7412 "EventCode": "0xB7, 0xBB", 7413 "EventName": "OCR.ALL_PF_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", 7414 "MSRIndex": "0x1a6,0x1a7", 7415 "MSRValue": "0x0400100120", 7416 "Offcore": "1", 7417 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7418 "SampleAfterValue": "100003", 7419 "UMask": "0x1" 7420 }, 7421 { 7422 "BriefDescription": "ALL_DATA_RD & PMM_HIT_LOCAL_PMM & SNOOP_NOT_NEEDED", 7423 "Counter": "0,1,2,3", 7424 "CounterHTOff": "0,1,2,3", 7425 "EventCode": "0xB7, 0xBB", 7426 "EventName": "OCR.ALL_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", 7427 "MSRIndex": "0x1a6,0x1a7", 7428 "MSRValue": "0x0100400491", 7429 "Offcore": "1", 7430 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7431 "SampleAfterValue": "100003", 7432 "UMask": "0x1" 7433 }, 7434 { 7435 "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads PF_L3_DATA_RD & L3_HIT_E & NO_SNOOP_NEEDED", 7436 "Counter": "0,1,2,3", 7437 "CounterHTOff": "0,1,2,3", 7438 "EventCode": "0xB7, 0xBB", 7439 "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDED", 7440 "MSRIndex": "0x1a6,0x1a7", 7441 "MSRValue": "0x0100080080", 7442 "Offcore": "1", 7443 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7444 "SampleAfterValue": "100003", 7445 "UMask": "0x1" 7446 }, 7447 { 7448 "BriefDescription": "Counts all demand data writes (RFOs) DEMAND_RFO & L3_HIT_F & ANY_SNOOP", 7449 "Counter": "0,1,2,3", 7450 "CounterHTOff": "0,1,2,3", 7451 "EventCode": "0xB7, 0xBB", 7452 "EventName": "OCR.DEMAND_RFO.L3_HIT_F.ANY_SNOOP", 7453 "MSRIndex": "0x1a6,0x1a7", 7454 "MSRValue": "0x3F80200002", 7455 "Offcore": "1", 7456 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7457 "SampleAfterValue": "100003", 7458 "UMask": "0x1" 7459 }, 7460 { 7461 "BriefDescription": "ALL_PF_RFO & L3_HIT & SNOOP_NONE", 7462 "Counter": "0,1,2,3", 7463 "CounterHTOff": "0,1,2,3", 7464 "EventCode": "0xB7, 0xBB", 7465 "EventName": "OCR.ALL_PF_RFO.L3_HIT.SNOOP_NONE", 7466 "MSRIndex": "0x1a6,0x1a7", 7467 "MSRValue": "0x00803C0120", 7468 "Offcore": "1", 7469 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7470 "SampleAfterValue": "100003", 7471 "UMask": "0x1" 7472 }, 7473 { 7474 "BriefDescription": "Number of hardware interrupts received by the processor.", 7475 "Counter": "0,1,2,3", 7476 "CounterHTOff": "0,1,2,3,4,5,6,7", 7477 "EventCode": "0xCB", 7478 "EventName": "HW_INTERRUPTS.RECEIVED", 7479 "PublicDescription": "Counts the number of hardware interruptions received by the processor.", 7480 "SampleAfterValue": "203", 7481 "UMask": "0x1" 7482 }, 7483 { 7484 "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads", 7485 "Counter": "0,1,2,3", 7486 "CounterHTOff": "0,1,2,3", 7487 "EventCode": "0xB7, 0xBB", 7488 "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_F.SNOOP_MISS", 7489 "MSRIndex": "0x1a6,0x1a7", 7490 "MSRValue": "0x0200200080", 7491 "Offcore": "1", 7492 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7493 "SampleAfterValue": "100003", 7494 "UMask": "0x1" 7495 }, 7496 { 7497 "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs", 7498 "Counter": "0,1,2,3", 7499 "CounterHTOff": "0,1,2,3", 7500 "EventCode": "0xB7, 0xBB", 7501 "EventName": "OCR.PF_L2_RFO.SUPPLIER_NONE.SNOOP_MISS", 7502 "MSRIndex": "0x1a6,0x1a7", 7503 "MSRValue": "0x0200020020", 7504 "Offcore": "1", 7505 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7506 "SampleAfterValue": "100003", 7507 "UMask": "0x1" 7508 }, 7509 { 7510 "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads", 7511 "Counter": "0,1,2,3", 7512 "CounterHTOff": "0,1,2,3", 7513 "EventCode": "0xB7, 0xBB", 7514 "EventName": "OCR.PF_L3_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD", 7515 "MSRIndex": "0x1a6,0x1a7", 7516 "MSRValue": "0x08007C0080", 7517 "Offcore": "1", 7518 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7519 "SampleAfterValue": "100003", 7520 "UMask": "0x1" 7521 }, 7522 { 7523 "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs PF_L2_RFO & L3_HIT & HITM_OTHER_CORE", 7524 "Counter": "0,1,2,3", 7525 "CounterHTOff": "0,1,2,3", 7526 "EventCode": "0xB7, 0xBB", 7527 "EventName": "OCR.PF_L2_RFO.L3_HIT.HITM_OTHER_CORE", 7528 "MSRIndex": "0x1a6,0x1a7", 7529 "MSRValue": "0x10003C0020", 7530 "Offcore": "1", 7531 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7532 "SampleAfterValue": "100003", 7533 "UMask": "0x1" 7534 }, 7535 { 7536 "BriefDescription": "Counts any other requests OTHER & L3_HIT_S & HITM_OTHER_CORE", 7537 "Counter": "0,1,2,3", 7538 "CounterHTOff": "0,1,2,3", 7539 "EventCode": "0xB7, 0xBB", 7540 "EventName": "OCR.OTHER.L3_HIT_S.HITM_OTHER_CORE", 7541 "MSRIndex": "0x1a6,0x1a7", 7542 "MSRValue": "0x1000108000", 7543 "Offcore": "1", 7544 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7545 "SampleAfterValue": "100003", 7546 "UMask": "0x1" 7547 }, 7548 { 7549 "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads PF_L3_DATA_RD & L3_HIT_S & NO_SNOOP_NEEDED", 7550 "Counter": "0,1,2,3", 7551 "CounterHTOff": "0,1,2,3", 7552 "EventCode": "0xB7, 0xBB", 7553 "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDED", 7554 "MSRIndex": "0x1a6,0x1a7", 7555 "MSRValue": "0x0100100080", 7556 "Offcore": "1", 7557 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7558 "SampleAfterValue": "100003", 7559 "UMask": "0x1" 7560 }, 7561 { 7562 "BriefDescription": "Counts demand data reads", 7563 "Counter": "0,1,2,3", 7564 "CounterHTOff": "0,1,2,3", 7565 "EventCode": "0xB7, 0xBB", 7566 "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_M.SNOOP_NONE", 7567 "MSRIndex": "0x1a6,0x1a7", 7568 "MSRValue": "0x0080040001", 7569 "Offcore": "1", 7570 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7571 "SampleAfterValue": "100003", 7572 "UMask": "0x1" 7573 }, 7574 { 7575 "BriefDescription": "Counts all demand data writes (RFOs) DEMAND_RFO & L3_HIT & SNOOP_NONE", 7576 "Counter": "0,1,2,3", 7577 "CounterHTOff": "0,1,2,3", 7578 "EventCode": "0xB7, 0xBB", 7579 "EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_NONE", 7580 "MSRIndex": "0x1a6,0x1a7", 7581 "MSRValue": "0x00803C0002", 7582 "Offcore": "1", 7583 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7584 "SampleAfterValue": "100003", 7585 "UMask": "0x1" 7586 }, 7587 { 7588 "BriefDescription": "ALL_DATA_RD & L3_HIT_M & HIT_OTHER_CORE_NO_FWD", 7589 "Counter": "0,1,2,3", 7590 "CounterHTOff": "0,1,2,3", 7591 "EventCode": "0xB7, 0xBB", 7592 "EventName": "OCR.ALL_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", 7593 "MSRIndex": "0x1a6,0x1a7", 7594 "MSRValue": "0x0400040491", 7595 "Offcore": "1", 7596 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7597 "SampleAfterValue": "100003", 7598 "UMask": "0x1" 7599 }, 7600 { 7601 "BriefDescription": "ALL_PF_RFO & SUPPLIER_NONE & HIT_OTHER_CORE_FWD", 7602 "Counter": "0,1,2,3", 7603 "CounterHTOff": "0,1,2,3", 7604 "EventCode": "0xB7, 0xBB", 7605 "EventName": "OCR.ALL_PF_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", 7606 "MSRIndex": "0x1a6,0x1a7", 7607 "MSRValue": "0x0800020120", 7608 "Offcore": "1", 7609 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7610 "SampleAfterValue": "100003", 7611 "UMask": "0x1" 7612 }, 7613 { 7614 "BriefDescription": "ALL_PF_DATA_RD & L3_HIT_S & NO_SNOOP_NEEDED", 7615 "Counter": "0,1,2,3", 7616 "CounterHTOff": "0,1,2,3", 7617 "EventCode": "0xB7, 0xBB", 7618 "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDED", 7619 "MSRIndex": "0x1a6,0x1a7", 7620 "MSRValue": "0x0100100490", 7621 "Offcore": "1", 7622 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7623 "SampleAfterValue": "100003", 7624 "UMask": "0x1" 7625 }, 7626 { 7627 "BriefDescription": "Counts all demand data writes (RFOs) have any response type.", 7628 "Counter": "0,1,2,3", 7629 "CounterHTOff": "0,1,2,3", 7630 "EventCode": "0xB7, 0xBB", 7631 "EventName": "OCR.DEMAND_RFO.ANY_RESPONSE", 7632 "MSRIndex": "0x1a6,0x1a7", 7633 "MSRValue": "0x0000010002", 7634 "Offcore": "1", 7635 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7636 "SampleAfterValue": "100003", 7637 "UMask": "0x1" 7638 }, 7639 { 7640 "BriefDescription": "Counts all demand code reads DEMAND_CODE_RD & L3_HIT_M & HITM_OTHER_CORE", 7641 "Counter": "0,1,2,3", 7642 "CounterHTOff": "0,1,2,3", 7643 "EventCode": "0xB7, 0xBB", 7644 "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_M.HITM_OTHER_CORE", 7645 "MSRIndex": "0x1a6,0x1a7", 7646 "MSRValue": "0x1000040004", 7647 "Offcore": "1", 7648 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7649 "SampleAfterValue": "100003", 7650 "UMask": "0x1" 7651 }, 7652 { 7653 "BriefDescription": "Counts all demand code reads DEMAND_CODE_RD & SUPPLIER_NONE & NO_SNOOP_NEEDED", 7654 "Counter": "0,1,2,3", 7655 "CounterHTOff": "0,1,2,3", 7656 "EventCode": "0xB7, 0xBB", 7657 "EventName": "OCR.DEMAND_CODE_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED", 7658 "MSRIndex": "0x1a6,0x1a7", 7659 "MSRValue": "0x0100020004", 7660 "Offcore": "1", 7661 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7662 "SampleAfterValue": "100003", 7663 "UMask": "0x1" 7664 }, 7665 { 7666 "BriefDescription": "Counts demand data reads", 7667 "Counter": "0,1,2,3", 7668 "CounterHTOff": "0,1,2,3", 7669 "EventCode": "0xB7, 0xBB", 7670 "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_S.SNOOP_NONE", 7671 "MSRIndex": "0x1a6,0x1a7", 7672 "MSRValue": "0x0080100001", 7673 "Offcore": "1", 7674 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7675 "SampleAfterValue": "100003", 7676 "UMask": "0x1" 7677 }, 7678 { 7679 "BriefDescription": "Counts all demand data writes (RFOs) DEMAND_RFO & SUPPLIER_NONE & HIT_OTHER_CORE_NO_FWD", 7680 "Counter": "0,1,2,3", 7681 "CounterHTOff": "0,1,2,3", 7682 "EventCode": "0xB7, 0xBB", 7683 "EventName": "OCR.DEMAND_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", 7684 "MSRIndex": "0x1a6,0x1a7", 7685 "MSRValue": "0x0400020002", 7686 "Offcore": "1", 7687 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7688 "SampleAfterValue": "100003", 7689 "UMask": "0x1" 7690 }, 7691 { 7692 "BriefDescription": "Counts all demand code reads DEMAND_CODE_RD & L3_HIT_S & HIT_OTHER_CORE_FWD", 7693 "Counter": "0,1,2,3", 7694 "CounterHTOff": "0,1,2,3", 7695 "EventCode": "0xB7, 0xBB", 7696 "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_S.HIT_OTHER_CORE_FWD", 7697 "MSRIndex": "0x1a6,0x1a7", 7698 "MSRValue": "0x0800100004", 7699 "Offcore": "1", 7700 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7701 "SampleAfterValue": "100003", 7702 "UMask": "0x1" 7703 }, 7704 { 7705 "BriefDescription": "Counts any other requests OTHER & L3_HIT_F & HIT_OTHER_CORE_NO_FWD", 7706 "Counter": "0,1,2,3", 7707 "CounterHTOff": "0,1,2,3", 7708 "EventCode": "0xB7, 0xBB", 7709 "EventName": "OCR.OTHER.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", 7710 "MSRIndex": "0x1a6,0x1a7", 7711 "MSRValue": "0x0400208000", 7712 "Offcore": "1", 7713 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7714 "SampleAfterValue": "100003", 7715 "UMask": "0x1" 7716 }, 7717 { 7718 "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs have any response type.", 7719 "Counter": "0,1,2,3", 7720 "CounterHTOff": "0,1,2,3", 7721 "EventCode": "0xB7, 0xBB", 7722 "EventName": "OCR.PF_L3_RFO.ANY_RESPONSE", 7723 "MSRIndex": "0x1a6,0x1a7", 7724 "MSRValue": "0x0000010100", 7725 "Offcore": "1", 7726 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7727 "SampleAfterValue": "100003", 7728 "UMask": "0x1" 7729 }, 7730 { 7731 "BriefDescription": "ALL_DATA_RD & L3_HIT_E & SNOOP_MISS", 7732 "Counter": "0,1,2,3", 7733 "CounterHTOff": "0,1,2,3", 7734 "EventCode": "0xB7, 0xBB", 7735 "EventName": "OCR.ALL_DATA_RD.L3_HIT_E.SNOOP_MISS", 7736 "MSRIndex": "0x1a6,0x1a7", 7737 "MSRValue": "0x0200080491", 7738 "Offcore": "1", 7739 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7740 "SampleAfterValue": "100003", 7741 "UMask": "0x1" 7742 }, 7743 { 7744 "BriefDescription": "ALL_PF_DATA_RD & L3_HIT_E & HIT_OTHER_CORE_NO_FWD", 7745 "Counter": "0,1,2,3", 7746 "CounterHTOff": "0,1,2,3", 7747 "EventCode": "0xB7, 0xBB", 7748 "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", 7749 "MSRIndex": "0x1a6,0x1a7", 7750 "MSRValue": "0x0400080490", 7751 "Offcore": "1", 7752 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7753 "SampleAfterValue": "100003", 7754 "UMask": "0x1" 7755 }, 7756 { 7757 "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs PF_L3_RFO & L3_HIT_M & NO_SNOOP_NEEDED", 7758 "Counter": "0,1,2,3", 7759 "CounterHTOff": "0,1,2,3", 7760 "EventCode": "0xB7, 0xBB", 7761 "EventName": "OCR.PF_L3_RFO.L3_HIT_M.NO_SNOOP_NEEDED", 7762 "MSRIndex": "0x1a6,0x1a7", 7763 "MSRValue": "0x0100040100", 7764 "Offcore": "1", 7765 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7766 "SampleAfterValue": "100003", 7767 "UMask": "0x1" 7768 }, 7769 { 7770 "BriefDescription": "Counts demand data reads DEMAND_DATA_RD & L3_HIT_S & ANY_SNOOP", 7771 "Counter": "0,1,2,3", 7772 "CounterHTOff": "0,1,2,3", 7773 "EventCode": "0xB7, 0xBB", 7774 "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_S.ANY_SNOOP", 7775 "MSRIndex": "0x1a6,0x1a7", 7776 "MSRValue": "0x3F80100001", 7777 "Offcore": "1", 7778 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7779 "SampleAfterValue": "100003", 7780 "UMask": "0x1" 7781 }, 7782 { 7783 "BriefDescription": "ALL_DATA_RD & L3_HIT & SNOOP_MISS", 7784 "Counter": "0,1,2,3", 7785 "CounterHTOff": "0,1,2,3", 7786 "EventCode": "0xB7, 0xBB", 7787 "EventName": "OCR.ALL_DATA_RD.L3_HIT.SNOOP_MISS", 7788 "MSRIndex": "0x1a6,0x1a7", 7789 "MSRValue": "0x02003C0491", 7790 "Offcore": "1", 7791 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7792 "SampleAfterValue": "100003", 7793 "UMask": "0x1" 7794 }, 7795 { 7796 "BriefDescription": "Counts any other requests OTHER & L3_HIT_M & HIT_OTHER_CORE_NO_FWD", 7797 "Counter": "0,1,2,3", 7798 "CounterHTOff": "0,1,2,3", 7799 "EventCode": "0xB7, 0xBB", 7800 "EventName": "OCR.OTHER.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", 7801 "MSRIndex": "0x1a6,0x1a7", 7802 "MSRValue": "0x0400048000", 7803 "Offcore": "1", 7804 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7805 "SampleAfterValue": "100003", 7806 "UMask": "0x1" 7807 }, 7808 { 7809 "BriefDescription": "Counts prefetch (that bring data to L2) data reads PF_L2_DATA_RD & L3_HIT & ANY_SNOOP", 7810 "Counter": "0,1,2,3", 7811 "CounterHTOff": "0,1,2,3", 7812 "EventCode": "0xB7, 0xBB", 7813 "EventName": "OCR.PF_L2_DATA_RD.L3_HIT.ANY_SNOOP", 7814 "MSRIndex": "0x1a6,0x1a7", 7815 "MSRValue": "0x3F803C0010", 7816 "Offcore": "1", 7817 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7818 "SampleAfterValue": "100003", 7819 "UMask": "0x1" 7820 }, 7821 { 7822 "BriefDescription": "Counts any other requests", 7823 "Counter": "0,1,2,3", 7824 "CounterHTOff": "0,1,2,3", 7825 "EventCode": "0xB7, 0xBB", 7826 "EventName": "OCR.OTHER.L3_HIT_F.SNOOP_MISS", 7827 "MSRIndex": "0x1a6,0x1a7", 7828 "MSRValue": "0x0200208000", 7829 "Offcore": "1", 7830 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7831 "SampleAfterValue": "100003", 7832 "UMask": "0x1" 7833 }, 7834 { 7835 "BriefDescription": "ALL_PF_DATA_RD & L3_HIT & SNOOP_NONE", 7836 "Counter": "0,1,2,3", 7837 "CounterHTOff": "0,1,2,3", 7838 "EventCode": "0xB7, 0xBB", 7839 "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT.SNOOP_NONE", 7840 "MSRIndex": "0x1a6,0x1a7", 7841 "MSRValue": "0x00803C0490", 7842 "Offcore": "1", 7843 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7844 "SampleAfterValue": "100003", 7845 "UMask": "0x1" 7846 }, 7847 { 7848 "BriefDescription": "ALL_PF_RFO & SUPPLIER_NONE & ANY_SNOOP", 7849 "Counter": "0,1,2,3", 7850 "CounterHTOff": "0,1,2,3", 7851 "EventCode": "0xB7, 0xBB", 7852 "EventName": "OCR.ALL_PF_RFO.SUPPLIER_NONE.ANY_SNOOP", 7853 "MSRIndex": "0x1a6,0x1a7", 7854 "MSRValue": "0x3F80020120", 7855 "Offcore": "1", 7856 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7857 "SampleAfterValue": "100003", 7858 "UMask": "0x1" 7859 }, 7860 { 7861 "BriefDescription": "Counts prefetch (that bring data to L2) data reads hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.", 7862 "Counter": "0,1,2,3", 7863 "CounterHTOff": "0,1,2,3", 7864 "EventCode": "0xB7, 0xBB", 7865 "EventName": "OCR.PF_L2_DATA_RD.L3_HIT.NO_SNOOP_NEEDED", 7866 "MSRIndex": "0x1a6,0x1a7", 7867 "MSRValue": "0x01003C0010", 7868 "Offcore": "1", 7869 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7870 "SampleAfterValue": "100003", 7871 "UMask": "0x1" 7872 }, 7873 { 7874 "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests", 7875 "Counter": "0,1,2,3", 7876 "CounterHTOff": "0,1,2,3", 7877 "EventCode": "0xB7, 0xBB", 7878 "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_F.SNOOP_NONE", 7879 "MSRIndex": "0x1a6,0x1a7", 7880 "MSRValue": "0x0080200400", 7881 "Offcore": "1", 7882 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7883 "SampleAfterValue": "100003", 7884 "UMask": "0x1" 7885 }, 7886 { 7887 "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs PF_L2_RFO & L3_HIT_E & HIT_OTHER_CORE_FWD", 7888 "Counter": "0,1,2,3", 7889 "CounterHTOff": "0,1,2,3", 7890 "EventCode": "0xB7, 0xBB", 7891 "EventName": "OCR.PF_L2_RFO.L3_HIT_E.HIT_OTHER_CORE_FWD", 7892 "MSRIndex": "0x1a6,0x1a7", 7893 "MSRValue": "0x0800080020", 7894 "Offcore": "1", 7895 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7896 "SampleAfterValue": "100003", 7897 "UMask": "0x1" 7898 }, 7899 { 7900 "BriefDescription": "ALL_DATA_RD & L3_HIT_F & HIT_OTHER_CORE_FWD", 7901 "Counter": "0,1,2,3", 7902 "CounterHTOff": "0,1,2,3", 7903 "EventCode": "0xB7, 0xBB", 7904 "EventName": "OCR.ALL_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWD", 7905 "MSRIndex": "0x1a6,0x1a7", 7906 "MSRValue": "0x0800200491", 7907 "Offcore": "1", 7908 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7909 "SampleAfterValue": "100003", 7910 "UMask": "0x1" 7911 }, 7912 { 7913 "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests PF_L1D_AND_SW & L3_HIT_S & HITM_OTHER_CORE", 7914 "Counter": "0,1,2,3", 7915 "CounterHTOff": "0,1,2,3", 7916 "EventCode": "0xB7, 0xBB", 7917 "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_S.HITM_OTHER_CORE", 7918 "MSRIndex": "0x1a6,0x1a7", 7919 "MSRValue": "0x1000100400", 7920 "Offcore": "1", 7921 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7922 "SampleAfterValue": "100003", 7923 "UMask": "0x1" 7924 }, 7925 { 7926 "BriefDescription": "Counts prefetch (that bring data to L2) data reads", 7927 "Counter": "0,1,2,3", 7928 "CounterHTOff": "0,1,2,3", 7929 "EventCode": "0xB7, 0xBB", 7930 "EventName": "OCR.PF_L2_DATA_RD.SUPPLIER_NONE.SNOOP_NONE", 7931 "MSRIndex": "0x1a6,0x1a7", 7932 "MSRValue": "0x0080020010", 7933 "Offcore": "1", 7934 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7935 "SampleAfterValue": "100003", 7936 "UMask": "0x1" 7937 }, 7938 { 7939 "BriefDescription": "Counts all demand code reads", 7940 "Counter": "0,1,2,3", 7941 "CounterHTOff": "0,1,2,3", 7942 "EventCode": "0xB7, 0xBB", 7943 "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_M.SNOOP_NONE", 7944 "MSRIndex": "0x1a6,0x1a7", 7945 "MSRValue": "0x0080040004", 7946 "Offcore": "1", 7947 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7948 "SampleAfterValue": "100003", 7949 "UMask": "0x1" 7950 }, 7951 { 7952 "BriefDescription": "Counts all demand code reads DEMAND_CODE_RD & L3_HIT_E & HIT_OTHER_CORE_NO_FWD", 7953 "Counter": "0,1,2,3", 7954 "CounterHTOff": "0,1,2,3", 7955 "EventCode": "0xB7, 0xBB", 7956 "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", 7957 "MSRIndex": "0x1a6,0x1a7", 7958 "MSRValue": "0x0400080004", 7959 "Offcore": "1", 7960 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7961 "SampleAfterValue": "100003", 7962 "UMask": "0x1" 7963 }, 7964 { 7965 "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs PF_L3_RFO & L3_HIT_E & HIT_OTHER_CORE_NO_FWD", 7966 "Counter": "0,1,2,3", 7967 "CounterHTOff": "0,1,2,3", 7968 "EventCode": "0xB7, 0xBB", 7969 "EventName": "OCR.PF_L3_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", 7970 "MSRIndex": "0x1a6,0x1a7", 7971 "MSRValue": "0x0400080100", 7972 "Offcore": "1", 7973 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7974 "SampleAfterValue": "100003", 7975 "UMask": "0x1" 7976 }, 7977 { 7978 "BriefDescription": "Counts prefetch (that bring data to L2) data reads PF_L2_DATA_RD & L3_HIT_M & HITM_OTHER_CORE", 7979 "Counter": "0,1,2,3", 7980 "CounterHTOff": "0,1,2,3", 7981 "EventCode": "0xB7, 0xBB", 7982 "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_M.HITM_OTHER_CORE", 7983 "MSRIndex": "0x1a6,0x1a7", 7984 "MSRValue": "0x1000040010", 7985 "Offcore": "1", 7986 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7987 "SampleAfterValue": "100003", 7988 "UMask": "0x1" 7989 }, 7990 { 7991 "BriefDescription": "Counts demand data reads", 7992 "Counter": "0,1,2,3", 7993 "CounterHTOff": "0,1,2,3", 7994 "EventCode": "0xB7, 0xBB", 7995 "EventName": "OCR.DEMAND_DATA_RD.SUPPLIER_NONE.SNOOP_MISS", 7996 "MSRIndex": "0x1a6,0x1a7", 7997 "MSRValue": "0x0200020001", 7998 "Offcore": "1", 7999 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8000 "SampleAfterValue": "100003", 8001 "UMask": "0x1" 8002 }, 8003 { 8004 "BriefDescription": "Counts demand data reads DEMAND_DATA_RD & L3_HIT_E & HIT_OTHER_CORE_NO_FWD", 8005 "Counter": "0,1,2,3", 8006 "CounterHTOff": "0,1,2,3", 8007 "EventCode": "0xB7, 0xBB", 8008 "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", 8009 "MSRIndex": "0x1a6,0x1a7", 8010 "MSRValue": "0x0400080001", 8011 "Offcore": "1", 8012 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8013 "SampleAfterValue": "100003", 8014 "UMask": "0x1" 8015 }, 8016 { 8017 "BriefDescription": "ALL_READS & L3_HIT_F & HIT_OTHER_CORE_NO_FWD", 8018 "Counter": "0,1,2,3", 8019 "CounterHTOff": "0,1,2,3", 8020 "EventCode": "0xB7, 0xBB", 8021 "EventName": "OCR.ALL_READS.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", 8022 "MSRIndex": "0x1a6,0x1a7", 8023 "MSRValue": "0x04002007F7", 8024 "Offcore": "1", 8025 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8026 "SampleAfterValue": "100003", 8027 "UMask": "0x1" 8028 }, 8029 { 8030 "BriefDescription": "ALL_RFO & L3_HIT_E & HITM_OTHER_CORE", 8031 "Counter": "0,1,2,3", 8032 "CounterHTOff": "0,1,2,3", 8033 "EventCode": "0xB7, 0xBB", 8034 "EventName": "OCR.ALL_RFO.L3_HIT_E.HITM_OTHER_CORE", 8035 "MSRIndex": "0x1a6,0x1a7", 8036 "MSRValue": "0x1000080122", 8037 "Offcore": "1", 8038 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8039 "SampleAfterValue": "100003", 8040 "UMask": "0x1" 8041 }, 8042 { 8043 "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs", 8044 "Counter": "0,1,2,3", 8045 "CounterHTOff": "0,1,2,3", 8046 "EventCode": "0xB7, 0xBB", 8047 "EventName": "OCR.PF_L2_RFO.L3_HIT.SNOOP_HIT_WITH_FWD", 8048 "MSRIndex": "0x1a6,0x1a7", 8049 "MSRValue": "0x08007C0020", 8050 "Offcore": "1", 8051 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8052 "SampleAfterValue": "100003", 8053 "UMask": "0x1" 8054 }, 8055 { 8056 "BriefDescription": "Counts all demand data writes (RFOs) DEMAND_RFO & L3_HIT_F & HIT_OTHER_CORE_NO_FWD", 8057 "Counter": "0,1,2,3", 8058 "CounterHTOff": "0,1,2,3", 8059 "EventCode": "0xB7, 0xBB", 8060 "EventName": "OCR.DEMAND_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", 8061 "MSRIndex": "0x1a6,0x1a7", 8062 "MSRValue": "0x0400200002", 8063 "Offcore": "1", 8064 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8065 "SampleAfterValue": "100003", 8066 "UMask": "0x1" 8067 }, 8068 { 8069 "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs", 8070 "Counter": "0,1,2,3", 8071 "CounterHTOff": "0,1,2,3", 8072 "EventCode": "0xB7, 0xBB", 8073 "EventName": "OCR.PF_L2_RFO.L3_HIT_E.SNOOP_MISS", 8074 "MSRIndex": "0x1a6,0x1a7", 8075 "MSRValue": "0x0200080020", 8076 "Offcore": "1", 8077 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8078 "SampleAfterValue": "100003", 8079 "UMask": "0x1" 8080 }, 8081 { 8082 "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests", 8083 "Counter": "0,1,2,3", 8084 "CounterHTOff": "0,1,2,3", 8085 "EventCode": "0xB7, 0xBB", 8086 "EventName": "OCR.PF_L1D_AND_SW.SUPPLIER_NONE.SNOOP_NONE", 8087 "MSRIndex": "0x1a6,0x1a7", 8088 "MSRValue": "0x0080020400", 8089 "Offcore": "1", 8090 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8091 "SampleAfterValue": "100003", 8092 "UMask": "0x1" 8093 }, 8094 { 8095 "BriefDescription": "ALL_DATA_RD & SUPPLIER_NONE & NO_SNOOP_NEEDED", 8096 "Counter": "0,1,2,3", 8097 "CounterHTOff": "0,1,2,3", 8098 "EventCode": "0xB7, 0xBB", 8099 "EventName": "OCR.ALL_DATA_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED", 8100 "MSRIndex": "0x1a6,0x1a7", 8101 "MSRValue": "0x0100020491", 8102 "Offcore": "1", 8103 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8104 "SampleAfterValue": "100003", 8105 "UMask": "0x1" 8106 }, 8107 { 8108 "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs PF_L3_RFO & L3_HIT_S & ANY_SNOOP", 8109 "Counter": "0,1,2,3", 8110 "CounterHTOff": "0,1,2,3", 8111 "EventCode": "0xB7, 0xBB", 8112 "EventName": "OCR.PF_L3_RFO.L3_HIT_S.ANY_SNOOP", 8113 "MSRIndex": "0x1a6,0x1a7", 8114 "MSRValue": "0x3F80100100", 8115 "Offcore": "1", 8116 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8117 "SampleAfterValue": "100003", 8118 "UMask": "0x1" 8119 }, 8120 { 8121 "BriefDescription": "ALL_PF_RFO & L3_HIT_F & ANY_SNOOP", 8122 "Counter": "0,1,2,3", 8123 "CounterHTOff": "0,1,2,3", 8124 "EventCode": "0xB7, 0xBB", 8125 "EventName": "OCR.ALL_PF_RFO.L3_HIT_F.ANY_SNOOP", 8126 "MSRIndex": "0x1a6,0x1a7", 8127 "MSRValue": "0x3F80200120", 8128 "Offcore": "1", 8129 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8130 "SampleAfterValue": "100003", 8131 "UMask": "0x1" 8132 }, 8133 { 8134 "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.", 8135 "Counter": "0,1,2,3", 8136 "CounterHTOff": "0,1,2,3", 8137 "EventCode": "0xB7, 0xBB", 8138 "EventName": "OCR.PF_L1D_AND_SW.L3_HIT.NO_SNOOP_NEEDED", 8139 "MSRIndex": "0x1a6,0x1a7", 8140 "MSRValue": "0x01003C0400", 8141 "Offcore": "1", 8142 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8143 "SampleAfterValue": "100003", 8144 "UMask": "0x1" 8145 }, 8146 { 8147 "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads PF_L3_DATA_RD & L3_HIT_M & HIT_OTHER_CORE_NO_FWD", 8148 "Counter": "0,1,2,3", 8149 "CounterHTOff": "0,1,2,3", 8150 "EventCode": "0xB7, 0xBB", 8151 "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", 8152 "MSRIndex": "0x1a6,0x1a7", 8153 "MSRValue": "0x0400040080", 8154 "Offcore": "1", 8155 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8156 "SampleAfterValue": "100003", 8157 "UMask": "0x1" 8158 }, 8159 { 8160 "BriefDescription": "Counts prefetch (that bring data to L2) data reads PF_L2_DATA_RD & L3_HIT_F & HITM_OTHER_CORE", 8161 "Counter": "0,1,2,3", 8162 "CounterHTOff": "0,1,2,3", 8163 "EventCode": "0xB7, 0xBB", 8164 "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_F.HITM_OTHER_CORE", 8165 "MSRIndex": "0x1a6,0x1a7", 8166 "MSRValue": "0x1000200010", 8167 "Offcore": "1", 8168 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8169 "SampleAfterValue": "100003", 8170 "UMask": "0x1" 8171 }, 8172 { 8173 "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs PF_L2_RFO & L3_HIT_M & NO_SNOOP_NEEDED", 8174 "Counter": "0,1,2,3", 8175 "CounterHTOff": "0,1,2,3", 8176 "EventCode": "0xB7, 0xBB", 8177 "EventName": "OCR.PF_L2_RFO.L3_HIT_M.NO_SNOOP_NEEDED", 8178 "MSRIndex": "0x1a6,0x1a7", 8179 "MSRValue": "0x0100040020", 8180 "Offcore": "1", 8181 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8182 "SampleAfterValue": "100003", 8183 "UMask": "0x1" 8184 }, 8185 { 8186 "BriefDescription": "Counts any other requests OTHER & L3_HIT & HITM_OTHER_CORE", 8187 "Counter": "0,1,2,3", 8188 "CounterHTOff": "0,1,2,3", 8189 "EventCode": "0xB7, 0xBB", 8190 "EventName": "OCR.OTHER.L3_HIT.HITM_OTHER_CORE", 8191 "MSRIndex": "0x1a6,0x1a7", 8192 "MSRValue": "0x10003C8000", 8193 "Offcore": "1", 8194 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8195 "SampleAfterValue": "100003", 8196 "UMask": "0x1" 8197 }, 8198 { 8199 "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs PF_L3_RFO & L3_HIT_M & HIT_OTHER_CORE_FWD", 8200 "Counter": "0,1,2,3", 8201 "CounterHTOff": "0,1,2,3", 8202 "EventCode": "0xB7, 0xBB", 8203 "EventName": "OCR.PF_L3_RFO.L3_HIT_M.HIT_OTHER_CORE_FWD", 8204 "MSRIndex": "0x1a6,0x1a7", 8205 "MSRValue": "0x0800040100", 8206 "Offcore": "1", 8207 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8208 "SampleAfterValue": "100003", 8209 "UMask": "0x1" 8210 }, 8211 { 8212 "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs", 8213 "Counter": "0,1,2,3", 8214 "CounterHTOff": "0,1,2,3", 8215 "EventCode": "0xB7, 0xBB", 8216 "EventName": "OCR.PF_L3_RFO.L3_HIT_S.SNOOP_MISS", 8217 "MSRIndex": "0x1a6,0x1a7", 8218 "MSRValue": "0x0200100100", 8219 "Offcore": "1", 8220 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8221 "SampleAfterValue": "100003", 8222 "UMask": "0x1" 8223 }, 8224 { 8225 "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests PF_L1D_AND_SW & L3_HIT_E & HIT_OTHER_CORE_NO_FWD", 8226 "Counter": "0,1,2,3", 8227 "CounterHTOff": "0,1,2,3", 8228 "EventCode": "0xB7, 0xBB", 8229 "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", 8230 "MSRIndex": "0x1a6,0x1a7", 8231 "MSRValue": "0x0400080400", 8232 "Offcore": "1", 8233 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8234 "SampleAfterValue": "100003", 8235 "UMask": "0x1" 8236 }, 8237 { 8238 "BriefDescription": "Counts demand data reads DEMAND_DATA_RD & L3_HIT_F & HITM_OTHER_CORE", 8239 "Counter": "0,1,2,3", 8240 "CounterHTOff": "0,1,2,3", 8241 "EventCode": "0xB7, 0xBB", 8242 "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_F.HITM_OTHER_CORE", 8243 "MSRIndex": "0x1a6,0x1a7", 8244 "MSRValue": "0x1000200001", 8245 "Offcore": "1", 8246 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8247 "SampleAfterValue": "100003", 8248 "UMask": "0x1" 8249 }, 8250 { 8251 "BriefDescription": "Number of PREFETCHNTA instructions executed.", 8252 "Counter": "0,1,2,3", 8253 "CounterHTOff": "0,1,2,3,4,5,6,7", 8254 "EventCode": "0x32", 8255 "EventName": "SW_PREFETCH_ACCESS.NTA", 8256 "SampleAfterValue": "2000003", 8257 "UMask": "0x1" 8258 }, 8259 { 8260 "BriefDescription": "Counts all demand code reads DEMAND_CODE_RD & L3_HIT_F & NO_SNOOP_NEEDED", 8261 "Counter": "0,1,2,3", 8262 "CounterHTOff": "0,1,2,3", 8263 "EventCode": "0xB7, 0xBB", 8264 "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_F.NO_SNOOP_NEEDED", 8265 "MSRIndex": "0x1a6,0x1a7", 8266 "MSRValue": "0x0100200004", 8267 "Offcore": "1", 8268 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8269 "SampleAfterValue": "100003", 8270 "UMask": "0x1" 8271 }, 8272 { 8273 "BriefDescription": "Counts all demand code reads DEMAND_CODE_RD & L3_HIT_M & HIT_OTHER_CORE_FWD", 8274 "Counter": "0,1,2,3", 8275 "CounterHTOff": "0,1,2,3", 8276 "EventCode": "0xB7, 0xBB", 8277 "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_M.HIT_OTHER_CORE_FWD", 8278 "MSRIndex": "0x1a6,0x1a7", 8279 "MSRValue": "0x0800040004", 8280 "Offcore": "1", 8281 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8282 "SampleAfterValue": "100003", 8283 "UMask": "0x1" 8284 }, 8285 { 8286 "BriefDescription": "ALL_PF_RFO & L3_HIT_S & SNOOP_NONE", 8287 "Counter": "0,1,2,3", 8288 "CounterHTOff": "0,1,2,3", 8289 "EventCode": "0xB7, 0xBB", 8290 "EventName": "OCR.ALL_PF_RFO.L3_HIT_S.SNOOP_NONE", 8291 "MSRIndex": "0x1a6,0x1a7", 8292 "MSRValue": "0x0080100120", 8293 "Offcore": "1", 8294 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8295 "SampleAfterValue": "100003", 8296 "UMask": "0x1" 8297 }, 8298 { 8299 "BriefDescription": "Counts all demand code reads", 8300 "Counter": "0,1,2,3", 8301 "CounterHTOff": "0,1,2,3", 8302 "EventCode": "0xB7, 0xBB", 8303 "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_S.SNOOP_NONE", 8304 "MSRIndex": "0x1a6,0x1a7", 8305 "MSRValue": "0x0080100004", 8306 "Offcore": "1", 8307 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8308 "SampleAfterValue": "100003", 8309 "UMask": "0x1" 8310 }, 8311 { 8312 "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests PF_L1D_AND_SW & L3_HIT_M & NO_SNOOP_NEEDED", 8313 "Counter": "0,1,2,3", 8314 "CounterHTOff": "0,1,2,3", 8315 "EventCode": "0xB7, 0xBB", 8316 "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_M.NO_SNOOP_NEEDED", 8317 "MSRIndex": "0x1a6,0x1a7", 8318 "MSRValue": "0x0100040400", 8319 "Offcore": "1", 8320 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8321 "SampleAfterValue": "100003", 8322 "UMask": "0x1" 8323 }, 8324 { 8325 "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests PF_L1D_AND_SW & L3_HIT & HIT_OTHER_CORE_FWD", 8326 "Counter": "0,1,2,3", 8327 "CounterHTOff": "0,1,2,3", 8328 "EventCode": "0xB7, 0xBB", 8329 "EventName": "OCR.PF_L1D_AND_SW.L3_HIT.HIT_OTHER_CORE_FWD", 8330 "MSRIndex": "0x1a6,0x1a7", 8331 "MSRValue": "0x08003C0400", 8332 "Offcore": "1", 8333 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8334 "SampleAfterValue": "100003", 8335 "UMask": "0x1" 8336 }, 8337 { 8338 "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests", 8339 "Counter": "0,1,2,3", 8340 "CounterHTOff": "0,1,2,3", 8341 "EventCode": "0xB7, 0xBB", 8342 "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_F.SNOOP_MISS", 8343 "MSRIndex": "0x1a6,0x1a7", 8344 "MSRValue": "0x0200200400", 8345 "Offcore": "1", 8346 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8347 "SampleAfterValue": "100003", 8348 "UMask": "0x1" 8349 }, 8350 { 8351 "BriefDescription": "ALL_RFO & L3_HIT_E & SNOOP_NONE", 8352 "Counter": "0,1,2,3", 8353 "CounterHTOff": "0,1,2,3", 8354 "EventCode": "0xB7, 0xBB", 8355 "EventName": "OCR.ALL_RFO.L3_HIT_E.SNOOP_NONE", 8356 "MSRIndex": "0x1a6,0x1a7", 8357 "MSRValue": "0x0080080122", 8358 "Offcore": "1", 8359 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8360 "SampleAfterValue": "100003", 8361 "UMask": "0x1" 8362 }, 8363 { 8364 "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs PF_L2_RFO & L3_HIT_S & ANY_SNOOP", 8365 "Counter": "0,1,2,3", 8366 "CounterHTOff": "0,1,2,3", 8367 "EventCode": "0xB7, 0xBB", 8368 "EventName": "OCR.PF_L2_RFO.L3_HIT_S.ANY_SNOOP", 8369 "MSRIndex": "0x1a6,0x1a7", 8370 "MSRValue": "0x3F80100020", 8371 "Offcore": "1", 8372 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8373 "SampleAfterValue": "100003", 8374 "UMask": "0x1" 8375 }, 8376 { 8377 "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs PF_L2_RFO & L3_HIT_S & NO_SNOOP_NEEDED", 8378 "Counter": "0,1,2,3", 8379 "CounterHTOff": "0,1,2,3", 8380 "EventCode": "0xB7, 0xBB", 8381 "EventName": "OCR.PF_L2_RFO.L3_HIT_S.NO_SNOOP_NEEDED", 8382 "MSRIndex": "0x1a6,0x1a7", 8383 "MSRValue": "0x0100100020", 8384 "Offcore": "1", 8385 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8386 "SampleAfterValue": "100003", 8387 "UMask": "0x1" 8388 }, 8389 { 8390 "BriefDescription": "ALL_RFO & L3_HIT_F & SNOOP_NONE", 8391 "Counter": "0,1,2,3", 8392 "CounterHTOff": "0,1,2,3", 8393 "EventCode": "0xB7, 0xBB", 8394 "EventName": "OCR.ALL_RFO.L3_HIT_F.SNOOP_NONE", 8395 "MSRIndex": "0x1a6,0x1a7", 8396 "MSRValue": "0x0080200122", 8397 "Offcore": "1", 8398 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8399 "SampleAfterValue": "100003", 8400 "UMask": "0x1" 8401 }, 8402 { 8403 "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads PF_L3_DATA_RD & L3_HIT & HIT_OTHER_CORE_FWD", 8404 "Counter": "0,1,2,3", 8405 "CounterHTOff": "0,1,2,3", 8406 "EventCode": "0xB7, 0xBB", 8407 "EventName": "OCR.PF_L3_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD", 8408 "MSRIndex": "0x1a6,0x1a7", 8409 "MSRValue": "0x08003C0080", 8410 "Offcore": "1", 8411 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8412 "SampleAfterValue": "100003", 8413 "UMask": "0x1" 8414 }, 8415 { 8416 "BriefDescription": "Counts demand data reads DEMAND_DATA_RD & L3_HIT_M & NO_SNOOP_NEEDED", 8417 "Counter": "0,1,2,3", 8418 "CounterHTOff": "0,1,2,3", 8419 "EventCode": "0xB7, 0xBB", 8420 "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDED", 8421 "MSRIndex": "0x1a6,0x1a7", 8422 "MSRValue": "0x0100040001", 8423 "Offcore": "1", 8424 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8425 "SampleAfterValue": "100003", 8426 "UMask": "0x1" 8427 }, 8428 { 8429 "BriefDescription": "Counts prefetch (that bring data to L2) data reads PF_L2_DATA_RD & L3_HIT_S & HIT_OTHER_CORE_FWD", 8430 "Counter": "0,1,2,3", 8431 "CounterHTOff": "0,1,2,3", 8432 "EventCode": "0xB7, 0xBB", 8433 "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWD", 8434 "MSRIndex": "0x1a6,0x1a7", 8435 "MSRValue": "0x0800100010", 8436 "Offcore": "1", 8437 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8438 "SampleAfterValue": "100003", 8439 "UMask": "0x1" 8440 }, 8441 { 8442 "BriefDescription": "ALL_DATA_RD & SUPPLIER_NONE & HITM_OTHER_CORE", 8443 "Counter": "0,1,2,3", 8444 "CounterHTOff": "0,1,2,3", 8445 "EventCode": "0xB7, 0xBB", 8446 "EventName": "OCR.ALL_DATA_RD.SUPPLIER_NONE.HITM_OTHER_CORE", 8447 "MSRIndex": "0x1a6,0x1a7", 8448 "MSRValue": "0x1000020491", 8449 "Offcore": "1", 8450 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8451 "SampleAfterValue": "100003", 8452 "UMask": "0x1" 8453 }, 8454 { 8455 "BriefDescription": "ALL_PF_DATA_RD & L3_HIT_E & HIT_OTHER_CORE_FWD", 8456 "Counter": "0,1,2,3", 8457 "CounterHTOff": "0,1,2,3", 8458 "EventCode": "0xB7, 0xBB", 8459 "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWD", 8460 "MSRIndex": "0x1a6,0x1a7", 8461 "MSRValue": "0x0800080490", 8462 "Offcore": "1", 8463 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8464 "SampleAfterValue": "100003", 8465 "UMask": "0x1" 8466 }, 8467 { 8468 "BriefDescription": "Counts any other requests OTHER & L3_HIT_F & NO_SNOOP_NEEDED", 8469 "Counter": "0,1,2,3", 8470 "CounterHTOff": "0,1,2,3", 8471 "EventCode": "0xB7, 0xBB", 8472 "EventName": "OCR.OTHER.L3_HIT_F.NO_SNOOP_NEEDED", 8473 "MSRIndex": "0x1a6,0x1a7", 8474 "MSRValue": "0x0100208000", 8475 "Offcore": "1", 8476 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8477 "SampleAfterValue": "100003", 8478 "UMask": "0x1" 8479 }, 8480 { 8481 "BriefDescription": "ALL_READS & L3_HIT_S & ANY_SNOOP", 8482 "Counter": "0,1,2,3", 8483 "CounterHTOff": "0,1,2,3", 8484 "EventCode": "0xB7, 0xBB", 8485 "EventName": "OCR.ALL_READS.L3_HIT_S.ANY_SNOOP", 8486 "MSRIndex": "0x1a6,0x1a7", 8487 "MSRValue": "0x3F801007F7", 8488 "Offcore": "1", 8489 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8490 "SampleAfterValue": "100003", 8491 "UMask": "0x1" 8492 }, 8493 { 8494 "BriefDescription": "Counts all demand data writes (RFOs)", 8495 "Counter": "0,1,2,3", 8496 "CounterHTOff": "0,1,2,3", 8497 "EventCode": "0xB7, 0xBB", 8498 "EventName": "OCR.DEMAND_RFO.L3_HIT_E.SNOOP_MISS", 8499 "MSRIndex": "0x1a6,0x1a7", 8500 "MSRValue": "0x0200080002", 8501 "Offcore": "1", 8502 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8503 "SampleAfterValue": "100003", 8504 "UMask": "0x1" 8505 }, 8506 { 8507 "BriefDescription": "Counts prefetch (that bring data to L2) data reads PF_L2_DATA_RD & SUPPLIER_NONE & HIT_OTHER_CORE_FWD", 8508 "Counter": "0,1,2,3", 8509 "CounterHTOff": "0,1,2,3", 8510 "EventCode": "0xB7, 0xBB", 8511 "EventName": "OCR.PF_L2_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", 8512 "MSRIndex": "0x1a6,0x1a7", 8513 "MSRValue": "0x0800020010", 8514 "Offcore": "1", 8515 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8516 "SampleAfterValue": "100003", 8517 "UMask": "0x1" 8518 }, 8519 { 8520 "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads PF_L3_DATA_RD & L3_HIT & HIT_OTHER_CORE_NO_FWD", 8521 "Counter": "0,1,2,3", 8522 "CounterHTOff": "0,1,2,3", 8523 "EventCode": "0xB7, 0xBB", 8524 "EventName": "OCR.PF_L3_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD", 8525 "MSRIndex": "0x1a6,0x1a7", 8526 "MSRValue": "0x04003C0080", 8527 "Offcore": "1", 8528 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8529 "SampleAfterValue": "100003", 8530 "UMask": "0x1" 8531 }, 8532 { 8533 "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs", 8534 "Counter": "0,1,2,3", 8535 "CounterHTOff": "0,1,2,3", 8536 "EventCode": "0xB7, 0xBB", 8537 "EventName": "OCR.PF_L3_RFO.L3_HIT_F.SNOOP_NONE", 8538 "MSRIndex": "0x1a6,0x1a7", 8539 "MSRValue": "0x0080200100", 8540 "Offcore": "1", 8541 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8542 "SampleAfterValue": "100003", 8543 "UMask": "0x1" 8544 }, 8545 { 8546 "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads PF_L3_DATA_RD & L3_HIT_E & HIT_OTHER_CORE_FWD", 8547 "Counter": "0,1,2,3", 8548 "CounterHTOff": "0,1,2,3", 8549 "EventCode": "0xB7, 0xBB", 8550 "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWD", 8551 "MSRIndex": "0x1a6,0x1a7", 8552 "MSRValue": "0x0800080080", 8553 "Offcore": "1", 8554 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8555 "SampleAfterValue": "100003", 8556 "UMask": "0x1" 8557 }, 8558 { 8559 "BriefDescription": "ALL_RFO & PMM_HIT_LOCAL_PMM & SNOOP_NOT_NEEDED", 8560 "Counter": "0,1,2,3", 8561 "CounterHTOff": "0,1,2,3", 8562 "EventCode": "0xB7, 0xBB", 8563 "EventName": "OCR.ALL_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", 8564 "MSRIndex": "0x1a6,0x1a7", 8565 "MSRValue": "0x0100400122", 8566 "Offcore": "1", 8567 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8568 "SampleAfterValue": "100003", 8569 "UMask": "0x1" 8570 }, 8571 { 8572 "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs PF_L3_RFO & L3_HIT_E & HIT_OTHER_CORE_FWD", 8573 "Counter": "0,1,2,3", 8574 "CounterHTOff": "0,1,2,3", 8575 "EventCode": "0xB7, 0xBB", 8576 "EventName": "OCR.PF_L3_RFO.L3_HIT_E.HIT_OTHER_CORE_FWD", 8577 "MSRIndex": "0x1a6,0x1a7", 8578 "MSRValue": "0x0800080100", 8579 "Offcore": "1", 8580 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8581 "SampleAfterValue": "100003", 8582 "UMask": "0x1" 8583 }, 8584 { 8585 "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads PF_L3_DATA_RD & L3_HIT_M & ANY_SNOOP", 8586 "Counter": "0,1,2,3", 8587 "CounterHTOff": "0,1,2,3", 8588 "EventCode": "0xB7, 0xBB", 8589 "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_M.ANY_SNOOP", 8590 "MSRIndex": "0x1a6,0x1a7", 8591 "MSRValue": "0x3F80040080", 8592 "Offcore": "1", 8593 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8594 "SampleAfterValue": "100003", 8595 "UMask": "0x1" 8596 }, 8597 { 8598 "BriefDescription": "ALL_PF_RFO & PMM_HIT_LOCAL_PMM & SNOOP_NOT_NEEDED", 8599 "Counter": "0,1,2,3", 8600 "CounterHTOff": "0,1,2,3", 8601 "EventCode": "0xB7, 0xBB", 8602 "EventName": "OCR.ALL_PF_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", 8603 "MSRIndex": "0x1a6,0x1a7", 8604 "MSRValue": "0x0100400120", 8605 "Offcore": "1", 8606 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8607 "SampleAfterValue": "100003", 8608 "UMask": "0x1" 8609 }, 8610 { 8611 "BriefDescription": "ALL_DATA_RD & SUPPLIER_NONE & HIT_OTHER_CORE_FWD", 8612 "Counter": "0,1,2,3", 8613 "CounterHTOff": "0,1,2,3", 8614 "EventCode": "0xB7, 0xBB", 8615 "EventName": "OCR.ALL_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", 8616 "MSRIndex": "0x1a6,0x1a7", 8617 "MSRValue": "0x0800020491", 8618 "Offcore": "1", 8619 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8620 "SampleAfterValue": "100003", 8621 "UMask": "0x1" 8622 }, 8623 { 8624 "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests PF_L1D_AND_SW & L3_HIT_E & HIT_OTHER_CORE_FWD", 8625 "Counter": "0,1,2,3", 8626 "CounterHTOff": "0,1,2,3", 8627 "EventCode": "0xB7, 0xBB", 8628 "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_E.HIT_OTHER_CORE_FWD", 8629 "MSRIndex": "0x1a6,0x1a7", 8630 "MSRValue": "0x0800080400", 8631 "Offcore": "1", 8632 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8633 "SampleAfterValue": "100003", 8634 "UMask": "0x1" 8635 }, 8636 { 8637 "BriefDescription": "Counts prefetch (that bring data to L2) data reads PF_L2_DATA_RD & L3_HIT_F & HIT_OTHER_CORE_NO_FWD", 8638 "Counter": "0,1,2,3", 8639 "CounterHTOff": "0,1,2,3", 8640 "EventCode": "0xB7, 0xBB", 8641 "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", 8642 "MSRIndex": "0x1a6,0x1a7", 8643 "MSRValue": "0x0400200010", 8644 "Offcore": "1", 8645 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8646 "SampleAfterValue": "100003", 8647 "UMask": "0x1" 8648 }, 8649 { 8650 "BriefDescription": "ALL_READS & L3_HIT_S & SNOOP_MISS", 8651 "Counter": "0,1,2,3", 8652 "CounterHTOff": "0,1,2,3", 8653 "EventCode": "0xB7, 0xBB", 8654 "EventName": "OCR.ALL_READS.L3_HIT_S.SNOOP_MISS", 8655 "MSRIndex": "0x1a6,0x1a7", 8656 "MSRValue": "0x02001007F7", 8657 "Offcore": "1", 8658 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8659 "SampleAfterValue": "100003", 8660 "UMask": "0x1" 8661 } 8662]