1ecd94f1bSKan Liang[ 2ecd94f1bSKan Liang { 3ecd94f1bSKan Liang "EventCode": "0x09", 4ecd94f1bSKan Liang "UMask": "0x1", 5ecd94f1bSKan Liang "Counter": "0,1,2,3", 6ecd94f1bSKan Liang "EventName": "MEMORY_DISAMBIGUATION.HISTORY_RESET", 7ecd94f1bSKan Liang "SampleAfterValue": "2000003", 8ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3,4,5,6,7" 9ecd94f1bSKan Liang }, 10ecd94f1bSKan Liang { 11ecd94f1bSKan Liang "EventCode": "0x28", 12ecd94f1bSKan Liang "UMask": "0x7", 13ecd94f1bSKan Liang "BriefDescription": "Core cycles where the core was running in a manner where Turbo may be clipped to the Non-AVX turbo schedule.", 14ecd94f1bSKan Liang "Counter": "0,1,2,3", 15ecd94f1bSKan Liang "EventName": "CORE_POWER.LVL0_TURBO_LICENSE", 16ecd94f1bSKan Liang "PublicDescription": "Core cycles where the core was running with power-delivery for baseline license level 0. This includes non-AVX codes, SSE, AVX 128-bit, and low-current AVX 256-bit codes.", 17ecd94f1bSKan Liang "SampleAfterValue": "200003", 18ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3,4,5,6,7" 19ecd94f1bSKan Liang }, 20ecd94f1bSKan Liang { 21ecd94f1bSKan Liang "EventCode": "0x28", 22ecd94f1bSKan Liang "UMask": "0x18", 23ecd94f1bSKan Liang "BriefDescription": "Core cycles where the core was running in a manner where Turbo may be clipped to the AVX2 turbo schedule.", 24ecd94f1bSKan Liang "Counter": "0,1,2,3", 25ecd94f1bSKan Liang "EventName": "CORE_POWER.LVL1_TURBO_LICENSE", 26ecd94f1bSKan Liang "PublicDescription": "Core cycles where the core was running with power-delivery for license level 1. This includes high current AVX 256-bit instructions as well as low current AVX 512-bit instructions.", 27ecd94f1bSKan Liang "SampleAfterValue": "200003", 28ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3,4,5,6,7" 29ecd94f1bSKan Liang }, 30ecd94f1bSKan Liang { 31ecd94f1bSKan Liang "EventCode": "0x28", 32ecd94f1bSKan Liang "UMask": "0x20", 33ecd94f1bSKan Liang "BriefDescription": "Core cycles where the core was running in a manner where Turbo may be clipped to the AVX512 turbo schedule.", 34ecd94f1bSKan Liang "Counter": "0,1,2,3", 35ecd94f1bSKan Liang "EventName": "CORE_POWER.LVL2_TURBO_LICENSE", 36ecd94f1bSKan Liang "PublicDescription": "Core cycles where the core was running with power-delivery for license level 2 (introduced in Skylake Server michroarchtecture). This includes high current AVX 512-bit instructions.", 37ecd94f1bSKan Liang "SampleAfterValue": "200003", 38ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3,4,5,6,7" 39ecd94f1bSKan Liang }, 40ecd94f1bSKan Liang { 41ecd94f1bSKan Liang "EventCode": "0x28", 42ecd94f1bSKan Liang "UMask": "0x40", 43ecd94f1bSKan Liang "BriefDescription": "Core cycles the core was throttled due to a pending power level request.", 44ecd94f1bSKan Liang "Counter": "0,1,2,3", 45ecd94f1bSKan Liang "EventName": "CORE_POWER.THROTTLE", 46ecd94f1bSKan Liang "PublicDescription": "Core cycles the out-of-order engine was throttled due to a pending power level request.", 47ecd94f1bSKan Liang "SampleAfterValue": "200003", 48ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3,4,5,6,7" 49ecd94f1bSKan Liang }, 50ecd94f1bSKan Liang { 51ecd94f1bSKan Liang "EventCode": "0x32", 52ecd94f1bSKan Liang "UMask": "0x1", 53ecd94f1bSKan Liang "BriefDescription": "Number of PREFETCHNTA instructions executed.", 54ecd94f1bSKan Liang "Counter": "0,1,2,3", 55ecd94f1bSKan Liang "EventName": "SW_PREFETCH_ACCESS.NTA", 56ecd94f1bSKan Liang "SampleAfterValue": "2000003", 57ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3,4,5,6,7" 58ecd94f1bSKan Liang }, 59ecd94f1bSKan Liang { 60ecd94f1bSKan Liang "EventCode": "0x32", 61ecd94f1bSKan Liang "UMask": "0x2", 62ecd94f1bSKan Liang "BriefDescription": "Number of PREFETCHT0 instructions executed.", 63ecd94f1bSKan Liang "Counter": "0,1,2,3", 64ecd94f1bSKan Liang "EventName": "SW_PREFETCH_ACCESS.T0", 65ecd94f1bSKan Liang "SampleAfterValue": "2000003", 66ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3,4,5,6,7" 67ecd94f1bSKan Liang }, 68ecd94f1bSKan Liang { 69ecd94f1bSKan Liang "EventCode": "0x32", 70ecd94f1bSKan Liang "UMask": "0x4", 71ecd94f1bSKan Liang "BriefDescription": "Number of PREFETCHT1 or PREFETCHT2 instructions executed.", 72ecd94f1bSKan Liang "Counter": "0,1,2,3", 73ecd94f1bSKan Liang "EventName": "SW_PREFETCH_ACCESS.T1_T2", 74ecd94f1bSKan Liang "SampleAfterValue": "2000003", 75ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3,4,5,6,7" 76ecd94f1bSKan Liang }, 77ecd94f1bSKan Liang { 78ecd94f1bSKan Liang "EventCode": "0x32", 79ecd94f1bSKan Liang "UMask": "0x8", 80ecd94f1bSKan Liang "BriefDescription": "Number of PREFETCHW instructions executed.", 81ecd94f1bSKan Liang "Counter": "0,1,2,3", 82ecd94f1bSKan Liang "EventName": "SW_PREFETCH_ACCESS.PREFETCHW", 83ecd94f1bSKan Liang "SampleAfterValue": "2000003", 84ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3,4,5,6,7" 85ecd94f1bSKan Liang }, 86ecd94f1bSKan Liang { 87ecd94f1bSKan Liang "EventCode": "0xCB", 88ecd94f1bSKan Liang "UMask": "0x1", 89ecd94f1bSKan Liang "BriefDescription": "Number of hardware interrupts received by the processor.", 90ecd94f1bSKan Liang "Counter": "0,1,2,3", 91ecd94f1bSKan Liang "EventName": "HW_INTERRUPTS.RECEIVED", 92ecd94f1bSKan Liang "PublicDescription": "Counts the number of hardware interruptions received by the processor.", 93ecd94f1bSKan Liang "SampleAfterValue": "203", 94ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3,4,5,6,7" 95ecd94f1bSKan Liang }, 96ecd94f1bSKan Liang { 97ecd94f1bSKan Liang "EventCode": "0xEF", 98ecd94f1bSKan Liang "UMask": "0x1", 99ecd94f1bSKan Liang "Counter": "0,1,2,3", 100ecd94f1bSKan Liang "EventName": "CORE_SNOOP_RESPONSE.RSP_IHITI", 101ecd94f1bSKan Liang "SampleAfterValue": "2000003", 102ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3,4,5,6,7" 103ecd94f1bSKan Liang }, 104ecd94f1bSKan Liang { 105ecd94f1bSKan Liang "EventCode": "0xEF", 106ecd94f1bSKan Liang "UMask": "0x2", 107ecd94f1bSKan Liang "Counter": "0,1,2,3", 108ecd94f1bSKan Liang "EventName": "CORE_SNOOP_RESPONSE.RSP_IHITFSE", 109ecd94f1bSKan Liang "SampleAfterValue": "2000003", 110ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3,4,5,6,7" 111ecd94f1bSKan Liang }, 112ecd94f1bSKan Liang { 113ecd94f1bSKan Liang "EventCode": "0xEF", 114ecd94f1bSKan Liang "UMask": "0x4", 115ecd94f1bSKan Liang "Counter": "0,1,2,3", 116ecd94f1bSKan Liang "EventName": "CORE_SNOOP_RESPONSE.RSP_SHITFSE", 117ecd94f1bSKan Liang "SampleAfterValue": "2000003", 118ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3,4,5,6,7" 119ecd94f1bSKan Liang }, 120ecd94f1bSKan Liang { 121ecd94f1bSKan Liang "EventCode": "0xEF", 122ecd94f1bSKan Liang "UMask": "0x8", 123ecd94f1bSKan Liang "Counter": "0,1,2,3", 124ecd94f1bSKan Liang "EventName": "CORE_SNOOP_RESPONSE.RSP_SFWDM", 125ecd94f1bSKan Liang "SampleAfterValue": "2000003", 126ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3,4,5,6,7" 127ecd94f1bSKan Liang }, 128ecd94f1bSKan Liang { 129ecd94f1bSKan Liang "EventCode": "0xEF", 130ecd94f1bSKan Liang "UMask": "0x10", 131ecd94f1bSKan Liang "Counter": "0,1,2,3", 132ecd94f1bSKan Liang "EventName": "CORE_SNOOP_RESPONSE.RSP_IFWDM", 133ecd94f1bSKan Liang "SampleAfterValue": "2000003", 134ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3,4,5,6,7" 135ecd94f1bSKan Liang }, 136ecd94f1bSKan Liang { 137ecd94f1bSKan Liang "EventCode": "0xEF", 138ecd94f1bSKan Liang "UMask": "0x20", 139ecd94f1bSKan Liang "Counter": "0,1,2,3", 140ecd94f1bSKan Liang "EventName": "CORE_SNOOP_RESPONSE.RSP_IFWDFE", 141ecd94f1bSKan Liang "SampleAfterValue": "2000003", 142ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3,4,5,6,7" 143ecd94f1bSKan Liang }, 144ecd94f1bSKan Liang { 145ecd94f1bSKan Liang "EventCode": "0xEF", 146ecd94f1bSKan Liang "UMask": "0x40", 147ecd94f1bSKan Liang "Counter": "0,1,2,3", 148ecd94f1bSKan Liang "EventName": "CORE_SNOOP_RESPONSE.RSP_SFWDFE", 149ecd94f1bSKan Liang "SampleAfterValue": "2000003", 150ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3,4,5,6,7" 151ecd94f1bSKan Liang }, 152ecd94f1bSKan Liang { 153ecd94f1bSKan Liang "EventCode": "0xFE", 154ecd94f1bSKan Liang "UMask": "0x2", 155ecd94f1bSKan Liang "BriefDescription": "Counts number of cache lines that are allocated and written back to L3 with the intention that they are more likely to be reused shortly", 156ecd94f1bSKan Liang "Counter": "0,1,2,3", 157ecd94f1bSKan Liang "EventName": "IDI_MISC.WB_UPGRADE", 158ecd94f1bSKan Liang "PublicDescription": "Counts number of cache lines that are allocated and written back to L3 with the intention that they are more likely to be reused shortly.", 159ecd94f1bSKan Liang "SampleAfterValue": "100003", 160ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3,4,5,6,7" 161ecd94f1bSKan Liang }, 162ecd94f1bSKan Liang { 163ecd94f1bSKan Liang "EventCode": "0xFE", 164ecd94f1bSKan Liang "UMask": "0x4", 165ecd94f1bSKan Liang "BriefDescription": "Counts number of cache lines that are dropped and not written back to L3 as they are deemed to be less likely to be reused shortly", 166ecd94f1bSKan Liang "Counter": "0,1,2,3", 167ecd94f1bSKan Liang "EventName": "IDI_MISC.WB_DOWNGRADE", 168ecd94f1bSKan Liang "PublicDescription": "Counts number of cache lines that are dropped and not written back to L3 as they are deemed to be less likely to be reused shortly.", 169ecd94f1bSKan Liang "SampleAfterValue": "100003", 170ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3,4,5,6,7" 171ecd94f1bSKan Liang }, 172ecd94f1bSKan Liang { 173ecd94f1bSKan Liang "Offcore": "1", 174ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 175ecd94f1bSKan Liang "UMask": "0x1", 176ecd94f1bSKan Liang "BriefDescription": "Counts demand data reads", 177ecd94f1bSKan Liang "MSRValue": "0x0080020001", 178ecd94f1bSKan Liang "Counter": "0,1,2,3", 179ecd94f1bSKan Liang "EventName": "OCR.DEMAND_DATA_RD.SUPPLIER_NONE.SNOOP_NONE", 180ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 181ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 182ecd94f1bSKan Liang "SampleAfterValue": "100003", 183ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 184ecd94f1bSKan Liang }, 185ecd94f1bSKan Liang { 186ecd94f1bSKan Liang "Offcore": "1", 187ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 188ecd94f1bSKan Liang "UMask": "0x1", 189ecd94f1bSKan Liang "BriefDescription": "Counts demand data reads TBD", 190ecd94f1bSKan Liang "MSRValue": "0x0100020001", 191ecd94f1bSKan Liang "Counter": "0,1,2,3", 192ecd94f1bSKan Liang "EventName": "OCR.DEMAND_DATA_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED", 193ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 194ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 195ecd94f1bSKan Liang "SampleAfterValue": "100003", 196ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 197ecd94f1bSKan Liang }, 198ecd94f1bSKan Liang { 199ecd94f1bSKan Liang "Offcore": "1", 200ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 201ecd94f1bSKan Liang "UMask": "0x1", 202ecd94f1bSKan Liang "BriefDescription": "Counts demand data reads", 203ecd94f1bSKan Liang "MSRValue": "0x0200020001", 204ecd94f1bSKan Liang "Counter": "0,1,2,3", 205ecd94f1bSKan Liang "EventName": "OCR.DEMAND_DATA_RD.SUPPLIER_NONE.SNOOP_MISS", 206ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 207ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 208ecd94f1bSKan Liang "SampleAfterValue": "100003", 209ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 210ecd94f1bSKan Liang }, 211ecd94f1bSKan Liang { 212ecd94f1bSKan Liang "Offcore": "1", 213ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 214ecd94f1bSKan Liang "UMask": "0x1", 215ecd94f1bSKan Liang "BriefDescription": "Counts demand data reads TBD", 216ecd94f1bSKan Liang "MSRValue": "0x0400020001", 217ecd94f1bSKan Liang "Counter": "0,1,2,3", 218ecd94f1bSKan Liang "EventName": "OCR.DEMAND_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", 219ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 220ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 221ecd94f1bSKan Liang "SampleAfterValue": "100003", 222ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 223ecd94f1bSKan Liang }, 224ecd94f1bSKan Liang { 225ecd94f1bSKan Liang "Offcore": "1", 226ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 227ecd94f1bSKan Liang "UMask": "0x1", 228ecd94f1bSKan Liang "BriefDescription": "Counts demand data reads TBD", 229ecd94f1bSKan Liang "MSRValue": "0x0800020001", 230ecd94f1bSKan Liang "Counter": "0,1,2,3", 231ecd94f1bSKan Liang "EventName": "OCR.DEMAND_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", 232ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 233ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 234ecd94f1bSKan Liang "SampleAfterValue": "100003", 235ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 236ecd94f1bSKan Liang }, 237ecd94f1bSKan Liang { 238ecd94f1bSKan Liang "Offcore": "1", 239ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 240ecd94f1bSKan Liang "UMask": "0x1", 241ecd94f1bSKan Liang "BriefDescription": "Counts demand data reads TBD", 242ecd94f1bSKan Liang "MSRValue": "0x1000020001", 243ecd94f1bSKan Liang "Counter": "0,1,2,3", 244ecd94f1bSKan Liang "EventName": "OCR.DEMAND_DATA_RD.SUPPLIER_NONE.HITM_OTHER_CORE", 245ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 246ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 247ecd94f1bSKan Liang "SampleAfterValue": "100003", 248ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 249ecd94f1bSKan Liang }, 250ecd94f1bSKan Liang { 251ecd94f1bSKan Liang "Offcore": "1", 252ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 253ecd94f1bSKan Liang "UMask": "0x1", 254ecd94f1bSKan Liang "BriefDescription": "Counts demand data reads TBD", 255ecd94f1bSKan Liang "MSRValue": "0x3F80020001", 256ecd94f1bSKan Liang "Counter": "0,1,2,3", 257ecd94f1bSKan Liang "EventName": "OCR.DEMAND_DATA_RD.SUPPLIER_NONE.ANY_SNOOP", 258ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 259ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 260ecd94f1bSKan Liang "SampleAfterValue": "100003", 261ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 262ecd94f1bSKan Liang }, 263ecd94f1bSKan Liang { 264ecd94f1bSKan Liang "Offcore": "1", 265ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 266ecd94f1bSKan Liang "UMask": "0x1", 267ecd94f1bSKan Liang "BriefDescription": "Counts demand data reads", 268ecd94f1bSKan Liang "MSRValue": "0x0080040001", 269ecd94f1bSKan Liang "Counter": "0,1,2,3", 270ecd94f1bSKan Liang "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_M.SNOOP_NONE", 271ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 272ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 273ecd94f1bSKan Liang "SampleAfterValue": "100003", 274ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 275ecd94f1bSKan Liang }, 276ecd94f1bSKan Liang { 277ecd94f1bSKan Liang "Offcore": "1", 278ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 279ecd94f1bSKan Liang "UMask": "0x1", 280ecd94f1bSKan Liang "BriefDescription": "Counts demand data reads TBD", 281ecd94f1bSKan Liang "MSRValue": "0x0100040001", 282ecd94f1bSKan Liang "Counter": "0,1,2,3", 283ecd94f1bSKan Liang "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDED", 284ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 285ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 286ecd94f1bSKan Liang "SampleAfterValue": "100003", 287ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 288ecd94f1bSKan Liang }, 289ecd94f1bSKan Liang { 290ecd94f1bSKan Liang "Offcore": "1", 291ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 292ecd94f1bSKan Liang "UMask": "0x1", 293ecd94f1bSKan Liang "BriefDescription": "Counts demand data reads", 294ecd94f1bSKan Liang "MSRValue": "0x0200040001", 295ecd94f1bSKan Liang "Counter": "0,1,2,3", 296ecd94f1bSKan Liang "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_M.SNOOP_MISS", 297ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 298ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 299ecd94f1bSKan Liang "SampleAfterValue": "100003", 300ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 301ecd94f1bSKan Liang }, 302ecd94f1bSKan Liang { 303ecd94f1bSKan Liang "Offcore": "1", 304ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 305ecd94f1bSKan Liang "UMask": "0x1", 306ecd94f1bSKan Liang "BriefDescription": "Counts demand data reads TBD", 307ecd94f1bSKan Liang "MSRValue": "0x0400040001", 308ecd94f1bSKan Liang "Counter": "0,1,2,3", 309ecd94f1bSKan Liang "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", 310ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 311ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 312ecd94f1bSKan Liang "SampleAfterValue": "100003", 313ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 314ecd94f1bSKan Liang }, 315ecd94f1bSKan Liang { 316ecd94f1bSKan Liang "Offcore": "1", 317ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 318ecd94f1bSKan Liang "UMask": "0x1", 319ecd94f1bSKan Liang "BriefDescription": "Counts demand data reads TBD", 320ecd94f1bSKan Liang "MSRValue": "0x0800040001", 321ecd94f1bSKan Liang "Counter": "0,1,2,3", 322ecd94f1bSKan Liang "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWD", 323ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 324ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 325ecd94f1bSKan Liang "SampleAfterValue": "100003", 326ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 327ecd94f1bSKan Liang }, 328ecd94f1bSKan Liang { 329ecd94f1bSKan Liang "Offcore": "1", 330ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 331ecd94f1bSKan Liang "UMask": "0x1", 332ecd94f1bSKan Liang "BriefDescription": "Counts demand data reads TBD", 333ecd94f1bSKan Liang "MSRValue": "0x1000040001", 334ecd94f1bSKan Liang "Counter": "0,1,2,3", 335ecd94f1bSKan Liang "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_M.HITM_OTHER_CORE", 336ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 337ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 338ecd94f1bSKan Liang "SampleAfterValue": "100003", 339ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 340ecd94f1bSKan Liang }, 341ecd94f1bSKan Liang { 342ecd94f1bSKan Liang "Offcore": "1", 343ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 344ecd94f1bSKan Liang "UMask": "0x1", 345ecd94f1bSKan Liang "BriefDescription": "Counts demand data reads TBD", 346ecd94f1bSKan Liang "MSRValue": "0x3F80040001", 347ecd94f1bSKan Liang "Counter": "0,1,2,3", 348ecd94f1bSKan Liang "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_M.ANY_SNOOP", 349ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 350ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 351ecd94f1bSKan Liang "SampleAfterValue": "100003", 352ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 353ecd94f1bSKan Liang }, 354ecd94f1bSKan Liang { 355ecd94f1bSKan Liang "Offcore": "1", 356ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 357ecd94f1bSKan Liang "UMask": "0x1", 358ecd94f1bSKan Liang "BriefDescription": "Counts demand data reads", 359ecd94f1bSKan Liang "MSRValue": "0x0080080001", 360ecd94f1bSKan Liang "Counter": "0,1,2,3", 361ecd94f1bSKan Liang "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_E.SNOOP_NONE", 362ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 363ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 364ecd94f1bSKan Liang "SampleAfterValue": "100003", 365ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 366ecd94f1bSKan Liang }, 367ecd94f1bSKan Liang { 368ecd94f1bSKan Liang "Offcore": "1", 369ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 370ecd94f1bSKan Liang "UMask": "0x1", 371ecd94f1bSKan Liang "BriefDescription": "Counts demand data reads TBD", 372ecd94f1bSKan Liang "MSRValue": "0x0100080001", 373ecd94f1bSKan Liang "Counter": "0,1,2,3", 374ecd94f1bSKan Liang "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDED", 375ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 376ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 377ecd94f1bSKan Liang "SampleAfterValue": "100003", 378ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 379ecd94f1bSKan Liang }, 380ecd94f1bSKan Liang { 381ecd94f1bSKan Liang "Offcore": "1", 382ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 383ecd94f1bSKan Liang "UMask": "0x1", 384ecd94f1bSKan Liang "BriefDescription": "Counts demand data reads", 385ecd94f1bSKan Liang "MSRValue": "0x0200080001", 386ecd94f1bSKan Liang "Counter": "0,1,2,3", 387ecd94f1bSKan Liang "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_E.SNOOP_MISS", 388ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 389ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 390ecd94f1bSKan Liang "SampleAfterValue": "100003", 391ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 392ecd94f1bSKan Liang }, 393ecd94f1bSKan Liang { 394ecd94f1bSKan Liang "Offcore": "1", 395ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 396ecd94f1bSKan Liang "UMask": "0x1", 397ecd94f1bSKan Liang "BriefDescription": "Counts demand data reads TBD", 398ecd94f1bSKan Liang "MSRValue": "0x0400080001", 399ecd94f1bSKan Liang "Counter": "0,1,2,3", 400ecd94f1bSKan Liang "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", 401ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 402ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 403ecd94f1bSKan Liang "SampleAfterValue": "100003", 404ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 405ecd94f1bSKan Liang }, 406ecd94f1bSKan Liang { 407ecd94f1bSKan Liang "Offcore": "1", 408ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 409ecd94f1bSKan Liang "UMask": "0x1", 410ecd94f1bSKan Liang "BriefDescription": "Counts demand data reads TBD", 411ecd94f1bSKan Liang "MSRValue": "0x0800080001", 412ecd94f1bSKan Liang "Counter": "0,1,2,3", 413ecd94f1bSKan Liang "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWD", 414ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 415ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 416ecd94f1bSKan Liang "SampleAfterValue": "100003", 417ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 418ecd94f1bSKan Liang }, 419ecd94f1bSKan Liang { 420ecd94f1bSKan Liang "Offcore": "1", 421ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 422ecd94f1bSKan Liang "UMask": "0x1", 423ecd94f1bSKan Liang "BriefDescription": "Counts demand data reads TBD", 424ecd94f1bSKan Liang "MSRValue": "0x1000080001", 425ecd94f1bSKan Liang "Counter": "0,1,2,3", 426ecd94f1bSKan Liang "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_E.HITM_OTHER_CORE", 427ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 428ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 429ecd94f1bSKan Liang "SampleAfterValue": "100003", 430ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 431ecd94f1bSKan Liang }, 432ecd94f1bSKan Liang { 433ecd94f1bSKan Liang "Offcore": "1", 434ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 435ecd94f1bSKan Liang "UMask": "0x1", 436ecd94f1bSKan Liang "BriefDescription": "Counts demand data reads TBD", 437ecd94f1bSKan Liang "MSRValue": "0x3F80080001", 438ecd94f1bSKan Liang "Counter": "0,1,2,3", 439ecd94f1bSKan Liang "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_E.ANY_SNOOP", 440ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 441ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 442ecd94f1bSKan Liang "SampleAfterValue": "100003", 443ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 444ecd94f1bSKan Liang }, 445ecd94f1bSKan Liang { 446ecd94f1bSKan Liang "Offcore": "1", 447ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 448ecd94f1bSKan Liang "UMask": "0x1", 449ecd94f1bSKan Liang "BriefDescription": "Counts demand data reads", 450ecd94f1bSKan Liang "MSRValue": "0x0080100001", 451ecd94f1bSKan Liang "Counter": "0,1,2,3", 452ecd94f1bSKan Liang "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_S.SNOOP_NONE", 453ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 454ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 455ecd94f1bSKan Liang "SampleAfterValue": "100003", 456ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 457ecd94f1bSKan Liang }, 458ecd94f1bSKan Liang { 459ecd94f1bSKan Liang "Offcore": "1", 460ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 461ecd94f1bSKan Liang "UMask": "0x1", 462ecd94f1bSKan Liang "BriefDescription": "Counts demand data reads TBD", 463ecd94f1bSKan Liang "MSRValue": "0x0100100001", 464ecd94f1bSKan Liang "Counter": "0,1,2,3", 465ecd94f1bSKan Liang "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDED", 466ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 467ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 468ecd94f1bSKan Liang "SampleAfterValue": "100003", 469ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 470ecd94f1bSKan Liang }, 471ecd94f1bSKan Liang { 472ecd94f1bSKan Liang "Offcore": "1", 473ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 474ecd94f1bSKan Liang "UMask": "0x1", 475ecd94f1bSKan Liang "BriefDescription": "Counts demand data reads", 476ecd94f1bSKan Liang "MSRValue": "0x0200100001", 477ecd94f1bSKan Liang "Counter": "0,1,2,3", 478ecd94f1bSKan Liang "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_S.SNOOP_MISS", 479ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 480ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 481ecd94f1bSKan Liang "SampleAfterValue": "100003", 482ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 483ecd94f1bSKan Liang }, 484ecd94f1bSKan Liang { 485ecd94f1bSKan Liang "Offcore": "1", 486ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 487ecd94f1bSKan Liang "UMask": "0x1", 488ecd94f1bSKan Liang "BriefDescription": "Counts demand data reads TBD", 489ecd94f1bSKan Liang "MSRValue": "0x0400100001", 490ecd94f1bSKan Liang "Counter": "0,1,2,3", 491ecd94f1bSKan Liang "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", 492ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 493ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 494ecd94f1bSKan Liang "SampleAfterValue": "100003", 495ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 496ecd94f1bSKan Liang }, 497ecd94f1bSKan Liang { 498ecd94f1bSKan Liang "Offcore": "1", 499ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 500ecd94f1bSKan Liang "UMask": "0x1", 501ecd94f1bSKan Liang "BriefDescription": "Counts demand data reads TBD", 502ecd94f1bSKan Liang "MSRValue": "0x0800100001", 503ecd94f1bSKan Liang "Counter": "0,1,2,3", 504ecd94f1bSKan Liang "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWD", 505ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 506ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 507ecd94f1bSKan Liang "SampleAfterValue": "100003", 508ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 509ecd94f1bSKan Liang }, 510ecd94f1bSKan Liang { 511ecd94f1bSKan Liang "Offcore": "1", 512ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 513ecd94f1bSKan Liang "UMask": "0x1", 514ecd94f1bSKan Liang "BriefDescription": "Counts demand data reads TBD", 515ecd94f1bSKan Liang "MSRValue": "0x1000100001", 516ecd94f1bSKan Liang "Counter": "0,1,2,3", 517ecd94f1bSKan Liang "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_S.HITM_OTHER_CORE", 518ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 519ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 520ecd94f1bSKan Liang "SampleAfterValue": "100003", 521ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 522ecd94f1bSKan Liang }, 523ecd94f1bSKan Liang { 524ecd94f1bSKan Liang "Offcore": "1", 525ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 526ecd94f1bSKan Liang "UMask": "0x1", 527ecd94f1bSKan Liang "BriefDescription": "Counts demand data reads TBD", 528ecd94f1bSKan Liang "MSRValue": "0x3F80100001", 529ecd94f1bSKan Liang "Counter": "0,1,2,3", 530ecd94f1bSKan Liang "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_S.ANY_SNOOP", 531ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 532ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 533ecd94f1bSKan Liang "SampleAfterValue": "100003", 534ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 535ecd94f1bSKan Liang }, 536ecd94f1bSKan Liang { 537ecd94f1bSKan Liang "Offcore": "1", 538ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 539ecd94f1bSKan Liang "UMask": "0x1", 540ecd94f1bSKan Liang "BriefDescription": "Counts demand data reads", 541ecd94f1bSKan Liang "MSRValue": "0x0080200001", 542ecd94f1bSKan Liang "Counter": "0,1,2,3", 543ecd94f1bSKan Liang "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_F.SNOOP_NONE", 544ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 545ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 546ecd94f1bSKan Liang "SampleAfterValue": "100003", 547ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 548ecd94f1bSKan Liang }, 549ecd94f1bSKan Liang { 550ecd94f1bSKan Liang "Offcore": "1", 551ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 552ecd94f1bSKan Liang "UMask": "0x1", 553ecd94f1bSKan Liang "BriefDescription": "Counts demand data reads TBD", 554ecd94f1bSKan Liang "MSRValue": "0x0100200001", 555ecd94f1bSKan Liang "Counter": "0,1,2,3", 556ecd94f1bSKan Liang "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDED", 557ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 558ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 559ecd94f1bSKan Liang "SampleAfterValue": "100003", 560ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 561ecd94f1bSKan Liang }, 562ecd94f1bSKan Liang { 563ecd94f1bSKan Liang "Offcore": "1", 564ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 565ecd94f1bSKan Liang "UMask": "0x1", 566ecd94f1bSKan Liang "BriefDescription": "Counts demand data reads", 567ecd94f1bSKan Liang "MSRValue": "0x0200200001", 568ecd94f1bSKan Liang "Counter": "0,1,2,3", 569ecd94f1bSKan Liang "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_F.SNOOP_MISS", 570ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 571ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 572ecd94f1bSKan Liang "SampleAfterValue": "100003", 573ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 574ecd94f1bSKan Liang }, 575ecd94f1bSKan Liang { 576ecd94f1bSKan Liang "Offcore": "1", 577ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 578ecd94f1bSKan Liang "UMask": "0x1", 579ecd94f1bSKan Liang "BriefDescription": "Counts demand data reads TBD", 580ecd94f1bSKan Liang "MSRValue": "0x0400200001", 581ecd94f1bSKan Liang "Counter": "0,1,2,3", 582ecd94f1bSKan Liang "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", 583ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 584ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 585ecd94f1bSKan Liang "SampleAfterValue": "100003", 586ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 587ecd94f1bSKan Liang }, 588ecd94f1bSKan Liang { 589ecd94f1bSKan Liang "Offcore": "1", 590ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 591ecd94f1bSKan Liang "UMask": "0x1", 592ecd94f1bSKan Liang "BriefDescription": "Counts demand data reads TBD", 593ecd94f1bSKan Liang "MSRValue": "0x0800200001", 594ecd94f1bSKan Liang "Counter": "0,1,2,3", 595ecd94f1bSKan Liang "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWD", 596ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 597ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 598ecd94f1bSKan Liang "SampleAfterValue": "100003", 599ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 600ecd94f1bSKan Liang }, 601ecd94f1bSKan Liang { 602ecd94f1bSKan Liang "Offcore": "1", 603ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 604ecd94f1bSKan Liang "UMask": "0x1", 605ecd94f1bSKan Liang "BriefDescription": "Counts demand data reads TBD", 606ecd94f1bSKan Liang "MSRValue": "0x1000200001", 607ecd94f1bSKan Liang "Counter": "0,1,2,3", 608ecd94f1bSKan Liang "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_F.HITM_OTHER_CORE", 609ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 610ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 611ecd94f1bSKan Liang "SampleAfterValue": "100003", 612ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 613ecd94f1bSKan Liang }, 614ecd94f1bSKan Liang { 615ecd94f1bSKan Liang "Offcore": "1", 616ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 617ecd94f1bSKan Liang "UMask": "0x1", 618ecd94f1bSKan Liang "BriefDescription": "Counts demand data reads TBD", 619ecd94f1bSKan Liang "MSRValue": "0x3F80200001", 620ecd94f1bSKan Liang "Counter": "0,1,2,3", 621ecd94f1bSKan Liang "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_F.ANY_SNOOP", 622ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 623ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 624ecd94f1bSKan Liang "SampleAfterValue": "100003", 625ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 626ecd94f1bSKan Liang }, 627ecd94f1bSKan Liang { 628ecd94f1bSKan Liang "Offcore": "1", 629ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 630ecd94f1bSKan Liang "UMask": "0x1", 631ecd94f1bSKan Liang "BriefDescription": "Counts demand data reads TBD", 632ecd94f1bSKan Liang "MSRValue": "0x00803C0001", 633ecd94f1bSKan Liang "Counter": "0,1,2,3", 634ecd94f1bSKan Liang "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_NONE", 635ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 636ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 637ecd94f1bSKan Liang "SampleAfterValue": "100003", 638ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 639ecd94f1bSKan Liang }, 640ecd94f1bSKan Liang { 641ecd94f1bSKan Liang "Offcore": "1", 642ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 643ecd94f1bSKan Liang "UMask": "0x1", 644ecd94f1bSKan Liang "BriefDescription": "Counts demand data reads TBD TBD", 645ecd94f1bSKan Liang "MSRValue": "0x01003C0001", 646ecd94f1bSKan Liang "Counter": "0,1,2,3", 647ecd94f1bSKan Liang "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.NO_SNOOP_NEEDED", 648ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 649ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 650ecd94f1bSKan Liang "SampleAfterValue": "100003", 651ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 652ecd94f1bSKan Liang }, 653ecd94f1bSKan Liang { 654ecd94f1bSKan Liang "Offcore": "1", 655ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 656ecd94f1bSKan Liang "UMask": "0x1", 657ecd94f1bSKan Liang "BriefDescription": "Counts demand data reads TBD", 658ecd94f1bSKan Liang "MSRValue": "0x02003C0001", 659ecd94f1bSKan Liang "Counter": "0,1,2,3", 660ecd94f1bSKan Liang "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_MISS", 661ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 662ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 663ecd94f1bSKan Liang "SampleAfterValue": "100003", 664ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 665ecd94f1bSKan Liang }, 666ecd94f1bSKan Liang { 667ecd94f1bSKan Liang "Offcore": "1", 668ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 669ecd94f1bSKan Liang "UMask": "0x1", 670ecd94f1bSKan Liang "BriefDescription": "Counts demand data reads TBD TBD", 671ecd94f1bSKan Liang "MSRValue": "0x04003C0001", 672ecd94f1bSKan Liang "Counter": "0,1,2,3", 673ecd94f1bSKan Liang "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD", 674ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 675ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 676ecd94f1bSKan Liang "SampleAfterValue": "100003", 677ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 678ecd94f1bSKan Liang }, 679ecd94f1bSKan Liang { 680ecd94f1bSKan Liang "Offcore": "1", 681ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 682ecd94f1bSKan Liang "UMask": "0x1", 683ecd94f1bSKan Liang "BriefDescription": "Counts demand data reads TBD TBD", 684ecd94f1bSKan Liang "MSRValue": "0x08003C0001", 685ecd94f1bSKan Liang "Counter": "0,1,2,3", 686ecd94f1bSKan Liang "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD", 687ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 688ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 689ecd94f1bSKan Liang "SampleAfterValue": "100003", 690ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 691ecd94f1bSKan Liang }, 692ecd94f1bSKan Liang { 693ecd94f1bSKan Liang "Offcore": "1", 694ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 695ecd94f1bSKan Liang "UMask": "0x1", 696ecd94f1bSKan Liang "BriefDescription": "Counts demand data reads TBD TBD", 697ecd94f1bSKan Liang "MSRValue": "0x10003C0001", 698ecd94f1bSKan Liang "Counter": "0,1,2,3", 699ecd94f1bSKan Liang "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.HITM_OTHER_CORE", 700ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 701ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 702ecd94f1bSKan Liang "SampleAfterValue": "100003", 703ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 704ecd94f1bSKan Liang }, 705ecd94f1bSKan Liang { 706ecd94f1bSKan Liang "Offcore": "1", 707ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 708ecd94f1bSKan Liang "UMask": "0x1", 709ecd94f1bSKan Liang "BriefDescription": "Counts demand data reads TBD TBD", 710ecd94f1bSKan Liang "MSRValue": "0x3F803C0001", 711ecd94f1bSKan Liang "Counter": "0,1,2,3", 712ecd94f1bSKan Liang "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.ANY_SNOOP", 713ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 714ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 715ecd94f1bSKan Liang "SampleAfterValue": "100003", 716ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 717ecd94f1bSKan Liang }, 718ecd94f1bSKan Liang { 719ecd94f1bSKan Liang "Offcore": "1", 720ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 721ecd94f1bSKan Liang "UMask": "0x1", 722ecd94f1bSKan Liang "BriefDescription": "Counts all demand data writes (RFOs)", 723ecd94f1bSKan Liang "MSRValue": "0x0080020002", 724ecd94f1bSKan Liang "Counter": "0,1,2,3", 725ecd94f1bSKan Liang "EventName": "OCR.DEMAND_RFO.SUPPLIER_NONE.SNOOP_NONE", 726ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 727ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 728ecd94f1bSKan Liang "SampleAfterValue": "100003", 729ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 730ecd94f1bSKan Liang }, 731ecd94f1bSKan Liang { 732ecd94f1bSKan Liang "Offcore": "1", 733ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 734ecd94f1bSKan Liang "UMask": "0x1", 735ecd94f1bSKan Liang "BriefDescription": "Counts all demand data writes (RFOs) TBD", 736ecd94f1bSKan Liang "MSRValue": "0x0100020002", 737ecd94f1bSKan Liang "Counter": "0,1,2,3", 738ecd94f1bSKan Liang "EventName": "OCR.DEMAND_RFO.SUPPLIER_NONE.NO_SNOOP_NEEDED", 739ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 740ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 741ecd94f1bSKan Liang "SampleAfterValue": "100003", 742ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 743ecd94f1bSKan Liang }, 744ecd94f1bSKan Liang { 745ecd94f1bSKan Liang "Offcore": "1", 746ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 747ecd94f1bSKan Liang "UMask": "0x1", 748ecd94f1bSKan Liang "BriefDescription": "Counts all demand data writes (RFOs)", 749ecd94f1bSKan Liang "MSRValue": "0x0200020002", 750ecd94f1bSKan Liang "Counter": "0,1,2,3", 751ecd94f1bSKan Liang "EventName": "OCR.DEMAND_RFO.SUPPLIER_NONE.SNOOP_MISS", 752ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 753ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 754ecd94f1bSKan Liang "SampleAfterValue": "100003", 755ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 756ecd94f1bSKan Liang }, 757ecd94f1bSKan Liang { 758ecd94f1bSKan Liang "Offcore": "1", 759ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 760ecd94f1bSKan Liang "UMask": "0x1", 761ecd94f1bSKan Liang "BriefDescription": "Counts all demand data writes (RFOs) TBD", 762ecd94f1bSKan Liang "MSRValue": "0x0400020002", 763ecd94f1bSKan Liang "Counter": "0,1,2,3", 764ecd94f1bSKan Liang "EventName": "OCR.DEMAND_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", 765ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 766ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 767ecd94f1bSKan Liang "SampleAfterValue": "100003", 768ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 769ecd94f1bSKan Liang }, 770ecd94f1bSKan Liang { 771ecd94f1bSKan Liang "Offcore": "1", 772ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 773ecd94f1bSKan Liang "UMask": "0x1", 774ecd94f1bSKan Liang "BriefDescription": "Counts all demand data writes (RFOs) TBD", 775ecd94f1bSKan Liang "MSRValue": "0x0800020002", 776ecd94f1bSKan Liang "Counter": "0,1,2,3", 777ecd94f1bSKan Liang "EventName": "OCR.DEMAND_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", 778ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 779ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 780ecd94f1bSKan Liang "SampleAfterValue": "100003", 781ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 782ecd94f1bSKan Liang }, 783ecd94f1bSKan Liang { 784ecd94f1bSKan Liang "Offcore": "1", 785ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 786ecd94f1bSKan Liang "UMask": "0x1", 787ecd94f1bSKan Liang "BriefDescription": "Counts all demand data writes (RFOs) TBD", 788ecd94f1bSKan Liang "MSRValue": "0x1000020002", 789ecd94f1bSKan Liang "Counter": "0,1,2,3", 790ecd94f1bSKan Liang "EventName": "OCR.DEMAND_RFO.SUPPLIER_NONE.HITM_OTHER_CORE", 791ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 792ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 793ecd94f1bSKan Liang "SampleAfterValue": "100003", 794ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 795ecd94f1bSKan Liang }, 796ecd94f1bSKan Liang { 797ecd94f1bSKan Liang "Offcore": "1", 798ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 799ecd94f1bSKan Liang "UMask": "0x1", 800ecd94f1bSKan Liang "BriefDescription": "Counts all demand data writes (RFOs) TBD", 801ecd94f1bSKan Liang "MSRValue": "0x3F80020002", 802ecd94f1bSKan Liang "Counter": "0,1,2,3", 803ecd94f1bSKan Liang "EventName": "OCR.DEMAND_RFO.SUPPLIER_NONE.ANY_SNOOP", 804ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 805ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 806ecd94f1bSKan Liang "SampleAfterValue": "100003", 807ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 808ecd94f1bSKan Liang }, 809ecd94f1bSKan Liang { 810ecd94f1bSKan Liang "Offcore": "1", 811ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 812ecd94f1bSKan Liang "UMask": "0x1", 813ecd94f1bSKan Liang "BriefDescription": "Counts all demand data writes (RFOs)", 814ecd94f1bSKan Liang "MSRValue": "0x0080040002", 815ecd94f1bSKan Liang "Counter": "0,1,2,3", 816ecd94f1bSKan Liang "EventName": "OCR.DEMAND_RFO.L3_HIT_M.SNOOP_NONE", 817ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 818ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 819ecd94f1bSKan Liang "SampleAfterValue": "100003", 820ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 821ecd94f1bSKan Liang }, 822ecd94f1bSKan Liang { 823ecd94f1bSKan Liang "Offcore": "1", 824ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 825ecd94f1bSKan Liang "UMask": "0x1", 826ecd94f1bSKan Liang "BriefDescription": "Counts all demand data writes (RFOs) TBD", 827ecd94f1bSKan Liang "MSRValue": "0x0100040002", 828ecd94f1bSKan Liang "Counter": "0,1,2,3", 829ecd94f1bSKan Liang "EventName": "OCR.DEMAND_RFO.L3_HIT_M.NO_SNOOP_NEEDED", 830ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 831ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 832ecd94f1bSKan Liang "SampleAfterValue": "100003", 833ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 834ecd94f1bSKan Liang }, 835ecd94f1bSKan Liang { 836ecd94f1bSKan Liang "Offcore": "1", 837ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 838ecd94f1bSKan Liang "UMask": "0x1", 839ecd94f1bSKan Liang "BriefDescription": "Counts all demand data writes (RFOs)", 840ecd94f1bSKan Liang "MSRValue": "0x0200040002", 841ecd94f1bSKan Liang "Counter": "0,1,2,3", 842ecd94f1bSKan Liang "EventName": "OCR.DEMAND_RFO.L3_HIT_M.SNOOP_MISS", 843ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 844ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 845ecd94f1bSKan Liang "SampleAfterValue": "100003", 846ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 847ecd94f1bSKan Liang }, 848ecd94f1bSKan Liang { 849ecd94f1bSKan Liang "Offcore": "1", 850ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 851ecd94f1bSKan Liang "UMask": "0x1", 852ecd94f1bSKan Liang "BriefDescription": "Counts all demand data writes (RFOs) TBD", 853ecd94f1bSKan Liang "MSRValue": "0x0400040002", 854ecd94f1bSKan Liang "Counter": "0,1,2,3", 855ecd94f1bSKan Liang "EventName": "OCR.DEMAND_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", 856ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 857ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 858ecd94f1bSKan Liang "SampleAfterValue": "100003", 859ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 860ecd94f1bSKan Liang }, 861ecd94f1bSKan Liang { 862ecd94f1bSKan Liang "Offcore": "1", 863ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 864ecd94f1bSKan Liang "UMask": "0x1", 865ecd94f1bSKan Liang "BriefDescription": "Counts all demand data writes (RFOs) TBD", 866ecd94f1bSKan Liang "MSRValue": "0x0800040002", 867ecd94f1bSKan Liang "Counter": "0,1,2,3", 868ecd94f1bSKan Liang "EventName": "OCR.DEMAND_RFO.L3_HIT_M.HIT_OTHER_CORE_FWD", 869ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 870ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 871ecd94f1bSKan Liang "SampleAfterValue": "100003", 872ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 873ecd94f1bSKan Liang }, 874ecd94f1bSKan Liang { 875ecd94f1bSKan Liang "Offcore": "1", 876ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 877ecd94f1bSKan Liang "UMask": "0x1", 878ecd94f1bSKan Liang "BriefDescription": "Counts all demand data writes (RFOs) TBD", 879ecd94f1bSKan Liang "MSRValue": "0x1000040002", 880ecd94f1bSKan Liang "Counter": "0,1,2,3", 881ecd94f1bSKan Liang "EventName": "OCR.DEMAND_RFO.L3_HIT_M.HITM_OTHER_CORE", 882ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 883ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 884ecd94f1bSKan Liang "SampleAfterValue": "100003", 885ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 886ecd94f1bSKan Liang }, 887ecd94f1bSKan Liang { 888ecd94f1bSKan Liang "Offcore": "1", 889ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 890ecd94f1bSKan Liang "UMask": "0x1", 891ecd94f1bSKan Liang "BriefDescription": "Counts all demand data writes (RFOs) TBD", 892ecd94f1bSKan Liang "MSRValue": "0x3F80040002", 893ecd94f1bSKan Liang "Counter": "0,1,2,3", 894ecd94f1bSKan Liang "EventName": "OCR.DEMAND_RFO.L3_HIT_M.ANY_SNOOP", 895ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 896ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 897ecd94f1bSKan Liang "SampleAfterValue": "100003", 898ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 899ecd94f1bSKan Liang }, 900ecd94f1bSKan Liang { 901ecd94f1bSKan Liang "Offcore": "1", 902ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 903ecd94f1bSKan Liang "UMask": "0x1", 904ecd94f1bSKan Liang "BriefDescription": "Counts all demand data writes (RFOs)", 905ecd94f1bSKan Liang "MSRValue": "0x0080080002", 906ecd94f1bSKan Liang "Counter": "0,1,2,3", 907ecd94f1bSKan Liang "EventName": "OCR.DEMAND_RFO.L3_HIT_E.SNOOP_NONE", 908ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 909ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 910ecd94f1bSKan Liang "SampleAfterValue": "100003", 911ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 912ecd94f1bSKan Liang }, 913ecd94f1bSKan Liang { 914ecd94f1bSKan Liang "Offcore": "1", 915ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 916ecd94f1bSKan Liang "UMask": "0x1", 917ecd94f1bSKan Liang "BriefDescription": "Counts all demand data writes (RFOs) TBD", 918ecd94f1bSKan Liang "MSRValue": "0x0100080002", 919ecd94f1bSKan Liang "Counter": "0,1,2,3", 920ecd94f1bSKan Liang "EventName": "OCR.DEMAND_RFO.L3_HIT_E.NO_SNOOP_NEEDED", 921ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 922ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 923ecd94f1bSKan Liang "SampleAfterValue": "100003", 924ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 925ecd94f1bSKan Liang }, 926ecd94f1bSKan Liang { 927ecd94f1bSKan Liang "Offcore": "1", 928ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 929ecd94f1bSKan Liang "UMask": "0x1", 930ecd94f1bSKan Liang "BriefDescription": "Counts all demand data writes (RFOs)", 931ecd94f1bSKan Liang "MSRValue": "0x0200080002", 932ecd94f1bSKan Liang "Counter": "0,1,2,3", 933ecd94f1bSKan Liang "EventName": "OCR.DEMAND_RFO.L3_HIT_E.SNOOP_MISS", 934ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 935ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 936ecd94f1bSKan Liang "SampleAfterValue": "100003", 937ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 938ecd94f1bSKan Liang }, 939ecd94f1bSKan Liang { 940ecd94f1bSKan Liang "Offcore": "1", 941ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 942ecd94f1bSKan Liang "UMask": "0x1", 943ecd94f1bSKan Liang "BriefDescription": "Counts all demand data writes (RFOs) TBD", 944ecd94f1bSKan Liang "MSRValue": "0x0400080002", 945ecd94f1bSKan Liang "Counter": "0,1,2,3", 946ecd94f1bSKan Liang "EventName": "OCR.DEMAND_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", 947ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 948ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 949ecd94f1bSKan Liang "SampleAfterValue": "100003", 950ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 951ecd94f1bSKan Liang }, 952ecd94f1bSKan Liang { 953ecd94f1bSKan Liang "Offcore": "1", 954ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 955ecd94f1bSKan Liang "UMask": "0x1", 956ecd94f1bSKan Liang "BriefDescription": "Counts all demand data writes (RFOs) TBD", 957ecd94f1bSKan Liang "MSRValue": "0x0800080002", 958ecd94f1bSKan Liang "Counter": "0,1,2,3", 959ecd94f1bSKan Liang "EventName": "OCR.DEMAND_RFO.L3_HIT_E.HIT_OTHER_CORE_FWD", 960ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 961ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 962ecd94f1bSKan Liang "SampleAfterValue": "100003", 963ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 964ecd94f1bSKan Liang }, 965ecd94f1bSKan Liang { 966ecd94f1bSKan Liang "Offcore": "1", 967ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 968ecd94f1bSKan Liang "UMask": "0x1", 969ecd94f1bSKan Liang "BriefDescription": "Counts all demand data writes (RFOs) TBD", 970ecd94f1bSKan Liang "MSRValue": "0x1000080002", 971ecd94f1bSKan Liang "Counter": "0,1,2,3", 972ecd94f1bSKan Liang "EventName": "OCR.DEMAND_RFO.L3_HIT_E.HITM_OTHER_CORE", 973ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 974ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 975ecd94f1bSKan Liang "SampleAfterValue": "100003", 976ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 977ecd94f1bSKan Liang }, 978ecd94f1bSKan Liang { 979ecd94f1bSKan Liang "Offcore": "1", 980ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 981ecd94f1bSKan Liang "UMask": "0x1", 982ecd94f1bSKan Liang "BriefDescription": "Counts all demand data writes (RFOs) TBD", 983ecd94f1bSKan Liang "MSRValue": "0x3F80080002", 984ecd94f1bSKan Liang "Counter": "0,1,2,3", 985ecd94f1bSKan Liang "EventName": "OCR.DEMAND_RFO.L3_HIT_E.ANY_SNOOP", 986ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 987ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 988ecd94f1bSKan Liang "SampleAfterValue": "100003", 989ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 990ecd94f1bSKan Liang }, 991ecd94f1bSKan Liang { 992ecd94f1bSKan Liang "Offcore": "1", 993ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 994ecd94f1bSKan Liang "UMask": "0x1", 995ecd94f1bSKan Liang "BriefDescription": "Counts all demand data writes (RFOs)", 996ecd94f1bSKan Liang "MSRValue": "0x0080100002", 997ecd94f1bSKan Liang "Counter": "0,1,2,3", 998ecd94f1bSKan Liang "EventName": "OCR.DEMAND_RFO.L3_HIT_S.SNOOP_NONE", 999ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 1000ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1001ecd94f1bSKan Liang "SampleAfterValue": "100003", 1002ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 1003ecd94f1bSKan Liang }, 1004ecd94f1bSKan Liang { 1005ecd94f1bSKan Liang "Offcore": "1", 1006ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 1007ecd94f1bSKan Liang "UMask": "0x1", 1008ecd94f1bSKan Liang "BriefDescription": "Counts all demand data writes (RFOs) TBD", 1009ecd94f1bSKan Liang "MSRValue": "0x0100100002", 1010ecd94f1bSKan Liang "Counter": "0,1,2,3", 1011ecd94f1bSKan Liang "EventName": "OCR.DEMAND_RFO.L3_HIT_S.NO_SNOOP_NEEDED", 1012ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 1013ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1014ecd94f1bSKan Liang "SampleAfterValue": "100003", 1015ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 1016ecd94f1bSKan Liang }, 1017ecd94f1bSKan Liang { 1018ecd94f1bSKan Liang "Offcore": "1", 1019ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 1020ecd94f1bSKan Liang "UMask": "0x1", 1021ecd94f1bSKan Liang "BriefDescription": "Counts all demand data writes (RFOs)", 1022ecd94f1bSKan Liang "MSRValue": "0x0200100002", 1023ecd94f1bSKan Liang "Counter": "0,1,2,3", 1024ecd94f1bSKan Liang "EventName": "OCR.DEMAND_RFO.L3_HIT_S.SNOOP_MISS", 1025ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 1026ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1027ecd94f1bSKan Liang "SampleAfterValue": "100003", 1028ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 1029ecd94f1bSKan Liang }, 1030ecd94f1bSKan Liang { 1031ecd94f1bSKan Liang "Offcore": "1", 1032ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 1033ecd94f1bSKan Liang "UMask": "0x1", 1034ecd94f1bSKan Liang "BriefDescription": "Counts all demand data writes (RFOs) TBD", 1035ecd94f1bSKan Liang "MSRValue": "0x0400100002", 1036ecd94f1bSKan Liang "Counter": "0,1,2,3", 1037ecd94f1bSKan Liang "EventName": "OCR.DEMAND_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", 1038ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 1039ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1040ecd94f1bSKan Liang "SampleAfterValue": "100003", 1041ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 1042ecd94f1bSKan Liang }, 1043ecd94f1bSKan Liang { 1044ecd94f1bSKan Liang "Offcore": "1", 1045ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 1046ecd94f1bSKan Liang "UMask": "0x1", 1047ecd94f1bSKan Liang "BriefDescription": "Counts all demand data writes (RFOs) TBD", 1048ecd94f1bSKan Liang "MSRValue": "0x0800100002", 1049ecd94f1bSKan Liang "Counter": "0,1,2,3", 1050ecd94f1bSKan Liang "EventName": "OCR.DEMAND_RFO.L3_HIT_S.HIT_OTHER_CORE_FWD", 1051ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 1052ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1053ecd94f1bSKan Liang "SampleAfterValue": "100003", 1054ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 1055ecd94f1bSKan Liang }, 1056ecd94f1bSKan Liang { 1057ecd94f1bSKan Liang "Offcore": "1", 1058ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 1059ecd94f1bSKan Liang "UMask": "0x1", 1060ecd94f1bSKan Liang "BriefDescription": "Counts all demand data writes (RFOs) TBD", 1061ecd94f1bSKan Liang "MSRValue": "0x1000100002", 1062ecd94f1bSKan Liang "Counter": "0,1,2,3", 1063ecd94f1bSKan Liang "EventName": "OCR.DEMAND_RFO.L3_HIT_S.HITM_OTHER_CORE", 1064ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 1065ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1066ecd94f1bSKan Liang "SampleAfterValue": "100003", 1067ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 1068ecd94f1bSKan Liang }, 1069ecd94f1bSKan Liang { 1070ecd94f1bSKan Liang "Offcore": "1", 1071ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 1072ecd94f1bSKan Liang "UMask": "0x1", 1073ecd94f1bSKan Liang "BriefDescription": "Counts all demand data writes (RFOs) TBD", 1074ecd94f1bSKan Liang "MSRValue": "0x3F80100002", 1075ecd94f1bSKan Liang "Counter": "0,1,2,3", 1076ecd94f1bSKan Liang "EventName": "OCR.DEMAND_RFO.L3_HIT_S.ANY_SNOOP", 1077ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 1078ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1079ecd94f1bSKan Liang "SampleAfterValue": "100003", 1080ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 1081ecd94f1bSKan Liang }, 1082ecd94f1bSKan Liang { 1083ecd94f1bSKan Liang "Offcore": "1", 1084ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 1085ecd94f1bSKan Liang "UMask": "0x1", 1086ecd94f1bSKan Liang "BriefDescription": "Counts all demand data writes (RFOs)", 1087ecd94f1bSKan Liang "MSRValue": "0x0080200002", 1088ecd94f1bSKan Liang "Counter": "0,1,2,3", 1089ecd94f1bSKan Liang "EventName": "OCR.DEMAND_RFO.L3_HIT_F.SNOOP_NONE", 1090ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 1091ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1092ecd94f1bSKan Liang "SampleAfterValue": "100003", 1093ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 1094ecd94f1bSKan Liang }, 1095ecd94f1bSKan Liang { 1096ecd94f1bSKan Liang "Offcore": "1", 1097ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 1098ecd94f1bSKan Liang "UMask": "0x1", 1099ecd94f1bSKan Liang "BriefDescription": "Counts all demand data writes (RFOs) TBD", 1100ecd94f1bSKan Liang "MSRValue": "0x0100200002", 1101ecd94f1bSKan Liang "Counter": "0,1,2,3", 1102ecd94f1bSKan Liang "EventName": "OCR.DEMAND_RFO.L3_HIT_F.NO_SNOOP_NEEDED", 1103ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 1104ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1105ecd94f1bSKan Liang "SampleAfterValue": "100003", 1106ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 1107ecd94f1bSKan Liang }, 1108ecd94f1bSKan Liang { 1109ecd94f1bSKan Liang "Offcore": "1", 1110ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 1111ecd94f1bSKan Liang "UMask": "0x1", 1112ecd94f1bSKan Liang "BriefDescription": "Counts all demand data writes (RFOs)", 1113ecd94f1bSKan Liang "MSRValue": "0x0200200002", 1114ecd94f1bSKan Liang "Counter": "0,1,2,3", 1115ecd94f1bSKan Liang "EventName": "OCR.DEMAND_RFO.L3_HIT_F.SNOOP_MISS", 1116ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 1117ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1118ecd94f1bSKan Liang "SampleAfterValue": "100003", 1119ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 1120ecd94f1bSKan Liang }, 1121ecd94f1bSKan Liang { 1122ecd94f1bSKan Liang "Offcore": "1", 1123ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 1124ecd94f1bSKan Liang "UMask": "0x1", 1125ecd94f1bSKan Liang "BriefDescription": "Counts all demand data writes (RFOs) TBD", 1126ecd94f1bSKan Liang "MSRValue": "0x0400200002", 1127ecd94f1bSKan Liang "Counter": "0,1,2,3", 1128ecd94f1bSKan Liang "EventName": "OCR.DEMAND_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", 1129ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 1130ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1131ecd94f1bSKan Liang "SampleAfterValue": "100003", 1132ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 1133ecd94f1bSKan Liang }, 1134ecd94f1bSKan Liang { 1135ecd94f1bSKan Liang "Offcore": "1", 1136ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 1137ecd94f1bSKan Liang "UMask": "0x1", 1138ecd94f1bSKan Liang "BriefDescription": "Counts all demand data writes (RFOs) TBD", 1139ecd94f1bSKan Liang "MSRValue": "0x0800200002", 1140ecd94f1bSKan Liang "Counter": "0,1,2,3", 1141ecd94f1bSKan Liang "EventName": "OCR.DEMAND_RFO.L3_HIT_F.HIT_OTHER_CORE_FWD", 1142ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 1143ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1144ecd94f1bSKan Liang "SampleAfterValue": "100003", 1145ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 1146ecd94f1bSKan Liang }, 1147ecd94f1bSKan Liang { 1148ecd94f1bSKan Liang "Offcore": "1", 1149ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 1150ecd94f1bSKan Liang "UMask": "0x1", 1151ecd94f1bSKan Liang "BriefDescription": "Counts all demand data writes (RFOs) TBD", 1152ecd94f1bSKan Liang "MSRValue": "0x1000200002", 1153ecd94f1bSKan Liang "Counter": "0,1,2,3", 1154ecd94f1bSKan Liang "EventName": "OCR.DEMAND_RFO.L3_HIT_F.HITM_OTHER_CORE", 1155ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 1156ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1157ecd94f1bSKan Liang "SampleAfterValue": "100003", 1158ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 1159ecd94f1bSKan Liang }, 1160ecd94f1bSKan Liang { 1161ecd94f1bSKan Liang "Offcore": "1", 1162ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 1163ecd94f1bSKan Liang "UMask": "0x1", 1164ecd94f1bSKan Liang "BriefDescription": "Counts all demand data writes (RFOs) TBD", 1165ecd94f1bSKan Liang "MSRValue": "0x3F80200002", 1166ecd94f1bSKan Liang "Counter": "0,1,2,3", 1167ecd94f1bSKan Liang "EventName": "OCR.DEMAND_RFO.L3_HIT_F.ANY_SNOOP", 1168ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 1169ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1170ecd94f1bSKan Liang "SampleAfterValue": "100003", 1171ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 1172ecd94f1bSKan Liang }, 1173ecd94f1bSKan Liang { 1174ecd94f1bSKan Liang "Offcore": "1", 1175ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 1176ecd94f1bSKan Liang "UMask": "0x1", 1177ecd94f1bSKan Liang "BriefDescription": "Counts all demand data writes (RFOs) TBD", 1178ecd94f1bSKan Liang "MSRValue": "0x00803C0002", 1179ecd94f1bSKan Liang "Counter": "0,1,2,3", 1180ecd94f1bSKan Liang "EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_NONE", 1181ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 1182ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1183ecd94f1bSKan Liang "SampleAfterValue": "100003", 1184ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 1185ecd94f1bSKan Liang }, 1186ecd94f1bSKan Liang { 1187ecd94f1bSKan Liang "Offcore": "1", 1188ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 1189ecd94f1bSKan Liang "UMask": "0x1", 1190ecd94f1bSKan Liang "BriefDescription": "Counts all demand data writes (RFOs) TBD TBD", 1191ecd94f1bSKan Liang "MSRValue": "0x01003C0002", 1192ecd94f1bSKan Liang "Counter": "0,1,2,3", 1193ecd94f1bSKan Liang "EventName": "OCR.DEMAND_RFO.L3_HIT.NO_SNOOP_NEEDED", 1194ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 1195ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1196ecd94f1bSKan Liang "SampleAfterValue": "100003", 1197ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 1198ecd94f1bSKan Liang }, 1199ecd94f1bSKan Liang { 1200ecd94f1bSKan Liang "Offcore": "1", 1201ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 1202ecd94f1bSKan Liang "UMask": "0x1", 1203ecd94f1bSKan Liang "BriefDescription": "Counts all demand data writes (RFOs) TBD", 1204ecd94f1bSKan Liang "MSRValue": "0x02003C0002", 1205ecd94f1bSKan Liang "Counter": "0,1,2,3", 1206ecd94f1bSKan Liang "EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_MISS", 1207ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 1208ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1209ecd94f1bSKan Liang "SampleAfterValue": "100003", 1210ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 1211ecd94f1bSKan Liang }, 1212ecd94f1bSKan Liang { 1213ecd94f1bSKan Liang "Offcore": "1", 1214ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 1215ecd94f1bSKan Liang "UMask": "0x1", 1216ecd94f1bSKan Liang "BriefDescription": "Counts all demand data writes (RFOs) TBD TBD", 1217ecd94f1bSKan Liang "MSRValue": "0x04003C0002", 1218ecd94f1bSKan Liang "Counter": "0,1,2,3", 1219ecd94f1bSKan Liang "EventName": "OCR.DEMAND_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD", 1220ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 1221ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1222ecd94f1bSKan Liang "SampleAfterValue": "100003", 1223ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 1224ecd94f1bSKan Liang }, 1225ecd94f1bSKan Liang { 1226ecd94f1bSKan Liang "Offcore": "1", 1227ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 1228ecd94f1bSKan Liang "UMask": "0x1", 1229ecd94f1bSKan Liang "BriefDescription": "Counts all demand data writes (RFOs) TBD TBD", 1230ecd94f1bSKan Liang "MSRValue": "0x08003C0002", 1231ecd94f1bSKan Liang "Counter": "0,1,2,3", 1232ecd94f1bSKan Liang "EventName": "OCR.DEMAND_RFO.L3_HIT.HIT_OTHER_CORE_FWD", 1233ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 1234ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1235ecd94f1bSKan Liang "SampleAfterValue": "100003", 1236ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 1237ecd94f1bSKan Liang }, 1238ecd94f1bSKan Liang { 1239ecd94f1bSKan Liang "Offcore": "1", 1240ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 1241ecd94f1bSKan Liang "UMask": "0x1", 1242ecd94f1bSKan Liang "BriefDescription": "Counts all demand data writes (RFOs) TBD TBD", 1243ecd94f1bSKan Liang "MSRValue": "0x10003C0002", 1244ecd94f1bSKan Liang "Counter": "0,1,2,3", 1245ecd94f1bSKan Liang "EventName": "OCR.DEMAND_RFO.L3_HIT.HITM_OTHER_CORE", 1246ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 1247ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1248ecd94f1bSKan Liang "SampleAfterValue": "100003", 1249ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 1250ecd94f1bSKan Liang }, 1251ecd94f1bSKan Liang { 1252ecd94f1bSKan Liang "Offcore": "1", 1253ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 1254ecd94f1bSKan Liang "UMask": "0x1", 1255ecd94f1bSKan Liang "BriefDescription": "Counts all demand data writes (RFOs) TBD TBD", 1256ecd94f1bSKan Liang "MSRValue": "0x3F803C0002", 1257ecd94f1bSKan Liang "Counter": "0,1,2,3", 1258ecd94f1bSKan Liang "EventName": "OCR.DEMAND_RFO.L3_HIT.ANY_SNOOP", 1259ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 1260ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1261ecd94f1bSKan Liang "SampleAfterValue": "100003", 1262ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 1263ecd94f1bSKan Liang }, 1264ecd94f1bSKan Liang { 1265ecd94f1bSKan Liang "Offcore": "1", 1266ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 1267ecd94f1bSKan Liang "UMask": "0x1", 1268ecd94f1bSKan Liang "BriefDescription": "Counts all demand code reads", 1269ecd94f1bSKan Liang "MSRValue": "0x0080020004", 1270ecd94f1bSKan Liang "Counter": "0,1,2,3", 1271ecd94f1bSKan Liang "EventName": "OCR.DEMAND_CODE_RD.SUPPLIER_NONE.SNOOP_NONE", 1272ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 1273ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1274ecd94f1bSKan Liang "SampleAfterValue": "100003", 1275ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 1276ecd94f1bSKan Liang }, 1277ecd94f1bSKan Liang { 1278ecd94f1bSKan Liang "Offcore": "1", 1279ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 1280ecd94f1bSKan Liang "UMask": "0x1", 1281ecd94f1bSKan Liang "BriefDescription": "Counts all demand code reads TBD", 1282ecd94f1bSKan Liang "MSRValue": "0x0100020004", 1283ecd94f1bSKan Liang "Counter": "0,1,2,3", 1284ecd94f1bSKan Liang "EventName": "OCR.DEMAND_CODE_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED", 1285ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 1286ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1287ecd94f1bSKan Liang "SampleAfterValue": "100003", 1288ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 1289ecd94f1bSKan Liang }, 1290ecd94f1bSKan Liang { 1291ecd94f1bSKan Liang "Offcore": "1", 1292ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 1293ecd94f1bSKan Liang "UMask": "0x1", 1294ecd94f1bSKan Liang "BriefDescription": "Counts all demand code reads", 1295ecd94f1bSKan Liang "MSRValue": "0x0200020004", 1296ecd94f1bSKan Liang "Counter": "0,1,2,3", 1297ecd94f1bSKan Liang "EventName": "OCR.DEMAND_CODE_RD.SUPPLIER_NONE.SNOOP_MISS", 1298ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 1299ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1300ecd94f1bSKan Liang "SampleAfterValue": "100003", 1301ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 1302ecd94f1bSKan Liang }, 1303ecd94f1bSKan Liang { 1304ecd94f1bSKan Liang "Offcore": "1", 1305ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 1306ecd94f1bSKan Liang "UMask": "0x1", 1307ecd94f1bSKan Liang "BriefDescription": "Counts all demand code reads TBD", 1308ecd94f1bSKan Liang "MSRValue": "0x0400020004", 1309ecd94f1bSKan Liang "Counter": "0,1,2,3", 1310ecd94f1bSKan Liang "EventName": "OCR.DEMAND_CODE_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", 1311ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 1312ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1313ecd94f1bSKan Liang "SampleAfterValue": "100003", 1314ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 1315ecd94f1bSKan Liang }, 1316ecd94f1bSKan Liang { 1317ecd94f1bSKan Liang "Offcore": "1", 1318ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 1319ecd94f1bSKan Liang "UMask": "0x1", 1320ecd94f1bSKan Liang "BriefDescription": "Counts all demand code reads TBD", 1321ecd94f1bSKan Liang "MSRValue": "0x0800020004", 1322ecd94f1bSKan Liang "Counter": "0,1,2,3", 1323ecd94f1bSKan Liang "EventName": "OCR.DEMAND_CODE_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", 1324ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 1325ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1326ecd94f1bSKan Liang "SampleAfterValue": "100003", 1327ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 1328ecd94f1bSKan Liang }, 1329ecd94f1bSKan Liang { 1330ecd94f1bSKan Liang "Offcore": "1", 1331ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 1332ecd94f1bSKan Liang "UMask": "0x1", 1333ecd94f1bSKan Liang "BriefDescription": "Counts all demand code reads TBD", 1334ecd94f1bSKan Liang "MSRValue": "0x1000020004", 1335ecd94f1bSKan Liang "Counter": "0,1,2,3", 1336ecd94f1bSKan Liang "EventName": "OCR.DEMAND_CODE_RD.SUPPLIER_NONE.HITM_OTHER_CORE", 1337ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 1338ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1339ecd94f1bSKan Liang "SampleAfterValue": "100003", 1340ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 1341ecd94f1bSKan Liang }, 1342ecd94f1bSKan Liang { 1343ecd94f1bSKan Liang "Offcore": "1", 1344ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 1345ecd94f1bSKan Liang "UMask": "0x1", 1346ecd94f1bSKan Liang "BriefDescription": "Counts all demand code reads TBD", 1347ecd94f1bSKan Liang "MSRValue": "0x3F80020004", 1348ecd94f1bSKan Liang "Counter": "0,1,2,3", 1349ecd94f1bSKan Liang "EventName": "OCR.DEMAND_CODE_RD.SUPPLIER_NONE.ANY_SNOOP", 1350ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 1351ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1352ecd94f1bSKan Liang "SampleAfterValue": "100003", 1353ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 1354ecd94f1bSKan Liang }, 1355ecd94f1bSKan Liang { 1356ecd94f1bSKan Liang "Offcore": "1", 1357ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 1358ecd94f1bSKan Liang "UMask": "0x1", 1359ecd94f1bSKan Liang "BriefDescription": "Counts all demand code reads", 1360ecd94f1bSKan Liang "MSRValue": "0x0080040004", 1361ecd94f1bSKan Liang "Counter": "0,1,2,3", 1362ecd94f1bSKan Liang "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_M.SNOOP_NONE", 1363ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 1364ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1365ecd94f1bSKan Liang "SampleAfterValue": "100003", 1366ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 1367ecd94f1bSKan Liang }, 1368ecd94f1bSKan Liang { 1369ecd94f1bSKan Liang "Offcore": "1", 1370ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 1371ecd94f1bSKan Liang "UMask": "0x1", 1372ecd94f1bSKan Liang "BriefDescription": "Counts all demand code reads TBD", 1373ecd94f1bSKan Liang "MSRValue": "0x0100040004", 1374ecd94f1bSKan Liang "Counter": "0,1,2,3", 1375ecd94f1bSKan Liang "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_M.NO_SNOOP_NEEDED", 1376ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 1377ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1378ecd94f1bSKan Liang "SampleAfterValue": "100003", 1379ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 1380ecd94f1bSKan Liang }, 1381ecd94f1bSKan Liang { 1382ecd94f1bSKan Liang "Offcore": "1", 1383ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 1384ecd94f1bSKan Liang "UMask": "0x1", 1385ecd94f1bSKan Liang "BriefDescription": "Counts all demand code reads", 1386ecd94f1bSKan Liang "MSRValue": "0x0200040004", 1387ecd94f1bSKan Liang "Counter": "0,1,2,3", 1388ecd94f1bSKan Liang "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_M.SNOOP_MISS", 1389ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 1390ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1391ecd94f1bSKan Liang "SampleAfterValue": "100003", 1392ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 1393ecd94f1bSKan Liang }, 1394ecd94f1bSKan Liang { 1395ecd94f1bSKan Liang "Offcore": "1", 1396ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 1397ecd94f1bSKan Liang "UMask": "0x1", 1398ecd94f1bSKan Liang "BriefDescription": "Counts all demand code reads TBD", 1399ecd94f1bSKan Liang "MSRValue": "0x0400040004", 1400ecd94f1bSKan Liang "Counter": "0,1,2,3", 1401ecd94f1bSKan Liang "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", 1402ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 1403ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1404ecd94f1bSKan Liang "SampleAfterValue": "100003", 1405ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 1406ecd94f1bSKan Liang }, 1407ecd94f1bSKan Liang { 1408ecd94f1bSKan Liang "Offcore": "1", 1409ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 1410ecd94f1bSKan Liang "UMask": "0x1", 1411ecd94f1bSKan Liang "BriefDescription": "Counts all demand code reads TBD", 1412ecd94f1bSKan Liang "MSRValue": "0x0800040004", 1413ecd94f1bSKan Liang "Counter": "0,1,2,3", 1414ecd94f1bSKan Liang "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_M.HIT_OTHER_CORE_FWD", 1415ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 1416ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1417ecd94f1bSKan Liang "SampleAfterValue": "100003", 1418ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 1419ecd94f1bSKan Liang }, 1420ecd94f1bSKan Liang { 1421ecd94f1bSKan Liang "Offcore": "1", 1422ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 1423ecd94f1bSKan Liang "UMask": "0x1", 1424ecd94f1bSKan Liang "BriefDescription": "Counts all demand code reads TBD", 1425ecd94f1bSKan Liang "MSRValue": "0x1000040004", 1426ecd94f1bSKan Liang "Counter": "0,1,2,3", 1427ecd94f1bSKan Liang "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_M.HITM_OTHER_CORE", 1428ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 1429ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1430ecd94f1bSKan Liang "SampleAfterValue": "100003", 1431ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 1432ecd94f1bSKan Liang }, 1433ecd94f1bSKan Liang { 1434ecd94f1bSKan Liang "Offcore": "1", 1435ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 1436ecd94f1bSKan Liang "UMask": "0x1", 1437ecd94f1bSKan Liang "BriefDescription": "Counts all demand code reads TBD", 1438ecd94f1bSKan Liang "MSRValue": "0x3F80040004", 1439ecd94f1bSKan Liang "Counter": "0,1,2,3", 1440ecd94f1bSKan Liang "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_M.ANY_SNOOP", 1441ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 1442ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1443ecd94f1bSKan Liang "SampleAfterValue": "100003", 1444ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 1445ecd94f1bSKan Liang }, 1446ecd94f1bSKan Liang { 1447ecd94f1bSKan Liang "Offcore": "1", 1448ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 1449ecd94f1bSKan Liang "UMask": "0x1", 1450ecd94f1bSKan Liang "BriefDescription": "Counts all demand code reads", 1451ecd94f1bSKan Liang "MSRValue": "0x0080080004", 1452ecd94f1bSKan Liang "Counter": "0,1,2,3", 1453ecd94f1bSKan Liang "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_E.SNOOP_NONE", 1454ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 1455ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1456ecd94f1bSKan Liang "SampleAfterValue": "100003", 1457ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 1458ecd94f1bSKan Liang }, 1459ecd94f1bSKan Liang { 1460ecd94f1bSKan Liang "Offcore": "1", 1461ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 1462ecd94f1bSKan Liang "UMask": "0x1", 1463ecd94f1bSKan Liang "BriefDescription": "Counts all demand code reads TBD", 1464ecd94f1bSKan Liang "MSRValue": "0x0100080004", 1465ecd94f1bSKan Liang "Counter": "0,1,2,3", 1466ecd94f1bSKan Liang "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_E.NO_SNOOP_NEEDED", 1467ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 1468ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1469ecd94f1bSKan Liang "SampleAfterValue": "100003", 1470ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 1471ecd94f1bSKan Liang }, 1472ecd94f1bSKan Liang { 1473ecd94f1bSKan Liang "Offcore": "1", 1474ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 1475ecd94f1bSKan Liang "UMask": "0x1", 1476ecd94f1bSKan Liang "BriefDescription": "Counts all demand code reads", 1477ecd94f1bSKan Liang "MSRValue": "0x0200080004", 1478ecd94f1bSKan Liang "Counter": "0,1,2,3", 1479ecd94f1bSKan Liang "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_E.SNOOP_MISS", 1480ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 1481ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1482ecd94f1bSKan Liang "SampleAfterValue": "100003", 1483ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 1484ecd94f1bSKan Liang }, 1485ecd94f1bSKan Liang { 1486ecd94f1bSKan Liang "Offcore": "1", 1487ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 1488ecd94f1bSKan Liang "UMask": "0x1", 1489ecd94f1bSKan Liang "BriefDescription": "Counts all demand code reads TBD", 1490ecd94f1bSKan Liang "MSRValue": "0x0400080004", 1491ecd94f1bSKan Liang "Counter": "0,1,2,3", 1492ecd94f1bSKan Liang "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", 1493ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 1494ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1495ecd94f1bSKan Liang "SampleAfterValue": "100003", 1496ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 1497ecd94f1bSKan Liang }, 1498ecd94f1bSKan Liang { 1499ecd94f1bSKan Liang "Offcore": "1", 1500ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 1501ecd94f1bSKan Liang "UMask": "0x1", 1502ecd94f1bSKan Liang "BriefDescription": "Counts all demand code reads TBD", 1503ecd94f1bSKan Liang "MSRValue": "0x0800080004", 1504ecd94f1bSKan Liang "Counter": "0,1,2,3", 1505ecd94f1bSKan Liang "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_E.HIT_OTHER_CORE_FWD", 1506ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 1507ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1508ecd94f1bSKan Liang "SampleAfterValue": "100003", 1509ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 1510ecd94f1bSKan Liang }, 1511ecd94f1bSKan Liang { 1512ecd94f1bSKan Liang "Offcore": "1", 1513ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 1514ecd94f1bSKan Liang "UMask": "0x1", 1515ecd94f1bSKan Liang "BriefDescription": "Counts all demand code reads TBD", 1516ecd94f1bSKan Liang "MSRValue": "0x1000080004", 1517ecd94f1bSKan Liang "Counter": "0,1,2,3", 1518ecd94f1bSKan Liang "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_E.HITM_OTHER_CORE", 1519ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 1520ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1521ecd94f1bSKan Liang "SampleAfterValue": "100003", 1522ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 1523ecd94f1bSKan Liang }, 1524ecd94f1bSKan Liang { 1525ecd94f1bSKan Liang "Offcore": "1", 1526ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 1527ecd94f1bSKan Liang "UMask": "0x1", 1528ecd94f1bSKan Liang "BriefDescription": "Counts all demand code reads TBD", 1529ecd94f1bSKan Liang "MSRValue": "0x3F80080004", 1530ecd94f1bSKan Liang "Counter": "0,1,2,3", 1531ecd94f1bSKan Liang "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_E.ANY_SNOOP", 1532ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 1533ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1534ecd94f1bSKan Liang "SampleAfterValue": "100003", 1535ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 1536ecd94f1bSKan Liang }, 1537ecd94f1bSKan Liang { 1538ecd94f1bSKan Liang "Offcore": "1", 1539ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 1540ecd94f1bSKan Liang "UMask": "0x1", 1541ecd94f1bSKan Liang "BriefDescription": "Counts all demand code reads", 1542ecd94f1bSKan Liang "MSRValue": "0x0080100004", 1543ecd94f1bSKan Liang "Counter": "0,1,2,3", 1544ecd94f1bSKan Liang "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_S.SNOOP_NONE", 1545ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 1546ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1547ecd94f1bSKan Liang "SampleAfterValue": "100003", 1548ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 1549ecd94f1bSKan Liang }, 1550ecd94f1bSKan Liang { 1551ecd94f1bSKan Liang "Offcore": "1", 1552ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 1553ecd94f1bSKan Liang "UMask": "0x1", 1554ecd94f1bSKan Liang "BriefDescription": "Counts all demand code reads TBD", 1555ecd94f1bSKan Liang "MSRValue": "0x0100100004", 1556ecd94f1bSKan Liang "Counter": "0,1,2,3", 1557ecd94f1bSKan Liang "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_S.NO_SNOOP_NEEDED", 1558ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 1559ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1560ecd94f1bSKan Liang "SampleAfterValue": "100003", 1561ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 1562ecd94f1bSKan Liang }, 1563ecd94f1bSKan Liang { 1564ecd94f1bSKan Liang "Offcore": "1", 1565ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 1566ecd94f1bSKan Liang "UMask": "0x1", 1567ecd94f1bSKan Liang "BriefDescription": "Counts all demand code reads", 1568ecd94f1bSKan Liang "MSRValue": "0x0200100004", 1569ecd94f1bSKan Liang "Counter": "0,1,2,3", 1570ecd94f1bSKan Liang "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_S.SNOOP_MISS", 1571ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 1572ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1573ecd94f1bSKan Liang "SampleAfterValue": "100003", 1574ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 1575ecd94f1bSKan Liang }, 1576ecd94f1bSKan Liang { 1577ecd94f1bSKan Liang "Offcore": "1", 1578ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 1579ecd94f1bSKan Liang "UMask": "0x1", 1580ecd94f1bSKan Liang "BriefDescription": "Counts all demand code reads TBD", 1581ecd94f1bSKan Liang "MSRValue": "0x0400100004", 1582ecd94f1bSKan Liang "Counter": "0,1,2,3", 1583ecd94f1bSKan Liang "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", 1584ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 1585ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1586ecd94f1bSKan Liang "SampleAfterValue": "100003", 1587ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 1588ecd94f1bSKan Liang }, 1589ecd94f1bSKan Liang { 1590ecd94f1bSKan Liang "Offcore": "1", 1591ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 1592ecd94f1bSKan Liang "UMask": "0x1", 1593ecd94f1bSKan Liang "BriefDescription": "Counts all demand code reads TBD", 1594ecd94f1bSKan Liang "MSRValue": "0x0800100004", 1595ecd94f1bSKan Liang "Counter": "0,1,2,3", 1596ecd94f1bSKan Liang "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_S.HIT_OTHER_CORE_FWD", 1597ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 1598ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1599ecd94f1bSKan Liang "SampleAfterValue": "100003", 1600ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 1601ecd94f1bSKan Liang }, 1602ecd94f1bSKan Liang { 1603ecd94f1bSKan Liang "Offcore": "1", 1604ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 1605ecd94f1bSKan Liang "UMask": "0x1", 1606ecd94f1bSKan Liang "BriefDescription": "Counts all demand code reads TBD", 1607ecd94f1bSKan Liang "MSRValue": "0x1000100004", 1608ecd94f1bSKan Liang "Counter": "0,1,2,3", 1609ecd94f1bSKan Liang "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_S.HITM_OTHER_CORE", 1610ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 1611ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1612ecd94f1bSKan Liang "SampleAfterValue": "100003", 1613ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 1614ecd94f1bSKan Liang }, 1615ecd94f1bSKan Liang { 1616ecd94f1bSKan Liang "Offcore": "1", 1617ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 1618ecd94f1bSKan Liang "UMask": "0x1", 1619ecd94f1bSKan Liang "BriefDescription": "Counts all demand code reads TBD", 1620ecd94f1bSKan Liang "MSRValue": "0x3F80100004", 1621ecd94f1bSKan Liang "Counter": "0,1,2,3", 1622ecd94f1bSKan Liang "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_S.ANY_SNOOP", 1623ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 1624ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1625ecd94f1bSKan Liang "SampleAfterValue": "100003", 1626ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 1627ecd94f1bSKan Liang }, 1628ecd94f1bSKan Liang { 1629ecd94f1bSKan Liang "Offcore": "1", 1630ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 1631ecd94f1bSKan Liang "UMask": "0x1", 1632ecd94f1bSKan Liang "BriefDescription": "Counts all demand code reads", 1633ecd94f1bSKan Liang "MSRValue": "0x0080200004", 1634ecd94f1bSKan Liang "Counter": "0,1,2,3", 1635ecd94f1bSKan Liang "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_F.SNOOP_NONE", 1636ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 1637ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1638ecd94f1bSKan Liang "SampleAfterValue": "100003", 1639ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 1640ecd94f1bSKan Liang }, 1641ecd94f1bSKan Liang { 1642ecd94f1bSKan Liang "Offcore": "1", 1643ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 1644ecd94f1bSKan Liang "UMask": "0x1", 1645ecd94f1bSKan Liang "BriefDescription": "Counts all demand code reads TBD", 1646ecd94f1bSKan Liang "MSRValue": "0x0100200004", 1647ecd94f1bSKan Liang "Counter": "0,1,2,3", 1648ecd94f1bSKan Liang "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_F.NO_SNOOP_NEEDED", 1649ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 1650ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1651ecd94f1bSKan Liang "SampleAfterValue": "100003", 1652ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 1653ecd94f1bSKan Liang }, 1654ecd94f1bSKan Liang { 1655ecd94f1bSKan Liang "Offcore": "1", 1656ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 1657ecd94f1bSKan Liang "UMask": "0x1", 1658ecd94f1bSKan Liang "BriefDescription": "Counts all demand code reads", 1659ecd94f1bSKan Liang "MSRValue": "0x0200200004", 1660ecd94f1bSKan Liang "Counter": "0,1,2,3", 1661ecd94f1bSKan Liang "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_F.SNOOP_MISS", 1662ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 1663ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1664ecd94f1bSKan Liang "SampleAfterValue": "100003", 1665ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 1666ecd94f1bSKan Liang }, 1667ecd94f1bSKan Liang { 1668ecd94f1bSKan Liang "Offcore": "1", 1669ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 1670ecd94f1bSKan Liang "UMask": "0x1", 1671ecd94f1bSKan Liang "BriefDescription": "Counts all demand code reads TBD", 1672ecd94f1bSKan Liang "MSRValue": "0x0400200004", 1673ecd94f1bSKan Liang "Counter": "0,1,2,3", 1674ecd94f1bSKan Liang "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", 1675ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 1676ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1677ecd94f1bSKan Liang "SampleAfterValue": "100003", 1678ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 1679ecd94f1bSKan Liang }, 1680ecd94f1bSKan Liang { 1681ecd94f1bSKan Liang "Offcore": "1", 1682ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 1683ecd94f1bSKan Liang "UMask": "0x1", 1684ecd94f1bSKan Liang "BriefDescription": "Counts all demand code reads TBD", 1685ecd94f1bSKan Liang "MSRValue": "0x0800200004", 1686ecd94f1bSKan Liang "Counter": "0,1,2,3", 1687ecd94f1bSKan Liang "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_F.HIT_OTHER_CORE_FWD", 1688ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 1689ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1690ecd94f1bSKan Liang "SampleAfterValue": "100003", 1691ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 1692ecd94f1bSKan Liang }, 1693ecd94f1bSKan Liang { 1694ecd94f1bSKan Liang "Offcore": "1", 1695ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 1696ecd94f1bSKan Liang "UMask": "0x1", 1697ecd94f1bSKan Liang "BriefDescription": "Counts all demand code reads TBD", 1698ecd94f1bSKan Liang "MSRValue": "0x1000200004", 1699ecd94f1bSKan Liang "Counter": "0,1,2,3", 1700ecd94f1bSKan Liang "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_F.HITM_OTHER_CORE", 1701ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 1702ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1703ecd94f1bSKan Liang "SampleAfterValue": "100003", 1704ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 1705ecd94f1bSKan Liang }, 1706ecd94f1bSKan Liang { 1707ecd94f1bSKan Liang "Offcore": "1", 1708ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 1709ecd94f1bSKan Liang "UMask": "0x1", 1710ecd94f1bSKan Liang "BriefDescription": "Counts all demand code reads TBD", 1711ecd94f1bSKan Liang "MSRValue": "0x3F80200004", 1712ecd94f1bSKan Liang "Counter": "0,1,2,3", 1713ecd94f1bSKan Liang "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_F.ANY_SNOOP", 1714ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 1715ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1716ecd94f1bSKan Liang "SampleAfterValue": "100003", 1717ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 1718ecd94f1bSKan Liang }, 1719ecd94f1bSKan Liang { 1720ecd94f1bSKan Liang "Offcore": "1", 1721ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 1722ecd94f1bSKan Liang "UMask": "0x1", 1723ecd94f1bSKan Liang "BriefDescription": "Counts all demand code reads TBD", 1724ecd94f1bSKan Liang "MSRValue": "0x00803C0004", 1725ecd94f1bSKan Liang "Counter": "0,1,2,3", 1726ecd94f1bSKan Liang "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_NONE", 1727ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 1728ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1729ecd94f1bSKan Liang "SampleAfterValue": "100003", 1730ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 1731ecd94f1bSKan Liang }, 1732ecd94f1bSKan Liang { 1733ecd94f1bSKan Liang "Offcore": "1", 1734ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 1735ecd94f1bSKan Liang "UMask": "0x1", 1736ecd94f1bSKan Liang "BriefDescription": "Counts all demand code reads TBD TBD", 1737ecd94f1bSKan Liang "MSRValue": "0x01003C0004", 1738ecd94f1bSKan Liang "Counter": "0,1,2,3", 1739ecd94f1bSKan Liang "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.NO_SNOOP_NEEDED", 1740ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 1741ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1742ecd94f1bSKan Liang "SampleAfterValue": "100003", 1743ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 1744ecd94f1bSKan Liang }, 1745ecd94f1bSKan Liang { 1746ecd94f1bSKan Liang "Offcore": "1", 1747ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 1748ecd94f1bSKan Liang "UMask": "0x1", 1749ecd94f1bSKan Liang "BriefDescription": "Counts all demand code reads TBD", 1750ecd94f1bSKan Liang "MSRValue": "0x02003C0004", 1751ecd94f1bSKan Liang "Counter": "0,1,2,3", 1752ecd94f1bSKan Liang "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_MISS", 1753ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 1754ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1755ecd94f1bSKan Liang "SampleAfterValue": "100003", 1756ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 1757ecd94f1bSKan Liang }, 1758ecd94f1bSKan Liang { 1759ecd94f1bSKan Liang "Offcore": "1", 1760ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 1761ecd94f1bSKan Liang "UMask": "0x1", 1762ecd94f1bSKan Liang "BriefDescription": "Counts all demand code reads TBD TBD", 1763ecd94f1bSKan Liang "MSRValue": "0x04003C0004", 1764ecd94f1bSKan Liang "Counter": "0,1,2,3", 1765ecd94f1bSKan Liang "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD", 1766ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 1767ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1768ecd94f1bSKan Liang "SampleAfterValue": "100003", 1769ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 1770ecd94f1bSKan Liang }, 1771ecd94f1bSKan Liang { 1772ecd94f1bSKan Liang "Offcore": "1", 1773ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 1774ecd94f1bSKan Liang "UMask": "0x1", 1775ecd94f1bSKan Liang "BriefDescription": "Counts all demand code reads TBD TBD", 1776ecd94f1bSKan Liang "MSRValue": "0x08003C0004", 1777ecd94f1bSKan Liang "Counter": "0,1,2,3", 1778ecd94f1bSKan Liang "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.HIT_OTHER_CORE_FWD", 1779ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 1780ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1781ecd94f1bSKan Liang "SampleAfterValue": "100003", 1782ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 1783ecd94f1bSKan Liang }, 1784ecd94f1bSKan Liang { 1785ecd94f1bSKan Liang "Offcore": "1", 1786ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 1787ecd94f1bSKan Liang "UMask": "0x1", 1788ecd94f1bSKan Liang "BriefDescription": "Counts all demand code reads TBD TBD", 1789ecd94f1bSKan Liang "MSRValue": "0x10003C0004", 1790ecd94f1bSKan Liang "Counter": "0,1,2,3", 1791ecd94f1bSKan Liang "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.HITM_OTHER_CORE", 1792ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 1793ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1794ecd94f1bSKan Liang "SampleAfterValue": "100003", 1795ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 1796ecd94f1bSKan Liang }, 1797ecd94f1bSKan Liang { 1798ecd94f1bSKan Liang "Offcore": "1", 1799ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 1800ecd94f1bSKan Liang "UMask": "0x1", 1801ecd94f1bSKan Liang "BriefDescription": "Counts all demand code reads TBD TBD", 1802ecd94f1bSKan Liang "MSRValue": "0x3F803C0004", 1803ecd94f1bSKan Liang "Counter": "0,1,2,3", 1804ecd94f1bSKan Liang "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.ANY_SNOOP", 1805ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 1806ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1807ecd94f1bSKan Liang "SampleAfterValue": "100003", 1808ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 1809ecd94f1bSKan Liang }, 1810ecd94f1bSKan Liang { 1811ecd94f1bSKan Liang "Offcore": "1", 1812ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 1813ecd94f1bSKan Liang "UMask": "0x1", 1814ecd94f1bSKan Liang "BriefDescription": "Counts prefetch (that bring data to L2) data reads", 1815ecd94f1bSKan Liang "MSRValue": "0x0080020010", 1816ecd94f1bSKan Liang "Counter": "0,1,2,3", 1817ecd94f1bSKan Liang "EventName": "OCR.PF_L2_DATA_RD.SUPPLIER_NONE.SNOOP_NONE", 1818ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 1819ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1820ecd94f1bSKan Liang "SampleAfterValue": "100003", 1821ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 1822ecd94f1bSKan Liang }, 1823ecd94f1bSKan Liang { 1824ecd94f1bSKan Liang "Offcore": "1", 1825ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 1826ecd94f1bSKan Liang "UMask": "0x1", 1827ecd94f1bSKan Liang "BriefDescription": "Counts prefetch (that bring data to L2) data reads TBD", 1828ecd94f1bSKan Liang "MSRValue": "0x0100020010", 1829ecd94f1bSKan Liang "Counter": "0,1,2,3", 1830ecd94f1bSKan Liang "EventName": "OCR.PF_L2_DATA_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED", 1831ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 1832ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1833ecd94f1bSKan Liang "SampleAfterValue": "100003", 1834ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 1835ecd94f1bSKan Liang }, 1836ecd94f1bSKan Liang { 1837ecd94f1bSKan Liang "Offcore": "1", 1838ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 1839ecd94f1bSKan Liang "UMask": "0x1", 1840ecd94f1bSKan Liang "BriefDescription": "Counts prefetch (that bring data to L2) data reads", 1841ecd94f1bSKan Liang "MSRValue": "0x0200020010", 1842ecd94f1bSKan Liang "Counter": "0,1,2,3", 1843ecd94f1bSKan Liang "EventName": "OCR.PF_L2_DATA_RD.SUPPLIER_NONE.SNOOP_MISS", 1844ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 1845ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1846ecd94f1bSKan Liang "SampleAfterValue": "100003", 1847ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 1848ecd94f1bSKan Liang }, 1849ecd94f1bSKan Liang { 1850ecd94f1bSKan Liang "Offcore": "1", 1851ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 1852ecd94f1bSKan Liang "UMask": "0x1", 1853ecd94f1bSKan Liang "BriefDescription": "Counts prefetch (that bring data to L2) data reads TBD", 1854ecd94f1bSKan Liang "MSRValue": "0x0400020010", 1855ecd94f1bSKan Liang "Counter": "0,1,2,3", 1856ecd94f1bSKan Liang "EventName": "OCR.PF_L2_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", 1857ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 1858ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1859ecd94f1bSKan Liang "SampleAfterValue": "100003", 1860ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 1861ecd94f1bSKan Liang }, 1862ecd94f1bSKan Liang { 1863ecd94f1bSKan Liang "Offcore": "1", 1864ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 1865ecd94f1bSKan Liang "UMask": "0x1", 1866ecd94f1bSKan Liang "BriefDescription": "Counts prefetch (that bring data to L2) data reads TBD", 1867ecd94f1bSKan Liang "MSRValue": "0x0800020010", 1868ecd94f1bSKan Liang "Counter": "0,1,2,3", 1869ecd94f1bSKan Liang "EventName": "OCR.PF_L2_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", 1870ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 1871ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1872ecd94f1bSKan Liang "SampleAfterValue": "100003", 1873ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 1874ecd94f1bSKan Liang }, 1875ecd94f1bSKan Liang { 1876ecd94f1bSKan Liang "Offcore": "1", 1877ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 1878ecd94f1bSKan Liang "UMask": "0x1", 1879ecd94f1bSKan Liang "BriefDescription": "Counts prefetch (that bring data to L2) data reads TBD", 1880ecd94f1bSKan Liang "MSRValue": "0x1000020010", 1881ecd94f1bSKan Liang "Counter": "0,1,2,3", 1882ecd94f1bSKan Liang "EventName": "OCR.PF_L2_DATA_RD.SUPPLIER_NONE.HITM_OTHER_CORE", 1883ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 1884ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1885ecd94f1bSKan Liang "SampleAfterValue": "100003", 1886ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 1887ecd94f1bSKan Liang }, 1888ecd94f1bSKan Liang { 1889ecd94f1bSKan Liang "Offcore": "1", 1890ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 1891ecd94f1bSKan Liang "UMask": "0x1", 1892ecd94f1bSKan Liang "BriefDescription": "Counts prefetch (that bring data to L2) data reads TBD", 1893ecd94f1bSKan Liang "MSRValue": "0x3F80020010", 1894ecd94f1bSKan Liang "Counter": "0,1,2,3", 1895ecd94f1bSKan Liang "EventName": "OCR.PF_L2_DATA_RD.SUPPLIER_NONE.ANY_SNOOP", 1896ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 1897ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1898ecd94f1bSKan Liang "SampleAfterValue": "100003", 1899ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 1900ecd94f1bSKan Liang }, 1901ecd94f1bSKan Liang { 1902ecd94f1bSKan Liang "Offcore": "1", 1903ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 1904ecd94f1bSKan Liang "UMask": "0x1", 1905ecd94f1bSKan Liang "BriefDescription": "Counts prefetch (that bring data to L2) data reads", 1906ecd94f1bSKan Liang "MSRValue": "0x0080040010", 1907ecd94f1bSKan Liang "Counter": "0,1,2,3", 1908ecd94f1bSKan Liang "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_M.SNOOP_NONE", 1909ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 1910ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1911ecd94f1bSKan Liang "SampleAfterValue": "100003", 1912ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 1913ecd94f1bSKan Liang }, 1914ecd94f1bSKan Liang { 1915ecd94f1bSKan Liang "Offcore": "1", 1916ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 1917ecd94f1bSKan Liang "UMask": "0x1", 1918ecd94f1bSKan Liang "BriefDescription": "Counts prefetch (that bring data to L2) data reads TBD", 1919ecd94f1bSKan Liang "MSRValue": "0x0100040010", 1920ecd94f1bSKan Liang "Counter": "0,1,2,3", 1921ecd94f1bSKan Liang "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDED", 1922ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 1923ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1924ecd94f1bSKan Liang "SampleAfterValue": "100003", 1925ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 1926ecd94f1bSKan Liang }, 1927ecd94f1bSKan Liang { 1928ecd94f1bSKan Liang "Offcore": "1", 1929ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 1930ecd94f1bSKan Liang "UMask": "0x1", 1931ecd94f1bSKan Liang "BriefDescription": "Counts prefetch (that bring data to L2) data reads", 1932ecd94f1bSKan Liang "MSRValue": "0x0200040010", 1933ecd94f1bSKan Liang "Counter": "0,1,2,3", 1934ecd94f1bSKan Liang "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_M.SNOOP_MISS", 1935ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 1936ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1937ecd94f1bSKan Liang "SampleAfterValue": "100003", 1938ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 1939ecd94f1bSKan Liang }, 1940ecd94f1bSKan Liang { 1941ecd94f1bSKan Liang "Offcore": "1", 1942ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 1943ecd94f1bSKan Liang "UMask": "0x1", 1944ecd94f1bSKan Liang "BriefDescription": "Counts prefetch (that bring data to L2) data reads TBD", 1945ecd94f1bSKan Liang "MSRValue": "0x0400040010", 1946ecd94f1bSKan Liang "Counter": "0,1,2,3", 1947ecd94f1bSKan Liang "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", 1948ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 1949ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1950ecd94f1bSKan Liang "SampleAfterValue": "100003", 1951ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 1952ecd94f1bSKan Liang }, 1953ecd94f1bSKan Liang { 1954ecd94f1bSKan Liang "Offcore": "1", 1955ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 1956ecd94f1bSKan Liang "UMask": "0x1", 1957ecd94f1bSKan Liang "BriefDescription": "Counts prefetch (that bring data to L2) data reads TBD", 1958ecd94f1bSKan Liang "MSRValue": "0x0800040010", 1959ecd94f1bSKan Liang "Counter": "0,1,2,3", 1960ecd94f1bSKan Liang "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWD", 1961ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 1962ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1963ecd94f1bSKan Liang "SampleAfterValue": "100003", 1964ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 1965ecd94f1bSKan Liang }, 1966ecd94f1bSKan Liang { 1967ecd94f1bSKan Liang "Offcore": "1", 1968ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 1969ecd94f1bSKan Liang "UMask": "0x1", 1970ecd94f1bSKan Liang "BriefDescription": "Counts prefetch (that bring data to L2) data reads TBD", 1971ecd94f1bSKan Liang "MSRValue": "0x1000040010", 1972ecd94f1bSKan Liang "Counter": "0,1,2,3", 1973ecd94f1bSKan Liang "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_M.HITM_OTHER_CORE", 1974ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 1975ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1976ecd94f1bSKan Liang "SampleAfterValue": "100003", 1977ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 1978ecd94f1bSKan Liang }, 1979ecd94f1bSKan Liang { 1980ecd94f1bSKan Liang "Offcore": "1", 1981ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 1982ecd94f1bSKan Liang "UMask": "0x1", 1983ecd94f1bSKan Liang "BriefDescription": "Counts prefetch (that bring data to L2) data reads TBD", 1984ecd94f1bSKan Liang "MSRValue": "0x3F80040010", 1985ecd94f1bSKan Liang "Counter": "0,1,2,3", 1986ecd94f1bSKan Liang "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_M.ANY_SNOOP", 1987ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 1988ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1989ecd94f1bSKan Liang "SampleAfterValue": "100003", 1990ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 1991ecd94f1bSKan Liang }, 1992ecd94f1bSKan Liang { 1993ecd94f1bSKan Liang "Offcore": "1", 1994ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 1995ecd94f1bSKan Liang "UMask": "0x1", 1996ecd94f1bSKan Liang "BriefDescription": "Counts prefetch (that bring data to L2) data reads", 1997ecd94f1bSKan Liang "MSRValue": "0x0080080010", 1998ecd94f1bSKan Liang "Counter": "0,1,2,3", 1999ecd94f1bSKan Liang "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_E.SNOOP_NONE", 2000ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 2001ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2002ecd94f1bSKan Liang "SampleAfterValue": "100003", 2003ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 2004ecd94f1bSKan Liang }, 2005ecd94f1bSKan Liang { 2006ecd94f1bSKan Liang "Offcore": "1", 2007ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 2008ecd94f1bSKan Liang "UMask": "0x1", 2009ecd94f1bSKan Liang "BriefDescription": "Counts prefetch (that bring data to L2) data reads TBD", 2010ecd94f1bSKan Liang "MSRValue": "0x0100080010", 2011ecd94f1bSKan Liang "Counter": "0,1,2,3", 2012ecd94f1bSKan Liang "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDED", 2013ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 2014ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2015ecd94f1bSKan Liang "SampleAfterValue": "100003", 2016ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 2017ecd94f1bSKan Liang }, 2018ecd94f1bSKan Liang { 2019ecd94f1bSKan Liang "Offcore": "1", 2020ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 2021ecd94f1bSKan Liang "UMask": "0x1", 2022ecd94f1bSKan Liang "BriefDescription": "Counts prefetch (that bring data to L2) data reads", 2023ecd94f1bSKan Liang "MSRValue": "0x0200080010", 2024ecd94f1bSKan Liang "Counter": "0,1,2,3", 2025ecd94f1bSKan Liang "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_E.SNOOP_MISS", 2026ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 2027ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2028ecd94f1bSKan Liang "SampleAfterValue": "100003", 2029ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 2030ecd94f1bSKan Liang }, 2031ecd94f1bSKan Liang { 2032ecd94f1bSKan Liang "Offcore": "1", 2033ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 2034ecd94f1bSKan Liang "UMask": "0x1", 2035ecd94f1bSKan Liang "BriefDescription": "Counts prefetch (that bring data to L2) data reads TBD", 2036ecd94f1bSKan Liang "MSRValue": "0x0400080010", 2037ecd94f1bSKan Liang "Counter": "0,1,2,3", 2038ecd94f1bSKan Liang "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", 2039ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 2040ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2041ecd94f1bSKan Liang "SampleAfterValue": "100003", 2042ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 2043ecd94f1bSKan Liang }, 2044ecd94f1bSKan Liang { 2045ecd94f1bSKan Liang "Offcore": "1", 2046ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 2047ecd94f1bSKan Liang "UMask": "0x1", 2048ecd94f1bSKan Liang "BriefDescription": "Counts prefetch (that bring data to L2) data reads TBD", 2049ecd94f1bSKan Liang "MSRValue": "0x0800080010", 2050ecd94f1bSKan Liang "Counter": "0,1,2,3", 2051ecd94f1bSKan Liang "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWD", 2052ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 2053ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2054ecd94f1bSKan Liang "SampleAfterValue": "100003", 2055ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 2056ecd94f1bSKan Liang }, 2057ecd94f1bSKan Liang { 2058ecd94f1bSKan Liang "Offcore": "1", 2059ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 2060ecd94f1bSKan Liang "UMask": "0x1", 2061ecd94f1bSKan Liang "BriefDescription": "Counts prefetch (that bring data to L2) data reads TBD", 2062ecd94f1bSKan Liang "MSRValue": "0x1000080010", 2063ecd94f1bSKan Liang "Counter": "0,1,2,3", 2064ecd94f1bSKan Liang "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_E.HITM_OTHER_CORE", 2065ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 2066ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2067ecd94f1bSKan Liang "SampleAfterValue": "100003", 2068ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 2069ecd94f1bSKan Liang }, 2070ecd94f1bSKan Liang { 2071ecd94f1bSKan Liang "Offcore": "1", 2072ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 2073ecd94f1bSKan Liang "UMask": "0x1", 2074ecd94f1bSKan Liang "BriefDescription": "Counts prefetch (that bring data to L2) data reads TBD", 2075ecd94f1bSKan Liang "MSRValue": "0x3F80080010", 2076ecd94f1bSKan Liang "Counter": "0,1,2,3", 2077ecd94f1bSKan Liang "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_E.ANY_SNOOP", 2078ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 2079ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2080ecd94f1bSKan Liang "SampleAfterValue": "100003", 2081ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 2082ecd94f1bSKan Liang }, 2083ecd94f1bSKan Liang { 2084ecd94f1bSKan Liang "Offcore": "1", 2085ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 2086ecd94f1bSKan Liang "UMask": "0x1", 2087ecd94f1bSKan Liang "BriefDescription": "Counts prefetch (that bring data to L2) data reads", 2088ecd94f1bSKan Liang "MSRValue": "0x0080100010", 2089ecd94f1bSKan Liang "Counter": "0,1,2,3", 2090ecd94f1bSKan Liang "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_S.SNOOP_NONE", 2091ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 2092ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2093ecd94f1bSKan Liang "SampleAfterValue": "100003", 2094ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 2095ecd94f1bSKan Liang }, 2096ecd94f1bSKan Liang { 2097ecd94f1bSKan Liang "Offcore": "1", 2098ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 2099ecd94f1bSKan Liang "UMask": "0x1", 2100ecd94f1bSKan Liang "BriefDescription": "Counts prefetch (that bring data to L2) data reads TBD", 2101ecd94f1bSKan Liang "MSRValue": "0x0100100010", 2102ecd94f1bSKan Liang "Counter": "0,1,2,3", 2103ecd94f1bSKan Liang "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDED", 2104ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 2105ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2106ecd94f1bSKan Liang "SampleAfterValue": "100003", 2107ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 2108ecd94f1bSKan Liang }, 2109ecd94f1bSKan Liang { 2110ecd94f1bSKan Liang "Offcore": "1", 2111ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 2112ecd94f1bSKan Liang "UMask": "0x1", 2113ecd94f1bSKan Liang "BriefDescription": "Counts prefetch (that bring data to L2) data reads", 2114ecd94f1bSKan Liang "MSRValue": "0x0200100010", 2115ecd94f1bSKan Liang "Counter": "0,1,2,3", 2116ecd94f1bSKan Liang "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_S.SNOOP_MISS", 2117ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 2118ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2119ecd94f1bSKan Liang "SampleAfterValue": "100003", 2120ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 2121ecd94f1bSKan Liang }, 2122ecd94f1bSKan Liang { 2123ecd94f1bSKan Liang "Offcore": "1", 2124ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 2125ecd94f1bSKan Liang "UMask": "0x1", 2126ecd94f1bSKan Liang "BriefDescription": "Counts prefetch (that bring data to L2) data reads TBD", 2127ecd94f1bSKan Liang "MSRValue": "0x0400100010", 2128ecd94f1bSKan Liang "Counter": "0,1,2,3", 2129ecd94f1bSKan Liang "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", 2130ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 2131ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2132ecd94f1bSKan Liang "SampleAfterValue": "100003", 2133ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 2134ecd94f1bSKan Liang }, 2135ecd94f1bSKan Liang { 2136ecd94f1bSKan Liang "Offcore": "1", 2137ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 2138ecd94f1bSKan Liang "UMask": "0x1", 2139ecd94f1bSKan Liang "BriefDescription": "Counts prefetch (that bring data to L2) data reads TBD", 2140ecd94f1bSKan Liang "MSRValue": "0x0800100010", 2141ecd94f1bSKan Liang "Counter": "0,1,2,3", 2142ecd94f1bSKan Liang "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWD", 2143ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 2144ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2145ecd94f1bSKan Liang "SampleAfterValue": "100003", 2146ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 2147ecd94f1bSKan Liang }, 2148ecd94f1bSKan Liang { 2149ecd94f1bSKan Liang "Offcore": "1", 2150ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 2151ecd94f1bSKan Liang "UMask": "0x1", 2152ecd94f1bSKan Liang "BriefDescription": "Counts prefetch (that bring data to L2) data reads TBD", 2153ecd94f1bSKan Liang "MSRValue": "0x1000100010", 2154ecd94f1bSKan Liang "Counter": "0,1,2,3", 2155ecd94f1bSKan Liang "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_S.HITM_OTHER_CORE", 2156ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 2157ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2158ecd94f1bSKan Liang "SampleAfterValue": "100003", 2159ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 2160ecd94f1bSKan Liang }, 2161ecd94f1bSKan Liang { 2162ecd94f1bSKan Liang "Offcore": "1", 2163ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 2164ecd94f1bSKan Liang "UMask": "0x1", 2165ecd94f1bSKan Liang "BriefDescription": "Counts prefetch (that bring data to L2) data reads TBD", 2166ecd94f1bSKan Liang "MSRValue": "0x3F80100010", 2167ecd94f1bSKan Liang "Counter": "0,1,2,3", 2168ecd94f1bSKan Liang "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_S.ANY_SNOOP", 2169ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 2170ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2171ecd94f1bSKan Liang "SampleAfterValue": "100003", 2172ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 2173ecd94f1bSKan Liang }, 2174ecd94f1bSKan Liang { 2175ecd94f1bSKan Liang "Offcore": "1", 2176ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 2177ecd94f1bSKan Liang "UMask": "0x1", 2178ecd94f1bSKan Liang "BriefDescription": "Counts prefetch (that bring data to L2) data reads", 2179ecd94f1bSKan Liang "MSRValue": "0x0080200010", 2180ecd94f1bSKan Liang "Counter": "0,1,2,3", 2181ecd94f1bSKan Liang "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_F.SNOOP_NONE", 2182ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 2183ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2184ecd94f1bSKan Liang "SampleAfterValue": "100003", 2185ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 2186ecd94f1bSKan Liang }, 2187ecd94f1bSKan Liang { 2188ecd94f1bSKan Liang "Offcore": "1", 2189ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 2190ecd94f1bSKan Liang "UMask": "0x1", 2191ecd94f1bSKan Liang "BriefDescription": "Counts prefetch (that bring data to L2) data reads TBD", 2192ecd94f1bSKan Liang "MSRValue": "0x0100200010", 2193ecd94f1bSKan Liang "Counter": "0,1,2,3", 2194ecd94f1bSKan Liang "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDED", 2195ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 2196ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2197ecd94f1bSKan Liang "SampleAfterValue": "100003", 2198ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 2199ecd94f1bSKan Liang }, 2200ecd94f1bSKan Liang { 2201ecd94f1bSKan Liang "Offcore": "1", 2202ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 2203ecd94f1bSKan Liang "UMask": "0x1", 2204ecd94f1bSKan Liang "BriefDescription": "Counts prefetch (that bring data to L2) data reads", 2205ecd94f1bSKan Liang "MSRValue": "0x0200200010", 2206ecd94f1bSKan Liang "Counter": "0,1,2,3", 2207ecd94f1bSKan Liang "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_F.SNOOP_MISS", 2208ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 2209ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2210ecd94f1bSKan Liang "SampleAfterValue": "100003", 2211ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 2212ecd94f1bSKan Liang }, 2213ecd94f1bSKan Liang { 2214ecd94f1bSKan Liang "Offcore": "1", 2215ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 2216ecd94f1bSKan Liang "UMask": "0x1", 2217ecd94f1bSKan Liang "BriefDescription": "Counts prefetch (that bring data to L2) data reads TBD", 2218ecd94f1bSKan Liang "MSRValue": "0x0400200010", 2219ecd94f1bSKan Liang "Counter": "0,1,2,3", 2220ecd94f1bSKan Liang "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", 2221ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 2222ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2223ecd94f1bSKan Liang "SampleAfterValue": "100003", 2224ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 2225ecd94f1bSKan Liang }, 2226ecd94f1bSKan Liang { 2227ecd94f1bSKan Liang "Offcore": "1", 2228ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 2229ecd94f1bSKan Liang "UMask": "0x1", 2230ecd94f1bSKan Liang "BriefDescription": "Counts prefetch (that bring data to L2) data reads TBD", 2231ecd94f1bSKan Liang "MSRValue": "0x0800200010", 2232ecd94f1bSKan Liang "Counter": "0,1,2,3", 2233ecd94f1bSKan Liang "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWD", 2234ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 2235ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2236ecd94f1bSKan Liang "SampleAfterValue": "100003", 2237ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 2238ecd94f1bSKan Liang }, 2239ecd94f1bSKan Liang { 2240ecd94f1bSKan Liang "Offcore": "1", 2241ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 2242ecd94f1bSKan Liang "UMask": "0x1", 2243ecd94f1bSKan Liang "BriefDescription": "Counts prefetch (that bring data to L2) data reads TBD", 2244ecd94f1bSKan Liang "MSRValue": "0x1000200010", 2245ecd94f1bSKan Liang "Counter": "0,1,2,3", 2246ecd94f1bSKan Liang "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_F.HITM_OTHER_CORE", 2247ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 2248ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2249ecd94f1bSKan Liang "SampleAfterValue": "100003", 2250ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 2251ecd94f1bSKan Liang }, 2252ecd94f1bSKan Liang { 2253ecd94f1bSKan Liang "Offcore": "1", 2254ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 2255ecd94f1bSKan Liang "UMask": "0x1", 2256ecd94f1bSKan Liang "BriefDescription": "Counts prefetch (that bring data to L2) data reads TBD", 2257ecd94f1bSKan Liang "MSRValue": "0x3F80200010", 2258ecd94f1bSKan Liang "Counter": "0,1,2,3", 2259ecd94f1bSKan Liang "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_F.ANY_SNOOP", 2260ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 2261ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2262ecd94f1bSKan Liang "SampleAfterValue": "100003", 2263ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 2264ecd94f1bSKan Liang }, 2265ecd94f1bSKan Liang { 2266ecd94f1bSKan Liang "Offcore": "1", 2267ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 2268ecd94f1bSKan Liang "UMask": "0x1", 2269ecd94f1bSKan Liang "BriefDescription": "Counts prefetch (that bring data to L2) data reads TBD", 2270ecd94f1bSKan Liang "MSRValue": "0x00803C0010", 2271ecd94f1bSKan Liang "Counter": "0,1,2,3", 2272ecd94f1bSKan Liang "EventName": "OCR.PF_L2_DATA_RD.L3_HIT.SNOOP_NONE", 2273ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 2274ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2275ecd94f1bSKan Liang "SampleAfterValue": "100003", 2276ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 2277ecd94f1bSKan Liang }, 2278ecd94f1bSKan Liang { 2279ecd94f1bSKan Liang "Offcore": "1", 2280ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 2281ecd94f1bSKan Liang "UMask": "0x1", 2282ecd94f1bSKan Liang "BriefDescription": "Counts prefetch (that bring data to L2) data reads TBD TBD", 2283ecd94f1bSKan Liang "MSRValue": "0x01003C0010", 2284ecd94f1bSKan Liang "Counter": "0,1,2,3", 2285ecd94f1bSKan Liang "EventName": "OCR.PF_L2_DATA_RD.L3_HIT.NO_SNOOP_NEEDED", 2286ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 2287ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2288ecd94f1bSKan Liang "SampleAfterValue": "100003", 2289ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 2290ecd94f1bSKan Liang }, 2291ecd94f1bSKan Liang { 2292ecd94f1bSKan Liang "Offcore": "1", 2293ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 2294ecd94f1bSKan Liang "UMask": "0x1", 2295ecd94f1bSKan Liang "BriefDescription": "Counts prefetch (that bring data to L2) data reads TBD", 2296ecd94f1bSKan Liang "MSRValue": "0x02003C0010", 2297ecd94f1bSKan Liang "Counter": "0,1,2,3", 2298ecd94f1bSKan Liang "EventName": "OCR.PF_L2_DATA_RD.L3_HIT.SNOOP_MISS", 2299ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 2300ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2301ecd94f1bSKan Liang "SampleAfterValue": "100003", 2302ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 2303ecd94f1bSKan Liang }, 2304ecd94f1bSKan Liang { 2305ecd94f1bSKan Liang "Offcore": "1", 2306ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 2307ecd94f1bSKan Liang "UMask": "0x1", 2308ecd94f1bSKan Liang "BriefDescription": "Counts prefetch (that bring data to L2) data reads TBD TBD", 2309ecd94f1bSKan Liang "MSRValue": "0x04003C0010", 2310ecd94f1bSKan Liang "Counter": "0,1,2,3", 2311ecd94f1bSKan Liang "EventName": "OCR.PF_L2_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD", 2312ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 2313ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2314ecd94f1bSKan Liang "SampleAfterValue": "100003", 2315ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 2316ecd94f1bSKan Liang }, 2317ecd94f1bSKan Liang { 2318ecd94f1bSKan Liang "Offcore": "1", 2319ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 2320ecd94f1bSKan Liang "UMask": "0x1", 2321ecd94f1bSKan Liang "BriefDescription": "Counts prefetch (that bring data to L2) data reads TBD TBD", 2322ecd94f1bSKan Liang "MSRValue": "0x08003C0010", 2323ecd94f1bSKan Liang "Counter": "0,1,2,3", 2324ecd94f1bSKan Liang "EventName": "OCR.PF_L2_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD", 2325ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 2326ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2327ecd94f1bSKan Liang "SampleAfterValue": "100003", 2328ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 2329ecd94f1bSKan Liang }, 2330ecd94f1bSKan Liang { 2331ecd94f1bSKan Liang "Offcore": "1", 2332ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 2333ecd94f1bSKan Liang "UMask": "0x1", 2334ecd94f1bSKan Liang "BriefDescription": "Counts prefetch (that bring data to L2) data reads TBD TBD", 2335ecd94f1bSKan Liang "MSRValue": "0x10003C0010", 2336ecd94f1bSKan Liang "Counter": "0,1,2,3", 2337ecd94f1bSKan Liang "EventName": "OCR.PF_L2_DATA_RD.L3_HIT.HITM_OTHER_CORE", 2338ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 2339ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2340ecd94f1bSKan Liang "SampleAfterValue": "100003", 2341ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 2342ecd94f1bSKan Liang }, 2343ecd94f1bSKan Liang { 2344ecd94f1bSKan Liang "Offcore": "1", 2345ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 2346ecd94f1bSKan Liang "UMask": "0x1", 2347ecd94f1bSKan Liang "BriefDescription": "Counts prefetch (that bring data to L2) data reads TBD TBD", 2348ecd94f1bSKan Liang "MSRValue": "0x3F803C0010", 2349ecd94f1bSKan Liang "Counter": "0,1,2,3", 2350ecd94f1bSKan Liang "EventName": "OCR.PF_L2_DATA_RD.L3_HIT.ANY_SNOOP", 2351ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 2352ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2353ecd94f1bSKan Liang "SampleAfterValue": "100003", 2354ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 2355ecd94f1bSKan Liang }, 2356ecd94f1bSKan Liang { 2357ecd94f1bSKan Liang "Offcore": "1", 2358ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 2359ecd94f1bSKan Liang "UMask": "0x1", 2360ecd94f1bSKan Liang "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs", 2361ecd94f1bSKan Liang "MSRValue": "0x0080020020", 2362ecd94f1bSKan Liang "Counter": "0,1,2,3", 2363ecd94f1bSKan Liang "EventName": "OCR.PF_L2_RFO.SUPPLIER_NONE.SNOOP_NONE", 2364ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 2365ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2366ecd94f1bSKan Liang "SampleAfterValue": "100003", 2367ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 2368ecd94f1bSKan Liang }, 2369ecd94f1bSKan Liang { 2370ecd94f1bSKan Liang "Offcore": "1", 2371ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 2372ecd94f1bSKan Liang "UMask": "0x1", 2373ecd94f1bSKan Liang "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs TBD", 2374ecd94f1bSKan Liang "MSRValue": "0x0100020020", 2375ecd94f1bSKan Liang "Counter": "0,1,2,3", 2376ecd94f1bSKan Liang "EventName": "OCR.PF_L2_RFO.SUPPLIER_NONE.NO_SNOOP_NEEDED", 2377ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 2378ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2379ecd94f1bSKan Liang "SampleAfterValue": "100003", 2380ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 2381ecd94f1bSKan Liang }, 2382ecd94f1bSKan Liang { 2383ecd94f1bSKan Liang "Offcore": "1", 2384ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 2385ecd94f1bSKan Liang "UMask": "0x1", 2386ecd94f1bSKan Liang "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs", 2387ecd94f1bSKan Liang "MSRValue": "0x0200020020", 2388ecd94f1bSKan Liang "Counter": "0,1,2,3", 2389ecd94f1bSKan Liang "EventName": "OCR.PF_L2_RFO.SUPPLIER_NONE.SNOOP_MISS", 2390ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 2391ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2392ecd94f1bSKan Liang "SampleAfterValue": "100003", 2393ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 2394ecd94f1bSKan Liang }, 2395ecd94f1bSKan Liang { 2396ecd94f1bSKan Liang "Offcore": "1", 2397ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 2398ecd94f1bSKan Liang "UMask": "0x1", 2399ecd94f1bSKan Liang "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs TBD", 2400ecd94f1bSKan Liang "MSRValue": "0x0400020020", 2401ecd94f1bSKan Liang "Counter": "0,1,2,3", 2402ecd94f1bSKan Liang "EventName": "OCR.PF_L2_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", 2403ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 2404ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2405ecd94f1bSKan Liang "SampleAfterValue": "100003", 2406ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 2407ecd94f1bSKan Liang }, 2408ecd94f1bSKan Liang { 2409ecd94f1bSKan Liang "Offcore": "1", 2410ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 2411ecd94f1bSKan Liang "UMask": "0x1", 2412ecd94f1bSKan Liang "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs TBD", 2413ecd94f1bSKan Liang "MSRValue": "0x0800020020", 2414ecd94f1bSKan Liang "Counter": "0,1,2,3", 2415ecd94f1bSKan Liang "EventName": "OCR.PF_L2_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", 2416ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 2417ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2418ecd94f1bSKan Liang "SampleAfterValue": "100003", 2419ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 2420ecd94f1bSKan Liang }, 2421ecd94f1bSKan Liang { 2422ecd94f1bSKan Liang "Offcore": "1", 2423ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 2424ecd94f1bSKan Liang "UMask": "0x1", 2425ecd94f1bSKan Liang "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs TBD", 2426ecd94f1bSKan Liang "MSRValue": "0x1000020020", 2427ecd94f1bSKan Liang "Counter": "0,1,2,3", 2428ecd94f1bSKan Liang "EventName": "OCR.PF_L2_RFO.SUPPLIER_NONE.HITM_OTHER_CORE", 2429ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 2430ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2431ecd94f1bSKan Liang "SampleAfterValue": "100003", 2432ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 2433ecd94f1bSKan Liang }, 2434ecd94f1bSKan Liang { 2435ecd94f1bSKan Liang "Offcore": "1", 2436ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 2437ecd94f1bSKan Liang "UMask": "0x1", 2438ecd94f1bSKan Liang "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs TBD", 2439ecd94f1bSKan Liang "MSRValue": "0x3F80020020", 2440ecd94f1bSKan Liang "Counter": "0,1,2,3", 2441ecd94f1bSKan Liang "EventName": "OCR.PF_L2_RFO.SUPPLIER_NONE.ANY_SNOOP", 2442ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 2443ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2444ecd94f1bSKan Liang "SampleAfterValue": "100003", 2445ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 2446ecd94f1bSKan Liang }, 2447ecd94f1bSKan Liang { 2448ecd94f1bSKan Liang "Offcore": "1", 2449ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 2450ecd94f1bSKan Liang "UMask": "0x1", 2451ecd94f1bSKan Liang "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs", 2452ecd94f1bSKan Liang "MSRValue": "0x0080040020", 2453ecd94f1bSKan Liang "Counter": "0,1,2,3", 2454ecd94f1bSKan Liang "EventName": "OCR.PF_L2_RFO.L3_HIT_M.SNOOP_NONE", 2455ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 2456ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2457ecd94f1bSKan Liang "SampleAfterValue": "100003", 2458ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 2459ecd94f1bSKan Liang }, 2460ecd94f1bSKan Liang { 2461ecd94f1bSKan Liang "Offcore": "1", 2462ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 2463ecd94f1bSKan Liang "UMask": "0x1", 2464ecd94f1bSKan Liang "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs TBD", 2465ecd94f1bSKan Liang "MSRValue": "0x0100040020", 2466ecd94f1bSKan Liang "Counter": "0,1,2,3", 2467ecd94f1bSKan Liang "EventName": "OCR.PF_L2_RFO.L3_HIT_M.NO_SNOOP_NEEDED", 2468ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 2469ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2470ecd94f1bSKan Liang "SampleAfterValue": "100003", 2471ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 2472ecd94f1bSKan Liang }, 2473ecd94f1bSKan Liang { 2474ecd94f1bSKan Liang "Offcore": "1", 2475ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 2476ecd94f1bSKan Liang "UMask": "0x1", 2477ecd94f1bSKan Liang "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs", 2478ecd94f1bSKan Liang "MSRValue": "0x0200040020", 2479ecd94f1bSKan Liang "Counter": "0,1,2,3", 2480ecd94f1bSKan Liang "EventName": "OCR.PF_L2_RFO.L3_HIT_M.SNOOP_MISS", 2481ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 2482ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2483ecd94f1bSKan Liang "SampleAfterValue": "100003", 2484ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 2485ecd94f1bSKan Liang }, 2486ecd94f1bSKan Liang { 2487ecd94f1bSKan Liang "Offcore": "1", 2488ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 2489ecd94f1bSKan Liang "UMask": "0x1", 2490ecd94f1bSKan Liang "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs TBD", 2491ecd94f1bSKan Liang "MSRValue": "0x0400040020", 2492ecd94f1bSKan Liang "Counter": "0,1,2,3", 2493ecd94f1bSKan Liang "EventName": "OCR.PF_L2_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", 2494ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 2495ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2496ecd94f1bSKan Liang "SampleAfterValue": "100003", 2497ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 2498ecd94f1bSKan Liang }, 2499ecd94f1bSKan Liang { 2500ecd94f1bSKan Liang "Offcore": "1", 2501ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 2502ecd94f1bSKan Liang "UMask": "0x1", 2503ecd94f1bSKan Liang "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs TBD", 2504ecd94f1bSKan Liang "MSRValue": "0x0800040020", 2505ecd94f1bSKan Liang "Counter": "0,1,2,3", 2506ecd94f1bSKan Liang "EventName": "OCR.PF_L2_RFO.L3_HIT_M.HIT_OTHER_CORE_FWD", 2507ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 2508ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2509ecd94f1bSKan Liang "SampleAfterValue": "100003", 2510ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 2511ecd94f1bSKan Liang }, 2512ecd94f1bSKan Liang { 2513ecd94f1bSKan Liang "Offcore": "1", 2514ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 2515ecd94f1bSKan Liang "UMask": "0x1", 2516ecd94f1bSKan Liang "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs TBD", 2517ecd94f1bSKan Liang "MSRValue": "0x1000040020", 2518ecd94f1bSKan Liang "Counter": "0,1,2,3", 2519ecd94f1bSKan Liang "EventName": "OCR.PF_L2_RFO.L3_HIT_M.HITM_OTHER_CORE", 2520ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 2521ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2522ecd94f1bSKan Liang "SampleAfterValue": "100003", 2523ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 2524ecd94f1bSKan Liang }, 2525ecd94f1bSKan Liang { 2526ecd94f1bSKan Liang "Offcore": "1", 2527ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 2528ecd94f1bSKan Liang "UMask": "0x1", 2529ecd94f1bSKan Liang "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs TBD", 2530ecd94f1bSKan Liang "MSRValue": "0x3F80040020", 2531ecd94f1bSKan Liang "Counter": "0,1,2,3", 2532ecd94f1bSKan Liang "EventName": "OCR.PF_L2_RFO.L3_HIT_M.ANY_SNOOP", 2533ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 2534ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2535ecd94f1bSKan Liang "SampleAfterValue": "100003", 2536ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 2537ecd94f1bSKan Liang }, 2538ecd94f1bSKan Liang { 2539ecd94f1bSKan Liang "Offcore": "1", 2540ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 2541ecd94f1bSKan Liang "UMask": "0x1", 2542ecd94f1bSKan Liang "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs", 2543ecd94f1bSKan Liang "MSRValue": "0x0080080020", 2544ecd94f1bSKan Liang "Counter": "0,1,2,3", 2545ecd94f1bSKan Liang "EventName": "OCR.PF_L2_RFO.L3_HIT_E.SNOOP_NONE", 2546ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 2547ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2548ecd94f1bSKan Liang "SampleAfterValue": "100003", 2549ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 2550ecd94f1bSKan Liang }, 2551ecd94f1bSKan Liang { 2552ecd94f1bSKan Liang "Offcore": "1", 2553ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 2554ecd94f1bSKan Liang "UMask": "0x1", 2555ecd94f1bSKan Liang "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs TBD", 2556ecd94f1bSKan Liang "MSRValue": "0x0100080020", 2557ecd94f1bSKan Liang "Counter": "0,1,2,3", 2558ecd94f1bSKan Liang "EventName": "OCR.PF_L2_RFO.L3_HIT_E.NO_SNOOP_NEEDED", 2559ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 2560ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2561ecd94f1bSKan Liang "SampleAfterValue": "100003", 2562ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 2563ecd94f1bSKan Liang }, 2564ecd94f1bSKan Liang { 2565ecd94f1bSKan Liang "Offcore": "1", 2566ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 2567ecd94f1bSKan Liang "UMask": "0x1", 2568ecd94f1bSKan Liang "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs", 2569ecd94f1bSKan Liang "MSRValue": "0x0200080020", 2570ecd94f1bSKan Liang "Counter": "0,1,2,3", 2571ecd94f1bSKan Liang "EventName": "OCR.PF_L2_RFO.L3_HIT_E.SNOOP_MISS", 2572ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 2573ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2574ecd94f1bSKan Liang "SampleAfterValue": "100003", 2575ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 2576ecd94f1bSKan Liang }, 2577ecd94f1bSKan Liang { 2578ecd94f1bSKan Liang "Offcore": "1", 2579ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 2580ecd94f1bSKan Liang "UMask": "0x1", 2581ecd94f1bSKan Liang "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs TBD", 2582ecd94f1bSKan Liang "MSRValue": "0x0400080020", 2583ecd94f1bSKan Liang "Counter": "0,1,2,3", 2584ecd94f1bSKan Liang "EventName": "OCR.PF_L2_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", 2585ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 2586ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2587ecd94f1bSKan Liang "SampleAfterValue": "100003", 2588ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 2589ecd94f1bSKan Liang }, 2590ecd94f1bSKan Liang { 2591ecd94f1bSKan Liang "Offcore": "1", 2592ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 2593ecd94f1bSKan Liang "UMask": "0x1", 2594ecd94f1bSKan Liang "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs TBD", 2595ecd94f1bSKan Liang "MSRValue": "0x0800080020", 2596ecd94f1bSKan Liang "Counter": "0,1,2,3", 2597ecd94f1bSKan Liang "EventName": "OCR.PF_L2_RFO.L3_HIT_E.HIT_OTHER_CORE_FWD", 2598ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 2599ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2600ecd94f1bSKan Liang "SampleAfterValue": "100003", 2601ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 2602ecd94f1bSKan Liang }, 2603ecd94f1bSKan Liang { 2604ecd94f1bSKan Liang "Offcore": "1", 2605ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 2606ecd94f1bSKan Liang "UMask": "0x1", 2607ecd94f1bSKan Liang "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs TBD", 2608ecd94f1bSKan Liang "MSRValue": "0x1000080020", 2609ecd94f1bSKan Liang "Counter": "0,1,2,3", 2610ecd94f1bSKan Liang "EventName": "OCR.PF_L2_RFO.L3_HIT_E.HITM_OTHER_CORE", 2611ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 2612ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2613ecd94f1bSKan Liang "SampleAfterValue": "100003", 2614ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 2615ecd94f1bSKan Liang }, 2616ecd94f1bSKan Liang { 2617ecd94f1bSKan Liang "Offcore": "1", 2618ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 2619ecd94f1bSKan Liang "UMask": "0x1", 2620ecd94f1bSKan Liang "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs TBD", 2621ecd94f1bSKan Liang "MSRValue": "0x3F80080020", 2622ecd94f1bSKan Liang "Counter": "0,1,2,3", 2623ecd94f1bSKan Liang "EventName": "OCR.PF_L2_RFO.L3_HIT_E.ANY_SNOOP", 2624ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 2625ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2626ecd94f1bSKan Liang "SampleAfterValue": "100003", 2627ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 2628ecd94f1bSKan Liang }, 2629ecd94f1bSKan Liang { 2630ecd94f1bSKan Liang "Offcore": "1", 2631ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 2632ecd94f1bSKan Liang "UMask": "0x1", 2633ecd94f1bSKan Liang "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs", 2634ecd94f1bSKan Liang "MSRValue": "0x0080100020", 2635ecd94f1bSKan Liang "Counter": "0,1,2,3", 2636ecd94f1bSKan Liang "EventName": "OCR.PF_L2_RFO.L3_HIT_S.SNOOP_NONE", 2637ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 2638ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2639ecd94f1bSKan Liang "SampleAfterValue": "100003", 2640ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 2641ecd94f1bSKan Liang }, 2642ecd94f1bSKan Liang { 2643ecd94f1bSKan Liang "Offcore": "1", 2644ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 2645ecd94f1bSKan Liang "UMask": "0x1", 2646ecd94f1bSKan Liang "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs TBD", 2647ecd94f1bSKan Liang "MSRValue": "0x0100100020", 2648ecd94f1bSKan Liang "Counter": "0,1,2,3", 2649ecd94f1bSKan Liang "EventName": "OCR.PF_L2_RFO.L3_HIT_S.NO_SNOOP_NEEDED", 2650ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 2651ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2652ecd94f1bSKan Liang "SampleAfterValue": "100003", 2653ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 2654ecd94f1bSKan Liang }, 2655ecd94f1bSKan Liang { 2656ecd94f1bSKan Liang "Offcore": "1", 2657ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 2658ecd94f1bSKan Liang "UMask": "0x1", 2659ecd94f1bSKan Liang "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs", 2660ecd94f1bSKan Liang "MSRValue": "0x0200100020", 2661ecd94f1bSKan Liang "Counter": "0,1,2,3", 2662ecd94f1bSKan Liang "EventName": "OCR.PF_L2_RFO.L3_HIT_S.SNOOP_MISS", 2663ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 2664ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2665ecd94f1bSKan Liang "SampleAfterValue": "100003", 2666ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 2667ecd94f1bSKan Liang }, 2668ecd94f1bSKan Liang { 2669ecd94f1bSKan Liang "Offcore": "1", 2670ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 2671ecd94f1bSKan Liang "UMask": "0x1", 2672ecd94f1bSKan Liang "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs TBD", 2673ecd94f1bSKan Liang "MSRValue": "0x0400100020", 2674ecd94f1bSKan Liang "Counter": "0,1,2,3", 2675ecd94f1bSKan Liang "EventName": "OCR.PF_L2_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", 2676ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 2677ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2678ecd94f1bSKan Liang "SampleAfterValue": "100003", 2679ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 2680ecd94f1bSKan Liang }, 2681ecd94f1bSKan Liang { 2682ecd94f1bSKan Liang "Offcore": "1", 2683ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 2684ecd94f1bSKan Liang "UMask": "0x1", 2685ecd94f1bSKan Liang "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs TBD", 2686ecd94f1bSKan Liang "MSRValue": "0x0800100020", 2687ecd94f1bSKan Liang "Counter": "0,1,2,3", 2688ecd94f1bSKan Liang "EventName": "OCR.PF_L2_RFO.L3_HIT_S.HIT_OTHER_CORE_FWD", 2689ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 2690ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2691ecd94f1bSKan Liang "SampleAfterValue": "100003", 2692ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 2693ecd94f1bSKan Liang }, 2694ecd94f1bSKan Liang { 2695ecd94f1bSKan Liang "Offcore": "1", 2696ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 2697ecd94f1bSKan Liang "UMask": "0x1", 2698ecd94f1bSKan Liang "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs TBD", 2699ecd94f1bSKan Liang "MSRValue": "0x1000100020", 2700ecd94f1bSKan Liang "Counter": "0,1,2,3", 2701ecd94f1bSKan Liang "EventName": "OCR.PF_L2_RFO.L3_HIT_S.HITM_OTHER_CORE", 2702ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 2703ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2704ecd94f1bSKan Liang "SampleAfterValue": "100003", 2705ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 2706ecd94f1bSKan Liang }, 2707ecd94f1bSKan Liang { 2708ecd94f1bSKan Liang "Offcore": "1", 2709ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 2710ecd94f1bSKan Liang "UMask": "0x1", 2711ecd94f1bSKan Liang "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs TBD", 2712ecd94f1bSKan Liang "MSRValue": "0x3F80100020", 2713ecd94f1bSKan Liang "Counter": "0,1,2,3", 2714ecd94f1bSKan Liang "EventName": "OCR.PF_L2_RFO.L3_HIT_S.ANY_SNOOP", 2715ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 2716ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2717ecd94f1bSKan Liang "SampleAfterValue": "100003", 2718ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 2719ecd94f1bSKan Liang }, 2720ecd94f1bSKan Liang { 2721ecd94f1bSKan Liang "Offcore": "1", 2722ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 2723ecd94f1bSKan Liang "UMask": "0x1", 2724ecd94f1bSKan Liang "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs", 2725ecd94f1bSKan Liang "MSRValue": "0x0080200020", 2726ecd94f1bSKan Liang "Counter": "0,1,2,3", 2727ecd94f1bSKan Liang "EventName": "OCR.PF_L2_RFO.L3_HIT_F.SNOOP_NONE", 2728ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 2729ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2730ecd94f1bSKan Liang "SampleAfterValue": "100003", 2731ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 2732ecd94f1bSKan Liang }, 2733ecd94f1bSKan Liang { 2734ecd94f1bSKan Liang "Offcore": "1", 2735ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 2736ecd94f1bSKan Liang "UMask": "0x1", 2737ecd94f1bSKan Liang "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs TBD", 2738ecd94f1bSKan Liang "MSRValue": "0x0100200020", 2739ecd94f1bSKan Liang "Counter": "0,1,2,3", 2740ecd94f1bSKan Liang "EventName": "OCR.PF_L2_RFO.L3_HIT_F.NO_SNOOP_NEEDED", 2741ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 2742ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2743ecd94f1bSKan Liang "SampleAfterValue": "100003", 2744ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 2745ecd94f1bSKan Liang }, 2746ecd94f1bSKan Liang { 2747ecd94f1bSKan Liang "Offcore": "1", 2748ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 2749ecd94f1bSKan Liang "UMask": "0x1", 2750ecd94f1bSKan Liang "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs", 2751ecd94f1bSKan Liang "MSRValue": "0x0200200020", 2752ecd94f1bSKan Liang "Counter": "0,1,2,3", 2753ecd94f1bSKan Liang "EventName": "OCR.PF_L2_RFO.L3_HIT_F.SNOOP_MISS", 2754ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 2755ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2756ecd94f1bSKan Liang "SampleAfterValue": "100003", 2757ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 2758ecd94f1bSKan Liang }, 2759ecd94f1bSKan Liang { 2760ecd94f1bSKan Liang "Offcore": "1", 2761ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 2762ecd94f1bSKan Liang "UMask": "0x1", 2763ecd94f1bSKan Liang "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs TBD", 2764ecd94f1bSKan Liang "MSRValue": "0x0400200020", 2765ecd94f1bSKan Liang "Counter": "0,1,2,3", 2766ecd94f1bSKan Liang "EventName": "OCR.PF_L2_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", 2767ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 2768ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2769ecd94f1bSKan Liang "SampleAfterValue": "100003", 2770ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 2771ecd94f1bSKan Liang }, 2772ecd94f1bSKan Liang { 2773ecd94f1bSKan Liang "Offcore": "1", 2774ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 2775ecd94f1bSKan Liang "UMask": "0x1", 2776ecd94f1bSKan Liang "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs TBD", 2777ecd94f1bSKan Liang "MSRValue": "0x0800200020", 2778ecd94f1bSKan Liang "Counter": "0,1,2,3", 2779ecd94f1bSKan Liang "EventName": "OCR.PF_L2_RFO.L3_HIT_F.HIT_OTHER_CORE_FWD", 2780ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 2781ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2782ecd94f1bSKan Liang "SampleAfterValue": "100003", 2783ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 2784ecd94f1bSKan Liang }, 2785ecd94f1bSKan Liang { 2786ecd94f1bSKan Liang "Offcore": "1", 2787ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 2788ecd94f1bSKan Liang "UMask": "0x1", 2789ecd94f1bSKan Liang "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs TBD", 2790ecd94f1bSKan Liang "MSRValue": "0x1000200020", 2791ecd94f1bSKan Liang "Counter": "0,1,2,3", 2792ecd94f1bSKan Liang "EventName": "OCR.PF_L2_RFO.L3_HIT_F.HITM_OTHER_CORE", 2793ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 2794ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2795ecd94f1bSKan Liang "SampleAfterValue": "100003", 2796ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 2797ecd94f1bSKan Liang }, 2798ecd94f1bSKan Liang { 2799ecd94f1bSKan Liang "Offcore": "1", 2800ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 2801ecd94f1bSKan Liang "UMask": "0x1", 2802ecd94f1bSKan Liang "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs TBD", 2803ecd94f1bSKan Liang "MSRValue": "0x3F80200020", 2804ecd94f1bSKan Liang "Counter": "0,1,2,3", 2805ecd94f1bSKan Liang "EventName": "OCR.PF_L2_RFO.L3_HIT_F.ANY_SNOOP", 2806ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 2807ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2808ecd94f1bSKan Liang "SampleAfterValue": "100003", 2809ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 2810ecd94f1bSKan Liang }, 2811ecd94f1bSKan Liang { 2812ecd94f1bSKan Liang "Offcore": "1", 2813ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 2814ecd94f1bSKan Liang "UMask": "0x1", 2815ecd94f1bSKan Liang "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs TBD", 2816ecd94f1bSKan Liang "MSRValue": "0x00803C0020", 2817ecd94f1bSKan Liang "Counter": "0,1,2,3", 2818ecd94f1bSKan Liang "EventName": "OCR.PF_L2_RFO.L3_HIT.SNOOP_NONE", 2819ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 2820ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2821ecd94f1bSKan Liang "SampleAfterValue": "100003", 2822ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 2823ecd94f1bSKan Liang }, 2824ecd94f1bSKan Liang { 2825ecd94f1bSKan Liang "Offcore": "1", 2826ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 2827ecd94f1bSKan Liang "UMask": "0x1", 2828ecd94f1bSKan Liang "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs TBD TBD", 2829ecd94f1bSKan Liang "MSRValue": "0x01003C0020", 2830ecd94f1bSKan Liang "Counter": "0,1,2,3", 2831ecd94f1bSKan Liang "EventName": "OCR.PF_L2_RFO.L3_HIT.NO_SNOOP_NEEDED", 2832ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 2833ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2834ecd94f1bSKan Liang "SampleAfterValue": "100003", 2835ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 2836ecd94f1bSKan Liang }, 2837ecd94f1bSKan Liang { 2838ecd94f1bSKan Liang "Offcore": "1", 2839ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 2840ecd94f1bSKan Liang "UMask": "0x1", 2841ecd94f1bSKan Liang "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs TBD", 2842ecd94f1bSKan Liang "MSRValue": "0x02003C0020", 2843ecd94f1bSKan Liang "Counter": "0,1,2,3", 2844ecd94f1bSKan Liang "EventName": "OCR.PF_L2_RFO.L3_HIT.SNOOP_MISS", 2845ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 2846ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2847ecd94f1bSKan Liang "SampleAfterValue": "100003", 2848ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 2849ecd94f1bSKan Liang }, 2850ecd94f1bSKan Liang { 2851ecd94f1bSKan Liang "Offcore": "1", 2852ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 2853ecd94f1bSKan Liang "UMask": "0x1", 2854ecd94f1bSKan Liang "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs TBD TBD", 2855ecd94f1bSKan Liang "MSRValue": "0x04003C0020", 2856ecd94f1bSKan Liang "Counter": "0,1,2,3", 2857ecd94f1bSKan Liang "EventName": "OCR.PF_L2_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD", 2858ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 2859ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2860ecd94f1bSKan Liang "SampleAfterValue": "100003", 2861ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 2862ecd94f1bSKan Liang }, 2863ecd94f1bSKan Liang { 2864ecd94f1bSKan Liang "Offcore": "1", 2865ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 2866ecd94f1bSKan Liang "UMask": "0x1", 2867ecd94f1bSKan Liang "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs TBD TBD", 2868ecd94f1bSKan Liang "MSRValue": "0x08003C0020", 2869ecd94f1bSKan Liang "Counter": "0,1,2,3", 2870ecd94f1bSKan Liang "EventName": "OCR.PF_L2_RFO.L3_HIT.HIT_OTHER_CORE_FWD", 2871ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 2872ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2873ecd94f1bSKan Liang "SampleAfterValue": "100003", 2874ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 2875ecd94f1bSKan Liang }, 2876ecd94f1bSKan Liang { 2877ecd94f1bSKan Liang "Offcore": "1", 2878ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 2879ecd94f1bSKan Liang "UMask": "0x1", 2880ecd94f1bSKan Liang "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs TBD TBD", 2881ecd94f1bSKan Liang "MSRValue": "0x10003C0020", 2882ecd94f1bSKan Liang "Counter": "0,1,2,3", 2883ecd94f1bSKan Liang "EventName": "OCR.PF_L2_RFO.L3_HIT.HITM_OTHER_CORE", 2884ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 2885ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2886ecd94f1bSKan Liang "SampleAfterValue": "100003", 2887ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 2888ecd94f1bSKan Liang }, 2889ecd94f1bSKan Liang { 2890ecd94f1bSKan Liang "Offcore": "1", 2891ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 2892ecd94f1bSKan Liang "UMask": "0x1", 2893ecd94f1bSKan Liang "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs TBD TBD", 2894ecd94f1bSKan Liang "MSRValue": "0x3F803C0020", 2895ecd94f1bSKan Liang "Counter": "0,1,2,3", 2896ecd94f1bSKan Liang "EventName": "OCR.PF_L2_RFO.L3_HIT.ANY_SNOOP", 2897ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 2898ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2899ecd94f1bSKan Liang "SampleAfterValue": "100003", 2900ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 2901ecd94f1bSKan Liang }, 2902ecd94f1bSKan Liang { 2903ecd94f1bSKan Liang "Offcore": "1", 2904ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 2905ecd94f1bSKan Liang "UMask": "0x1", 2906ecd94f1bSKan Liang "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads", 2907ecd94f1bSKan Liang "MSRValue": "0x0080020080", 2908ecd94f1bSKan Liang "Counter": "0,1,2,3", 2909ecd94f1bSKan Liang "EventName": "OCR.PF_L3_DATA_RD.SUPPLIER_NONE.SNOOP_NONE", 2910ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 2911ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2912ecd94f1bSKan Liang "SampleAfterValue": "100003", 2913ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 2914ecd94f1bSKan Liang }, 2915ecd94f1bSKan Liang { 2916ecd94f1bSKan Liang "Offcore": "1", 2917ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 2918ecd94f1bSKan Liang "UMask": "0x1", 2919ecd94f1bSKan Liang "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads TBD", 2920ecd94f1bSKan Liang "MSRValue": "0x0100020080", 2921ecd94f1bSKan Liang "Counter": "0,1,2,3", 2922ecd94f1bSKan Liang "EventName": "OCR.PF_L3_DATA_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED", 2923ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 2924ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2925ecd94f1bSKan Liang "SampleAfterValue": "100003", 2926ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 2927ecd94f1bSKan Liang }, 2928ecd94f1bSKan Liang { 2929ecd94f1bSKan Liang "Offcore": "1", 2930ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 2931ecd94f1bSKan Liang "UMask": "0x1", 2932ecd94f1bSKan Liang "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads", 2933ecd94f1bSKan Liang "MSRValue": "0x0200020080", 2934ecd94f1bSKan Liang "Counter": "0,1,2,3", 2935ecd94f1bSKan Liang "EventName": "OCR.PF_L3_DATA_RD.SUPPLIER_NONE.SNOOP_MISS", 2936ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 2937ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2938ecd94f1bSKan Liang "SampleAfterValue": "100003", 2939ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 2940ecd94f1bSKan Liang }, 2941ecd94f1bSKan Liang { 2942ecd94f1bSKan Liang "Offcore": "1", 2943ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 2944ecd94f1bSKan Liang "UMask": "0x1", 2945ecd94f1bSKan Liang "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads TBD", 2946ecd94f1bSKan Liang "MSRValue": "0x0400020080", 2947ecd94f1bSKan Liang "Counter": "0,1,2,3", 2948ecd94f1bSKan Liang "EventName": "OCR.PF_L3_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", 2949ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 2950ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2951ecd94f1bSKan Liang "SampleAfterValue": "100003", 2952ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 2953ecd94f1bSKan Liang }, 2954ecd94f1bSKan Liang { 2955ecd94f1bSKan Liang "Offcore": "1", 2956ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 2957ecd94f1bSKan Liang "UMask": "0x1", 2958ecd94f1bSKan Liang "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads TBD", 2959ecd94f1bSKan Liang "MSRValue": "0x0800020080", 2960ecd94f1bSKan Liang "Counter": "0,1,2,3", 2961ecd94f1bSKan Liang "EventName": "OCR.PF_L3_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", 2962ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 2963ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2964ecd94f1bSKan Liang "SampleAfterValue": "100003", 2965ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 2966ecd94f1bSKan Liang }, 2967ecd94f1bSKan Liang { 2968ecd94f1bSKan Liang "Offcore": "1", 2969ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 2970ecd94f1bSKan Liang "UMask": "0x1", 2971ecd94f1bSKan Liang "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads TBD", 2972ecd94f1bSKan Liang "MSRValue": "0x1000020080", 2973ecd94f1bSKan Liang "Counter": "0,1,2,3", 2974ecd94f1bSKan Liang "EventName": "OCR.PF_L3_DATA_RD.SUPPLIER_NONE.HITM_OTHER_CORE", 2975ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 2976ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2977ecd94f1bSKan Liang "SampleAfterValue": "100003", 2978ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 2979ecd94f1bSKan Liang }, 2980ecd94f1bSKan Liang { 2981ecd94f1bSKan Liang "Offcore": "1", 2982ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 2983ecd94f1bSKan Liang "UMask": "0x1", 2984ecd94f1bSKan Liang "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads TBD", 2985ecd94f1bSKan Liang "MSRValue": "0x3F80020080", 2986ecd94f1bSKan Liang "Counter": "0,1,2,3", 2987ecd94f1bSKan Liang "EventName": "OCR.PF_L3_DATA_RD.SUPPLIER_NONE.ANY_SNOOP", 2988ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 2989ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2990ecd94f1bSKan Liang "SampleAfterValue": "100003", 2991ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 2992ecd94f1bSKan Liang }, 2993ecd94f1bSKan Liang { 2994ecd94f1bSKan Liang "Offcore": "1", 2995ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 2996ecd94f1bSKan Liang "UMask": "0x1", 2997ecd94f1bSKan Liang "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads", 2998ecd94f1bSKan Liang "MSRValue": "0x0080040080", 2999ecd94f1bSKan Liang "Counter": "0,1,2,3", 3000ecd94f1bSKan Liang "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_M.SNOOP_NONE", 3001ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 3002ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3003ecd94f1bSKan Liang "SampleAfterValue": "100003", 3004ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 3005ecd94f1bSKan Liang }, 3006ecd94f1bSKan Liang { 3007ecd94f1bSKan Liang "Offcore": "1", 3008ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 3009ecd94f1bSKan Liang "UMask": "0x1", 3010ecd94f1bSKan Liang "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads TBD", 3011ecd94f1bSKan Liang "MSRValue": "0x0100040080", 3012ecd94f1bSKan Liang "Counter": "0,1,2,3", 3013ecd94f1bSKan Liang "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDED", 3014ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 3015ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3016ecd94f1bSKan Liang "SampleAfterValue": "100003", 3017ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 3018ecd94f1bSKan Liang }, 3019ecd94f1bSKan Liang { 3020ecd94f1bSKan Liang "Offcore": "1", 3021ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 3022ecd94f1bSKan Liang "UMask": "0x1", 3023ecd94f1bSKan Liang "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads", 3024ecd94f1bSKan Liang "MSRValue": "0x0200040080", 3025ecd94f1bSKan Liang "Counter": "0,1,2,3", 3026ecd94f1bSKan Liang "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_M.SNOOP_MISS", 3027ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 3028ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3029ecd94f1bSKan Liang "SampleAfterValue": "100003", 3030ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 3031ecd94f1bSKan Liang }, 3032ecd94f1bSKan Liang { 3033ecd94f1bSKan Liang "Offcore": "1", 3034ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 3035ecd94f1bSKan Liang "UMask": "0x1", 3036ecd94f1bSKan Liang "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads TBD", 3037ecd94f1bSKan Liang "MSRValue": "0x0400040080", 3038ecd94f1bSKan Liang "Counter": "0,1,2,3", 3039ecd94f1bSKan Liang "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", 3040ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 3041ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3042ecd94f1bSKan Liang "SampleAfterValue": "100003", 3043ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 3044ecd94f1bSKan Liang }, 3045ecd94f1bSKan Liang { 3046ecd94f1bSKan Liang "Offcore": "1", 3047ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 3048ecd94f1bSKan Liang "UMask": "0x1", 3049ecd94f1bSKan Liang "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads TBD", 3050ecd94f1bSKan Liang "MSRValue": "0x0800040080", 3051ecd94f1bSKan Liang "Counter": "0,1,2,3", 3052ecd94f1bSKan Liang "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWD", 3053ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 3054ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3055ecd94f1bSKan Liang "SampleAfterValue": "100003", 3056ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 3057ecd94f1bSKan Liang }, 3058ecd94f1bSKan Liang { 3059ecd94f1bSKan Liang "Offcore": "1", 3060ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 3061ecd94f1bSKan Liang "UMask": "0x1", 3062ecd94f1bSKan Liang "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads TBD", 3063ecd94f1bSKan Liang "MSRValue": "0x1000040080", 3064ecd94f1bSKan Liang "Counter": "0,1,2,3", 3065ecd94f1bSKan Liang "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_M.HITM_OTHER_CORE", 3066ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 3067ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3068ecd94f1bSKan Liang "SampleAfterValue": "100003", 3069ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 3070ecd94f1bSKan Liang }, 3071ecd94f1bSKan Liang { 3072ecd94f1bSKan Liang "Offcore": "1", 3073ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 3074ecd94f1bSKan Liang "UMask": "0x1", 3075ecd94f1bSKan Liang "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads TBD", 3076ecd94f1bSKan Liang "MSRValue": "0x3F80040080", 3077ecd94f1bSKan Liang "Counter": "0,1,2,3", 3078ecd94f1bSKan Liang "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_M.ANY_SNOOP", 3079ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 3080ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3081ecd94f1bSKan Liang "SampleAfterValue": "100003", 3082ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 3083ecd94f1bSKan Liang }, 3084ecd94f1bSKan Liang { 3085ecd94f1bSKan Liang "Offcore": "1", 3086ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 3087ecd94f1bSKan Liang "UMask": "0x1", 3088ecd94f1bSKan Liang "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads", 3089ecd94f1bSKan Liang "MSRValue": "0x0080080080", 3090ecd94f1bSKan Liang "Counter": "0,1,2,3", 3091ecd94f1bSKan Liang "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_E.SNOOP_NONE", 3092ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 3093ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3094ecd94f1bSKan Liang "SampleAfterValue": "100003", 3095ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 3096ecd94f1bSKan Liang }, 3097ecd94f1bSKan Liang { 3098ecd94f1bSKan Liang "Offcore": "1", 3099ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 3100ecd94f1bSKan Liang "UMask": "0x1", 3101ecd94f1bSKan Liang "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads TBD", 3102ecd94f1bSKan Liang "MSRValue": "0x0100080080", 3103ecd94f1bSKan Liang "Counter": "0,1,2,3", 3104ecd94f1bSKan Liang "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDED", 3105ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 3106ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3107ecd94f1bSKan Liang "SampleAfterValue": "100003", 3108ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 3109ecd94f1bSKan Liang }, 3110ecd94f1bSKan Liang { 3111ecd94f1bSKan Liang "Offcore": "1", 3112ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 3113ecd94f1bSKan Liang "UMask": "0x1", 3114ecd94f1bSKan Liang "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads", 3115ecd94f1bSKan Liang "MSRValue": "0x0200080080", 3116ecd94f1bSKan Liang "Counter": "0,1,2,3", 3117ecd94f1bSKan Liang "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_E.SNOOP_MISS", 3118ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 3119ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3120ecd94f1bSKan Liang "SampleAfterValue": "100003", 3121ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 3122ecd94f1bSKan Liang }, 3123ecd94f1bSKan Liang { 3124ecd94f1bSKan Liang "Offcore": "1", 3125ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 3126ecd94f1bSKan Liang "UMask": "0x1", 3127ecd94f1bSKan Liang "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads TBD", 3128ecd94f1bSKan Liang "MSRValue": "0x0400080080", 3129ecd94f1bSKan Liang "Counter": "0,1,2,3", 3130ecd94f1bSKan Liang "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", 3131ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 3132ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3133ecd94f1bSKan Liang "SampleAfterValue": "100003", 3134ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 3135ecd94f1bSKan Liang }, 3136ecd94f1bSKan Liang { 3137ecd94f1bSKan Liang "Offcore": "1", 3138ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 3139ecd94f1bSKan Liang "UMask": "0x1", 3140ecd94f1bSKan Liang "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads TBD", 3141ecd94f1bSKan Liang "MSRValue": "0x0800080080", 3142ecd94f1bSKan Liang "Counter": "0,1,2,3", 3143ecd94f1bSKan Liang "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWD", 3144ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 3145ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3146ecd94f1bSKan Liang "SampleAfterValue": "100003", 3147ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 3148ecd94f1bSKan Liang }, 3149ecd94f1bSKan Liang { 3150ecd94f1bSKan Liang "Offcore": "1", 3151ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 3152ecd94f1bSKan Liang "UMask": "0x1", 3153ecd94f1bSKan Liang "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads TBD", 3154ecd94f1bSKan Liang "MSRValue": "0x1000080080", 3155ecd94f1bSKan Liang "Counter": "0,1,2,3", 3156ecd94f1bSKan Liang "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_E.HITM_OTHER_CORE", 3157ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 3158ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3159ecd94f1bSKan Liang "SampleAfterValue": "100003", 3160ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 3161ecd94f1bSKan Liang }, 3162ecd94f1bSKan Liang { 3163ecd94f1bSKan Liang "Offcore": "1", 3164ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 3165ecd94f1bSKan Liang "UMask": "0x1", 3166ecd94f1bSKan Liang "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads TBD", 3167ecd94f1bSKan Liang "MSRValue": "0x3F80080080", 3168ecd94f1bSKan Liang "Counter": "0,1,2,3", 3169ecd94f1bSKan Liang "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_E.ANY_SNOOP", 3170ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 3171ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3172ecd94f1bSKan Liang "SampleAfterValue": "100003", 3173ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 3174ecd94f1bSKan Liang }, 3175ecd94f1bSKan Liang { 3176ecd94f1bSKan Liang "Offcore": "1", 3177ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 3178ecd94f1bSKan Liang "UMask": "0x1", 3179ecd94f1bSKan Liang "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads", 3180ecd94f1bSKan Liang "MSRValue": "0x0080100080", 3181ecd94f1bSKan Liang "Counter": "0,1,2,3", 3182ecd94f1bSKan Liang "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_S.SNOOP_NONE", 3183ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 3184ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3185ecd94f1bSKan Liang "SampleAfterValue": "100003", 3186ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 3187ecd94f1bSKan Liang }, 3188ecd94f1bSKan Liang { 3189ecd94f1bSKan Liang "Offcore": "1", 3190ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 3191ecd94f1bSKan Liang "UMask": "0x1", 3192ecd94f1bSKan Liang "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads TBD", 3193ecd94f1bSKan Liang "MSRValue": "0x0100100080", 3194ecd94f1bSKan Liang "Counter": "0,1,2,3", 3195ecd94f1bSKan Liang "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDED", 3196ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 3197ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3198ecd94f1bSKan Liang "SampleAfterValue": "100003", 3199ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 3200ecd94f1bSKan Liang }, 3201ecd94f1bSKan Liang { 3202ecd94f1bSKan Liang "Offcore": "1", 3203ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 3204ecd94f1bSKan Liang "UMask": "0x1", 3205ecd94f1bSKan Liang "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads", 3206ecd94f1bSKan Liang "MSRValue": "0x0200100080", 3207ecd94f1bSKan Liang "Counter": "0,1,2,3", 3208ecd94f1bSKan Liang "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_S.SNOOP_MISS", 3209ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 3210ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3211ecd94f1bSKan Liang "SampleAfterValue": "100003", 3212ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 3213ecd94f1bSKan Liang }, 3214ecd94f1bSKan Liang { 3215ecd94f1bSKan Liang "Offcore": "1", 3216ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 3217ecd94f1bSKan Liang "UMask": "0x1", 3218ecd94f1bSKan Liang "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads TBD", 3219ecd94f1bSKan Liang "MSRValue": "0x0400100080", 3220ecd94f1bSKan Liang "Counter": "0,1,2,3", 3221ecd94f1bSKan Liang "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", 3222ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 3223ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3224ecd94f1bSKan Liang "SampleAfterValue": "100003", 3225ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 3226ecd94f1bSKan Liang }, 3227ecd94f1bSKan Liang { 3228ecd94f1bSKan Liang "Offcore": "1", 3229ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 3230ecd94f1bSKan Liang "UMask": "0x1", 3231ecd94f1bSKan Liang "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads TBD", 3232ecd94f1bSKan Liang "MSRValue": "0x0800100080", 3233ecd94f1bSKan Liang "Counter": "0,1,2,3", 3234ecd94f1bSKan Liang "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWD", 3235ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 3236ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3237ecd94f1bSKan Liang "SampleAfterValue": "100003", 3238ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 3239ecd94f1bSKan Liang }, 3240ecd94f1bSKan Liang { 3241ecd94f1bSKan Liang "Offcore": "1", 3242ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 3243ecd94f1bSKan Liang "UMask": "0x1", 3244ecd94f1bSKan Liang "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads TBD", 3245ecd94f1bSKan Liang "MSRValue": "0x1000100080", 3246ecd94f1bSKan Liang "Counter": "0,1,2,3", 3247ecd94f1bSKan Liang "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_S.HITM_OTHER_CORE", 3248ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 3249ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3250ecd94f1bSKan Liang "SampleAfterValue": "100003", 3251ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 3252ecd94f1bSKan Liang }, 3253ecd94f1bSKan Liang { 3254ecd94f1bSKan Liang "Offcore": "1", 3255ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 3256ecd94f1bSKan Liang "UMask": "0x1", 3257ecd94f1bSKan Liang "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads TBD", 3258ecd94f1bSKan Liang "MSRValue": "0x3F80100080", 3259ecd94f1bSKan Liang "Counter": "0,1,2,3", 3260ecd94f1bSKan Liang "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_S.ANY_SNOOP", 3261ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 3262ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3263ecd94f1bSKan Liang "SampleAfterValue": "100003", 3264ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 3265ecd94f1bSKan Liang }, 3266ecd94f1bSKan Liang { 3267ecd94f1bSKan Liang "Offcore": "1", 3268ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 3269ecd94f1bSKan Liang "UMask": "0x1", 3270ecd94f1bSKan Liang "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads", 3271ecd94f1bSKan Liang "MSRValue": "0x0080200080", 3272ecd94f1bSKan Liang "Counter": "0,1,2,3", 3273ecd94f1bSKan Liang "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_F.SNOOP_NONE", 3274ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 3275ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3276ecd94f1bSKan Liang "SampleAfterValue": "100003", 3277ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 3278ecd94f1bSKan Liang }, 3279ecd94f1bSKan Liang { 3280ecd94f1bSKan Liang "Offcore": "1", 3281ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 3282ecd94f1bSKan Liang "UMask": "0x1", 3283ecd94f1bSKan Liang "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads TBD", 3284ecd94f1bSKan Liang "MSRValue": "0x0100200080", 3285ecd94f1bSKan Liang "Counter": "0,1,2,3", 3286ecd94f1bSKan Liang "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDED", 3287ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 3288ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3289ecd94f1bSKan Liang "SampleAfterValue": "100003", 3290ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 3291ecd94f1bSKan Liang }, 3292ecd94f1bSKan Liang { 3293ecd94f1bSKan Liang "Offcore": "1", 3294ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 3295ecd94f1bSKan Liang "UMask": "0x1", 3296ecd94f1bSKan Liang "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads", 3297ecd94f1bSKan Liang "MSRValue": "0x0200200080", 3298ecd94f1bSKan Liang "Counter": "0,1,2,3", 3299ecd94f1bSKan Liang "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_F.SNOOP_MISS", 3300ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 3301ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3302ecd94f1bSKan Liang "SampleAfterValue": "100003", 3303ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 3304ecd94f1bSKan Liang }, 3305ecd94f1bSKan Liang { 3306ecd94f1bSKan Liang "Offcore": "1", 3307ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 3308ecd94f1bSKan Liang "UMask": "0x1", 3309ecd94f1bSKan Liang "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads TBD", 3310ecd94f1bSKan Liang "MSRValue": "0x0400200080", 3311ecd94f1bSKan Liang "Counter": "0,1,2,3", 3312ecd94f1bSKan Liang "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", 3313ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 3314ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3315ecd94f1bSKan Liang "SampleAfterValue": "100003", 3316ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 3317ecd94f1bSKan Liang }, 3318ecd94f1bSKan Liang { 3319ecd94f1bSKan Liang "Offcore": "1", 3320ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 3321ecd94f1bSKan Liang "UMask": "0x1", 3322ecd94f1bSKan Liang "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads TBD", 3323ecd94f1bSKan Liang "MSRValue": "0x0800200080", 3324ecd94f1bSKan Liang "Counter": "0,1,2,3", 3325ecd94f1bSKan Liang "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWD", 3326ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 3327ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3328ecd94f1bSKan Liang "SampleAfterValue": "100003", 3329ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 3330ecd94f1bSKan Liang }, 3331ecd94f1bSKan Liang { 3332ecd94f1bSKan Liang "Offcore": "1", 3333ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 3334ecd94f1bSKan Liang "UMask": "0x1", 3335ecd94f1bSKan Liang "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads TBD", 3336ecd94f1bSKan Liang "MSRValue": "0x1000200080", 3337ecd94f1bSKan Liang "Counter": "0,1,2,3", 3338ecd94f1bSKan Liang "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_F.HITM_OTHER_CORE", 3339ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 3340ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3341ecd94f1bSKan Liang "SampleAfterValue": "100003", 3342ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 3343ecd94f1bSKan Liang }, 3344ecd94f1bSKan Liang { 3345ecd94f1bSKan Liang "Offcore": "1", 3346ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 3347ecd94f1bSKan Liang "UMask": "0x1", 3348ecd94f1bSKan Liang "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads TBD", 3349ecd94f1bSKan Liang "MSRValue": "0x3F80200080", 3350ecd94f1bSKan Liang "Counter": "0,1,2,3", 3351ecd94f1bSKan Liang "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_F.ANY_SNOOP", 3352ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 3353ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3354ecd94f1bSKan Liang "SampleAfterValue": "100003", 3355ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 3356ecd94f1bSKan Liang }, 3357ecd94f1bSKan Liang { 3358ecd94f1bSKan Liang "Offcore": "1", 3359ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 3360ecd94f1bSKan Liang "UMask": "0x1", 3361ecd94f1bSKan Liang "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads TBD", 3362ecd94f1bSKan Liang "MSRValue": "0x00803C0080", 3363ecd94f1bSKan Liang "Counter": "0,1,2,3", 3364ecd94f1bSKan Liang "EventName": "OCR.PF_L3_DATA_RD.L3_HIT.SNOOP_NONE", 3365ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 3366ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3367ecd94f1bSKan Liang "SampleAfterValue": "100003", 3368ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 3369ecd94f1bSKan Liang }, 3370ecd94f1bSKan Liang { 3371ecd94f1bSKan Liang "Offcore": "1", 3372ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 3373ecd94f1bSKan Liang "UMask": "0x1", 3374ecd94f1bSKan Liang "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads TBD TBD", 3375ecd94f1bSKan Liang "MSRValue": "0x01003C0080", 3376ecd94f1bSKan Liang "Counter": "0,1,2,3", 3377ecd94f1bSKan Liang "EventName": "OCR.PF_L3_DATA_RD.L3_HIT.NO_SNOOP_NEEDED", 3378ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 3379ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3380ecd94f1bSKan Liang "SampleAfterValue": "100003", 3381ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 3382ecd94f1bSKan Liang }, 3383ecd94f1bSKan Liang { 3384ecd94f1bSKan Liang "Offcore": "1", 3385ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 3386ecd94f1bSKan Liang "UMask": "0x1", 3387ecd94f1bSKan Liang "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads TBD", 3388ecd94f1bSKan Liang "MSRValue": "0x02003C0080", 3389ecd94f1bSKan Liang "Counter": "0,1,2,3", 3390ecd94f1bSKan Liang "EventName": "OCR.PF_L3_DATA_RD.L3_HIT.SNOOP_MISS", 3391ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 3392ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3393ecd94f1bSKan Liang "SampleAfterValue": "100003", 3394ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 3395ecd94f1bSKan Liang }, 3396ecd94f1bSKan Liang { 3397ecd94f1bSKan Liang "Offcore": "1", 3398ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 3399ecd94f1bSKan Liang "UMask": "0x1", 3400ecd94f1bSKan Liang "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads TBD TBD", 3401ecd94f1bSKan Liang "MSRValue": "0x04003C0080", 3402ecd94f1bSKan Liang "Counter": "0,1,2,3", 3403ecd94f1bSKan Liang "EventName": "OCR.PF_L3_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD", 3404ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 3405ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3406ecd94f1bSKan Liang "SampleAfterValue": "100003", 3407ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 3408ecd94f1bSKan Liang }, 3409ecd94f1bSKan Liang { 3410ecd94f1bSKan Liang "Offcore": "1", 3411ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 3412ecd94f1bSKan Liang "UMask": "0x1", 3413ecd94f1bSKan Liang "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads TBD TBD", 3414ecd94f1bSKan Liang "MSRValue": "0x08003C0080", 3415ecd94f1bSKan Liang "Counter": "0,1,2,3", 3416ecd94f1bSKan Liang "EventName": "OCR.PF_L3_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD", 3417ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 3418ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3419ecd94f1bSKan Liang "SampleAfterValue": "100003", 3420ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 3421ecd94f1bSKan Liang }, 3422ecd94f1bSKan Liang { 3423ecd94f1bSKan Liang "Offcore": "1", 3424ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 3425ecd94f1bSKan Liang "UMask": "0x1", 3426ecd94f1bSKan Liang "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads TBD TBD", 3427ecd94f1bSKan Liang "MSRValue": "0x10003C0080", 3428ecd94f1bSKan Liang "Counter": "0,1,2,3", 3429ecd94f1bSKan Liang "EventName": "OCR.PF_L3_DATA_RD.L3_HIT.HITM_OTHER_CORE", 3430ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 3431ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3432ecd94f1bSKan Liang "SampleAfterValue": "100003", 3433ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 3434ecd94f1bSKan Liang }, 3435ecd94f1bSKan Liang { 3436ecd94f1bSKan Liang "Offcore": "1", 3437ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 3438ecd94f1bSKan Liang "UMask": "0x1", 3439ecd94f1bSKan Liang "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads TBD TBD", 3440ecd94f1bSKan Liang "MSRValue": "0x3F803C0080", 3441ecd94f1bSKan Liang "Counter": "0,1,2,3", 3442ecd94f1bSKan Liang "EventName": "OCR.PF_L3_DATA_RD.L3_HIT.ANY_SNOOP", 3443ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 3444ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3445ecd94f1bSKan Liang "SampleAfterValue": "100003", 3446ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 3447ecd94f1bSKan Liang }, 3448ecd94f1bSKan Liang { 3449ecd94f1bSKan Liang "Offcore": "1", 3450ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 3451ecd94f1bSKan Liang "UMask": "0x1", 3452ecd94f1bSKan Liang "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs", 3453ecd94f1bSKan Liang "MSRValue": "0x0080020100", 3454ecd94f1bSKan Liang "Counter": "0,1,2,3", 3455ecd94f1bSKan Liang "EventName": "OCR.PF_L3_RFO.SUPPLIER_NONE.SNOOP_NONE", 3456ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 3457ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3458ecd94f1bSKan Liang "SampleAfterValue": "100003", 3459ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 3460ecd94f1bSKan Liang }, 3461ecd94f1bSKan Liang { 3462ecd94f1bSKan Liang "Offcore": "1", 3463ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 3464ecd94f1bSKan Liang "UMask": "0x1", 3465ecd94f1bSKan Liang "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs TBD", 3466ecd94f1bSKan Liang "MSRValue": "0x0100020100", 3467ecd94f1bSKan Liang "Counter": "0,1,2,3", 3468ecd94f1bSKan Liang "EventName": "OCR.PF_L3_RFO.SUPPLIER_NONE.NO_SNOOP_NEEDED", 3469ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 3470ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3471ecd94f1bSKan Liang "SampleAfterValue": "100003", 3472ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 3473ecd94f1bSKan Liang }, 3474ecd94f1bSKan Liang { 3475ecd94f1bSKan Liang "Offcore": "1", 3476ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 3477ecd94f1bSKan Liang "UMask": "0x1", 3478ecd94f1bSKan Liang "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs", 3479ecd94f1bSKan Liang "MSRValue": "0x0200020100", 3480ecd94f1bSKan Liang "Counter": "0,1,2,3", 3481ecd94f1bSKan Liang "EventName": "OCR.PF_L3_RFO.SUPPLIER_NONE.SNOOP_MISS", 3482ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 3483ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3484ecd94f1bSKan Liang "SampleAfterValue": "100003", 3485ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 3486ecd94f1bSKan Liang }, 3487ecd94f1bSKan Liang { 3488ecd94f1bSKan Liang "Offcore": "1", 3489ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 3490ecd94f1bSKan Liang "UMask": "0x1", 3491ecd94f1bSKan Liang "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs TBD", 3492ecd94f1bSKan Liang "MSRValue": "0x0400020100", 3493ecd94f1bSKan Liang "Counter": "0,1,2,3", 3494ecd94f1bSKan Liang "EventName": "OCR.PF_L3_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", 3495ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 3496ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3497ecd94f1bSKan Liang "SampleAfterValue": "100003", 3498ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 3499ecd94f1bSKan Liang }, 3500ecd94f1bSKan Liang { 3501ecd94f1bSKan Liang "Offcore": "1", 3502ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 3503ecd94f1bSKan Liang "UMask": "0x1", 3504ecd94f1bSKan Liang "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs TBD", 3505ecd94f1bSKan Liang "MSRValue": "0x0800020100", 3506ecd94f1bSKan Liang "Counter": "0,1,2,3", 3507ecd94f1bSKan Liang "EventName": "OCR.PF_L3_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", 3508ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 3509ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3510ecd94f1bSKan Liang "SampleAfterValue": "100003", 3511ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 3512ecd94f1bSKan Liang }, 3513ecd94f1bSKan Liang { 3514ecd94f1bSKan Liang "Offcore": "1", 3515ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 3516ecd94f1bSKan Liang "UMask": "0x1", 3517ecd94f1bSKan Liang "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs TBD", 3518ecd94f1bSKan Liang "MSRValue": "0x1000020100", 3519ecd94f1bSKan Liang "Counter": "0,1,2,3", 3520ecd94f1bSKan Liang "EventName": "OCR.PF_L3_RFO.SUPPLIER_NONE.HITM_OTHER_CORE", 3521ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 3522ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3523ecd94f1bSKan Liang "SampleAfterValue": "100003", 3524ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 3525ecd94f1bSKan Liang }, 3526ecd94f1bSKan Liang { 3527ecd94f1bSKan Liang "Offcore": "1", 3528ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 3529ecd94f1bSKan Liang "UMask": "0x1", 3530ecd94f1bSKan Liang "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs TBD", 3531ecd94f1bSKan Liang "MSRValue": "0x3F80020100", 3532ecd94f1bSKan Liang "Counter": "0,1,2,3", 3533ecd94f1bSKan Liang "EventName": "OCR.PF_L3_RFO.SUPPLIER_NONE.ANY_SNOOP", 3534ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 3535ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3536ecd94f1bSKan Liang "SampleAfterValue": "100003", 3537ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 3538ecd94f1bSKan Liang }, 3539ecd94f1bSKan Liang { 3540ecd94f1bSKan Liang "Offcore": "1", 3541ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 3542ecd94f1bSKan Liang "UMask": "0x1", 3543ecd94f1bSKan Liang "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs", 3544ecd94f1bSKan Liang "MSRValue": "0x0080040100", 3545ecd94f1bSKan Liang "Counter": "0,1,2,3", 3546ecd94f1bSKan Liang "EventName": "OCR.PF_L3_RFO.L3_HIT_M.SNOOP_NONE", 3547ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 3548ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3549ecd94f1bSKan Liang "SampleAfterValue": "100003", 3550ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 3551ecd94f1bSKan Liang }, 3552ecd94f1bSKan Liang { 3553ecd94f1bSKan Liang "Offcore": "1", 3554ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 3555ecd94f1bSKan Liang "UMask": "0x1", 3556ecd94f1bSKan Liang "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs TBD", 3557ecd94f1bSKan Liang "MSRValue": "0x0100040100", 3558ecd94f1bSKan Liang "Counter": "0,1,2,3", 3559ecd94f1bSKan Liang "EventName": "OCR.PF_L3_RFO.L3_HIT_M.NO_SNOOP_NEEDED", 3560ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 3561ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3562ecd94f1bSKan Liang "SampleAfterValue": "100003", 3563ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 3564ecd94f1bSKan Liang }, 3565ecd94f1bSKan Liang { 3566ecd94f1bSKan Liang "Offcore": "1", 3567ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 3568ecd94f1bSKan Liang "UMask": "0x1", 3569ecd94f1bSKan Liang "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs", 3570ecd94f1bSKan Liang "MSRValue": "0x0200040100", 3571ecd94f1bSKan Liang "Counter": "0,1,2,3", 3572ecd94f1bSKan Liang "EventName": "OCR.PF_L3_RFO.L3_HIT_M.SNOOP_MISS", 3573ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 3574ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3575ecd94f1bSKan Liang "SampleAfterValue": "100003", 3576ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 3577ecd94f1bSKan Liang }, 3578ecd94f1bSKan Liang { 3579ecd94f1bSKan Liang "Offcore": "1", 3580ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 3581ecd94f1bSKan Liang "UMask": "0x1", 3582ecd94f1bSKan Liang "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs TBD", 3583ecd94f1bSKan Liang "MSRValue": "0x0400040100", 3584ecd94f1bSKan Liang "Counter": "0,1,2,3", 3585ecd94f1bSKan Liang "EventName": "OCR.PF_L3_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", 3586ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 3587ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3588ecd94f1bSKan Liang "SampleAfterValue": "100003", 3589ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 3590ecd94f1bSKan Liang }, 3591ecd94f1bSKan Liang { 3592ecd94f1bSKan Liang "Offcore": "1", 3593ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 3594ecd94f1bSKan Liang "UMask": "0x1", 3595ecd94f1bSKan Liang "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs TBD", 3596ecd94f1bSKan Liang "MSRValue": "0x0800040100", 3597ecd94f1bSKan Liang "Counter": "0,1,2,3", 3598ecd94f1bSKan Liang "EventName": "OCR.PF_L3_RFO.L3_HIT_M.HIT_OTHER_CORE_FWD", 3599ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 3600ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3601ecd94f1bSKan Liang "SampleAfterValue": "100003", 3602ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 3603ecd94f1bSKan Liang }, 3604ecd94f1bSKan Liang { 3605ecd94f1bSKan Liang "Offcore": "1", 3606ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 3607ecd94f1bSKan Liang "UMask": "0x1", 3608ecd94f1bSKan Liang "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs TBD", 3609ecd94f1bSKan Liang "MSRValue": "0x1000040100", 3610ecd94f1bSKan Liang "Counter": "0,1,2,3", 3611ecd94f1bSKan Liang "EventName": "OCR.PF_L3_RFO.L3_HIT_M.HITM_OTHER_CORE", 3612ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 3613ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3614ecd94f1bSKan Liang "SampleAfterValue": "100003", 3615ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 3616ecd94f1bSKan Liang }, 3617ecd94f1bSKan Liang { 3618ecd94f1bSKan Liang "Offcore": "1", 3619ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 3620ecd94f1bSKan Liang "UMask": "0x1", 3621ecd94f1bSKan Liang "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs TBD", 3622ecd94f1bSKan Liang "MSRValue": "0x3F80040100", 3623ecd94f1bSKan Liang "Counter": "0,1,2,3", 3624ecd94f1bSKan Liang "EventName": "OCR.PF_L3_RFO.L3_HIT_M.ANY_SNOOP", 3625ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 3626ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3627ecd94f1bSKan Liang "SampleAfterValue": "100003", 3628ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 3629ecd94f1bSKan Liang }, 3630ecd94f1bSKan Liang { 3631ecd94f1bSKan Liang "Offcore": "1", 3632ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 3633ecd94f1bSKan Liang "UMask": "0x1", 3634ecd94f1bSKan Liang "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs", 3635ecd94f1bSKan Liang "MSRValue": "0x0080080100", 3636ecd94f1bSKan Liang "Counter": "0,1,2,3", 3637ecd94f1bSKan Liang "EventName": "OCR.PF_L3_RFO.L3_HIT_E.SNOOP_NONE", 3638ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 3639ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3640ecd94f1bSKan Liang "SampleAfterValue": "100003", 3641ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 3642ecd94f1bSKan Liang }, 3643ecd94f1bSKan Liang { 3644ecd94f1bSKan Liang "Offcore": "1", 3645ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 3646ecd94f1bSKan Liang "UMask": "0x1", 3647ecd94f1bSKan Liang "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs TBD", 3648ecd94f1bSKan Liang "MSRValue": "0x0100080100", 3649ecd94f1bSKan Liang "Counter": "0,1,2,3", 3650ecd94f1bSKan Liang "EventName": "OCR.PF_L3_RFO.L3_HIT_E.NO_SNOOP_NEEDED", 3651ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 3652ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3653ecd94f1bSKan Liang "SampleAfterValue": "100003", 3654ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 3655ecd94f1bSKan Liang }, 3656ecd94f1bSKan Liang { 3657ecd94f1bSKan Liang "Offcore": "1", 3658ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 3659ecd94f1bSKan Liang "UMask": "0x1", 3660ecd94f1bSKan Liang "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs", 3661ecd94f1bSKan Liang "MSRValue": "0x0200080100", 3662ecd94f1bSKan Liang "Counter": "0,1,2,3", 3663ecd94f1bSKan Liang "EventName": "OCR.PF_L3_RFO.L3_HIT_E.SNOOP_MISS", 3664ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 3665ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3666ecd94f1bSKan Liang "SampleAfterValue": "100003", 3667ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 3668ecd94f1bSKan Liang }, 3669ecd94f1bSKan Liang { 3670ecd94f1bSKan Liang "Offcore": "1", 3671ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 3672ecd94f1bSKan Liang "UMask": "0x1", 3673ecd94f1bSKan Liang "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs TBD", 3674ecd94f1bSKan Liang "MSRValue": "0x0400080100", 3675ecd94f1bSKan Liang "Counter": "0,1,2,3", 3676ecd94f1bSKan Liang "EventName": "OCR.PF_L3_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", 3677ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 3678ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3679ecd94f1bSKan Liang "SampleAfterValue": "100003", 3680ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 3681ecd94f1bSKan Liang }, 3682ecd94f1bSKan Liang { 3683ecd94f1bSKan Liang "Offcore": "1", 3684ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 3685ecd94f1bSKan Liang "UMask": "0x1", 3686ecd94f1bSKan Liang "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs TBD", 3687ecd94f1bSKan Liang "MSRValue": "0x0800080100", 3688ecd94f1bSKan Liang "Counter": "0,1,2,3", 3689ecd94f1bSKan Liang "EventName": "OCR.PF_L3_RFO.L3_HIT_E.HIT_OTHER_CORE_FWD", 3690ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 3691ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3692ecd94f1bSKan Liang "SampleAfterValue": "100003", 3693ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 3694ecd94f1bSKan Liang }, 3695ecd94f1bSKan Liang { 3696ecd94f1bSKan Liang "Offcore": "1", 3697ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 3698ecd94f1bSKan Liang "UMask": "0x1", 3699ecd94f1bSKan Liang "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs TBD", 3700ecd94f1bSKan Liang "MSRValue": "0x1000080100", 3701ecd94f1bSKan Liang "Counter": "0,1,2,3", 3702ecd94f1bSKan Liang "EventName": "OCR.PF_L3_RFO.L3_HIT_E.HITM_OTHER_CORE", 3703ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 3704ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3705ecd94f1bSKan Liang "SampleAfterValue": "100003", 3706ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 3707ecd94f1bSKan Liang }, 3708ecd94f1bSKan Liang { 3709ecd94f1bSKan Liang "Offcore": "1", 3710ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 3711ecd94f1bSKan Liang "UMask": "0x1", 3712ecd94f1bSKan Liang "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs TBD", 3713ecd94f1bSKan Liang "MSRValue": "0x3F80080100", 3714ecd94f1bSKan Liang "Counter": "0,1,2,3", 3715ecd94f1bSKan Liang "EventName": "OCR.PF_L3_RFO.L3_HIT_E.ANY_SNOOP", 3716ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 3717ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3718ecd94f1bSKan Liang "SampleAfterValue": "100003", 3719ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 3720ecd94f1bSKan Liang }, 3721ecd94f1bSKan Liang { 3722ecd94f1bSKan Liang "Offcore": "1", 3723ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 3724ecd94f1bSKan Liang "UMask": "0x1", 3725ecd94f1bSKan Liang "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs", 3726ecd94f1bSKan Liang "MSRValue": "0x0080100100", 3727ecd94f1bSKan Liang "Counter": "0,1,2,3", 3728ecd94f1bSKan Liang "EventName": "OCR.PF_L3_RFO.L3_HIT_S.SNOOP_NONE", 3729ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 3730ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3731ecd94f1bSKan Liang "SampleAfterValue": "100003", 3732ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 3733ecd94f1bSKan Liang }, 3734ecd94f1bSKan Liang { 3735ecd94f1bSKan Liang "Offcore": "1", 3736ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 3737ecd94f1bSKan Liang "UMask": "0x1", 3738ecd94f1bSKan Liang "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs TBD", 3739ecd94f1bSKan Liang "MSRValue": "0x0100100100", 3740ecd94f1bSKan Liang "Counter": "0,1,2,3", 3741ecd94f1bSKan Liang "EventName": "OCR.PF_L3_RFO.L3_HIT_S.NO_SNOOP_NEEDED", 3742ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 3743ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3744ecd94f1bSKan Liang "SampleAfterValue": "100003", 3745ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 3746ecd94f1bSKan Liang }, 3747ecd94f1bSKan Liang { 3748ecd94f1bSKan Liang "Offcore": "1", 3749ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 3750ecd94f1bSKan Liang "UMask": "0x1", 3751ecd94f1bSKan Liang "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs", 3752ecd94f1bSKan Liang "MSRValue": "0x0200100100", 3753ecd94f1bSKan Liang "Counter": "0,1,2,3", 3754ecd94f1bSKan Liang "EventName": "OCR.PF_L3_RFO.L3_HIT_S.SNOOP_MISS", 3755ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 3756ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3757ecd94f1bSKan Liang "SampleAfterValue": "100003", 3758ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 3759ecd94f1bSKan Liang }, 3760ecd94f1bSKan Liang { 3761ecd94f1bSKan Liang "Offcore": "1", 3762ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 3763ecd94f1bSKan Liang "UMask": "0x1", 3764ecd94f1bSKan Liang "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs TBD", 3765ecd94f1bSKan Liang "MSRValue": "0x0400100100", 3766ecd94f1bSKan Liang "Counter": "0,1,2,3", 3767ecd94f1bSKan Liang "EventName": "OCR.PF_L3_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", 3768ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 3769ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3770ecd94f1bSKan Liang "SampleAfterValue": "100003", 3771ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 3772ecd94f1bSKan Liang }, 3773ecd94f1bSKan Liang { 3774ecd94f1bSKan Liang "Offcore": "1", 3775ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 3776ecd94f1bSKan Liang "UMask": "0x1", 3777ecd94f1bSKan Liang "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs TBD", 3778ecd94f1bSKan Liang "MSRValue": "0x0800100100", 3779ecd94f1bSKan Liang "Counter": "0,1,2,3", 3780ecd94f1bSKan Liang "EventName": "OCR.PF_L3_RFO.L3_HIT_S.HIT_OTHER_CORE_FWD", 3781ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 3782ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3783ecd94f1bSKan Liang "SampleAfterValue": "100003", 3784ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 3785ecd94f1bSKan Liang }, 3786ecd94f1bSKan Liang { 3787ecd94f1bSKan Liang "Offcore": "1", 3788ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 3789ecd94f1bSKan Liang "UMask": "0x1", 3790ecd94f1bSKan Liang "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs TBD", 3791ecd94f1bSKan Liang "MSRValue": "0x1000100100", 3792ecd94f1bSKan Liang "Counter": "0,1,2,3", 3793ecd94f1bSKan Liang "EventName": "OCR.PF_L3_RFO.L3_HIT_S.HITM_OTHER_CORE", 3794ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 3795ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3796ecd94f1bSKan Liang "SampleAfterValue": "100003", 3797ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 3798ecd94f1bSKan Liang }, 3799ecd94f1bSKan Liang { 3800ecd94f1bSKan Liang "Offcore": "1", 3801ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 3802ecd94f1bSKan Liang "UMask": "0x1", 3803ecd94f1bSKan Liang "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs TBD", 3804ecd94f1bSKan Liang "MSRValue": "0x3F80100100", 3805ecd94f1bSKan Liang "Counter": "0,1,2,3", 3806ecd94f1bSKan Liang "EventName": "OCR.PF_L3_RFO.L3_HIT_S.ANY_SNOOP", 3807ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 3808ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3809ecd94f1bSKan Liang "SampleAfterValue": "100003", 3810ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 3811ecd94f1bSKan Liang }, 3812ecd94f1bSKan Liang { 3813ecd94f1bSKan Liang "Offcore": "1", 3814ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 3815ecd94f1bSKan Liang "UMask": "0x1", 3816ecd94f1bSKan Liang "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs", 3817ecd94f1bSKan Liang "MSRValue": "0x0080200100", 3818ecd94f1bSKan Liang "Counter": "0,1,2,3", 3819ecd94f1bSKan Liang "EventName": "OCR.PF_L3_RFO.L3_HIT_F.SNOOP_NONE", 3820ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 3821ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3822ecd94f1bSKan Liang "SampleAfterValue": "100003", 3823ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 3824ecd94f1bSKan Liang }, 3825ecd94f1bSKan Liang { 3826ecd94f1bSKan Liang "Offcore": "1", 3827ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 3828ecd94f1bSKan Liang "UMask": "0x1", 3829ecd94f1bSKan Liang "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs TBD", 3830ecd94f1bSKan Liang "MSRValue": "0x0100200100", 3831ecd94f1bSKan Liang "Counter": "0,1,2,3", 3832ecd94f1bSKan Liang "EventName": "OCR.PF_L3_RFO.L3_HIT_F.NO_SNOOP_NEEDED", 3833ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 3834ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3835ecd94f1bSKan Liang "SampleAfterValue": "100003", 3836ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 3837ecd94f1bSKan Liang }, 3838ecd94f1bSKan Liang { 3839ecd94f1bSKan Liang "Offcore": "1", 3840ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 3841ecd94f1bSKan Liang "UMask": "0x1", 3842ecd94f1bSKan Liang "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs", 3843ecd94f1bSKan Liang "MSRValue": "0x0200200100", 3844ecd94f1bSKan Liang "Counter": "0,1,2,3", 3845ecd94f1bSKan Liang "EventName": "OCR.PF_L3_RFO.L3_HIT_F.SNOOP_MISS", 3846ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 3847ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3848ecd94f1bSKan Liang "SampleAfterValue": "100003", 3849ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 3850ecd94f1bSKan Liang }, 3851ecd94f1bSKan Liang { 3852ecd94f1bSKan Liang "Offcore": "1", 3853ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 3854ecd94f1bSKan Liang "UMask": "0x1", 3855ecd94f1bSKan Liang "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs TBD", 3856ecd94f1bSKan Liang "MSRValue": "0x0400200100", 3857ecd94f1bSKan Liang "Counter": "0,1,2,3", 3858ecd94f1bSKan Liang "EventName": "OCR.PF_L3_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", 3859ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 3860ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3861ecd94f1bSKan Liang "SampleAfterValue": "100003", 3862ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 3863ecd94f1bSKan Liang }, 3864ecd94f1bSKan Liang { 3865ecd94f1bSKan Liang "Offcore": "1", 3866ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 3867ecd94f1bSKan Liang "UMask": "0x1", 3868ecd94f1bSKan Liang "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs TBD", 3869ecd94f1bSKan Liang "MSRValue": "0x0800200100", 3870ecd94f1bSKan Liang "Counter": "0,1,2,3", 3871ecd94f1bSKan Liang "EventName": "OCR.PF_L3_RFO.L3_HIT_F.HIT_OTHER_CORE_FWD", 3872ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 3873ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3874ecd94f1bSKan Liang "SampleAfterValue": "100003", 3875ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 3876ecd94f1bSKan Liang }, 3877ecd94f1bSKan Liang { 3878ecd94f1bSKan Liang "Offcore": "1", 3879ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 3880ecd94f1bSKan Liang "UMask": "0x1", 3881ecd94f1bSKan Liang "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs TBD", 3882ecd94f1bSKan Liang "MSRValue": "0x1000200100", 3883ecd94f1bSKan Liang "Counter": "0,1,2,3", 3884ecd94f1bSKan Liang "EventName": "OCR.PF_L3_RFO.L3_HIT_F.HITM_OTHER_CORE", 3885ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 3886ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3887ecd94f1bSKan Liang "SampleAfterValue": "100003", 3888ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 3889ecd94f1bSKan Liang }, 3890ecd94f1bSKan Liang { 3891ecd94f1bSKan Liang "Offcore": "1", 3892ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 3893ecd94f1bSKan Liang "UMask": "0x1", 3894ecd94f1bSKan Liang "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs TBD", 3895ecd94f1bSKan Liang "MSRValue": "0x3F80200100", 3896ecd94f1bSKan Liang "Counter": "0,1,2,3", 3897ecd94f1bSKan Liang "EventName": "OCR.PF_L3_RFO.L3_HIT_F.ANY_SNOOP", 3898ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 3899ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3900ecd94f1bSKan Liang "SampleAfterValue": "100003", 3901ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 3902ecd94f1bSKan Liang }, 3903ecd94f1bSKan Liang { 3904ecd94f1bSKan Liang "Offcore": "1", 3905ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 3906ecd94f1bSKan Liang "UMask": "0x1", 3907ecd94f1bSKan Liang "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs TBD", 3908ecd94f1bSKan Liang "MSRValue": "0x00803C0100", 3909ecd94f1bSKan Liang "Counter": "0,1,2,3", 3910ecd94f1bSKan Liang "EventName": "OCR.PF_L3_RFO.L3_HIT.SNOOP_NONE", 3911ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 3912ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3913ecd94f1bSKan Liang "SampleAfterValue": "100003", 3914ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 3915ecd94f1bSKan Liang }, 3916ecd94f1bSKan Liang { 3917ecd94f1bSKan Liang "Offcore": "1", 3918ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 3919ecd94f1bSKan Liang "UMask": "0x1", 3920ecd94f1bSKan Liang "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs TBD TBD", 3921ecd94f1bSKan Liang "MSRValue": "0x01003C0100", 3922ecd94f1bSKan Liang "Counter": "0,1,2,3", 3923ecd94f1bSKan Liang "EventName": "OCR.PF_L3_RFO.L3_HIT.NO_SNOOP_NEEDED", 3924ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 3925ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3926ecd94f1bSKan Liang "SampleAfterValue": "100003", 3927ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 3928ecd94f1bSKan Liang }, 3929ecd94f1bSKan Liang { 3930ecd94f1bSKan Liang "Offcore": "1", 3931ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 3932ecd94f1bSKan Liang "UMask": "0x1", 3933ecd94f1bSKan Liang "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs TBD", 3934ecd94f1bSKan Liang "MSRValue": "0x02003C0100", 3935ecd94f1bSKan Liang "Counter": "0,1,2,3", 3936ecd94f1bSKan Liang "EventName": "OCR.PF_L3_RFO.L3_HIT.SNOOP_MISS", 3937ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 3938ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3939ecd94f1bSKan Liang "SampleAfterValue": "100003", 3940ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 3941ecd94f1bSKan Liang }, 3942ecd94f1bSKan Liang { 3943ecd94f1bSKan Liang "Offcore": "1", 3944ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 3945ecd94f1bSKan Liang "UMask": "0x1", 3946ecd94f1bSKan Liang "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs TBD TBD", 3947ecd94f1bSKan Liang "MSRValue": "0x04003C0100", 3948ecd94f1bSKan Liang "Counter": "0,1,2,3", 3949ecd94f1bSKan Liang "EventName": "OCR.PF_L3_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD", 3950ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 3951ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3952ecd94f1bSKan Liang "SampleAfterValue": "100003", 3953ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 3954ecd94f1bSKan Liang }, 3955ecd94f1bSKan Liang { 3956ecd94f1bSKan Liang "Offcore": "1", 3957ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 3958ecd94f1bSKan Liang "UMask": "0x1", 3959ecd94f1bSKan Liang "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs TBD TBD", 3960ecd94f1bSKan Liang "MSRValue": "0x08003C0100", 3961ecd94f1bSKan Liang "Counter": "0,1,2,3", 3962ecd94f1bSKan Liang "EventName": "OCR.PF_L3_RFO.L3_HIT.HIT_OTHER_CORE_FWD", 3963ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 3964ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3965ecd94f1bSKan Liang "SampleAfterValue": "100003", 3966ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 3967ecd94f1bSKan Liang }, 3968ecd94f1bSKan Liang { 3969ecd94f1bSKan Liang "Offcore": "1", 3970ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 3971ecd94f1bSKan Liang "UMask": "0x1", 3972ecd94f1bSKan Liang "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs TBD TBD", 3973ecd94f1bSKan Liang "MSRValue": "0x10003C0100", 3974ecd94f1bSKan Liang "Counter": "0,1,2,3", 3975ecd94f1bSKan Liang "EventName": "OCR.PF_L3_RFO.L3_HIT.HITM_OTHER_CORE", 3976ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 3977ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3978ecd94f1bSKan Liang "SampleAfterValue": "100003", 3979ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 3980ecd94f1bSKan Liang }, 3981ecd94f1bSKan Liang { 3982ecd94f1bSKan Liang "Offcore": "1", 3983ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 3984ecd94f1bSKan Liang "UMask": "0x1", 3985ecd94f1bSKan Liang "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs TBD TBD", 3986ecd94f1bSKan Liang "MSRValue": "0x3F803C0100", 3987ecd94f1bSKan Liang "Counter": "0,1,2,3", 3988ecd94f1bSKan Liang "EventName": "OCR.PF_L3_RFO.L3_HIT.ANY_SNOOP", 3989ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 3990ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3991ecd94f1bSKan Liang "SampleAfterValue": "100003", 3992ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 3993ecd94f1bSKan Liang }, 3994ecd94f1bSKan Liang { 3995ecd94f1bSKan Liang "Offcore": "1", 3996ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 3997ecd94f1bSKan Liang "UMask": "0x1", 3998ecd94f1bSKan Liang "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests", 3999ecd94f1bSKan Liang "MSRValue": "0x0080020400", 4000ecd94f1bSKan Liang "Counter": "0,1,2,3", 4001ecd94f1bSKan Liang "EventName": "OCR.PF_L1D_AND_SW.SUPPLIER_NONE.SNOOP_NONE", 4002ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 4003ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4004ecd94f1bSKan Liang "SampleAfterValue": "100003", 4005ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 4006ecd94f1bSKan Liang }, 4007ecd94f1bSKan Liang { 4008ecd94f1bSKan Liang "Offcore": "1", 4009ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 4010ecd94f1bSKan Liang "UMask": "0x1", 4011ecd94f1bSKan Liang "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests TBD", 4012ecd94f1bSKan Liang "MSRValue": "0x0100020400", 4013ecd94f1bSKan Liang "Counter": "0,1,2,3", 4014ecd94f1bSKan Liang "EventName": "OCR.PF_L1D_AND_SW.SUPPLIER_NONE.NO_SNOOP_NEEDED", 4015ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 4016ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4017ecd94f1bSKan Liang "SampleAfterValue": "100003", 4018ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 4019ecd94f1bSKan Liang }, 4020ecd94f1bSKan Liang { 4021ecd94f1bSKan Liang "Offcore": "1", 4022ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 4023ecd94f1bSKan Liang "UMask": "0x1", 4024ecd94f1bSKan Liang "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests", 4025ecd94f1bSKan Liang "MSRValue": "0x0200020400", 4026ecd94f1bSKan Liang "Counter": "0,1,2,3", 4027ecd94f1bSKan Liang "EventName": "OCR.PF_L1D_AND_SW.SUPPLIER_NONE.SNOOP_MISS", 4028ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 4029ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4030ecd94f1bSKan Liang "SampleAfterValue": "100003", 4031ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 4032ecd94f1bSKan Liang }, 4033ecd94f1bSKan Liang { 4034ecd94f1bSKan Liang "Offcore": "1", 4035ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 4036ecd94f1bSKan Liang "UMask": "0x1", 4037ecd94f1bSKan Liang "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests TBD", 4038ecd94f1bSKan Liang "MSRValue": "0x0400020400", 4039ecd94f1bSKan Liang "Counter": "0,1,2,3", 4040ecd94f1bSKan Liang "EventName": "OCR.PF_L1D_AND_SW.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", 4041ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 4042ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4043ecd94f1bSKan Liang "SampleAfterValue": "100003", 4044ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 4045ecd94f1bSKan Liang }, 4046ecd94f1bSKan Liang { 4047ecd94f1bSKan Liang "Offcore": "1", 4048ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 4049ecd94f1bSKan Liang "UMask": "0x1", 4050ecd94f1bSKan Liang "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests TBD", 4051ecd94f1bSKan Liang "MSRValue": "0x0800020400", 4052ecd94f1bSKan Liang "Counter": "0,1,2,3", 4053ecd94f1bSKan Liang "EventName": "OCR.PF_L1D_AND_SW.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", 4054ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 4055ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4056ecd94f1bSKan Liang "SampleAfterValue": "100003", 4057ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 4058ecd94f1bSKan Liang }, 4059ecd94f1bSKan Liang { 4060ecd94f1bSKan Liang "Offcore": "1", 4061ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 4062ecd94f1bSKan Liang "UMask": "0x1", 4063ecd94f1bSKan Liang "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests TBD", 4064ecd94f1bSKan Liang "MSRValue": "0x1000020400", 4065ecd94f1bSKan Liang "Counter": "0,1,2,3", 4066ecd94f1bSKan Liang "EventName": "OCR.PF_L1D_AND_SW.SUPPLIER_NONE.HITM_OTHER_CORE", 4067ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 4068ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4069ecd94f1bSKan Liang "SampleAfterValue": "100003", 4070ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 4071ecd94f1bSKan Liang }, 4072ecd94f1bSKan Liang { 4073ecd94f1bSKan Liang "Offcore": "1", 4074ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 4075ecd94f1bSKan Liang "UMask": "0x1", 4076ecd94f1bSKan Liang "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests TBD", 4077ecd94f1bSKan Liang "MSRValue": "0x3F80020400", 4078ecd94f1bSKan Liang "Counter": "0,1,2,3", 4079ecd94f1bSKan Liang "EventName": "OCR.PF_L1D_AND_SW.SUPPLIER_NONE.ANY_SNOOP", 4080ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 4081ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4082ecd94f1bSKan Liang "SampleAfterValue": "100003", 4083ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 4084ecd94f1bSKan Liang }, 4085ecd94f1bSKan Liang { 4086ecd94f1bSKan Liang "Offcore": "1", 4087ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 4088ecd94f1bSKan Liang "UMask": "0x1", 4089ecd94f1bSKan Liang "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests", 4090ecd94f1bSKan Liang "MSRValue": "0x0080040400", 4091ecd94f1bSKan Liang "Counter": "0,1,2,3", 4092ecd94f1bSKan Liang "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_M.SNOOP_NONE", 4093ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 4094ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4095ecd94f1bSKan Liang "SampleAfterValue": "100003", 4096ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 4097ecd94f1bSKan Liang }, 4098ecd94f1bSKan Liang { 4099ecd94f1bSKan Liang "Offcore": "1", 4100ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 4101ecd94f1bSKan Liang "UMask": "0x1", 4102ecd94f1bSKan Liang "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests TBD", 4103ecd94f1bSKan Liang "MSRValue": "0x0100040400", 4104ecd94f1bSKan Liang "Counter": "0,1,2,3", 4105ecd94f1bSKan Liang "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_M.NO_SNOOP_NEEDED", 4106ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 4107ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4108ecd94f1bSKan Liang "SampleAfterValue": "100003", 4109ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 4110ecd94f1bSKan Liang }, 4111ecd94f1bSKan Liang { 4112ecd94f1bSKan Liang "Offcore": "1", 4113ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 4114ecd94f1bSKan Liang "UMask": "0x1", 4115ecd94f1bSKan Liang "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests", 4116ecd94f1bSKan Liang "MSRValue": "0x0200040400", 4117ecd94f1bSKan Liang "Counter": "0,1,2,3", 4118ecd94f1bSKan Liang "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_M.SNOOP_MISS", 4119ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 4120ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4121ecd94f1bSKan Liang "SampleAfterValue": "100003", 4122ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 4123ecd94f1bSKan Liang }, 4124ecd94f1bSKan Liang { 4125ecd94f1bSKan Liang "Offcore": "1", 4126ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 4127ecd94f1bSKan Liang "UMask": "0x1", 4128ecd94f1bSKan Liang "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests TBD", 4129ecd94f1bSKan Liang "MSRValue": "0x0400040400", 4130ecd94f1bSKan Liang "Counter": "0,1,2,3", 4131ecd94f1bSKan Liang "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", 4132ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 4133ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4134ecd94f1bSKan Liang "SampleAfterValue": "100003", 4135ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 4136ecd94f1bSKan Liang }, 4137ecd94f1bSKan Liang { 4138ecd94f1bSKan Liang "Offcore": "1", 4139ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 4140ecd94f1bSKan Liang "UMask": "0x1", 4141ecd94f1bSKan Liang "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests TBD", 4142ecd94f1bSKan Liang "MSRValue": "0x0800040400", 4143ecd94f1bSKan Liang "Counter": "0,1,2,3", 4144ecd94f1bSKan Liang "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_M.HIT_OTHER_CORE_FWD", 4145ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 4146ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4147ecd94f1bSKan Liang "SampleAfterValue": "100003", 4148ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 4149ecd94f1bSKan Liang }, 4150ecd94f1bSKan Liang { 4151ecd94f1bSKan Liang "Offcore": "1", 4152ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 4153ecd94f1bSKan Liang "UMask": "0x1", 4154ecd94f1bSKan Liang "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests TBD", 4155ecd94f1bSKan Liang "MSRValue": "0x1000040400", 4156ecd94f1bSKan Liang "Counter": "0,1,2,3", 4157ecd94f1bSKan Liang "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_M.HITM_OTHER_CORE", 4158ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 4159ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4160ecd94f1bSKan Liang "SampleAfterValue": "100003", 4161ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 4162ecd94f1bSKan Liang }, 4163ecd94f1bSKan Liang { 4164ecd94f1bSKan Liang "Offcore": "1", 4165ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 4166ecd94f1bSKan Liang "UMask": "0x1", 4167ecd94f1bSKan Liang "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests TBD", 4168ecd94f1bSKan Liang "MSRValue": "0x3F80040400", 4169ecd94f1bSKan Liang "Counter": "0,1,2,3", 4170ecd94f1bSKan Liang "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_M.ANY_SNOOP", 4171ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 4172ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4173ecd94f1bSKan Liang "SampleAfterValue": "100003", 4174ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 4175ecd94f1bSKan Liang }, 4176ecd94f1bSKan Liang { 4177ecd94f1bSKan Liang "Offcore": "1", 4178ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 4179ecd94f1bSKan Liang "UMask": "0x1", 4180ecd94f1bSKan Liang "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests", 4181ecd94f1bSKan Liang "MSRValue": "0x0080080400", 4182ecd94f1bSKan Liang "Counter": "0,1,2,3", 4183ecd94f1bSKan Liang "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_E.SNOOP_NONE", 4184ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 4185ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4186ecd94f1bSKan Liang "SampleAfterValue": "100003", 4187ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 4188ecd94f1bSKan Liang }, 4189ecd94f1bSKan Liang { 4190ecd94f1bSKan Liang "Offcore": "1", 4191ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 4192ecd94f1bSKan Liang "UMask": "0x1", 4193ecd94f1bSKan Liang "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests TBD", 4194ecd94f1bSKan Liang "MSRValue": "0x0100080400", 4195ecd94f1bSKan Liang "Counter": "0,1,2,3", 4196ecd94f1bSKan Liang "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_E.NO_SNOOP_NEEDED", 4197ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 4198ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4199ecd94f1bSKan Liang "SampleAfterValue": "100003", 4200ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 4201ecd94f1bSKan Liang }, 4202ecd94f1bSKan Liang { 4203ecd94f1bSKan Liang "Offcore": "1", 4204ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 4205ecd94f1bSKan Liang "UMask": "0x1", 4206ecd94f1bSKan Liang "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests", 4207ecd94f1bSKan Liang "MSRValue": "0x0200080400", 4208ecd94f1bSKan Liang "Counter": "0,1,2,3", 4209ecd94f1bSKan Liang "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_E.SNOOP_MISS", 4210ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 4211ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4212ecd94f1bSKan Liang "SampleAfterValue": "100003", 4213ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 4214ecd94f1bSKan Liang }, 4215ecd94f1bSKan Liang { 4216ecd94f1bSKan Liang "Offcore": "1", 4217ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 4218ecd94f1bSKan Liang "UMask": "0x1", 4219ecd94f1bSKan Liang "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests TBD", 4220ecd94f1bSKan Liang "MSRValue": "0x0400080400", 4221ecd94f1bSKan Liang "Counter": "0,1,2,3", 4222ecd94f1bSKan Liang "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", 4223ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 4224ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4225ecd94f1bSKan Liang "SampleAfterValue": "100003", 4226ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 4227ecd94f1bSKan Liang }, 4228ecd94f1bSKan Liang { 4229ecd94f1bSKan Liang "Offcore": "1", 4230ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 4231ecd94f1bSKan Liang "UMask": "0x1", 4232ecd94f1bSKan Liang "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests TBD", 4233ecd94f1bSKan Liang "MSRValue": "0x0800080400", 4234ecd94f1bSKan Liang "Counter": "0,1,2,3", 4235ecd94f1bSKan Liang "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_E.HIT_OTHER_CORE_FWD", 4236ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 4237ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4238ecd94f1bSKan Liang "SampleAfterValue": "100003", 4239ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 4240ecd94f1bSKan Liang }, 4241ecd94f1bSKan Liang { 4242ecd94f1bSKan Liang "Offcore": "1", 4243ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 4244ecd94f1bSKan Liang "UMask": "0x1", 4245ecd94f1bSKan Liang "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests TBD", 4246ecd94f1bSKan Liang "MSRValue": "0x1000080400", 4247ecd94f1bSKan Liang "Counter": "0,1,2,3", 4248ecd94f1bSKan Liang "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_E.HITM_OTHER_CORE", 4249ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 4250ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4251ecd94f1bSKan Liang "SampleAfterValue": "100003", 4252ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 4253ecd94f1bSKan Liang }, 4254ecd94f1bSKan Liang { 4255ecd94f1bSKan Liang "Offcore": "1", 4256ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 4257ecd94f1bSKan Liang "UMask": "0x1", 4258ecd94f1bSKan Liang "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests TBD", 4259ecd94f1bSKan Liang "MSRValue": "0x3F80080400", 4260ecd94f1bSKan Liang "Counter": "0,1,2,3", 4261ecd94f1bSKan Liang "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_E.ANY_SNOOP", 4262ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 4263ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4264ecd94f1bSKan Liang "SampleAfterValue": "100003", 4265ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 4266ecd94f1bSKan Liang }, 4267ecd94f1bSKan Liang { 4268ecd94f1bSKan Liang "Offcore": "1", 4269ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 4270ecd94f1bSKan Liang "UMask": "0x1", 4271ecd94f1bSKan Liang "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests", 4272ecd94f1bSKan Liang "MSRValue": "0x0080100400", 4273ecd94f1bSKan Liang "Counter": "0,1,2,3", 4274ecd94f1bSKan Liang "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_S.SNOOP_NONE", 4275ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 4276ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4277ecd94f1bSKan Liang "SampleAfterValue": "100003", 4278ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 4279ecd94f1bSKan Liang }, 4280ecd94f1bSKan Liang { 4281ecd94f1bSKan Liang "Offcore": "1", 4282ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 4283ecd94f1bSKan Liang "UMask": "0x1", 4284ecd94f1bSKan Liang "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests TBD", 4285ecd94f1bSKan Liang "MSRValue": "0x0100100400", 4286ecd94f1bSKan Liang "Counter": "0,1,2,3", 4287ecd94f1bSKan Liang "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_S.NO_SNOOP_NEEDED", 4288ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 4289ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4290ecd94f1bSKan Liang "SampleAfterValue": "100003", 4291ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 4292ecd94f1bSKan Liang }, 4293ecd94f1bSKan Liang { 4294ecd94f1bSKan Liang "Offcore": "1", 4295ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 4296ecd94f1bSKan Liang "UMask": "0x1", 4297ecd94f1bSKan Liang "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests", 4298ecd94f1bSKan Liang "MSRValue": "0x0200100400", 4299ecd94f1bSKan Liang "Counter": "0,1,2,3", 4300ecd94f1bSKan Liang "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_S.SNOOP_MISS", 4301ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 4302ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4303ecd94f1bSKan Liang "SampleAfterValue": "100003", 4304ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 4305ecd94f1bSKan Liang }, 4306ecd94f1bSKan Liang { 4307ecd94f1bSKan Liang "Offcore": "1", 4308ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 4309ecd94f1bSKan Liang "UMask": "0x1", 4310ecd94f1bSKan Liang "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests TBD", 4311ecd94f1bSKan Liang "MSRValue": "0x0400100400", 4312ecd94f1bSKan Liang "Counter": "0,1,2,3", 4313ecd94f1bSKan Liang "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", 4314ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 4315ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4316ecd94f1bSKan Liang "SampleAfterValue": "100003", 4317ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 4318ecd94f1bSKan Liang }, 4319ecd94f1bSKan Liang { 4320ecd94f1bSKan Liang "Offcore": "1", 4321ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 4322ecd94f1bSKan Liang "UMask": "0x1", 4323ecd94f1bSKan Liang "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests TBD", 4324ecd94f1bSKan Liang "MSRValue": "0x0800100400", 4325ecd94f1bSKan Liang "Counter": "0,1,2,3", 4326ecd94f1bSKan Liang "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_S.HIT_OTHER_CORE_FWD", 4327ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 4328ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4329ecd94f1bSKan Liang "SampleAfterValue": "100003", 4330ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 4331ecd94f1bSKan Liang }, 4332ecd94f1bSKan Liang { 4333ecd94f1bSKan Liang "Offcore": "1", 4334ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 4335ecd94f1bSKan Liang "UMask": "0x1", 4336ecd94f1bSKan Liang "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests TBD", 4337ecd94f1bSKan Liang "MSRValue": "0x1000100400", 4338ecd94f1bSKan Liang "Counter": "0,1,2,3", 4339ecd94f1bSKan Liang "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_S.HITM_OTHER_CORE", 4340ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 4341ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4342ecd94f1bSKan Liang "SampleAfterValue": "100003", 4343ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 4344ecd94f1bSKan Liang }, 4345ecd94f1bSKan Liang { 4346ecd94f1bSKan Liang "Offcore": "1", 4347ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 4348ecd94f1bSKan Liang "UMask": "0x1", 4349ecd94f1bSKan Liang "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests TBD", 4350ecd94f1bSKan Liang "MSRValue": "0x3F80100400", 4351ecd94f1bSKan Liang "Counter": "0,1,2,3", 4352ecd94f1bSKan Liang "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_S.ANY_SNOOP", 4353ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 4354ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4355ecd94f1bSKan Liang "SampleAfterValue": "100003", 4356ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 4357ecd94f1bSKan Liang }, 4358ecd94f1bSKan Liang { 4359ecd94f1bSKan Liang "Offcore": "1", 4360ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 4361ecd94f1bSKan Liang "UMask": "0x1", 4362ecd94f1bSKan Liang "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests", 4363ecd94f1bSKan Liang "MSRValue": "0x0080200400", 4364ecd94f1bSKan Liang "Counter": "0,1,2,3", 4365ecd94f1bSKan Liang "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_F.SNOOP_NONE", 4366ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 4367ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4368ecd94f1bSKan Liang "SampleAfterValue": "100003", 4369ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 4370ecd94f1bSKan Liang }, 4371ecd94f1bSKan Liang { 4372ecd94f1bSKan Liang "Offcore": "1", 4373ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 4374ecd94f1bSKan Liang "UMask": "0x1", 4375ecd94f1bSKan Liang "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests TBD", 4376ecd94f1bSKan Liang "MSRValue": "0x0100200400", 4377ecd94f1bSKan Liang "Counter": "0,1,2,3", 4378ecd94f1bSKan Liang "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_F.NO_SNOOP_NEEDED", 4379ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 4380ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4381ecd94f1bSKan Liang "SampleAfterValue": "100003", 4382ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 4383ecd94f1bSKan Liang }, 4384ecd94f1bSKan Liang { 4385ecd94f1bSKan Liang "Offcore": "1", 4386ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 4387ecd94f1bSKan Liang "UMask": "0x1", 4388ecd94f1bSKan Liang "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests", 4389ecd94f1bSKan Liang "MSRValue": "0x0200200400", 4390ecd94f1bSKan Liang "Counter": "0,1,2,3", 4391ecd94f1bSKan Liang "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_F.SNOOP_MISS", 4392ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 4393ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4394ecd94f1bSKan Liang "SampleAfterValue": "100003", 4395ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 4396ecd94f1bSKan Liang }, 4397ecd94f1bSKan Liang { 4398ecd94f1bSKan Liang "Offcore": "1", 4399ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 4400ecd94f1bSKan Liang "UMask": "0x1", 4401ecd94f1bSKan Liang "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests TBD", 4402ecd94f1bSKan Liang "MSRValue": "0x0400200400", 4403ecd94f1bSKan Liang "Counter": "0,1,2,3", 4404ecd94f1bSKan Liang "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", 4405ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 4406ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4407ecd94f1bSKan Liang "SampleAfterValue": "100003", 4408ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 4409ecd94f1bSKan Liang }, 4410ecd94f1bSKan Liang { 4411ecd94f1bSKan Liang "Offcore": "1", 4412ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 4413ecd94f1bSKan Liang "UMask": "0x1", 4414ecd94f1bSKan Liang "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests TBD", 4415ecd94f1bSKan Liang "MSRValue": "0x0800200400", 4416ecd94f1bSKan Liang "Counter": "0,1,2,3", 4417ecd94f1bSKan Liang "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_F.HIT_OTHER_CORE_FWD", 4418ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 4419ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4420ecd94f1bSKan Liang "SampleAfterValue": "100003", 4421ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 4422ecd94f1bSKan Liang }, 4423ecd94f1bSKan Liang { 4424ecd94f1bSKan Liang "Offcore": "1", 4425ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 4426ecd94f1bSKan Liang "UMask": "0x1", 4427ecd94f1bSKan Liang "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests TBD", 4428ecd94f1bSKan Liang "MSRValue": "0x1000200400", 4429ecd94f1bSKan Liang "Counter": "0,1,2,3", 4430ecd94f1bSKan Liang "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_F.HITM_OTHER_CORE", 4431ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 4432ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4433ecd94f1bSKan Liang "SampleAfterValue": "100003", 4434ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 4435ecd94f1bSKan Liang }, 4436ecd94f1bSKan Liang { 4437ecd94f1bSKan Liang "Offcore": "1", 4438ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 4439ecd94f1bSKan Liang "UMask": "0x1", 4440ecd94f1bSKan Liang "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests TBD", 4441ecd94f1bSKan Liang "MSRValue": "0x3F80200400", 4442ecd94f1bSKan Liang "Counter": "0,1,2,3", 4443ecd94f1bSKan Liang "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_F.ANY_SNOOP", 4444ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 4445ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4446ecd94f1bSKan Liang "SampleAfterValue": "100003", 4447ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 4448ecd94f1bSKan Liang }, 4449ecd94f1bSKan Liang { 4450ecd94f1bSKan Liang "Offcore": "1", 4451ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 4452ecd94f1bSKan Liang "UMask": "0x1", 4453ecd94f1bSKan Liang "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests TBD", 4454ecd94f1bSKan Liang "MSRValue": "0x00803C0400", 4455ecd94f1bSKan Liang "Counter": "0,1,2,3", 4456ecd94f1bSKan Liang "EventName": "OCR.PF_L1D_AND_SW.L3_HIT.SNOOP_NONE", 4457ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 4458ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4459ecd94f1bSKan Liang "SampleAfterValue": "100003", 4460ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 4461ecd94f1bSKan Liang }, 4462ecd94f1bSKan Liang { 4463ecd94f1bSKan Liang "Offcore": "1", 4464ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 4465ecd94f1bSKan Liang "UMask": "0x1", 4466ecd94f1bSKan Liang "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests TBD TBD", 4467ecd94f1bSKan Liang "MSRValue": "0x01003C0400", 4468ecd94f1bSKan Liang "Counter": "0,1,2,3", 4469ecd94f1bSKan Liang "EventName": "OCR.PF_L1D_AND_SW.L3_HIT.NO_SNOOP_NEEDED", 4470ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 4471ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4472ecd94f1bSKan Liang "SampleAfterValue": "100003", 4473ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 4474ecd94f1bSKan Liang }, 4475ecd94f1bSKan Liang { 4476ecd94f1bSKan Liang "Offcore": "1", 4477ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 4478ecd94f1bSKan Liang "UMask": "0x1", 4479ecd94f1bSKan Liang "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests TBD", 4480ecd94f1bSKan Liang "MSRValue": "0x02003C0400", 4481ecd94f1bSKan Liang "Counter": "0,1,2,3", 4482ecd94f1bSKan Liang "EventName": "OCR.PF_L1D_AND_SW.L3_HIT.SNOOP_MISS", 4483ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 4484ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4485ecd94f1bSKan Liang "SampleAfterValue": "100003", 4486ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 4487ecd94f1bSKan Liang }, 4488ecd94f1bSKan Liang { 4489ecd94f1bSKan Liang "Offcore": "1", 4490ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 4491ecd94f1bSKan Liang "UMask": "0x1", 4492ecd94f1bSKan Liang "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests TBD TBD", 4493ecd94f1bSKan Liang "MSRValue": "0x04003C0400", 4494ecd94f1bSKan Liang "Counter": "0,1,2,3", 4495ecd94f1bSKan Liang "EventName": "OCR.PF_L1D_AND_SW.L3_HIT.HIT_OTHER_CORE_NO_FWD", 4496ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 4497ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4498ecd94f1bSKan Liang "SampleAfterValue": "100003", 4499ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 4500ecd94f1bSKan Liang }, 4501ecd94f1bSKan Liang { 4502ecd94f1bSKan Liang "Offcore": "1", 4503ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 4504ecd94f1bSKan Liang "UMask": "0x1", 4505ecd94f1bSKan Liang "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests TBD TBD", 4506ecd94f1bSKan Liang "MSRValue": "0x08003C0400", 4507ecd94f1bSKan Liang "Counter": "0,1,2,3", 4508ecd94f1bSKan Liang "EventName": "OCR.PF_L1D_AND_SW.L3_HIT.HIT_OTHER_CORE_FWD", 4509ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 4510ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4511ecd94f1bSKan Liang "SampleAfterValue": "100003", 4512ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 4513ecd94f1bSKan Liang }, 4514ecd94f1bSKan Liang { 4515ecd94f1bSKan Liang "Offcore": "1", 4516ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 4517ecd94f1bSKan Liang "UMask": "0x1", 4518ecd94f1bSKan Liang "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests TBD TBD", 4519ecd94f1bSKan Liang "MSRValue": "0x10003C0400", 4520ecd94f1bSKan Liang "Counter": "0,1,2,3", 4521ecd94f1bSKan Liang "EventName": "OCR.PF_L1D_AND_SW.L3_HIT.HITM_OTHER_CORE", 4522ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 4523ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4524ecd94f1bSKan Liang "SampleAfterValue": "100003", 4525ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 4526ecd94f1bSKan Liang }, 4527ecd94f1bSKan Liang { 4528ecd94f1bSKan Liang "Offcore": "1", 4529ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 4530ecd94f1bSKan Liang "UMask": "0x1", 4531ecd94f1bSKan Liang "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests TBD TBD", 4532ecd94f1bSKan Liang "MSRValue": "0x3F803C0400", 4533ecd94f1bSKan Liang "Counter": "0,1,2,3", 4534ecd94f1bSKan Liang "EventName": "OCR.PF_L1D_AND_SW.L3_HIT.ANY_SNOOP", 4535ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 4536ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4537ecd94f1bSKan Liang "SampleAfterValue": "100003", 4538ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 4539ecd94f1bSKan Liang }, 4540ecd94f1bSKan Liang { 4541ecd94f1bSKan Liang "Offcore": "1", 4542ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 4543ecd94f1bSKan Liang "UMask": "0x1", 4544ecd94f1bSKan Liang "BriefDescription": "Counts any other requests", 4545ecd94f1bSKan Liang "MSRValue": "0x0080028000", 4546ecd94f1bSKan Liang "Counter": "0,1,2,3", 4547ecd94f1bSKan Liang "EventName": "OCR.OTHER.SUPPLIER_NONE.SNOOP_NONE", 4548ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 4549ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4550ecd94f1bSKan Liang "SampleAfterValue": "100003", 4551ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 4552ecd94f1bSKan Liang }, 4553ecd94f1bSKan Liang { 4554ecd94f1bSKan Liang "Offcore": "1", 4555ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 4556ecd94f1bSKan Liang "UMask": "0x1", 4557ecd94f1bSKan Liang "BriefDescription": "Counts any other requests TBD", 4558ecd94f1bSKan Liang "MSRValue": "0x0100028000", 4559ecd94f1bSKan Liang "Counter": "0,1,2,3", 4560ecd94f1bSKan Liang "EventName": "OCR.OTHER.SUPPLIER_NONE.NO_SNOOP_NEEDED", 4561ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 4562ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4563ecd94f1bSKan Liang "SampleAfterValue": "100003", 4564ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 4565ecd94f1bSKan Liang }, 4566ecd94f1bSKan Liang { 4567ecd94f1bSKan Liang "Offcore": "1", 4568ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 4569ecd94f1bSKan Liang "UMask": "0x1", 4570ecd94f1bSKan Liang "BriefDescription": "Counts any other requests", 4571ecd94f1bSKan Liang "MSRValue": "0x0200028000", 4572ecd94f1bSKan Liang "Counter": "0,1,2,3", 4573ecd94f1bSKan Liang "EventName": "OCR.OTHER.SUPPLIER_NONE.SNOOP_MISS", 4574ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 4575ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4576ecd94f1bSKan Liang "SampleAfterValue": "100003", 4577ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 4578ecd94f1bSKan Liang }, 4579ecd94f1bSKan Liang { 4580ecd94f1bSKan Liang "Offcore": "1", 4581ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 4582ecd94f1bSKan Liang "UMask": "0x1", 4583ecd94f1bSKan Liang "BriefDescription": "Counts any other requests TBD", 4584ecd94f1bSKan Liang "MSRValue": "0x0400028000", 4585ecd94f1bSKan Liang "Counter": "0,1,2,3", 4586ecd94f1bSKan Liang "EventName": "OCR.OTHER.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", 4587ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 4588ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4589ecd94f1bSKan Liang "SampleAfterValue": "100003", 4590ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 4591ecd94f1bSKan Liang }, 4592ecd94f1bSKan Liang { 4593ecd94f1bSKan Liang "Offcore": "1", 4594ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 4595ecd94f1bSKan Liang "UMask": "0x1", 4596ecd94f1bSKan Liang "BriefDescription": "Counts any other requests TBD", 4597ecd94f1bSKan Liang "MSRValue": "0x0800028000", 4598ecd94f1bSKan Liang "Counter": "0,1,2,3", 4599ecd94f1bSKan Liang "EventName": "OCR.OTHER.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", 4600ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 4601ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4602ecd94f1bSKan Liang "SampleAfterValue": "100003", 4603ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 4604ecd94f1bSKan Liang }, 4605ecd94f1bSKan Liang { 4606ecd94f1bSKan Liang "Offcore": "1", 4607ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 4608ecd94f1bSKan Liang "UMask": "0x1", 4609ecd94f1bSKan Liang "BriefDescription": "Counts any other requests TBD", 4610ecd94f1bSKan Liang "MSRValue": "0x1000028000", 4611ecd94f1bSKan Liang "Counter": "0,1,2,3", 4612ecd94f1bSKan Liang "EventName": "OCR.OTHER.SUPPLIER_NONE.HITM_OTHER_CORE", 4613ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 4614ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4615ecd94f1bSKan Liang "SampleAfterValue": "100003", 4616ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 4617ecd94f1bSKan Liang }, 4618ecd94f1bSKan Liang { 4619ecd94f1bSKan Liang "Offcore": "1", 4620ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 4621ecd94f1bSKan Liang "UMask": "0x1", 4622ecd94f1bSKan Liang "BriefDescription": "Counts any other requests TBD", 4623ecd94f1bSKan Liang "MSRValue": "0x3F80028000", 4624ecd94f1bSKan Liang "Counter": "0,1,2,3", 4625ecd94f1bSKan Liang "EventName": "OCR.OTHER.SUPPLIER_NONE.ANY_SNOOP", 4626ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 4627ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4628ecd94f1bSKan Liang "SampleAfterValue": "100003", 4629ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 4630ecd94f1bSKan Liang }, 4631ecd94f1bSKan Liang { 4632ecd94f1bSKan Liang "Offcore": "1", 4633ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 4634ecd94f1bSKan Liang "UMask": "0x1", 4635ecd94f1bSKan Liang "BriefDescription": "Counts any other requests", 4636ecd94f1bSKan Liang "MSRValue": "0x0080048000", 4637ecd94f1bSKan Liang "Counter": "0,1,2,3", 4638ecd94f1bSKan Liang "EventName": "OCR.OTHER.L3_HIT_M.SNOOP_NONE", 4639ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 4640ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4641ecd94f1bSKan Liang "SampleAfterValue": "100003", 4642ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 4643ecd94f1bSKan Liang }, 4644ecd94f1bSKan Liang { 4645ecd94f1bSKan Liang "Offcore": "1", 4646ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 4647ecd94f1bSKan Liang "UMask": "0x1", 4648ecd94f1bSKan Liang "BriefDescription": "Counts any other requests TBD", 4649ecd94f1bSKan Liang "MSRValue": "0x0100048000", 4650ecd94f1bSKan Liang "Counter": "0,1,2,3", 4651ecd94f1bSKan Liang "EventName": "OCR.OTHER.L3_HIT_M.NO_SNOOP_NEEDED", 4652ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 4653ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4654ecd94f1bSKan Liang "SampleAfterValue": "100003", 4655ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 4656ecd94f1bSKan Liang }, 4657ecd94f1bSKan Liang { 4658ecd94f1bSKan Liang "Offcore": "1", 4659ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 4660ecd94f1bSKan Liang "UMask": "0x1", 4661ecd94f1bSKan Liang "BriefDescription": "Counts any other requests", 4662ecd94f1bSKan Liang "MSRValue": "0x0200048000", 4663ecd94f1bSKan Liang "Counter": "0,1,2,3", 4664ecd94f1bSKan Liang "EventName": "OCR.OTHER.L3_HIT_M.SNOOP_MISS", 4665ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 4666ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4667ecd94f1bSKan Liang "SampleAfterValue": "100003", 4668ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 4669ecd94f1bSKan Liang }, 4670ecd94f1bSKan Liang { 4671ecd94f1bSKan Liang "Offcore": "1", 4672ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 4673ecd94f1bSKan Liang "UMask": "0x1", 4674ecd94f1bSKan Liang "BriefDescription": "Counts any other requests TBD", 4675ecd94f1bSKan Liang "MSRValue": "0x0400048000", 4676ecd94f1bSKan Liang "Counter": "0,1,2,3", 4677ecd94f1bSKan Liang "EventName": "OCR.OTHER.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", 4678ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 4679ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4680ecd94f1bSKan Liang "SampleAfterValue": "100003", 4681ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 4682ecd94f1bSKan Liang }, 4683ecd94f1bSKan Liang { 4684ecd94f1bSKan Liang "Offcore": "1", 4685ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 4686ecd94f1bSKan Liang "UMask": "0x1", 4687ecd94f1bSKan Liang "BriefDescription": "Counts any other requests TBD", 4688ecd94f1bSKan Liang "MSRValue": "0x0800048000", 4689ecd94f1bSKan Liang "Counter": "0,1,2,3", 4690ecd94f1bSKan Liang "EventName": "OCR.OTHER.L3_HIT_M.HIT_OTHER_CORE_FWD", 4691ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 4692ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4693ecd94f1bSKan Liang "SampleAfterValue": "100003", 4694ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 4695ecd94f1bSKan Liang }, 4696ecd94f1bSKan Liang { 4697ecd94f1bSKan Liang "Offcore": "1", 4698ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 4699ecd94f1bSKan Liang "UMask": "0x1", 4700ecd94f1bSKan Liang "BriefDescription": "Counts any other requests TBD", 4701ecd94f1bSKan Liang "MSRValue": "0x1000048000", 4702ecd94f1bSKan Liang "Counter": "0,1,2,3", 4703ecd94f1bSKan Liang "EventName": "OCR.OTHER.L3_HIT_M.HITM_OTHER_CORE", 4704ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 4705ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4706ecd94f1bSKan Liang "SampleAfterValue": "100003", 4707ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 4708ecd94f1bSKan Liang }, 4709ecd94f1bSKan Liang { 4710ecd94f1bSKan Liang "Offcore": "1", 4711ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 4712ecd94f1bSKan Liang "UMask": "0x1", 4713ecd94f1bSKan Liang "BriefDescription": "Counts any other requests TBD", 4714ecd94f1bSKan Liang "MSRValue": "0x3F80048000", 4715ecd94f1bSKan Liang "Counter": "0,1,2,3", 4716ecd94f1bSKan Liang "EventName": "OCR.OTHER.L3_HIT_M.ANY_SNOOP", 4717ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 4718ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4719ecd94f1bSKan Liang "SampleAfterValue": "100003", 4720ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 4721ecd94f1bSKan Liang }, 4722ecd94f1bSKan Liang { 4723ecd94f1bSKan Liang "Offcore": "1", 4724ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 4725ecd94f1bSKan Liang "UMask": "0x1", 4726ecd94f1bSKan Liang "BriefDescription": "Counts any other requests", 4727ecd94f1bSKan Liang "MSRValue": "0x0080088000", 4728ecd94f1bSKan Liang "Counter": "0,1,2,3", 4729ecd94f1bSKan Liang "EventName": "OCR.OTHER.L3_HIT_E.SNOOP_NONE", 4730ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 4731ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4732ecd94f1bSKan Liang "SampleAfterValue": "100003", 4733ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 4734ecd94f1bSKan Liang }, 4735ecd94f1bSKan Liang { 4736ecd94f1bSKan Liang "Offcore": "1", 4737ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 4738ecd94f1bSKan Liang "UMask": "0x1", 4739ecd94f1bSKan Liang "BriefDescription": "Counts any other requests TBD", 4740ecd94f1bSKan Liang "MSRValue": "0x0100088000", 4741ecd94f1bSKan Liang "Counter": "0,1,2,3", 4742ecd94f1bSKan Liang "EventName": "OCR.OTHER.L3_HIT_E.NO_SNOOP_NEEDED", 4743ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 4744ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4745ecd94f1bSKan Liang "SampleAfterValue": "100003", 4746ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 4747ecd94f1bSKan Liang }, 4748ecd94f1bSKan Liang { 4749ecd94f1bSKan Liang "Offcore": "1", 4750ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 4751ecd94f1bSKan Liang "UMask": "0x1", 4752ecd94f1bSKan Liang "BriefDescription": "Counts any other requests", 4753ecd94f1bSKan Liang "MSRValue": "0x0200088000", 4754ecd94f1bSKan Liang "Counter": "0,1,2,3", 4755ecd94f1bSKan Liang "EventName": "OCR.OTHER.L3_HIT_E.SNOOP_MISS", 4756ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 4757ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4758ecd94f1bSKan Liang "SampleAfterValue": "100003", 4759ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 4760ecd94f1bSKan Liang }, 4761ecd94f1bSKan Liang { 4762ecd94f1bSKan Liang "Offcore": "1", 4763ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 4764ecd94f1bSKan Liang "UMask": "0x1", 4765ecd94f1bSKan Liang "BriefDescription": "Counts any other requests TBD", 4766ecd94f1bSKan Liang "MSRValue": "0x0400088000", 4767ecd94f1bSKan Liang "Counter": "0,1,2,3", 4768ecd94f1bSKan Liang "EventName": "OCR.OTHER.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", 4769ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 4770ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4771ecd94f1bSKan Liang "SampleAfterValue": "100003", 4772ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 4773ecd94f1bSKan Liang }, 4774ecd94f1bSKan Liang { 4775ecd94f1bSKan Liang "Offcore": "1", 4776ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 4777ecd94f1bSKan Liang "UMask": "0x1", 4778ecd94f1bSKan Liang "BriefDescription": "Counts any other requests TBD", 4779ecd94f1bSKan Liang "MSRValue": "0x0800088000", 4780ecd94f1bSKan Liang "Counter": "0,1,2,3", 4781ecd94f1bSKan Liang "EventName": "OCR.OTHER.L3_HIT_E.HIT_OTHER_CORE_FWD", 4782ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 4783ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4784ecd94f1bSKan Liang "SampleAfterValue": "100003", 4785ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 4786ecd94f1bSKan Liang }, 4787ecd94f1bSKan Liang { 4788ecd94f1bSKan Liang "Offcore": "1", 4789ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 4790ecd94f1bSKan Liang "UMask": "0x1", 4791ecd94f1bSKan Liang "BriefDescription": "Counts any other requests TBD", 4792ecd94f1bSKan Liang "MSRValue": "0x1000088000", 4793ecd94f1bSKan Liang "Counter": "0,1,2,3", 4794ecd94f1bSKan Liang "EventName": "OCR.OTHER.L3_HIT_E.HITM_OTHER_CORE", 4795ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 4796ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4797ecd94f1bSKan Liang "SampleAfterValue": "100003", 4798ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 4799ecd94f1bSKan Liang }, 4800ecd94f1bSKan Liang { 4801ecd94f1bSKan Liang "Offcore": "1", 4802ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 4803ecd94f1bSKan Liang "UMask": "0x1", 4804ecd94f1bSKan Liang "BriefDescription": "Counts any other requests TBD", 4805ecd94f1bSKan Liang "MSRValue": "0x3F80088000", 4806ecd94f1bSKan Liang "Counter": "0,1,2,3", 4807ecd94f1bSKan Liang "EventName": "OCR.OTHER.L3_HIT_E.ANY_SNOOP", 4808ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 4809ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4810ecd94f1bSKan Liang "SampleAfterValue": "100003", 4811ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 4812ecd94f1bSKan Liang }, 4813ecd94f1bSKan Liang { 4814ecd94f1bSKan Liang "Offcore": "1", 4815ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 4816ecd94f1bSKan Liang "UMask": "0x1", 4817ecd94f1bSKan Liang "BriefDescription": "Counts any other requests", 4818ecd94f1bSKan Liang "MSRValue": "0x0080108000", 4819ecd94f1bSKan Liang "Counter": "0,1,2,3", 4820ecd94f1bSKan Liang "EventName": "OCR.OTHER.L3_HIT_S.SNOOP_NONE", 4821ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 4822ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4823ecd94f1bSKan Liang "SampleAfterValue": "100003", 4824ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 4825ecd94f1bSKan Liang }, 4826ecd94f1bSKan Liang { 4827ecd94f1bSKan Liang "Offcore": "1", 4828ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 4829ecd94f1bSKan Liang "UMask": "0x1", 4830ecd94f1bSKan Liang "BriefDescription": "Counts any other requests TBD", 4831ecd94f1bSKan Liang "MSRValue": "0x0100108000", 4832ecd94f1bSKan Liang "Counter": "0,1,2,3", 4833ecd94f1bSKan Liang "EventName": "OCR.OTHER.L3_HIT_S.NO_SNOOP_NEEDED", 4834ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 4835ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4836ecd94f1bSKan Liang "SampleAfterValue": "100003", 4837ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 4838ecd94f1bSKan Liang }, 4839ecd94f1bSKan Liang { 4840ecd94f1bSKan Liang "Offcore": "1", 4841ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 4842ecd94f1bSKan Liang "UMask": "0x1", 4843ecd94f1bSKan Liang "BriefDescription": "Counts any other requests", 4844ecd94f1bSKan Liang "MSRValue": "0x0200108000", 4845ecd94f1bSKan Liang "Counter": "0,1,2,3", 4846ecd94f1bSKan Liang "EventName": "OCR.OTHER.L3_HIT_S.SNOOP_MISS", 4847ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 4848ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4849ecd94f1bSKan Liang "SampleAfterValue": "100003", 4850ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 4851ecd94f1bSKan Liang }, 4852ecd94f1bSKan Liang { 4853ecd94f1bSKan Liang "Offcore": "1", 4854ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 4855ecd94f1bSKan Liang "UMask": "0x1", 4856ecd94f1bSKan Liang "BriefDescription": "Counts any other requests TBD", 4857ecd94f1bSKan Liang "MSRValue": "0x0400108000", 4858ecd94f1bSKan Liang "Counter": "0,1,2,3", 4859ecd94f1bSKan Liang "EventName": "OCR.OTHER.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", 4860ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 4861ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4862ecd94f1bSKan Liang "SampleAfterValue": "100003", 4863ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 4864ecd94f1bSKan Liang }, 4865ecd94f1bSKan Liang { 4866ecd94f1bSKan Liang "Offcore": "1", 4867ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 4868ecd94f1bSKan Liang "UMask": "0x1", 4869ecd94f1bSKan Liang "BriefDescription": "Counts any other requests TBD", 4870ecd94f1bSKan Liang "MSRValue": "0x0800108000", 4871ecd94f1bSKan Liang "Counter": "0,1,2,3", 4872ecd94f1bSKan Liang "EventName": "OCR.OTHER.L3_HIT_S.HIT_OTHER_CORE_FWD", 4873ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 4874ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4875ecd94f1bSKan Liang "SampleAfterValue": "100003", 4876ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 4877ecd94f1bSKan Liang }, 4878ecd94f1bSKan Liang { 4879ecd94f1bSKan Liang "Offcore": "1", 4880ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 4881ecd94f1bSKan Liang "UMask": "0x1", 4882ecd94f1bSKan Liang "BriefDescription": "Counts any other requests TBD", 4883ecd94f1bSKan Liang "MSRValue": "0x1000108000", 4884ecd94f1bSKan Liang "Counter": "0,1,2,3", 4885ecd94f1bSKan Liang "EventName": "OCR.OTHER.L3_HIT_S.HITM_OTHER_CORE", 4886ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 4887ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4888ecd94f1bSKan Liang "SampleAfterValue": "100003", 4889ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 4890ecd94f1bSKan Liang }, 4891ecd94f1bSKan Liang { 4892ecd94f1bSKan Liang "Offcore": "1", 4893ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 4894ecd94f1bSKan Liang "UMask": "0x1", 4895ecd94f1bSKan Liang "BriefDescription": "Counts any other requests TBD", 4896ecd94f1bSKan Liang "MSRValue": "0x3F80108000", 4897ecd94f1bSKan Liang "Counter": "0,1,2,3", 4898ecd94f1bSKan Liang "EventName": "OCR.OTHER.L3_HIT_S.ANY_SNOOP", 4899ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 4900ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4901ecd94f1bSKan Liang "SampleAfterValue": "100003", 4902ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 4903ecd94f1bSKan Liang }, 4904ecd94f1bSKan Liang { 4905ecd94f1bSKan Liang "Offcore": "1", 4906ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 4907ecd94f1bSKan Liang "UMask": "0x1", 4908ecd94f1bSKan Liang "BriefDescription": "Counts any other requests", 4909ecd94f1bSKan Liang "MSRValue": "0x0080208000", 4910ecd94f1bSKan Liang "Counter": "0,1,2,3", 4911ecd94f1bSKan Liang "EventName": "OCR.OTHER.L3_HIT_F.SNOOP_NONE", 4912ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 4913ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4914ecd94f1bSKan Liang "SampleAfterValue": "100003", 4915ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 4916ecd94f1bSKan Liang }, 4917ecd94f1bSKan Liang { 4918ecd94f1bSKan Liang "Offcore": "1", 4919ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 4920ecd94f1bSKan Liang "UMask": "0x1", 4921ecd94f1bSKan Liang "BriefDescription": "Counts any other requests TBD", 4922ecd94f1bSKan Liang "MSRValue": "0x0100208000", 4923ecd94f1bSKan Liang "Counter": "0,1,2,3", 4924ecd94f1bSKan Liang "EventName": "OCR.OTHER.L3_HIT_F.NO_SNOOP_NEEDED", 4925ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 4926ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4927ecd94f1bSKan Liang "SampleAfterValue": "100003", 4928ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 4929ecd94f1bSKan Liang }, 4930ecd94f1bSKan Liang { 4931ecd94f1bSKan Liang "Offcore": "1", 4932ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 4933ecd94f1bSKan Liang "UMask": "0x1", 4934ecd94f1bSKan Liang "BriefDescription": "Counts any other requests", 4935ecd94f1bSKan Liang "MSRValue": "0x0200208000", 4936ecd94f1bSKan Liang "Counter": "0,1,2,3", 4937ecd94f1bSKan Liang "EventName": "OCR.OTHER.L3_HIT_F.SNOOP_MISS", 4938ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 4939ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4940ecd94f1bSKan Liang "SampleAfterValue": "100003", 4941ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 4942ecd94f1bSKan Liang }, 4943ecd94f1bSKan Liang { 4944ecd94f1bSKan Liang "Offcore": "1", 4945ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 4946ecd94f1bSKan Liang "UMask": "0x1", 4947ecd94f1bSKan Liang "BriefDescription": "Counts any other requests TBD", 4948ecd94f1bSKan Liang "MSRValue": "0x0400208000", 4949ecd94f1bSKan Liang "Counter": "0,1,2,3", 4950ecd94f1bSKan Liang "EventName": "OCR.OTHER.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", 4951ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 4952ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4953ecd94f1bSKan Liang "SampleAfterValue": "100003", 4954ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 4955ecd94f1bSKan Liang }, 4956ecd94f1bSKan Liang { 4957ecd94f1bSKan Liang "Offcore": "1", 4958ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 4959ecd94f1bSKan Liang "UMask": "0x1", 4960ecd94f1bSKan Liang "BriefDescription": "Counts any other requests TBD", 4961ecd94f1bSKan Liang "MSRValue": "0x0800208000", 4962ecd94f1bSKan Liang "Counter": "0,1,2,3", 4963ecd94f1bSKan Liang "EventName": "OCR.OTHER.L3_HIT_F.HIT_OTHER_CORE_FWD", 4964ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 4965ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4966ecd94f1bSKan Liang "SampleAfterValue": "100003", 4967ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 4968ecd94f1bSKan Liang }, 4969ecd94f1bSKan Liang { 4970ecd94f1bSKan Liang "Offcore": "1", 4971ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 4972ecd94f1bSKan Liang "UMask": "0x1", 4973ecd94f1bSKan Liang "BriefDescription": "Counts any other requests TBD", 4974ecd94f1bSKan Liang "MSRValue": "0x1000208000", 4975ecd94f1bSKan Liang "Counter": "0,1,2,3", 4976ecd94f1bSKan Liang "EventName": "OCR.OTHER.L3_HIT_F.HITM_OTHER_CORE", 4977ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 4978ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4979ecd94f1bSKan Liang "SampleAfterValue": "100003", 4980ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 4981ecd94f1bSKan Liang }, 4982ecd94f1bSKan Liang { 4983ecd94f1bSKan Liang "Offcore": "1", 4984ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 4985ecd94f1bSKan Liang "UMask": "0x1", 4986ecd94f1bSKan Liang "BriefDescription": "Counts any other requests TBD", 4987ecd94f1bSKan Liang "MSRValue": "0x3F80208000", 4988ecd94f1bSKan Liang "Counter": "0,1,2,3", 4989ecd94f1bSKan Liang "EventName": "OCR.OTHER.L3_HIT_F.ANY_SNOOP", 4990ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 4991ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4992ecd94f1bSKan Liang "SampleAfterValue": "100003", 4993ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 4994ecd94f1bSKan Liang }, 4995ecd94f1bSKan Liang { 4996ecd94f1bSKan Liang "Offcore": "1", 4997ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 4998ecd94f1bSKan Liang "UMask": "0x1", 4999ecd94f1bSKan Liang "BriefDescription": "Counts any other requests TBD", 5000ecd94f1bSKan Liang "MSRValue": "0x00803C8000", 5001ecd94f1bSKan Liang "Counter": "0,1,2,3", 5002ecd94f1bSKan Liang "EventName": "OCR.OTHER.L3_HIT.SNOOP_NONE", 5003ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 5004ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5005ecd94f1bSKan Liang "SampleAfterValue": "100003", 5006ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 5007ecd94f1bSKan Liang }, 5008ecd94f1bSKan Liang { 5009ecd94f1bSKan Liang "Offcore": "1", 5010ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 5011ecd94f1bSKan Liang "UMask": "0x1", 5012ecd94f1bSKan Liang "BriefDescription": "Counts any other requests TBD TBD", 5013ecd94f1bSKan Liang "MSRValue": "0x01003C8000", 5014ecd94f1bSKan Liang "Counter": "0,1,2,3", 5015ecd94f1bSKan Liang "EventName": "OCR.OTHER.L3_HIT.NO_SNOOP_NEEDED", 5016ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 5017ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5018ecd94f1bSKan Liang "SampleAfterValue": "100003", 5019ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 5020ecd94f1bSKan Liang }, 5021ecd94f1bSKan Liang { 5022ecd94f1bSKan Liang "Offcore": "1", 5023ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 5024ecd94f1bSKan Liang "UMask": "0x1", 5025ecd94f1bSKan Liang "BriefDescription": "Counts any other requests TBD", 5026ecd94f1bSKan Liang "MSRValue": "0x02003C8000", 5027ecd94f1bSKan Liang "Counter": "0,1,2,3", 5028ecd94f1bSKan Liang "EventName": "OCR.OTHER.L3_HIT.SNOOP_MISS", 5029ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 5030ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5031ecd94f1bSKan Liang "SampleAfterValue": "100003", 5032ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 5033ecd94f1bSKan Liang }, 5034ecd94f1bSKan Liang { 5035ecd94f1bSKan Liang "Offcore": "1", 5036ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 5037ecd94f1bSKan Liang "UMask": "0x1", 5038ecd94f1bSKan Liang "BriefDescription": "Counts any other requests TBD TBD", 5039ecd94f1bSKan Liang "MSRValue": "0x04003C8000", 5040ecd94f1bSKan Liang "Counter": "0,1,2,3", 5041ecd94f1bSKan Liang "EventName": "OCR.OTHER.L3_HIT.HIT_OTHER_CORE_NO_FWD", 5042ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 5043ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5044ecd94f1bSKan Liang "SampleAfterValue": "100003", 5045ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 5046ecd94f1bSKan Liang }, 5047ecd94f1bSKan Liang { 5048ecd94f1bSKan Liang "Offcore": "1", 5049ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 5050ecd94f1bSKan Liang "UMask": "0x1", 5051ecd94f1bSKan Liang "BriefDescription": "Counts any other requests TBD TBD", 5052ecd94f1bSKan Liang "MSRValue": "0x08003C8000", 5053ecd94f1bSKan Liang "Counter": "0,1,2,3", 5054ecd94f1bSKan Liang "EventName": "OCR.OTHER.L3_HIT.HIT_OTHER_CORE_FWD", 5055ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 5056ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5057ecd94f1bSKan Liang "SampleAfterValue": "100003", 5058ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 5059ecd94f1bSKan Liang }, 5060ecd94f1bSKan Liang { 5061ecd94f1bSKan Liang "Offcore": "1", 5062ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 5063ecd94f1bSKan Liang "UMask": "0x1", 5064ecd94f1bSKan Liang "BriefDescription": "Counts any other requests TBD TBD", 5065ecd94f1bSKan Liang "MSRValue": "0x10003C8000", 5066ecd94f1bSKan Liang "Counter": "0,1,2,3", 5067ecd94f1bSKan Liang "EventName": "OCR.OTHER.L3_HIT.HITM_OTHER_CORE", 5068ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 5069ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5070ecd94f1bSKan Liang "SampleAfterValue": "100003", 5071ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 5072ecd94f1bSKan Liang }, 5073ecd94f1bSKan Liang { 5074ecd94f1bSKan Liang "Offcore": "1", 5075ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 5076ecd94f1bSKan Liang "UMask": "0x1", 5077ecd94f1bSKan Liang "BriefDescription": "Counts any other requests TBD TBD", 5078ecd94f1bSKan Liang "MSRValue": "0x3F803C8000", 5079ecd94f1bSKan Liang "Counter": "0,1,2,3", 5080ecd94f1bSKan Liang "EventName": "OCR.OTHER.L3_HIT.ANY_SNOOP", 5081ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 5082ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5083ecd94f1bSKan Liang "SampleAfterValue": "100003", 5084ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 5085ecd94f1bSKan Liang }, 5086ecd94f1bSKan Liang { 5087ecd94f1bSKan Liang "Offcore": "1", 5088ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 5089ecd94f1bSKan Liang "UMask": "0x1", 5090ecd94f1bSKan Liang "BriefDescription": "TBD", 5091ecd94f1bSKan Liang "MSRValue": "0x0080020490", 5092ecd94f1bSKan Liang "Counter": "0,1,2,3", 5093ecd94f1bSKan Liang "EventName": "OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.SNOOP_NONE", 5094ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 5095ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5096ecd94f1bSKan Liang "SampleAfterValue": "100003", 5097ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 5098ecd94f1bSKan Liang }, 5099ecd94f1bSKan Liang { 5100ecd94f1bSKan Liang "Offcore": "1", 5101ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 5102ecd94f1bSKan Liang "UMask": "0x1", 5103ecd94f1bSKan Liang "BriefDescription": "TBD TBD", 5104ecd94f1bSKan Liang "MSRValue": "0x0100020490", 5105ecd94f1bSKan Liang "Counter": "0,1,2,3", 5106ecd94f1bSKan Liang "EventName": "OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED", 5107ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 5108ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5109ecd94f1bSKan Liang "SampleAfterValue": "100003", 5110ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 5111ecd94f1bSKan Liang }, 5112ecd94f1bSKan Liang { 5113ecd94f1bSKan Liang "Offcore": "1", 5114ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 5115ecd94f1bSKan Liang "UMask": "0x1", 5116ecd94f1bSKan Liang "BriefDescription": "TBD", 5117ecd94f1bSKan Liang "MSRValue": "0x0200020490", 5118ecd94f1bSKan Liang "Counter": "0,1,2,3", 5119ecd94f1bSKan Liang "EventName": "OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.SNOOP_MISS", 5120ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 5121ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5122ecd94f1bSKan Liang "SampleAfterValue": "100003", 5123ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 5124ecd94f1bSKan Liang }, 5125ecd94f1bSKan Liang { 5126ecd94f1bSKan Liang "Offcore": "1", 5127ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 5128ecd94f1bSKan Liang "UMask": "0x1", 5129ecd94f1bSKan Liang "BriefDescription": "TBD TBD", 5130ecd94f1bSKan Liang "MSRValue": "0x0400020490", 5131ecd94f1bSKan Liang "Counter": "0,1,2,3", 5132ecd94f1bSKan Liang "EventName": "OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", 5133ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 5134ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5135ecd94f1bSKan Liang "SampleAfterValue": "100003", 5136ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 5137ecd94f1bSKan Liang }, 5138ecd94f1bSKan Liang { 5139ecd94f1bSKan Liang "Offcore": "1", 5140ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 5141ecd94f1bSKan Liang "UMask": "0x1", 5142ecd94f1bSKan Liang "BriefDescription": "TBD TBD", 5143ecd94f1bSKan Liang "MSRValue": "0x0800020490", 5144ecd94f1bSKan Liang "Counter": "0,1,2,3", 5145ecd94f1bSKan Liang "EventName": "OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", 5146ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 5147ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5148ecd94f1bSKan Liang "SampleAfterValue": "100003", 5149ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 5150ecd94f1bSKan Liang }, 5151ecd94f1bSKan Liang { 5152ecd94f1bSKan Liang "Offcore": "1", 5153ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 5154ecd94f1bSKan Liang "UMask": "0x1", 5155ecd94f1bSKan Liang "BriefDescription": "TBD TBD", 5156ecd94f1bSKan Liang "MSRValue": "0x1000020490", 5157ecd94f1bSKan Liang "Counter": "0,1,2,3", 5158ecd94f1bSKan Liang "EventName": "OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.HITM_OTHER_CORE", 5159ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 5160ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5161ecd94f1bSKan Liang "SampleAfterValue": "100003", 5162ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 5163ecd94f1bSKan Liang }, 5164ecd94f1bSKan Liang { 5165ecd94f1bSKan Liang "Offcore": "1", 5166ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 5167ecd94f1bSKan Liang "UMask": "0x1", 5168ecd94f1bSKan Liang "BriefDescription": "TBD TBD", 5169ecd94f1bSKan Liang "MSRValue": "0x3F80020490", 5170ecd94f1bSKan Liang "Counter": "0,1,2,3", 5171ecd94f1bSKan Liang "EventName": "OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.ANY_SNOOP", 5172ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 5173ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5174ecd94f1bSKan Liang "SampleAfterValue": "100003", 5175ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 5176ecd94f1bSKan Liang }, 5177ecd94f1bSKan Liang { 5178ecd94f1bSKan Liang "Offcore": "1", 5179ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 5180ecd94f1bSKan Liang "UMask": "0x1", 5181ecd94f1bSKan Liang "BriefDescription": "TBD", 5182ecd94f1bSKan Liang "MSRValue": "0x0080040490", 5183ecd94f1bSKan Liang "Counter": "0,1,2,3", 5184ecd94f1bSKan Liang "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_M.SNOOP_NONE", 5185ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 5186ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5187ecd94f1bSKan Liang "SampleAfterValue": "100003", 5188ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 5189ecd94f1bSKan Liang }, 5190ecd94f1bSKan Liang { 5191ecd94f1bSKan Liang "Offcore": "1", 5192ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 5193ecd94f1bSKan Liang "UMask": "0x1", 5194ecd94f1bSKan Liang "BriefDescription": "TBD TBD", 5195ecd94f1bSKan Liang "MSRValue": "0x0100040490", 5196ecd94f1bSKan Liang "Counter": "0,1,2,3", 5197ecd94f1bSKan Liang "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDED", 5198ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 5199ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5200ecd94f1bSKan Liang "SampleAfterValue": "100003", 5201ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 5202ecd94f1bSKan Liang }, 5203ecd94f1bSKan Liang { 5204ecd94f1bSKan Liang "Offcore": "1", 5205ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 5206ecd94f1bSKan Liang "UMask": "0x1", 5207ecd94f1bSKan Liang "BriefDescription": "TBD", 5208ecd94f1bSKan Liang "MSRValue": "0x0200040490", 5209ecd94f1bSKan Liang "Counter": "0,1,2,3", 5210ecd94f1bSKan Liang "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_M.SNOOP_MISS", 5211ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 5212ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5213ecd94f1bSKan Liang "SampleAfterValue": "100003", 5214ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 5215ecd94f1bSKan Liang }, 5216ecd94f1bSKan Liang { 5217ecd94f1bSKan Liang "Offcore": "1", 5218ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 5219ecd94f1bSKan Liang "UMask": "0x1", 5220ecd94f1bSKan Liang "BriefDescription": "TBD TBD", 5221ecd94f1bSKan Liang "MSRValue": "0x0400040490", 5222ecd94f1bSKan Liang "Counter": "0,1,2,3", 5223ecd94f1bSKan Liang "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", 5224ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 5225ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5226ecd94f1bSKan Liang "SampleAfterValue": "100003", 5227ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 5228ecd94f1bSKan Liang }, 5229ecd94f1bSKan Liang { 5230ecd94f1bSKan Liang "Offcore": "1", 5231ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 5232ecd94f1bSKan Liang "UMask": "0x1", 5233ecd94f1bSKan Liang "BriefDescription": "TBD TBD", 5234ecd94f1bSKan Liang "MSRValue": "0x0800040490", 5235ecd94f1bSKan Liang "Counter": "0,1,2,3", 5236ecd94f1bSKan Liang "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWD", 5237ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 5238ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5239ecd94f1bSKan Liang "SampleAfterValue": "100003", 5240ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 5241ecd94f1bSKan Liang }, 5242ecd94f1bSKan Liang { 5243ecd94f1bSKan Liang "Offcore": "1", 5244ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 5245ecd94f1bSKan Liang "UMask": "0x1", 5246ecd94f1bSKan Liang "BriefDescription": "TBD TBD", 5247ecd94f1bSKan Liang "MSRValue": "0x1000040490", 5248ecd94f1bSKan Liang "Counter": "0,1,2,3", 5249ecd94f1bSKan Liang "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_M.HITM_OTHER_CORE", 5250ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 5251ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5252ecd94f1bSKan Liang "SampleAfterValue": "100003", 5253ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 5254ecd94f1bSKan Liang }, 5255ecd94f1bSKan Liang { 5256ecd94f1bSKan Liang "Offcore": "1", 5257ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 5258ecd94f1bSKan Liang "UMask": "0x1", 5259ecd94f1bSKan Liang "BriefDescription": "TBD TBD", 5260ecd94f1bSKan Liang "MSRValue": "0x3F80040490", 5261ecd94f1bSKan Liang "Counter": "0,1,2,3", 5262ecd94f1bSKan Liang "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_M.ANY_SNOOP", 5263ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 5264ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5265ecd94f1bSKan Liang "SampleAfterValue": "100003", 5266ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 5267ecd94f1bSKan Liang }, 5268ecd94f1bSKan Liang { 5269ecd94f1bSKan Liang "Offcore": "1", 5270ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 5271ecd94f1bSKan Liang "UMask": "0x1", 5272ecd94f1bSKan Liang "BriefDescription": "TBD", 5273ecd94f1bSKan Liang "MSRValue": "0x0080080490", 5274ecd94f1bSKan Liang "Counter": "0,1,2,3", 5275ecd94f1bSKan Liang "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_E.SNOOP_NONE", 5276ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 5277ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5278ecd94f1bSKan Liang "SampleAfterValue": "100003", 5279ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 5280ecd94f1bSKan Liang }, 5281ecd94f1bSKan Liang { 5282ecd94f1bSKan Liang "Offcore": "1", 5283ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 5284ecd94f1bSKan Liang "UMask": "0x1", 5285ecd94f1bSKan Liang "BriefDescription": "TBD TBD", 5286ecd94f1bSKan Liang "MSRValue": "0x0100080490", 5287ecd94f1bSKan Liang "Counter": "0,1,2,3", 5288ecd94f1bSKan Liang "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDED", 5289ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 5290ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5291ecd94f1bSKan Liang "SampleAfterValue": "100003", 5292ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 5293ecd94f1bSKan Liang }, 5294ecd94f1bSKan Liang { 5295ecd94f1bSKan Liang "Offcore": "1", 5296ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 5297ecd94f1bSKan Liang "UMask": "0x1", 5298ecd94f1bSKan Liang "BriefDescription": "TBD", 5299ecd94f1bSKan Liang "MSRValue": "0x0200080490", 5300ecd94f1bSKan Liang "Counter": "0,1,2,3", 5301ecd94f1bSKan Liang "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_E.SNOOP_MISS", 5302ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 5303ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5304ecd94f1bSKan Liang "SampleAfterValue": "100003", 5305ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 5306ecd94f1bSKan Liang }, 5307ecd94f1bSKan Liang { 5308ecd94f1bSKan Liang "Offcore": "1", 5309ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 5310ecd94f1bSKan Liang "UMask": "0x1", 5311ecd94f1bSKan Liang "BriefDescription": "TBD TBD", 5312ecd94f1bSKan Liang "MSRValue": "0x0400080490", 5313ecd94f1bSKan Liang "Counter": "0,1,2,3", 5314ecd94f1bSKan Liang "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", 5315ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 5316ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5317ecd94f1bSKan Liang "SampleAfterValue": "100003", 5318ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 5319ecd94f1bSKan Liang }, 5320ecd94f1bSKan Liang { 5321ecd94f1bSKan Liang "Offcore": "1", 5322ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 5323ecd94f1bSKan Liang "UMask": "0x1", 5324ecd94f1bSKan Liang "BriefDescription": "TBD TBD", 5325ecd94f1bSKan Liang "MSRValue": "0x0800080490", 5326ecd94f1bSKan Liang "Counter": "0,1,2,3", 5327ecd94f1bSKan Liang "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWD", 5328ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 5329ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5330ecd94f1bSKan Liang "SampleAfterValue": "100003", 5331ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 5332ecd94f1bSKan Liang }, 5333ecd94f1bSKan Liang { 5334ecd94f1bSKan Liang "Offcore": "1", 5335ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 5336ecd94f1bSKan Liang "UMask": "0x1", 5337ecd94f1bSKan Liang "BriefDescription": "TBD TBD", 5338ecd94f1bSKan Liang "MSRValue": "0x1000080490", 5339ecd94f1bSKan Liang "Counter": "0,1,2,3", 5340ecd94f1bSKan Liang "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_E.HITM_OTHER_CORE", 5341ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 5342ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5343ecd94f1bSKan Liang "SampleAfterValue": "100003", 5344ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 5345ecd94f1bSKan Liang }, 5346ecd94f1bSKan Liang { 5347ecd94f1bSKan Liang "Offcore": "1", 5348ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 5349ecd94f1bSKan Liang "UMask": "0x1", 5350ecd94f1bSKan Liang "BriefDescription": "TBD TBD", 5351ecd94f1bSKan Liang "MSRValue": "0x3F80080490", 5352ecd94f1bSKan Liang "Counter": "0,1,2,3", 5353ecd94f1bSKan Liang "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_E.ANY_SNOOP", 5354ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 5355ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5356ecd94f1bSKan Liang "SampleAfterValue": "100003", 5357ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 5358ecd94f1bSKan Liang }, 5359ecd94f1bSKan Liang { 5360ecd94f1bSKan Liang "Offcore": "1", 5361ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 5362ecd94f1bSKan Liang "UMask": "0x1", 5363ecd94f1bSKan Liang "BriefDescription": "TBD", 5364ecd94f1bSKan Liang "MSRValue": "0x0080100490", 5365ecd94f1bSKan Liang "Counter": "0,1,2,3", 5366ecd94f1bSKan Liang "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_S.SNOOP_NONE", 5367ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 5368ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5369ecd94f1bSKan Liang "SampleAfterValue": "100003", 5370ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 5371ecd94f1bSKan Liang }, 5372ecd94f1bSKan Liang { 5373ecd94f1bSKan Liang "Offcore": "1", 5374ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 5375ecd94f1bSKan Liang "UMask": "0x1", 5376ecd94f1bSKan Liang "BriefDescription": "TBD TBD", 5377ecd94f1bSKan Liang "MSRValue": "0x0100100490", 5378ecd94f1bSKan Liang "Counter": "0,1,2,3", 5379ecd94f1bSKan Liang "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDED", 5380ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 5381ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5382ecd94f1bSKan Liang "SampleAfterValue": "100003", 5383ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 5384ecd94f1bSKan Liang }, 5385ecd94f1bSKan Liang { 5386ecd94f1bSKan Liang "Offcore": "1", 5387ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 5388ecd94f1bSKan Liang "UMask": "0x1", 5389ecd94f1bSKan Liang "BriefDescription": "TBD", 5390ecd94f1bSKan Liang "MSRValue": "0x0200100490", 5391ecd94f1bSKan Liang "Counter": "0,1,2,3", 5392ecd94f1bSKan Liang "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_S.SNOOP_MISS", 5393ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 5394ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5395ecd94f1bSKan Liang "SampleAfterValue": "100003", 5396ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 5397ecd94f1bSKan Liang }, 5398ecd94f1bSKan Liang { 5399ecd94f1bSKan Liang "Offcore": "1", 5400ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 5401ecd94f1bSKan Liang "UMask": "0x1", 5402ecd94f1bSKan Liang "BriefDescription": "TBD TBD", 5403ecd94f1bSKan Liang "MSRValue": "0x0400100490", 5404ecd94f1bSKan Liang "Counter": "0,1,2,3", 5405ecd94f1bSKan Liang "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", 5406ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 5407ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5408ecd94f1bSKan Liang "SampleAfterValue": "100003", 5409ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 5410ecd94f1bSKan Liang }, 5411ecd94f1bSKan Liang { 5412ecd94f1bSKan Liang "Offcore": "1", 5413ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 5414ecd94f1bSKan Liang "UMask": "0x1", 5415ecd94f1bSKan Liang "BriefDescription": "TBD TBD", 5416ecd94f1bSKan Liang "MSRValue": "0x0800100490", 5417ecd94f1bSKan Liang "Counter": "0,1,2,3", 5418ecd94f1bSKan Liang "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWD", 5419ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 5420ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5421ecd94f1bSKan Liang "SampleAfterValue": "100003", 5422ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 5423ecd94f1bSKan Liang }, 5424ecd94f1bSKan Liang { 5425ecd94f1bSKan Liang "Offcore": "1", 5426ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 5427ecd94f1bSKan Liang "UMask": "0x1", 5428ecd94f1bSKan Liang "BriefDescription": "TBD TBD", 5429ecd94f1bSKan Liang "MSRValue": "0x1000100490", 5430ecd94f1bSKan Liang "Counter": "0,1,2,3", 5431ecd94f1bSKan Liang "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_S.HITM_OTHER_CORE", 5432ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 5433ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5434ecd94f1bSKan Liang "SampleAfterValue": "100003", 5435ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 5436ecd94f1bSKan Liang }, 5437ecd94f1bSKan Liang { 5438ecd94f1bSKan Liang "Offcore": "1", 5439ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 5440ecd94f1bSKan Liang "UMask": "0x1", 5441ecd94f1bSKan Liang "BriefDescription": "TBD TBD", 5442ecd94f1bSKan Liang "MSRValue": "0x3F80100490", 5443ecd94f1bSKan Liang "Counter": "0,1,2,3", 5444ecd94f1bSKan Liang "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_S.ANY_SNOOP", 5445ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 5446ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5447ecd94f1bSKan Liang "SampleAfterValue": "100003", 5448ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 5449ecd94f1bSKan Liang }, 5450ecd94f1bSKan Liang { 5451ecd94f1bSKan Liang "Offcore": "1", 5452ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 5453ecd94f1bSKan Liang "UMask": "0x1", 5454ecd94f1bSKan Liang "BriefDescription": "TBD", 5455ecd94f1bSKan Liang "MSRValue": "0x0080200490", 5456ecd94f1bSKan Liang "Counter": "0,1,2,3", 5457ecd94f1bSKan Liang "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_F.SNOOP_NONE", 5458ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 5459ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5460ecd94f1bSKan Liang "SampleAfterValue": "100003", 5461ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 5462ecd94f1bSKan Liang }, 5463ecd94f1bSKan Liang { 5464ecd94f1bSKan Liang "Offcore": "1", 5465ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 5466ecd94f1bSKan Liang "UMask": "0x1", 5467ecd94f1bSKan Liang "BriefDescription": "TBD TBD", 5468ecd94f1bSKan Liang "MSRValue": "0x0100200490", 5469ecd94f1bSKan Liang "Counter": "0,1,2,3", 5470ecd94f1bSKan Liang "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDED", 5471ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 5472ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5473ecd94f1bSKan Liang "SampleAfterValue": "100003", 5474ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 5475ecd94f1bSKan Liang }, 5476ecd94f1bSKan Liang { 5477ecd94f1bSKan Liang "Offcore": "1", 5478ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 5479ecd94f1bSKan Liang "UMask": "0x1", 5480ecd94f1bSKan Liang "BriefDescription": "TBD", 5481ecd94f1bSKan Liang "MSRValue": "0x0200200490", 5482ecd94f1bSKan Liang "Counter": "0,1,2,3", 5483ecd94f1bSKan Liang "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_F.SNOOP_MISS", 5484ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 5485ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5486ecd94f1bSKan Liang "SampleAfterValue": "100003", 5487ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 5488ecd94f1bSKan Liang }, 5489ecd94f1bSKan Liang { 5490ecd94f1bSKan Liang "Offcore": "1", 5491ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 5492ecd94f1bSKan Liang "UMask": "0x1", 5493ecd94f1bSKan Liang "BriefDescription": "TBD TBD", 5494ecd94f1bSKan Liang "MSRValue": "0x0400200490", 5495ecd94f1bSKan Liang "Counter": "0,1,2,3", 5496ecd94f1bSKan Liang "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", 5497ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 5498ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5499ecd94f1bSKan Liang "SampleAfterValue": "100003", 5500ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 5501ecd94f1bSKan Liang }, 5502ecd94f1bSKan Liang { 5503ecd94f1bSKan Liang "Offcore": "1", 5504ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 5505ecd94f1bSKan Liang "UMask": "0x1", 5506ecd94f1bSKan Liang "BriefDescription": "TBD TBD", 5507ecd94f1bSKan Liang "MSRValue": "0x0800200490", 5508ecd94f1bSKan Liang "Counter": "0,1,2,3", 5509ecd94f1bSKan Liang "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWD", 5510ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 5511ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5512ecd94f1bSKan Liang "SampleAfterValue": "100003", 5513ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 5514ecd94f1bSKan Liang }, 5515ecd94f1bSKan Liang { 5516ecd94f1bSKan Liang "Offcore": "1", 5517ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 5518ecd94f1bSKan Liang "UMask": "0x1", 5519ecd94f1bSKan Liang "BriefDescription": "TBD TBD", 5520ecd94f1bSKan Liang "MSRValue": "0x1000200490", 5521ecd94f1bSKan Liang "Counter": "0,1,2,3", 5522ecd94f1bSKan Liang "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_F.HITM_OTHER_CORE", 5523ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 5524ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5525ecd94f1bSKan Liang "SampleAfterValue": "100003", 5526ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 5527ecd94f1bSKan Liang }, 5528ecd94f1bSKan Liang { 5529ecd94f1bSKan Liang "Offcore": "1", 5530ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 5531ecd94f1bSKan Liang "UMask": "0x1", 5532ecd94f1bSKan Liang "BriefDescription": "TBD TBD", 5533ecd94f1bSKan Liang "MSRValue": "0x3F80200490", 5534ecd94f1bSKan Liang "Counter": "0,1,2,3", 5535ecd94f1bSKan Liang "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_F.ANY_SNOOP", 5536ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 5537ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5538ecd94f1bSKan Liang "SampleAfterValue": "100003", 5539ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 5540ecd94f1bSKan Liang }, 5541ecd94f1bSKan Liang { 5542ecd94f1bSKan Liang "Offcore": "1", 5543ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 5544ecd94f1bSKan Liang "UMask": "0x1", 5545ecd94f1bSKan Liang "BriefDescription": "TBD TBD", 5546ecd94f1bSKan Liang "MSRValue": "0x00803C0490", 5547ecd94f1bSKan Liang "Counter": "0,1,2,3", 5548ecd94f1bSKan Liang "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT.SNOOP_NONE", 5549ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 5550ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5551ecd94f1bSKan Liang "SampleAfterValue": "100003", 5552ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 5553ecd94f1bSKan Liang }, 5554ecd94f1bSKan Liang { 5555ecd94f1bSKan Liang "Offcore": "1", 5556ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 5557ecd94f1bSKan Liang "UMask": "0x1", 5558ecd94f1bSKan Liang "BriefDescription": "TBD TBD TBD", 5559ecd94f1bSKan Liang "MSRValue": "0x01003C0490", 5560ecd94f1bSKan Liang "Counter": "0,1,2,3", 5561ecd94f1bSKan Liang "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT.NO_SNOOP_NEEDED", 5562ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 5563ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5564ecd94f1bSKan Liang "SampleAfterValue": "100003", 5565ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 5566ecd94f1bSKan Liang }, 5567ecd94f1bSKan Liang { 5568ecd94f1bSKan Liang "Offcore": "1", 5569ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 5570ecd94f1bSKan Liang "UMask": "0x1", 5571ecd94f1bSKan Liang "BriefDescription": "TBD TBD", 5572ecd94f1bSKan Liang "MSRValue": "0x02003C0490", 5573ecd94f1bSKan Liang "Counter": "0,1,2,3", 5574ecd94f1bSKan Liang "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT.SNOOP_MISS", 5575ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 5576ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5577ecd94f1bSKan Liang "SampleAfterValue": "100003", 5578ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 5579ecd94f1bSKan Liang }, 5580ecd94f1bSKan Liang { 5581ecd94f1bSKan Liang "Offcore": "1", 5582ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 5583ecd94f1bSKan Liang "UMask": "0x1", 5584ecd94f1bSKan Liang "BriefDescription": "TBD TBD TBD", 5585ecd94f1bSKan Liang "MSRValue": "0x04003C0490", 5586ecd94f1bSKan Liang "Counter": "0,1,2,3", 5587ecd94f1bSKan Liang "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD", 5588ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 5589ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5590ecd94f1bSKan Liang "SampleAfterValue": "100003", 5591ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 5592ecd94f1bSKan Liang }, 5593ecd94f1bSKan Liang { 5594ecd94f1bSKan Liang "Offcore": "1", 5595ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 5596ecd94f1bSKan Liang "UMask": "0x1", 5597ecd94f1bSKan Liang "BriefDescription": "TBD TBD TBD", 5598ecd94f1bSKan Liang "MSRValue": "0x08003C0490", 5599ecd94f1bSKan Liang "Counter": "0,1,2,3", 5600ecd94f1bSKan Liang "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD", 5601ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 5602ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5603ecd94f1bSKan Liang "SampleAfterValue": "100003", 5604ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 5605ecd94f1bSKan Liang }, 5606ecd94f1bSKan Liang { 5607ecd94f1bSKan Liang "Offcore": "1", 5608ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 5609ecd94f1bSKan Liang "UMask": "0x1", 5610ecd94f1bSKan Liang "BriefDescription": "TBD TBD TBD", 5611ecd94f1bSKan Liang "MSRValue": "0x10003C0490", 5612ecd94f1bSKan Liang "Counter": "0,1,2,3", 5613ecd94f1bSKan Liang "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT.HITM_OTHER_CORE", 5614ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 5615ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5616ecd94f1bSKan Liang "SampleAfterValue": "100003", 5617ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 5618ecd94f1bSKan Liang }, 5619ecd94f1bSKan Liang { 5620ecd94f1bSKan Liang "Offcore": "1", 5621ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 5622ecd94f1bSKan Liang "UMask": "0x1", 5623ecd94f1bSKan Liang "BriefDescription": "TBD TBD TBD", 5624ecd94f1bSKan Liang "MSRValue": "0x3F803C0490", 5625ecd94f1bSKan Liang "Counter": "0,1,2,3", 5626ecd94f1bSKan Liang "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT.ANY_SNOOP", 5627ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 5628ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5629ecd94f1bSKan Liang "SampleAfterValue": "100003", 5630ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 5631ecd94f1bSKan Liang }, 5632ecd94f1bSKan Liang { 5633ecd94f1bSKan Liang "Offcore": "1", 5634ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 5635ecd94f1bSKan Liang "UMask": "0x1", 5636ecd94f1bSKan Liang "BriefDescription": "TBD", 5637ecd94f1bSKan Liang "MSRValue": "0x0080020120", 5638ecd94f1bSKan Liang "Counter": "0,1,2,3", 5639ecd94f1bSKan Liang "EventName": "OCR.ALL_PF_RFO.SUPPLIER_NONE.SNOOP_NONE", 5640ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 5641ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5642ecd94f1bSKan Liang "SampleAfterValue": "100003", 5643ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 5644ecd94f1bSKan Liang }, 5645ecd94f1bSKan Liang { 5646ecd94f1bSKan Liang "Offcore": "1", 5647ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 5648ecd94f1bSKan Liang "UMask": "0x1", 5649ecd94f1bSKan Liang "BriefDescription": "TBD TBD", 5650ecd94f1bSKan Liang "MSRValue": "0x0100020120", 5651ecd94f1bSKan Liang "Counter": "0,1,2,3", 5652ecd94f1bSKan Liang "EventName": "OCR.ALL_PF_RFO.SUPPLIER_NONE.NO_SNOOP_NEEDED", 5653ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 5654ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5655ecd94f1bSKan Liang "SampleAfterValue": "100003", 5656ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 5657ecd94f1bSKan Liang }, 5658ecd94f1bSKan Liang { 5659ecd94f1bSKan Liang "Offcore": "1", 5660ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 5661ecd94f1bSKan Liang "UMask": "0x1", 5662ecd94f1bSKan Liang "BriefDescription": "TBD", 5663ecd94f1bSKan Liang "MSRValue": "0x0200020120", 5664ecd94f1bSKan Liang "Counter": "0,1,2,3", 5665ecd94f1bSKan Liang "EventName": "OCR.ALL_PF_RFO.SUPPLIER_NONE.SNOOP_MISS", 5666ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 5667ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5668ecd94f1bSKan Liang "SampleAfterValue": "100003", 5669ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 5670ecd94f1bSKan Liang }, 5671ecd94f1bSKan Liang { 5672ecd94f1bSKan Liang "Offcore": "1", 5673ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 5674ecd94f1bSKan Liang "UMask": "0x1", 5675ecd94f1bSKan Liang "BriefDescription": "TBD TBD", 5676ecd94f1bSKan Liang "MSRValue": "0x0400020120", 5677ecd94f1bSKan Liang "Counter": "0,1,2,3", 5678ecd94f1bSKan Liang "EventName": "OCR.ALL_PF_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", 5679ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 5680ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5681ecd94f1bSKan Liang "SampleAfterValue": "100003", 5682ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 5683ecd94f1bSKan Liang }, 5684ecd94f1bSKan Liang { 5685ecd94f1bSKan Liang "Offcore": "1", 5686ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 5687ecd94f1bSKan Liang "UMask": "0x1", 5688ecd94f1bSKan Liang "BriefDescription": "TBD TBD", 5689ecd94f1bSKan Liang "MSRValue": "0x0800020120", 5690ecd94f1bSKan Liang "Counter": "0,1,2,3", 5691ecd94f1bSKan Liang "EventName": "OCR.ALL_PF_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", 5692ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 5693ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5694ecd94f1bSKan Liang "SampleAfterValue": "100003", 5695ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 5696ecd94f1bSKan Liang }, 5697ecd94f1bSKan Liang { 5698ecd94f1bSKan Liang "Offcore": "1", 5699ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 5700ecd94f1bSKan Liang "UMask": "0x1", 5701ecd94f1bSKan Liang "BriefDescription": "TBD TBD", 5702ecd94f1bSKan Liang "MSRValue": "0x1000020120", 5703ecd94f1bSKan Liang "Counter": "0,1,2,3", 5704ecd94f1bSKan Liang "EventName": "OCR.ALL_PF_RFO.SUPPLIER_NONE.HITM_OTHER_CORE", 5705ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 5706ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5707ecd94f1bSKan Liang "SampleAfterValue": "100003", 5708ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 5709ecd94f1bSKan Liang }, 5710ecd94f1bSKan Liang { 5711ecd94f1bSKan Liang "Offcore": "1", 5712ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 5713ecd94f1bSKan Liang "UMask": "0x1", 5714ecd94f1bSKan Liang "BriefDescription": "TBD TBD", 5715ecd94f1bSKan Liang "MSRValue": "0x3F80020120", 5716ecd94f1bSKan Liang "Counter": "0,1,2,3", 5717ecd94f1bSKan Liang "EventName": "OCR.ALL_PF_RFO.SUPPLIER_NONE.ANY_SNOOP", 5718ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 5719ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5720ecd94f1bSKan Liang "SampleAfterValue": "100003", 5721ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 5722ecd94f1bSKan Liang }, 5723ecd94f1bSKan Liang { 5724ecd94f1bSKan Liang "Offcore": "1", 5725ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 5726ecd94f1bSKan Liang "UMask": "0x1", 5727ecd94f1bSKan Liang "BriefDescription": "TBD", 5728ecd94f1bSKan Liang "MSRValue": "0x0080040120", 5729ecd94f1bSKan Liang "Counter": "0,1,2,3", 5730ecd94f1bSKan Liang "EventName": "OCR.ALL_PF_RFO.L3_HIT_M.SNOOP_NONE", 5731ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 5732ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5733ecd94f1bSKan Liang "SampleAfterValue": "100003", 5734ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 5735ecd94f1bSKan Liang }, 5736ecd94f1bSKan Liang { 5737ecd94f1bSKan Liang "Offcore": "1", 5738ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 5739ecd94f1bSKan Liang "UMask": "0x1", 5740ecd94f1bSKan Liang "BriefDescription": "TBD TBD", 5741ecd94f1bSKan Liang "MSRValue": "0x0100040120", 5742ecd94f1bSKan Liang "Counter": "0,1,2,3", 5743ecd94f1bSKan Liang "EventName": "OCR.ALL_PF_RFO.L3_HIT_M.NO_SNOOP_NEEDED", 5744ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 5745ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5746ecd94f1bSKan Liang "SampleAfterValue": "100003", 5747ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 5748ecd94f1bSKan Liang }, 5749ecd94f1bSKan Liang { 5750ecd94f1bSKan Liang "Offcore": "1", 5751ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 5752ecd94f1bSKan Liang "UMask": "0x1", 5753ecd94f1bSKan Liang "BriefDescription": "TBD", 5754ecd94f1bSKan Liang "MSRValue": "0x0200040120", 5755ecd94f1bSKan Liang "Counter": "0,1,2,3", 5756ecd94f1bSKan Liang "EventName": "OCR.ALL_PF_RFO.L3_HIT_M.SNOOP_MISS", 5757ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 5758ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5759ecd94f1bSKan Liang "SampleAfterValue": "100003", 5760ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 5761ecd94f1bSKan Liang }, 5762ecd94f1bSKan Liang { 5763ecd94f1bSKan Liang "Offcore": "1", 5764ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 5765ecd94f1bSKan Liang "UMask": "0x1", 5766ecd94f1bSKan Liang "BriefDescription": "TBD TBD", 5767ecd94f1bSKan Liang "MSRValue": "0x0400040120", 5768ecd94f1bSKan Liang "Counter": "0,1,2,3", 5769ecd94f1bSKan Liang "EventName": "OCR.ALL_PF_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", 5770ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 5771ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5772ecd94f1bSKan Liang "SampleAfterValue": "100003", 5773ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 5774ecd94f1bSKan Liang }, 5775ecd94f1bSKan Liang { 5776ecd94f1bSKan Liang "Offcore": "1", 5777ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 5778ecd94f1bSKan Liang "UMask": "0x1", 5779ecd94f1bSKan Liang "BriefDescription": "TBD TBD", 5780ecd94f1bSKan Liang "MSRValue": "0x0800040120", 5781ecd94f1bSKan Liang "Counter": "0,1,2,3", 5782ecd94f1bSKan Liang "EventName": "OCR.ALL_PF_RFO.L3_HIT_M.HIT_OTHER_CORE_FWD", 5783ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 5784ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5785ecd94f1bSKan Liang "SampleAfterValue": "100003", 5786ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 5787ecd94f1bSKan Liang }, 5788ecd94f1bSKan Liang { 5789ecd94f1bSKan Liang "Offcore": "1", 5790ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 5791ecd94f1bSKan Liang "UMask": "0x1", 5792ecd94f1bSKan Liang "BriefDescription": "TBD TBD", 5793ecd94f1bSKan Liang "MSRValue": "0x1000040120", 5794ecd94f1bSKan Liang "Counter": "0,1,2,3", 5795ecd94f1bSKan Liang "EventName": "OCR.ALL_PF_RFO.L3_HIT_M.HITM_OTHER_CORE", 5796ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 5797ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5798ecd94f1bSKan Liang "SampleAfterValue": "100003", 5799ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 5800ecd94f1bSKan Liang }, 5801ecd94f1bSKan Liang { 5802ecd94f1bSKan Liang "Offcore": "1", 5803ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 5804ecd94f1bSKan Liang "UMask": "0x1", 5805ecd94f1bSKan Liang "BriefDescription": "TBD TBD", 5806ecd94f1bSKan Liang "MSRValue": "0x3F80040120", 5807ecd94f1bSKan Liang "Counter": "0,1,2,3", 5808ecd94f1bSKan Liang "EventName": "OCR.ALL_PF_RFO.L3_HIT_M.ANY_SNOOP", 5809ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 5810ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5811ecd94f1bSKan Liang "SampleAfterValue": "100003", 5812ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 5813ecd94f1bSKan Liang }, 5814ecd94f1bSKan Liang { 5815ecd94f1bSKan Liang "Offcore": "1", 5816ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 5817ecd94f1bSKan Liang "UMask": "0x1", 5818ecd94f1bSKan Liang "BriefDescription": "TBD", 5819ecd94f1bSKan Liang "MSRValue": "0x0080080120", 5820ecd94f1bSKan Liang "Counter": "0,1,2,3", 5821ecd94f1bSKan Liang "EventName": "OCR.ALL_PF_RFO.L3_HIT_E.SNOOP_NONE", 5822ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 5823ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5824ecd94f1bSKan Liang "SampleAfterValue": "100003", 5825ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 5826ecd94f1bSKan Liang }, 5827ecd94f1bSKan Liang { 5828ecd94f1bSKan Liang "Offcore": "1", 5829ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 5830ecd94f1bSKan Liang "UMask": "0x1", 5831ecd94f1bSKan Liang "BriefDescription": "TBD TBD", 5832ecd94f1bSKan Liang "MSRValue": "0x0100080120", 5833ecd94f1bSKan Liang "Counter": "0,1,2,3", 5834ecd94f1bSKan Liang "EventName": "OCR.ALL_PF_RFO.L3_HIT_E.NO_SNOOP_NEEDED", 5835ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 5836ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5837ecd94f1bSKan Liang "SampleAfterValue": "100003", 5838ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 5839ecd94f1bSKan Liang }, 5840ecd94f1bSKan Liang { 5841ecd94f1bSKan Liang "Offcore": "1", 5842ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 5843ecd94f1bSKan Liang "UMask": "0x1", 5844ecd94f1bSKan Liang "BriefDescription": "TBD", 5845ecd94f1bSKan Liang "MSRValue": "0x0200080120", 5846ecd94f1bSKan Liang "Counter": "0,1,2,3", 5847ecd94f1bSKan Liang "EventName": "OCR.ALL_PF_RFO.L3_HIT_E.SNOOP_MISS", 5848ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 5849ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5850ecd94f1bSKan Liang "SampleAfterValue": "100003", 5851ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 5852ecd94f1bSKan Liang }, 5853ecd94f1bSKan Liang { 5854ecd94f1bSKan Liang "Offcore": "1", 5855ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 5856ecd94f1bSKan Liang "UMask": "0x1", 5857ecd94f1bSKan Liang "BriefDescription": "TBD TBD", 5858ecd94f1bSKan Liang "MSRValue": "0x0400080120", 5859ecd94f1bSKan Liang "Counter": "0,1,2,3", 5860ecd94f1bSKan Liang "EventName": "OCR.ALL_PF_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", 5861ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 5862ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5863ecd94f1bSKan Liang "SampleAfterValue": "100003", 5864ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 5865ecd94f1bSKan Liang }, 5866ecd94f1bSKan Liang { 5867ecd94f1bSKan Liang "Offcore": "1", 5868ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 5869ecd94f1bSKan Liang "UMask": "0x1", 5870ecd94f1bSKan Liang "BriefDescription": "TBD TBD", 5871ecd94f1bSKan Liang "MSRValue": "0x0800080120", 5872ecd94f1bSKan Liang "Counter": "0,1,2,3", 5873ecd94f1bSKan Liang "EventName": "OCR.ALL_PF_RFO.L3_HIT_E.HIT_OTHER_CORE_FWD", 5874ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 5875ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5876ecd94f1bSKan Liang "SampleAfterValue": "100003", 5877ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 5878ecd94f1bSKan Liang }, 5879ecd94f1bSKan Liang { 5880ecd94f1bSKan Liang "Offcore": "1", 5881ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 5882ecd94f1bSKan Liang "UMask": "0x1", 5883ecd94f1bSKan Liang "BriefDescription": "TBD TBD", 5884ecd94f1bSKan Liang "MSRValue": "0x1000080120", 5885ecd94f1bSKan Liang "Counter": "0,1,2,3", 5886ecd94f1bSKan Liang "EventName": "OCR.ALL_PF_RFO.L3_HIT_E.HITM_OTHER_CORE", 5887ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 5888ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5889ecd94f1bSKan Liang "SampleAfterValue": "100003", 5890ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 5891ecd94f1bSKan Liang }, 5892ecd94f1bSKan Liang { 5893ecd94f1bSKan Liang "Offcore": "1", 5894ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 5895ecd94f1bSKan Liang "UMask": "0x1", 5896ecd94f1bSKan Liang "BriefDescription": "TBD TBD", 5897ecd94f1bSKan Liang "MSRValue": "0x3F80080120", 5898ecd94f1bSKan Liang "Counter": "0,1,2,3", 5899ecd94f1bSKan Liang "EventName": "OCR.ALL_PF_RFO.L3_HIT_E.ANY_SNOOP", 5900ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 5901ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5902ecd94f1bSKan Liang "SampleAfterValue": "100003", 5903ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 5904ecd94f1bSKan Liang }, 5905ecd94f1bSKan Liang { 5906ecd94f1bSKan Liang "Offcore": "1", 5907ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 5908ecd94f1bSKan Liang "UMask": "0x1", 5909ecd94f1bSKan Liang "BriefDescription": "TBD", 5910ecd94f1bSKan Liang "MSRValue": "0x0080100120", 5911ecd94f1bSKan Liang "Counter": "0,1,2,3", 5912ecd94f1bSKan Liang "EventName": "OCR.ALL_PF_RFO.L3_HIT_S.SNOOP_NONE", 5913ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 5914ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5915ecd94f1bSKan Liang "SampleAfterValue": "100003", 5916ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 5917ecd94f1bSKan Liang }, 5918ecd94f1bSKan Liang { 5919ecd94f1bSKan Liang "Offcore": "1", 5920ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 5921ecd94f1bSKan Liang "UMask": "0x1", 5922ecd94f1bSKan Liang "BriefDescription": "TBD TBD", 5923ecd94f1bSKan Liang "MSRValue": "0x0100100120", 5924ecd94f1bSKan Liang "Counter": "0,1,2,3", 5925ecd94f1bSKan Liang "EventName": "OCR.ALL_PF_RFO.L3_HIT_S.NO_SNOOP_NEEDED", 5926ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 5927ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5928ecd94f1bSKan Liang "SampleAfterValue": "100003", 5929ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 5930ecd94f1bSKan Liang }, 5931ecd94f1bSKan Liang { 5932ecd94f1bSKan Liang "Offcore": "1", 5933ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 5934ecd94f1bSKan Liang "UMask": "0x1", 5935ecd94f1bSKan Liang "BriefDescription": "TBD", 5936ecd94f1bSKan Liang "MSRValue": "0x0200100120", 5937ecd94f1bSKan Liang "Counter": "0,1,2,3", 5938ecd94f1bSKan Liang "EventName": "OCR.ALL_PF_RFO.L3_HIT_S.SNOOP_MISS", 5939ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 5940ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5941ecd94f1bSKan Liang "SampleAfterValue": "100003", 5942ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 5943ecd94f1bSKan Liang }, 5944ecd94f1bSKan Liang { 5945ecd94f1bSKan Liang "Offcore": "1", 5946ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 5947ecd94f1bSKan Liang "UMask": "0x1", 5948ecd94f1bSKan Liang "BriefDescription": "TBD TBD", 5949ecd94f1bSKan Liang "MSRValue": "0x0400100120", 5950ecd94f1bSKan Liang "Counter": "0,1,2,3", 5951ecd94f1bSKan Liang "EventName": "OCR.ALL_PF_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", 5952ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 5953ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5954ecd94f1bSKan Liang "SampleAfterValue": "100003", 5955ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 5956ecd94f1bSKan Liang }, 5957ecd94f1bSKan Liang { 5958ecd94f1bSKan Liang "Offcore": "1", 5959ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 5960ecd94f1bSKan Liang "UMask": "0x1", 5961ecd94f1bSKan Liang "BriefDescription": "TBD TBD", 5962ecd94f1bSKan Liang "MSRValue": "0x0800100120", 5963ecd94f1bSKan Liang "Counter": "0,1,2,3", 5964ecd94f1bSKan Liang "EventName": "OCR.ALL_PF_RFO.L3_HIT_S.HIT_OTHER_CORE_FWD", 5965ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 5966ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5967ecd94f1bSKan Liang "SampleAfterValue": "100003", 5968ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 5969ecd94f1bSKan Liang }, 5970ecd94f1bSKan Liang { 5971ecd94f1bSKan Liang "Offcore": "1", 5972ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 5973ecd94f1bSKan Liang "UMask": "0x1", 5974ecd94f1bSKan Liang "BriefDescription": "TBD TBD", 5975ecd94f1bSKan Liang "MSRValue": "0x1000100120", 5976ecd94f1bSKan Liang "Counter": "0,1,2,3", 5977ecd94f1bSKan Liang "EventName": "OCR.ALL_PF_RFO.L3_HIT_S.HITM_OTHER_CORE", 5978ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 5979ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5980ecd94f1bSKan Liang "SampleAfterValue": "100003", 5981ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 5982ecd94f1bSKan Liang }, 5983ecd94f1bSKan Liang { 5984ecd94f1bSKan Liang "Offcore": "1", 5985ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 5986ecd94f1bSKan Liang "UMask": "0x1", 5987ecd94f1bSKan Liang "BriefDescription": "TBD TBD", 5988ecd94f1bSKan Liang "MSRValue": "0x3F80100120", 5989ecd94f1bSKan Liang "Counter": "0,1,2,3", 5990ecd94f1bSKan Liang "EventName": "OCR.ALL_PF_RFO.L3_HIT_S.ANY_SNOOP", 5991ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 5992ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5993ecd94f1bSKan Liang "SampleAfterValue": "100003", 5994ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 5995ecd94f1bSKan Liang }, 5996ecd94f1bSKan Liang { 5997ecd94f1bSKan Liang "Offcore": "1", 5998ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 5999ecd94f1bSKan Liang "UMask": "0x1", 6000ecd94f1bSKan Liang "BriefDescription": "TBD", 6001ecd94f1bSKan Liang "MSRValue": "0x0080200120", 6002ecd94f1bSKan Liang "Counter": "0,1,2,3", 6003ecd94f1bSKan Liang "EventName": "OCR.ALL_PF_RFO.L3_HIT_F.SNOOP_NONE", 6004ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 6005ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6006ecd94f1bSKan Liang "SampleAfterValue": "100003", 6007ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 6008ecd94f1bSKan Liang }, 6009ecd94f1bSKan Liang { 6010ecd94f1bSKan Liang "Offcore": "1", 6011ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 6012ecd94f1bSKan Liang "UMask": "0x1", 6013ecd94f1bSKan Liang "BriefDescription": "TBD TBD", 6014ecd94f1bSKan Liang "MSRValue": "0x0100200120", 6015ecd94f1bSKan Liang "Counter": "0,1,2,3", 6016ecd94f1bSKan Liang "EventName": "OCR.ALL_PF_RFO.L3_HIT_F.NO_SNOOP_NEEDED", 6017ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 6018ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6019ecd94f1bSKan Liang "SampleAfterValue": "100003", 6020ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 6021ecd94f1bSKan Liang }, 6022ecd94f1bSKan Liang { 6023ecd94f1bSKan Liang "Offcore": "1", 6024ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 6025ecd94f1bSKan Liang "UMask": "0x1", 6026ecd94f1bSKan Liang "BriefDescription": "TBD", 6027ecd94f1bSKan Liang "MSRValue": "0x0200200120", 6028ecd94f1bSKan Liang "Counter": "0,1,2,3", 6029ecd94f1bSKan Liang "EventName": "OCR.ALL_PF_RFO.L3_HIT_F.SNOOP_MISS", 6030ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 6031ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6032ecd94f1bSKan Liang "SampleAfterValue": "100003", 6033ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 6034ecd94f1bSKan Liang }, 6035ecd94f1bSKan Liang { 6036ecd94f1bSKan Liang "Offcore": "1", 6037ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 6038ecd94f1bSKan Liang "UMask": "0x1", 6039ecd94f1bSKan Liang "BriefDescription": "TBD TBD", 6040ecd94f1bSKan Liang "MSRValue": "0x0400200120", 6041ecd94f1bSKan Liang "Counter": "0,1,2,3", 6042ecd94f1bSKan Liang "EventName": "OCR.ALL_PF_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", 6043ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 6044ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6045ecd94f1bSKan Liang "SampleAfterValue": "100003", 6046ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 6047ecd94f1bSKan Liang }, 6048ecd94f1bSKan Liang { 6049ecd94f1bSKan Liang "Offcore": "1", 6050ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 6051ecd94f1bSKan Liang "UMask": "0x1", 6052ecd94f1bSKan Liang "BriefDescription": "TBD TBD", 6053ecd94f1bSKan Liang "MSRValue": "0x0800200120", 6054ecd94f1bSKan Liang "Counter": "0,1,2,3", 6055ecd94f1bSKan Liang "EventName": "OCR.ALL_PF_RFO.L3_HIT_F.HIT_OTHER_CORE_FWD", 6056ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 6057ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6058ecd94f1bSKan Liang "SampleAfterValue": "100003", 6059ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 6060ecd94f1bSKan Liang }, 6061ecd94f1bSKan Liang { 6062ecd94f1bSKan Liang "Offcore": "1", 6063ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 6064ecd94f1bSKan Liang "UMask": "0x1", 6065ecd94f1bSKan Liang "BriefDescription": "TBD TBD", 6066ecd94f1bSKan Liang "MSRValue": "0x1000200120", 6067ecd94f1bSKan Liang "Counter": "0,1,2,3", 6068ecd94f1bSKan Liang "EventName": "OCR.ALL_PF_RFO.L3_HIT_F.HITM_OTHER_CORE", 6069ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 6070ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6071ecd94f1bSKan Liang "SampleAfterValue": "100003", 6072ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 6073ecd94f1bSKan Liang }, 6074ecd94f1bSKan Liang { 6075ecd94f1bSKan Liang "Offcore": "1", 6076ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 6077ecd94f1bSKan Liang "UMask": "0x1", 6078ecd94f1bSKan Liang "BriefDescription": "TBD TBD", 6079ecd94f1bSKan Liang "MSRValue": "0x3F80200120", 6080ecd94f1bSKan Liang "Counter": "0,1,2,3", 6081ecd94f1bSKan Liang "EventName": "OCR.ALL_PF_RFO.L3_HIT_F.ANY_SNOOP", 6082ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 6083ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6084ecd94f1bSKan Liang "SampleAfterValue": "100003", 6085ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 6086ecd94f1bSKan Liang }, 6087ecd94f1bSKan Liang { 6088ecd94f1bSKan Liang "Offcore": "1", 6089ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 6090ecd94f1bSKan Liang "UMask": "0x1", 6091ecd94f1bSKan Liang "BriefDescription": "TBD TBD", 6092ecd94f1bSKan Liang "MSRValue": "0x00803C0120", 6093ecd94f1bSKan Liang "Counter": "0,1,2,3", 6094ecd94f1bSKan Liang "EventName": "OCR.ALL_PF_RFO.L3_HIT.SNOOP_NONE", 6095ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 6096ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6097ecd94f1bSKan Liang "SampleAfterValue": "100003", 6098ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 6099ecd94f1bSKan Liang }, 6100ecd94f1bSKan Liang { 6101ecd94f1bSKan Liang "Offcore": "1", 6102ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 6103ecd94f1bSKan Liang "UMask": "0x1", 6104ecd94f1bSKan Liang "BriefDescription": "TBD TBD TBD", 6105ecd94f1bSKan Liang "MSRValue": "0x01003C0120", 6106ecd94f1bSKan Liang "Counter": "0,1,2,3", 6107ecd94f1bSKan Liang "EventName": "OCR.ALL_PF_RFO.L3_HIT.NO_SNOOP_NEEDED", 6108ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 6109ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6110ecd94f1bSKan Liang "SampleAfterValue": "100003", 6111ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 6112ecd94f1bSKan Liang }, 6113ecd94f1bSKan Liang { 6114ecd94f1bSKan Liang "Offcore": "1", 6115ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 6116ecd94f1bSKan Liang "UMask": "0x1", 6117ecd94f1bSKan Liang "BriefDescription": "TBD TBD", 6118ecd94f1bSKan Liang "MSRValue": "0x02003C0120", 6119ecd94f1bSKan Liang "Counter": "0,1,2,3", 6120ecd94f1bSKan Liang "EventName": "OCR.ALL_PF_RFO.L3_HIT.SNOOP_MISS", 6121ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 6122ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6123ecd94f1bSKan Liang "SampleAfterValue": "100003", 6124ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 6125ecd94f1bSKan Liang }, 6126ecd94f1bSKan Liang { 6127ecd94f1bSKan Liang "Offcore": "1", 6128ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 6129ecd94f1bSKan Liang "UMask": "0x1", 6130ecd94f1bSKan Liang "BriefDescription": "TBD TBD TBD", 6131ecd94f1bSKan Liang "MSRValue": "0x04003C0120", 6132ecd94f1bSKan Liang "Counter": "0,1,2,3", 6133ecd94f1bSKan Liang "EventName": "OCR.ALL_PF_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD", 6134ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 6135ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6136ecd94f1bSKan Liang "SampleAfterValue": "100003", 6137ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 6138ecd94f1bSKan Liang }, 6139ecd94f1bSKan Liang { 6140ecd94f1bSKan Liang "Offcore": "1", 6141ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 6142ecd94f1bSKan Liang "UMask": "0x1", 6143ecd94f1bSKan Liang "BriefDescription": "TBD TBD TBD", 6144ecd94f1bSKan Liang "MSRValue": "0x08003C0120", 6145ecd94f1bSKan Liang "Counter": "0,1,2,3", 6146ecd94f1bSKan Liang "EventName": "OCR.ALL_PF_RFO.L3_HIT.HIT_OTHER_CORE_FWD", 6147ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 6148ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6149ecd94f1bSKan Liang "SampleAfterValue": "100003", 6150ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 6151ecd94f1bSKan Liang }, 6152ecd94f1bSKan Liang { 6153ecd94f1bSKan Liang "Offcore": "1", 6154ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 6155ecd94f1bSKan Liang "UMask": "0x1", 6156ecd94f1bSKan Liang "BriefDescription": "TBD TBD TBD", 6157ecd94f1bSKan Liang "MSRValue": "0x10003C0120", 6158ecd94f1bSKan Liang "Counter": "0,1,2,3", 6159ecd94f1bSKan Liang "EventName": "OCR.ALL_PF_RFO.L3_HIT.HITM_OTHER_CORE", 6160ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 6161ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6162ecd94f1bSKan Liang "SampleAfterValue": "100003", 6163ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 6164ecd94f1bSKan Liang }, 6165ecd94f1bSKan Liang { 6166ecd94f1bSKan Liang "Offcore": "1", 6167ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 6168ecd94f1bSKan Liang "UMask": "0x1", 6169ecd94f1bSKan Liang "BriefDescription": "TBD TBD TBD", 6170ecd94f1bSKan Liang "MSRValue": "0x3F803C0120", 6171ecd94f1bSKan Liang "Counter": "0,1,2,3", 6172ecd94f1bSKan Liang "EventName": "OCR.ALL_PF_RFO.L3_HIT.ANY_SNOOP", 6173ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 6174ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6175ecd94f1bSKan Liang "SampleAfterValue": "100003", 6176ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 6177ecd94f1bSKan Liang }, 6178ecd94f1bSKan Liang { 6179ecd94f1bSKan Liang "Offcore": "1", 6180ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 6181ecd94f1bSKan Liang "UMask": "0x1", 6182ecd94f1bSKan Liang "BriefDescription": "TBD", 6183ecd94f1bSKan Liang "MSRValue": "0x0080020491", 6184ecd94f1bSKan Liang "Counter": "0,1,2,3", 6185ecd94f1bSKan Liang "EventName": "OCR.ALL_DATA_RD.SUPPLIER_NONE.SNOOP_NONE", 6186ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 6187ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6188ecd94f1bSKan Liang "SampleAfterValue": "100003", 6189ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 6190ecd94f1bSKan Liang }, 6191ecd94f1bSKan Liang { 6192ecd94f1bSKan Liang "Offcore": "1", 6193ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 6194ecd94f1bSKan Liang "UMask": "0x1", 6195ecd94f1bSKan Liang "BriefDescription": "TBD TBD", 6196ecd94f1bSKan Liang "MSRValue": "0x0100020491", 6197ecd94f1bSKan Liang "Counter": "0,1,2,3", 6198ecd94f1bSKan Liang "EventName": "OCR.ALL_DATA_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED", 6199ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 6200ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6201ecd94f1bSKan Liang "SampleAfterValue": "100003", 6202ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 6203ecd94f1bSKan Liang }, 6204ecd94f1bSKan Liang { 6205ecd94f1bSKan Liang "Offcore": "1", 6206ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 6207ecd94f1bSKan Liang "UMask": "0x1", 6208ecd94f1bSKan Liang "BriefDescription": "TBD", 6209ecd94f1bSKan Liang "MSRValue": "0x0200020491", 6210ecd94f1bSKan Liang "Counter": "0,1,2,3", 6211ecd94f1bSKan Liang "EventName": "OCR.ALL_DATA_RD.SUPPLIER_NONE.SNOOP_MISS", 6212ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 6213ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6214ecd94f1bSKan Liang "SampleAfterValue": "100003", 6215ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 6216ecd94f1bSKan Liang }, 6217ecd94f1bSKan Liang { 6218ecd94f1bSKan Liang "Offcore": "1", 6219ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 6220ecd94f1bSKan Liang "UMask": "0x1", 6221ecd94f1bSKan Liang "BriefDescription": "TBD TBD", 6222ecd94f1bSKan Liang "MSRValue": "0x0400020491", 6223ecd94f1bSKan Liang "Counter": "0,1,2,3", 6224ecd94f1bSKan Liang "EventName": "OCR.ALL_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", 6225ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 6226ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6227ecd94f1bSKan Liang "SampleAfterValue": "100003", 6228ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 6229ecd94f1bSKan Liang }, 6230ecd94f1bSKan Liang { 6231ecd94f1bSKan Liang "Offcore": "1", 6232ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 6233ecd94f1bSKan Liang "UMask": "0x1", 6234ecd94f1bSKan Liang "BriefDescription": "TBD TBD", 6235ecd94f1bSKan Liang "MSRValue": "0x0800020491", 6236ecd94f1bSKan Liang "Counter": "0,1,2,3", 6237ecd94f1bSKan Liang "EventName": "OCR.ALL_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", 6238ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 6239ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6240ecd94f1bSKan Liang "SampleAfterValue": "100003", 6241ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 6242ecd94f1bSKan Liang }, 6243ecd94f1bSKan Liang { 6244ecd94f1bSKan Liang "Offcore": "1", 6245ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 6246ecd94f1bSKan Liang "UMask": "0x1", 6247ecd94f1bSKan Liang "BriefDescription": "TBD TBD", 6248ecd94f1bSKan Liang "MSRValue": "0x1000020491", 6249ecd94f1bSKan Liang "Counter": "0,1,2,3", 6250ecd94f1bSKan Liang "EventName": "OCR.ALL_DATA_RD.SUPPLIER_NONE.HITM_OTHER_CORE", 6251ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 6252ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6253ecd94f1bSKan Liang "SampleAfterValue": "100003", 6254ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 6255ecd94f1bSKan Liang }, 6256ecd94f1bSKan Liang { 6257ecd94f1bSKan Liang "Offcore": "1", 6258ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 6259ecd94f1bSKan Liang "UMask": "0x1", 6260ecd94f1bSKan Liang "BriefDescription": "TBD TBD", 6261ecd94f1bSKan Liang "MSRValue": "0x3F80020491", 6262ecd94f1bSKan Liang "Counter": "0,1,2,3", 6263ecd94f1bSKan Liang "EventName": "OCR.ALL_DATA_RD.SUPPLIER_NONE.ANY_SNOOP", 6264ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 6265ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6266ecd94f1bSKan Liang "SampleAfterValue": "100003", 6267ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 6268ecd94f1bSKan Liang }, 6269ecd94f1bSKan Liang { 6270ecd94f1bSKan Liang "Offcore": "1", 6271ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 6272ecd94f1bSKan Liang "UMask": "0x1", 6273ecd94f1bSKan Liang "BriefDescription": "TBD", 6274ecd94f1bSKan Liang "MSRValue": "0x0080040491", 6275ecd94f1bSKan Liang "Counter": "0,1,2,3", 6276ecd94f1bSKan Liang "EventName": "OCR.ALL_DATA_RD.L3_HIT_M.SNOOP_NONE", 6277ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 6278ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6279ecd94f1bSKan Liang "SampleAfterValue": "100003", 6280ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 6281ecd94f1bSKan Liang }, 6282ecd94f1bSKan Liang { 6283ecd94f1bSKan Liang "Offcore": "1", 6284ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 6285ecd94f1bSKan Liang "UMask": "0x1", 6286ecd94f1bSKan Liang "BriefDescription": "TBD TBD", 6287ecd94f1bSKan Liang "MSRValue": "0x0100040491", 6288ecd94f1bSKan Liang "Counter": "0,1,2,3", 6289ecd94f1bSKan Liang "EventName": "OCR.ALL_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDED", 6290ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 6291ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6292ecd94f1bSKan Liang "SampleAfterValue": "100003", 6293ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 6294ecd94f1bSKan Liang }, 6295ecd94f1bSKan Liang { 6296ecd94f1bSKan Liang "Offcore": "1", 6297ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 6298ecd94f1bSKan Liang "UMask": "0x1", 6299ecd94f1bSKan Liang "BriefDescription": "TBD", 6300ecd94f1bSKan Liang "MSRValue": "0x0200040491", 6301ecd94f1bSKan Liang "Counter": "0,1,2,3", 6302ecd94f1bSKan Liang "EventName": "OCR.ALL_DATA_RD.L3_HIT_M.SNOOP_MISS", 6303ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 6304ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6305ecd94f1bSKan Liang "SampleAfterValue": "100003", 6306ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 6307ecd94f1bSKan Liang }, 6308ecd94f1bSKan Liang { 6309ecd94f1bSKan Liang "Offcore": "1", 6310ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 6311ecd94f1bSKan Liang "UMask": "0x1", 6312ecd94f1bSKan Liang "BriefDescription": "TBD TBD", 6313ecd94f1bSKan Liang "MSRValue": "0x0400040491", 6314ecd94f1bSKan Liang "Counter": "0,1,2,3", 6315ecd94f1bSKan Liang "EventName": "OCR.ALL_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", 6316ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 6317ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6318ecd94f1bSKan Liang "SampleAfterValue": "100003", 6319ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 6320ecd94f1bSKan Liang }, 6321ecd94f1bSKan Liang { 6322ecd94f1bSKan Liang "Offcore": "1", 6323ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 6324ecd94f1bSKan Liang "UMask": "0x1", 6325ecd94f1bSKan Liang "BriefDescription": "TBD TBD", 6326ecd94f1bSKan Liang "MSRValue": "0x0800040491", 6327ecd94f1bSKan Liang "Counter": "0,1,2,3", 6328ecd94f1bSKan Liang "EventName": "OCR.ALL_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWD", 6329ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 6330ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6331ecd94f1bSKan Liang "SampleAfterValue": "100003", 6332ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 6333ecd94f1bSKan Liang }, 6334ecd94f1bSKan Liang { 6335ecd94f1bSKan Liang "Offcore": "1", 6336ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 6337ecd94f1bSKan Liang "UMask": "0x1", 6338ecd94f1bSKan Liang "BriefDescription": "TBD TBD", 6339ecd94f1bSKan Liang "MSRValue": "0x1000040491", 6340ecd94f1bSKan Liang "Counter": "0,1,2,3", 6341ecd94f1bSKan Liang "EventName": "OCR.ALL_DATA_RD.L3_HIT_M.HITM_OTHER_CORE", 6342ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 6343ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6344ecd94f1bSKan Liang "SampleAfterValue": "100003", 6345ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 6346ecd94f1bSKan Liang }, 6347ecd94f1bSKan Liang { 6348ecd94f1bSKan Liang "Offcore": "1", 6349ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 6350ecd94f1bSKan Liang "UMask": "0x1", 6351ecd94f1bSKan Liang "BriefDescription": "TBD TBD", 6352ecd94f1bSKan Liang "MSRValue": "0x3F80040491", 6353ecd94f1bSKan Liang "Counter": "0,1,2,3", 6354ecd94f1bSKan Liang "EventName": "OCR.ALL_DATA_RD.L3_HIT_M.ANY_SNOOP", 6355ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 6356ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6357ecd94f1bSKan Liang "SampleAfterValue": "100003", 6358ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 6359ecd94f1bSKan Liang }, 6360ecd94f1bSKan Liang { 6361ecd94f1bSKan Liang "Offcore": "1", 6362ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 6363ecd94f1bSKan Liang "UMask": "0x1", 6364ecd94f1bSKan Liang "BriefDescription": "TBD", 6365ecd94f1bSKan Liang "MSRValue": "0x0080080491", 6366ecd94f1bSKan Liang "Counter": "0,1,2,3", 6367ecd94f1bSKan Liang "EventName": "OCR.ALL_DATA_RD.L3_HIT_E.SNOOP_NONE", 6368ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 6369ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6370ecd94f1bSKan Liang "SampleAfterValue": "100003", 6371ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 6372ecd94f1bSKan Liang }, 6373ecd94f1bSKan Liang { 6374ecd94f1bSKan Liang "Offcore": "1", 6375ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 6376ecd94f1bSKan Liang "UMask": "0x1", 6377ecd94f1bSKan Liang "BriefDescription": "TBD TBD", 6378ecd94f1bSKan Liang "MSRValue": "0x0100080491", 6379ecd94f1bSKan Liang "Counter": "0,1,2,3", 6380ecd94f1bSKan Liang "EventName": "OCR.ALL_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDED", 6381ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 6382ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6383ecd94f1bSKan Liang "SampleAfterValue": "100003", 6384ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 6385ecd94f1bSKan Liang }, 6386ecd94f1bSKan Liang { 6387ecd94f1bSKan Liang "Offcore": "1", 6388ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 6389ecd94f1bSKan Liang "UMask": "0x1", 6390ecd94f1bSKan Liang "BriefDescription": "TBD", 6391ecd94f1bSKan Liang "MSRValue": "0x0200080491", 6392ecd94f1bSKan Liang "Counter": "0,1,2,3", 6393ecd94f1bSKan Liang "EventName": "OCR.ALL_DATA_RD.L3_HIT_E.SNOOP_MISS", 6394ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 6395ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6396ecd94f1bSKan Liang "SampleAfterValue": "100003", 6397ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 6398ecd94f1bSKan Liang }, 6399ecd94f1bSKan Liang { 6400ecd94f1bSKan Liang "Offcore": "1", 6401ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 6402ecd94f1bSKan Liang "UMask": "0x1", 6403ecd94f1bSKan Liang "BriefDescription": "TBD TBD", 6404ecd94f1bSKan Liang "MSRValue": "0x0400080491", 6405ecd94f1bSKan Liang "Counter": "0,1,2,3", 6406ecd94f1bSKan Liang "EventName": "OCR.ALL_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", 6407ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 6408ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6409ecd94f1bSKan Liang "SampleAfterValue": "100003", 6410ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 6411ecd94f1bSKan Liang }, 6412ecd94f1bSKan Liang { 6413ecd94f1bSKan Liang "Offcore": "1", 6414ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 6415ecd94f1bSKan Liang "UMask": "0x1", 6416ecd94f1bSKan Liang "BriefDescription": "TBD TBD", 6417ecd94f1bSKan Liang "MSRValue": "0x0800080491", 6418ecd94f1bSKan Liang "Counter": "0,1,2,3", 6419ecd94f1bSKan Liang "EventName": "OCR.ALL_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWD", 6420ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 6421ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6422ecd94f1bSKan Liang "SampleAfterValue": "100003", 6423ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 6424ecd94f1bSKan Liang }, 6425ecd94f1bSKan Liang { 6426ecd94f1bSKan Liang "Offcore": "1", 6427ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 6428ecd94f1bSKan Liang "UMask": "0x1", 6429ecd94f1bSKan Liang "BriefDescription": "TBD TBD", 6430ecd94f1bSKan Liang "MSRValue": "0x1000080491", 6431ecd94f1bSKan Liang "Counter": "0,1,2,3", 6432ecd94f1bSKan Liang "EventName": "OCR.ALL_DATA_RD.L3_HIT_E.HITM_OTHER_CORE", 6433ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 6434ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6435ecd94f1bSKan Liang "SampleAfterValue": "100003", 6436ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 6437ecd94f1bSKan Liang }, 6438ecd94f1bSKan Liang { 6439ecd94f1bSKan Liang "Offcore": "1", 6440ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 6441ecd94f1bSKan Liang "UMask": "0x1", 6442ecd94f1bSKan Liang "BriefDescription": "TBD TBD", 6443ecd94f1bSKan Liang "MSRValue": "0x3F80080491", 6444ecd94f1bSKan Liang "Counter": "0,1,2,3", 6445ecd94f1bSKan Liang "EventName": "OCR.ALL_DATA_RD.L3_HIT_E.ANY_SNOOP", 6446ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 6447ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6448ecd94f1bSKan Liang "SampleAfterValue": "100003", 6449ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 6450ecd94f1bSKan Liang }, 6451ecd94f1bSKan Liang { 6452ecd94f1bSKan Liang "Offcore": "1", 6453ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 6454ecd94f1bSKan Liang "UMask": "0x1", 6455ecd94f1bSKan Liang "BriefDescription": "TBD", 6456ecd94f1bSKan Liang "MSRValue": "0x0080100491", 6457ecd94f1bSKan Liang "Counter": "0,1,2,3", 6458ecd94f1bSKan Liang "EventName": "OCR.ALL_DATA_RD.L3_HIT_S.SNOOP_NONE", 6459ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 6460ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6461ecd94f1bSKan Liang "SampleAfterValue": "100003", 6462ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 6463ecd94f1bSKan Liang }, 6464ecd94f1bSKan Liang { 6465ecd94f1bSKan Liang "Offcore": "1", 6466ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 6467ecd94f1bSKan Liang "UMask": "0x1", 6468ecd94f1bSKan Liang "BriefDescription": "TBD TBD", 6469ecd94f1bSKan Liang "MSRValue": "0x0100100491", 6470ecd94f1bSKan Liang "Counter": "0,1,2,3", 6471ecd94f1bSKan Liang "EventName": "OCR.ALL_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDED", 6472ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 6473ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6474ecd94f1bSKan Liang "SampleAfterValue": "100003", 6475ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 6476ecd94f1bSKan Liang }, 6477ecd94f1bSKan Liang { 6478ecd94f1bSKan Liang "Offcore": "1", 6479ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 6480ecd94f1bSKan Liang "UMask": "0x1", 6481ecd94f1bSKan Liang "BriefDescription": "TBD", 6482ecd94f1bSKan Liang "MSRValue": "0x0200100491", 6483ecd94f1bSKan Liang "Counter": "0,1,2,3", 6484ecd94f1bSKan Liang "EventName": "OCR.ALL_DATA_RD.L3_HIT_S.SNOOP_MISS", 6485ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 6486ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6487ecd94f1bSKan Liang "SampleAfterValue": "100003", 6488ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 6489ecd94f1bSKan Liang }, 6490ecd94f1bSKan Liang { 6491ecd94f1bSKan Liang "Offcore": "1", 6492ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 6493ecd94f1bSKan Liang "UMask": "0x1", 6494ecd94f1bSKan Liang "BriefDescription": "TBD TBD", 6495ecd94f1bSKan Liang "MSRValue": "0x0400100491", 6496ecd94f1bSKan Liang "Counter": "0,1,2,3", 6497ecd94f1bSKan Liang "EventName": "OCR.ALL_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", 6498ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 6499ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6500ecd94f1bSKan Liang "SampleAfterValue": "100003", 6501ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 6502ecd94f1bSKan Liang }, 6503ecd94f1bSKan Liang { 6504ecd94f1bSKan Liang "Offcore": "1", 6505ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 6506ecd94f1bSKan Liang "UMask": "0x1", 6507ecd94f1bSKan Liang "BriefDescription": "TBD TBD", 6508ecd94f1bSKan Liang "MSRValue": "0x0800100491", 6509ecd94f1bSKan Liang "Counter": "0,1,2,3", 6510ecd94f1bSKan Liang "EventName": "OCR.ALL_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWD", 6511ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 6512ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6513ecd94f1bSKan Liang "SampleAfterValue": "100003", 6514ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 6515ecd94f1bSKan Liang }, 6516ecd94f1bSKan Liang { 6517ecd94f1bSKan Liang "Offcore": "1", 6518ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 6519ecd94f1bSKan Liang "UMask": "0x1", 6520ecd94f1bSKan Liang "BriefDescription": "TBD TBD", 6521ecd94f1bSKan Liang "MSRValue": "0x1000100491", 6522ecd94f1bSKan Liang "Counter": "0,1,2,3", 6523ecd94f1bSKan Liang "EventName": "OCR.ALL_DATA_RD.L3_HIT_S.HITM_OTHER_CORE", 6524ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 6525ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6526ecd94f1bSKan Liang "SampleAfterValue": "100003", 6527ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 6528ecd94f1bSKan Liang }, 6529ecd94f1bSKan Liang { 6530ecd94f1bSKan Liang "Offcore": "1", 6531ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 6532ecd94f1bSKan Liang "UMask": "0x1", 6533ecd94f1bSKan Liang "BriefDescription": "TBD TBD", 6534ecd94f1bSKan Liang "MSRValue": "0x3F80100491", 6535ecd94f1bSKan Liang "Counter": "0,1,2,3", 6536ecd94f1bSKan Liang "EventName": "OCR.ALL_DATA_RD.L3_HIT_S.ANY_SNOOP", 6537ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 6538ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6539ecd94f1bSKan Liang "SampleAfterValue": "100003", 6540ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 6541ecd94f1bSKan Liang }, 6542ecd94f1bSKan Liang { 6543ecd94f1bSKan Liang "Offcore": "1", 6544ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 6545ecd94f1bSKan Liang "UMask": "0x1", 6546ecd94f1bSKan Liang "BriefDescription": "TBD", 6547ecd94f1bSKan Liang "MSRValue": "0x0080200491", 6548ecd94f1bSKan Liang "Counter": "0,1,2,3", 6549ecd94f1bSKan Liang "EventName": "OCR.ALL_DATA_RD.L3_HIT_F.SNOOP_NONE", 6550ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 6551ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6552ecd94f1bSKan Liang "SampleAfterValue": "100003", 6553ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 6554ecd94f1bSKan Liang }, 6555ecd94f1bSKan Liang { 6556ecd94f1bSKan Liang "Offcore": "1", 6557ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 6558ecd94f1bSKan Liang "UMask": "0x1", 6559ecd94f1bSKan Liang "BriefDescription": "TBD TBD", 6560ecd94f1bSKan Liang "MSRValue": "0x0100200491", 6561ecd94f1bSKan Liang "Counter": "0,1,2,3", 6562ecd94f1bSKan Liang "EventName": "OCR.ALL_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDED", 6563ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 6564ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6565ecd94f1bSKan Liang "SampleAfterValue": "100003", 6566ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 6567ecd94f1bSKan Liang }, 6568ecd94f1bSKan Liang { 6569ecd94f1bSKan Liang "Offcore": "1", 6570ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 6571ecd94f1bSKan Liang "UMask": "0x1", 6572ecd94f1bSKan Liang "BriefDescription": "TBD", 6573ecd94f1bSKan Liang "MSRValue": "0x0200200491", 6574ecd94f1bSKan Liang "Counter": "0,1,2,3", 6575ecd94f1bSKan Liang "EventName": "OCR.ALL_DATA_RD.L3_HIT_F.SNOOP_MISS", 6576ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 6577ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6578ecd94f1bSKan Liang "SampleAfterValue": "100003", 6579ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 6580ecd94f1bSKan Liang }, 6581ecd94f1bSKan Liang { 6582ecd94f1bSKan Liang "Offcore": "1", 6583ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 6584ecd94f1bSKan Liang "UMask": "0x1", 6585ecd94f1bSKan Liang "BriefDescription": "TBD TBD", 6586ecd94f1bSKan Liang "MSRValue": "0x0400200491", 6587ecd94f1bSKan Liang "Counter": "0,1,2,3", 6588ecd94f1bSKan Liang "EventName": "OCR.ALL_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", 6589ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 6590ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6591ecd94f1bSKan Liang "SampleAfterValue": "100003", 6592ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 6593ecd94f1bSKan Liang }, 6594ecd94f1bSKan Liang { 6595ecd94f1bSKan Liang "Offcore": "1", 6596ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 6597ecd94f1bSKan Liang "UMask": "0x1", 6598ecd94f1bSKan Liang "BriefDescription": "TBD TBD", 6599ecd94f1bSKan Liang "MSRValue": "0x0800200491", 6600ecd94f1bSKan Liang "Counter": "0,1,2,3", 6601ecd94f1bSKan Liang "EventName": "OCR.ALL_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWD", 6602ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 6603ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6604ecd94f1bSKan Liang "SampleAfterValue": "100003", 6605ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 6606ecd94f1bSKan Liang }, 6607ecd94f1bSKan Liang { 6608ecd94f1bSKan Liang "Offcore": "1", 6609ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 6610ecd94f1bSKan Liang "UMask": "0x1", 6611ecd94f1bSKan Liang "BriefDescription": "TBD TBD", 6612ecd94f1bSKan Liang "MSRValue": "0x1000200491", 6613ecd94f1bSKan Liang "Counter": "0,1,2,3", 6614ecd94f1bSKan Liang "EventName": "OCR.ALL_DATA_RD.L3_HIT_F.HITM_OTHER_CORE", 6615ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 6616ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6617ecd94f1bSKan Liang "SampleAfterValue": "100003", 6618ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 6619ecd94f1bSKan Liang }, 6620ecd94f1bSKan Liang { 6621ecd94f1bSKan Liang "Offcore": "1", 6622ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 6623ecd94f1bSKan Liang "UMask": "0x1", 6624ecd94f1bSKan Liang "BriefDescription": "TBD TBD", 6625ecd94f1bSKan Liang "MSRValue": "0x3F80200491", 6626ecd94f1bSKan Liang "Counter": "0,1,2,3", 6627ecd94f1bSKan Liang "EventName": "OCR.ALL_DATA_RD.L3_HIT_F.ANY_SNOOP", 6628ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 6629ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6630ecd94f1bSKan Liang "SampleAfterValue": "100003", 6631ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 6632ecd94f1bSKan Liang }, 6633ecd94f1bSKan Liang { 6634ecd94f1bSKan Liang "Offcore": "1", 6635ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 6636ecd94f1bSKan Liang "UMask": "0x1", 6637ecd94f1bSKan Liang "BriefDescription": "TBD TBD", 6638ecd94f1bSKan Liang "MSRValue": "0x00803C0491", 6639ecd94f1bSKan Liang "Counter": "0,1,2,3", 6640ecd94f1bSKan Liang "EventName": "OCR.ALL_DATA_RD.L3_HIT.SNOOP_NONE", 6641ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 6642ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6643ecd94f1bSKan Liang "SampleAfterValue": "100003", 6644ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 6645ecd94f1bSKan Liang }, 6646ecd94f1bSKan Liang { 6647ecd94f1bSKan Liang "Offcore": "1", 6648ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 6649ecd94f1bSKan Liang "UMask": "0x1", 6650ecd94f1bSKan Liang "BriefDescription": "TBD TBD TBD", 6651ecd94f1bSKan Liang "MSRValue": "0x01003C0491", 6652ecd94f1bSKan Liang "Counter": "0,1,2,3", 6653ecd94f1bSKan Liang "EventName": "OCR.ALL_DATA_RD.L3_HIT.NO_SNOOP_NEEDED", 6654ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 6655ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6656ecd94f1bSKan Liang "SampleAfterValue": "100003", 6657ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 6658ecd94f1bSKan Liang }, 6659ecd94f1bSKan Liang { 6660ecd94f1bSKan Liang "Offcore": "1", 6661ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 6662ecd94f1bSKan Liang "UMask": "0x1", 6663ecd94f1bSKan Liang "BriefDescription": "TBD TBD", 6664ecd94f1bSKan Liang "MSRValue": "0x02003C0491", 6665ecd94f1bSKan Liang "Counter": "0,1,2,3", 6666ecd94f1bSKan Liang "EventName": "OCR.ALL_DATA_RD.L3_HIT.SNOOP_MISS", 6667ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 6668ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6669ecd94f1bSKan Liang "SampleAfterValue": "100003", 6670ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 6671ecd94f1bSKan Liang }, 6672ecd94f1bSKan Liang { 6673ecd94f1bSKan Liang "Offcore": "1", 6674ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 6675ecd94f1bSKan Liang "UMask": "0x1", 6676ecd94f1bSKan Liang "BriefDescription": "TBD TBD TBD", 6677ecd94f1bSKan Liang "MSRValue": "0x04003C0491", 6678ecd94f1bSKan Liang "Counter": "0,1,2,3", 6679ecd94f1bSKan Liang "EventName": "OCR.ALL_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD", 6680ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 6681ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6682ecd94f1bSKan Liang "SampleAfterValue": "100003", 6683ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 6684ecd94f1bSKan Liang }, 6685ecd94f1bSKan Liang { 6686ecd94f1bSKan Liang "Offcore": "1", 6687ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 6688ecd94f1bSKan Liang "UMask": "0x1", 6689ecd94f1bSKan Liang "BriefDescription": "TBD TBD TBD", 6690ecd94f1bSKan Liang "MSRValue": "0x08003C0491", 6691ecd94f1bSKan Liang "Counter": "0,1,2,3", 6692ecd94f1bSKan Liang "EventName": "OCR.ALL_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD", 6693ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 6694ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6695ecd94f1bSKan Liang "SampleAfterValue": "100003", 6696ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 6697ecd94f1bSKan Liang }, 6698ecd94f1bSKan Liang { 6699ecd94f1bSKan Liang "Offcore": "1", 6700ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 6701ecd94f1bSKan Liang "UMask": "0x1", 6702ecd94f1bSKan Liang "BriefDescription": "TBD TBD TBD", 6703ecd94f1bSKan Liang "MSRValue": "0x10003C0491", 6704ecd94f1bSKan Liang "Counter": "0,1,2,3", 6705ecd94f1bSKan Liang "EventName": "OCR.ALL_DATA_RD.L3_HIT.HITM_OTHER_CORE", 6706ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 6707ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6708ecd94f1bSKan Liang "SampleAfterValue": "100003", 6709ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 6710ecd94f1bSKan Liang }, 6711ecd94f1bSKan Liang { 6712ecd94f1bSKan Liang "Offcore": "1", 6713ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 6714ecd94f1bSKan Liang "UMask": "0x1", 6715ecd94f1bSKan Liang "BriefDescription": "TBD TBD TBD", 6716ecd94f1bSKan Liang "MSRValue": "0x3F803C0491", 6717ecd94f1bSKan Liang "Counter": "0,1,2,3", 6718ecd94f1bSKan Liang "EventName": "OCR.ALL_DATA_RD.L3_HIT.ANY_SNOOP", 6719ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 6720ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6721ecd94f1bSKan Liang "SampleAfterValue": "100003", 6722ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 6723ecd94f1bSKan Liang }, 6724ecd94f1bSKan Liang { 6725ecd94f1bSKan Liang "Offcore": "1", 6726ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 6727ecd94f1bSKan Liang "UMask": "0x1", 6728ecd94f1bSKan Liang "BriefDescription": "TBD", 6729ecd94f1bSKan Liang "MSRValue": "0x0080020122", 6730ecd94f1bSKan Liang "Counter": "0,1,2,3", 6731ecd94f1bSKan Liang "EventName": "OCR.ALL_RFO.SUPPLIER_NONE.SNOOP_NONE", 6732ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 6733ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6734ecd94f1bSKan Liang "SampleAfterValue": "100003", 6735ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 6736ecd94f1bSKan Liang }, 6737ecd94f1bSKan Liang { 6738ecd94f1bSKan Liang "Offcore": "1", 6739ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 6740ecd94f1bSKan Liang "UMask": "0x1", 6741ecd94f1bSKan Liang "BriefDescription": "TBD TBD", 6742ecd94f1bSKan Liang "MSRValue": "0x0100020122", 6743ecd94f1bSKan Liang "Counter": "0,1,2,3", 6744ecd94f1bSKan Liang "EventName": "OCR.ALL_RFO.SUPPLIER_NONE.NO_SNOOP_NEEDED", 6745ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 6746ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6747ecd94f1bSKan Liang "SampleAfterValue": "100003", 6748ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 6749ecd94f1bSKan Liang }, 6750ecd94f1bSKan Liang { 6751ecd94f1bSKan Liang "Offcore": "1", 6752ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 6753ecd94f1bSKan Liang "UMask": "0x1", 6754ecd94f1bSKan Liang "BriefDescription": "TBD", 6755ecd94f1bSKan Liang "MSRValue": "0x0200020122", 6756ecd94f1bSKan Liang "Counter": "0,1,2,3", 6757ecd94f1bSKan Liang "EventName": "OCR.ALL_RFO.SUPPLIER_NONE.SNOOP_MISS", 6758ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 6759ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6760ecd94f1bSKan Liang "SampleAfterValue": "100003", 6761ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 6762ecd94f1bSKan Liang }, 6763ecd94f1bSKan Liang { 6764ecd94f1bSKan Liang "Offcore": "1", 6765ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 6766ecd94f1bSKan Liang "UMask": "0x1", 6767ecd94f1bSKan Liang "BriefDescription": "TBD TBD", 6768ecd94f1bSKan Liang "MSRValue": "0x0400020122", 6769ecd94f1bSKan Liang "Counter": "0,1,2,3", 6770ecd94f1bSKan Liang "EventName": "OCR.ALL_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", 6771ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 6772ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6773ecd94f1bSKan Liang "SampleAfterValue": "100003", 6774ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 6775ecd94f1bSKan Liang }, 6776ecd94f1bSKan Liang { 6777ecd94f1bSKan Liang "Offcore": "1", 6778ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 6779ecd94f1bSKan Liang "UMask": "0x1", 6780ecd94f1bSKan Liang "BriefDescription": "TBD TBD", 6781ecd94f1bSKan Liang "MSRValue": "0x0800020122", 6782ecd94f1bSKan Liang "Counter": "0,1,2,3", 6783ecd94f1bSKan Liang "EventName": "OCR.ALL_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", 6784ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 6785ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6786ecd94f1bSKan Liang "SampleAfterValue": "100003", 6787ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 6788ecd94f1bSKan Liang }, 6789ecd94f1bSKan Liang { 6790ecd94f1bSKan Liang "Offcore": "1", 6791ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 6792ecd94f1bSKan Liang "UMask": "0x1", 6793ecd94f1bSKan Liang "BriefDescription": "TBD TBD", 6794ecd94f1bSKan Liang "MSRValue": "0x1000020122", 6795ecd94f1bSKan Liang "Counter": "0,1,2,3", 6796ecd94f1bSKan Liang "EventName": "OCR.ALL_RFO.SUPPLIER_NONE.HITM_OTHER_CORE", 6797ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 6798ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6799ecd94f1bSKan Liang "SampleAfterValue": "100003", 6800ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 6801ecd94f1bSKan Liang }, 6802ecd94f1bSKan Liang { 6803ecd94f1bSKan Liang "Offcore": "1", 6804ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 6805ecd94f1bSKan Liang "UMask": "0x1", 6806ecd94f1bSKan Liang "BriefDescription": "TBD TBD", 6807ecd94f1bSKan Liang "MSRValue": "0x3F80020122", 6808ecd94f1bSKan Liang "Counter": "0,1,2,3", 6809ecd94f1bSKan Liang "EventName": "OCR.ALL_RFO.SUPPLIER_NONE.ANY_SNOOP", 6810ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 6811ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6812ecd94f1bSKan Liang "SampleAfterValue": "100003", 6813ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 6814ecd94f1bSKan Liang }, 6815ecd94f1bSKan Liang { 6816ecd94f1bSKan Liang "Offcore": "1", 6817ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 6818ecd94f1bSKan Liang "UMask": "0x1", 6819ecd94f1bSKan Liang "BriefDescription": "TBD", 6820ecd94f1bSKan Liang "MSRValue": "0x0080040122", 6821ecd94f1bSKan Liang "Counter": "0,1,2,3", 6822ecd94f1bSKan Liang "EventName": "OCR.ALL_RFO.L3_HIT_M.SNOOP_NONE", 6823ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 6824ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6825ecd94f1bSKan Liang "SampleAfterValue": "100003", 6826ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 6827ecd94f1bSKan Liang }, 6828ecd94f1bSKan Liang { 6829ecd94f1bSKan Liang "Offcore": "1", 6830ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 6831ecd94f1bSKan Liang "UMask": "0x1", 6832ecd94f1bSKan Liang "BriefDescription": "TBD TBD", 6833ecd94f1bSKan Liang "MSRValue": "0x0100040122", 6834ecd94f1bSKan Liang "Counter": "0,1,2,3", 6835ecd94f1bSKan Liang "EventName": "OCR.ALL_RFO.L3_HIT_M.NO_SNOOP_NEEDED", 6836ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 6837ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6838ecd94f1bSKan Liang "SampleAfterValue": "100003", 6839ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 6840ecd94f1bSKan Liang }, 6841ecd94f1bSKan Liang { 6842ecd94f1bSKan Liang "Offcore": "1", 6843ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 6844ecd94f1bSKan Liang "UMask": "0x1", 6845ecd94f1bSKan Liang "BriefDescription": "TBD", 6846ecd94f1bSKan Liang "MSRValue": "0x0200040122", 6847ecd94f1bSKan Liang "Counter": "0,1,2,3", 6848ecd94f1bSKan Liang "EventName": "OCR.ALL_RFO.L3_HIT_M.SNOOP_MISS", 6849ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 6850ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6851ecd94f1bSKan Liang "SampleAfterValue": "100003", 6852ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 6853ecd94f1bSKan Liang }, 6854ecd94f1bSKan Liang { 6855ecd94f1bSKan Liang "Offcore": "1", 6856ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 6857ecd94f1bSKan Liang "UMask": "0x1", 6858ecd94f1bSKan Liang "BriefDescription": "TBD TBD", 6859ecd94f1bSKan Liang "MSRValue": "0x0400040122", 6860ecd94f1bSKan Liang "Counter": "0,1,2,3", 6861ecd94f1bSKan Liang "EventName": "OCR.ALL_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", 6862ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 6863ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6864ecd94f1bSKan Liang "SampleAfterValue": "100003", 6865ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 6866ecd94f1bSKan Liang }, 6867ecd94f1bSKan Liang { 6868ecd94f1bSKan Liang "Offcore": "1", 6869ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 6870ecd94f1bSKan Liang "UMask": "0x1", 6871ecd94f1bSKan Liang "BriefDescription": "TBD TBD", 6872ecd94f1bSKan Liang "MSRValue": "0x0800040122", 6873ecd94f1bSKan Liang "Counter": "0,1,2,3", 6874ecd94f1bSKan Liang "EventName": "OCR.ALL_RFO.L3_HIT_M.HIT_OTHER_CORE_FWD", 6875ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 6876ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6877ecd94f1bSKan Liang "SampleAfterValue": "100003", 6878ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 6879ecd94f1bSKan Liang }, 6880ecd94f1bSKan Liang { 6881ecd94f1bSKan Liang "Offcore": "1", 6882ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 6883ecd94f1bSKan Liang "UMask": "0x1", 6884ecd94f1bSKan Liang "BriefDescription": "TBD TBD", 6885ecd94f1bSKan Liang "MSRValue": "0x1000040122", 6886ecd94f1bSKan Liang "Counter": "0,1,2,3", 6887ecd94f1bSKan Liang "EventName": "OCR.ALL_RFO.L3_HIT_M.HITM_OTHER_CORE", 6888ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 6889ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6890ecd94f1bSKan Liang "SampleAfterValue": "100003", 6891ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 6892ecd94f1bSKan Liang }, 6893ecd94f1bSKan Liang { 6894ecd94f1bSKan Liang "Offcore": "1", 6895ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 6896ecd94f1bSKan Liang "UMask": "0x1", 6897ecd94f1bSKan Liang "BriefDescription": "TBD TBD", 6898ecd94f1bSKan Liang "MSRValue": "0x3F80040122", 6899ecd94f1bSKan Liang "Counter": "0,1,2,3", 6900ecd94f1bSKan Liang "EventName": "OCR.ALL_RFO.L3_HIT_M.ANY_SNOOP", 6901ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 6902ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6903ecd94f1bSKan Liang "SampleAfterValue": "100003", 6904ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 6905ecd94f1bSKan Liang }, 6906ecd94f1bSKan Liang { 6907ecd94f1bSKan Liang "Offcore": "1", 6908ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 6909ecd94f1bSKan Liang "UMask": "0x1", 6910ecd94f1bSKan Liang "BriefDescription": "TBD", 6911ecd94f1bSKan Liang "MSRValue": "0x0080080122", 6912ecd94f1bSKan Liang "Counter": "0,1,2,3", 6913ecd94f1bSKan Liang "EventName": "OCR.ALL_RFO.L3_HIT_E.SNOOP_NONE", 6914ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 6915ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6916ecd94f1bSKan Liang "SampleAfterValue": "100003", 6917ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 6918ecd94f1bSKan Liang }, 6919ecd94f1bSKan Liang { 6920ecd94f1bSKan Liang "Offcore": "1", 6921ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 6922ecd94f1bSKan Liang "UMask": "0x1", 6923ecd94f1bSKan Liang "BriefDescription": "TBD TBD", 6924ecd94f1bSKan Liang "MSRValue": "0x0100080122", 6925ecd94f1bSKan Liang "Counter": "0,1,2,3", 6926ecd94f1bSKan Liang "EventName": "OCR.ALL_RFO.L3_HIT_E.NO_SNOOP_NEEDED", 6927ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 6928ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6929ecd94f1bSKan Liang "SampleAfterValue": "100003", 6930ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 6931ecd94f1bSKan Liang }, 6932ecd94f1bSKan Liang { 6933ecd94f1bSKan Liang "Offcore": "1", 6934ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 6935ecd94f1bSKan Liang "UMask": "0x1", 6936ecd94f1bSKan Liang "BriefDescription": "TBD", 6937ecd94f1bSKan Liang "MSRValue": "0x0200080122", 6938ecd94f1bSKan Liang "Counter": "0,1,2,3", 6939ecd94f1bSKan Liang "EventName": "OCR.ALL_RFO.L3_HIT_E.SNOOP_MISS", 6940ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 6941ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6942ecd94f1bSKan Liang "SampleAfterValue": "100003", 6943ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 6944ecd94f1bSKan Liang }, 6945ecd94f1bSKan Liang { 6946ecd94f1bSKan Liang "Offcore": "1", 6947ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 6948ecd94f1bSKan Liang "UMask": "0x1", 6949ecd94f1bSKan Liang "BriefDescription": "TBD TBD", 6950ecd94f1bSKan Liang "MSRValue": "0x0400080122", 6951ecd94f1bSKan Liang "Counter": "0,1,2,3", 6952ecd94f1bSKan Liang "EventName": "OCR.ALL_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", 6953ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 6954ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6955ecd94f1bSKan Liang "SampleAfterValue": "100003", 6956ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 6957ecd94f1bSKan Liang }, 6958ecd94f1bSKan Liang { 6959ecd94f1bSKan Liang "Offcore": "1", 6960ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 6961ecd94f1bSKan Liang "UMask": "0x1", 6962ecd94f1bSKan Liang "BriefDescription": "TBD TBD", 6963ecd94f1bSKan Liang "MSRValue": "0x0800080122", 6964ecd94f1bSKan Liang "Counter": "0,1,2,3", 6965ecd94f1bSKan Liang "EventName": "OCR.ALL_RFO.L3_HIT_E.HIT_OTHER_CORE_FWD", 6966ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 6967ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6968ecd94f1bSKan Liang "SampleAfterValue": "100003", 6969ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 6970ecd94f1bSKan Liang }, 6971ecd94f1bSKan Liang { 6972ecd94f1bSKan Liang "Offcore": "1", 6973ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 6974ecd94f1bSKan Liang "UMask": "0x1", 6975ecd94f1bSKan Liang "BriefDescription": "TBD TBD", 6976ecd94f1bSKan Liang "MSRValue": "0x1000080122", 6977ecd94f1bSKan Liang "Counter": "0,1,2,3", 6978ecd94f1bSKan Liang "EventName": "OCR.ALL_RFO.L3_HIT_E.HITM_OTHER_CORE", 6979ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 6980ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6981ecd94f1bSKan Liang "SampleAfterValue": "100003", 6982ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 6983ecd94f1bSKan Liang }, 6984ecd94f1bSKan Liang { 6985ecd94f1bSKan Liang "Offcore": "1", 6986ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 6987ecd94f1bSKan Liang "UMask": "0x1", 6988ecd94f1bSKan Liang "BriefDescription": "TBD TBD", 6989ecd94f1bSKan Liang "MSRValue": "0x3F80080122", 6990ecd94f1bSKan Liang "Counter": "0,1,2,3", 6991ecd94f1bSKan Liang "EventName": "OCR.ALL_RFO.L3_HIT_E.ANY_SNOOP", 6992ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 6993ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6994ecd94f1bSKan Liang "SampleAfterValue": "100003", 6995ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 6996ecd94f1bSKan Liang }, 6997ecd94f1bSKan Liang { 6998ecd94f1bSKan Liang "Offcore": "1", 6999ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 7000ecd94f1bSKan Liang "UMask": "0x1", 7001ecd94f1bSKan Liang "BriefDescription": "TBD", 7002ecd94f1bSKan Liang "MSRValue": "0x0080100122", 7003ecd94f1bSKan Liang "Counter": "0,1,2,3", 7004ecd94f1bSKan Liang "EventName": "OCR.ALL_RFO.L3_HIT_S.SNOOP_NONE", 7005ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 7006ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7007ecd94f1bSKan Liang "SampleAfterValue": "100003", 7008ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 7009ecd94f1bSKan Liang }, 7010ecd94f1bSKan Liang { 7011ecd94f1bSKan Liang "Offcore": "1", 7012ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 7013ecd94f1bSKan Liang "UMask": "0x1", 7014ecd94f1bSKan Liang "BriefDescription": "TBD TBD", 7015ecd94f1bSKan Liang "MSRValue": "0x0100100122", 7016ecd94f1bSKan Liang "Counter": "0,1,2,3", 7017ecd94f1bSKan Liang "EventName": "OCR.ALL_RFO.L3_HIT_S.NO_SNOOP_NEEDED", 7018ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 7019ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7020ecd94f1bSKan Liang "SampleAfterValue": "100003", 7021ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 7022ecd94f1bSKan Liang }, 7023ecd94f1bSKan Liang { 7024ecd94f1bSKan Liang "Offcore": "1", 7025ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 7026ecd94f1bSKan Liang "UMask": "0x1", 7027ecd94f1bSKan Liang "BriefDescription": "TBD", 7028ecd94f1bSKan Liang "MSRValue": "0x0200100122", 7029ecd94f1bSKan Liang "Counter": "0,1,2,3", 7030ecd94f1bSKan Liang "EventName": "OCR.ALL_RFO.L3_HIT_S.SNOOP_MISS", 7031ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 7032ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7033ecd94f1bSKan Liang "SampleAfterValue": "100003", 7034ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 7035ecd94f1bSKan Liang }, 7036ecd94f1bSKan Liang { 7037ecd94f1bSKan Liang "Offcore": "1", 7038ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 7039ecd94f1bSKan Liang "UMask": "0x1", 7040ecd94f1bSKan Liang "BriefDescription": "TBD TBD", 7041ecd94f1bSKan Liang "MSRValue": "0x0400100122", 7042ecd94f1bSKan Liang "Counter": "0,1,2,3", 7043ecd94f1bSKan Liang "EventName": "OCR.ALL_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", 7044ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 7045ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7046ecd94f1bSKan Liang "SampleAfterValue": "100003", 7047ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 7048ecd94f1bSKan Liang }, 7049ecd94f1bSKan Liang { 7050ecd94f1bSKan Liang "Offcore": "1", 7051ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 7052ecd94f1bSKan Liang "UMask": "0x1", 7053ecd94f1bSKan Liang "BriefDescription": "TBD TBD", 7054ecd94f1bSKan Liang "MSRValue": "0x0800100122", 7055ecd94f1bSKan Liang "Counter": "0,1,2,3", 7056ecd94f1bSKan Liang "EventName": "OCR.ALL_RFO.L3_HIT_S.HIT_OTHER_CORE_FWD", 7057ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 7058ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7059ecd94f1bSKan Liang "SampleAfterValue": "100003", 7060ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 7061ecd94f1bSKan Liang }, 7062ecd94f1bSKan Liang { 7063ecd94f1bSKan Liang "Offcore": "1", 7064ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 7065ecd94f1bSKan Liang "UMask": "0x1", 7066ecd94f1bSKan Liang "BriefDescription": "TBD TBD", 7067ecd94f1bSKan Liang "MSRValue": "0x1000100122", 7068ecd94f1bSKan Liang "Counter": "0,1,2,3", 7069ecd94f1bSKan Liang "EventName": "OCR.ALL_RFO.L3_HIT_S.HITM_OTHER_CORE", 7070ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 7071ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7072ecd94f1bSKan Liang "SampleAfterValue": "100003", 7073ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 7074ecd94f1bSKan Liang }, 7075ecd94f1bSKan Liang { 7076ecd94f1bSKan Liang "Offcore": "1", 7077ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 7078ecd94f1bSKan Liang "UMask": "0x1", 7079ecd94f1bSKan Liang "BriefDescription": "TBD TBD", 7080ecd94f1bSKan Liang "MSRValue": "0x3F80100122", 7081ecd94f1bSKan Liang "Counter": "0,1,2,3", 7082ecd94f1bSKan Liang "EventName": "OCR.ALL_RFO.L3_HIT_S.ANY_SNOOP", 7083ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 7084ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7085ecd94f1bSKan Liang "SampleAfterValue": "100003", 7086ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 7087ecd94f1bSKan Liang }, 7088ecd94f1bSKan Liang { 7089ecd94f1bSKan Liang "Offcore": "1", 7090ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 7091ecd94f1bSKan Liang "UMask": "0x1", 7092ecd94f1bSKan Liang "BriefDescription": "TBD", 7093ecd94f1bSKan Liang "MSRValue": "0x0080200122", 7094ecd94f1bSKan Liang "Counter": "0,1,2,3", 7095ecd94f1bSKan Liang "EventName": "OCR.ALL_RFO.L3_HIT_F.SNOOP_NONE", 7096ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 7097ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7098ecd94f1bSKan Liang "SampleAfterValue": "100003", 7099ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 7100ecd94f1bSKan Liang }, 7101ecd94f1bSKan Liang { 7102ecd94f1bSKan Liang "Offcore": "1", 7103ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 7104ecd94f1bSKan Liang "UMask": "0x1", 7105ecd94f1bSKan Liang "BriefDescription": "TBD TBD", 7106ecd94f1bSKan Liang "MSRValue": "0x0100200122", 7107ecd94f1bSKan Liang "Counter": "0,1,2,3", 7108ecd94f1bSKan Liang "EventName": "OCR.ALL_RFO.L3_HIT_F.NO_SNOOP_NEEDED", 7109ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 7110ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7111ecd94f1bSKan Liang "SampleAfterValue": "100003", 7112ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 7113ecd94f1bSKan Liang }, 7114ecd94f1bSKan Liang { 7115ecd94f1bSKan Liang "Offcore": "1", 7116ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 7117ecd94f1bSKan Liang "UMask": "0x1", 7118ecd94f1bSKan Liang "BriefDescription": "TBD", 7119ecd94f1bSKan Liang "MSRValue": "0x0200200122", 7120ecd94f1bSKan Liang "Counter": "0,1,2,3", 7121ecd94f1bSKan Liang "EventName": "OCR.ALL_RFO.L3_HIT_F.SNOOP_MISS", 7122ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 7123ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7124ecd94f1bSKan Liang "SampleAfterValue": "100003", 7125ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 7126ecd94f1bSKan Liang }, 7127ecd94f1bSKan Liang { 7128ecd94f1bSKan Liang "Offcore": "1", 7129ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 7130ecd94f1bSKan Liang "UMask": "0x1", 7131ecd94f1bSKan Liang "BriefDescription": "TBD TBD", 7132ecd94f1bSKan Liang "MSRValue": "0x0400200122", 7133ecd94f1bSKan Liang "Counter": "0,1,2,3", 7134ecd94f1bSKan Liang "EventName": "OCR.ALL_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", 7135ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 7136ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7137ecd94f1bSKan Liang "SampleAfterValue": "100003", 7138ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 7139ecd94f1bSKan Liang }, 7140ecd94f1bSKan Liang { 7141ecd94f1bSKan Liang "Offcore": "1", 7142ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 7143ecd94f1bSKan Liang "UMask": "0x1", 7144ecd94f1bSKan Liang "BriefDescription": "TBD TBD", 7145ecd94f1bSKan Liang "MSRValue": "0x0800200122", 7146ecd94f1bSKan Liang "Counter": "0,1,2,3", 7147ecd94f1bSKan Liang "EventName": "OCR.ALL_RFO.L3_HIT_F.HIT_OTHER_CORE_FWD", 7148ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 7149ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7150ecd94f1bSKan Liang "SampleAfterValue": "100003", 7151ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 7152ecd94f1bSKan Liang }, 7153ecd94f1bSKan Liang { 7154ecd94f1bSKan Liang "Offcore": "1", 7155ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 7156ecd94f1bSKan Liang "UMask": "0x1", 7157ecd94f1bSKan Liang "BriefDescription": "TBD TBD", 7158ecd94f1bSKan Liang "MSRValue": "0x1000200122", 7159ecd94f1bSKan Liang "Counter": "0,1,2,3", 7160ecd94f1bSKan Liang "EventName": "OCR.ALL_RFO.L3_HIT_F.HITM_OTHER_CORE", 7161ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 7162ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7163ecd94f1bSKan Liang "SampleAfterValue": "100003", 7164ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 7165ecd94f1bSKan Liang }, 7166ecd94f1bSKan Liang { 7167ecd94f1bSKan Liang "Offcore": "1", 7168ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 7169ecd94f1bSKan Liang "UMask": "0x1", 7170ecd94f1bSKan Liang "BriefDescription": "TBD TBD", 7171ecd94f1bSKan Liang "MSRValue": "0x3F80200122", 7172ecd94f1bSKan Liang "Counter": "0,1,2,3", 7173ecd94f1bSKan Liang "EventName": "OCR.ALL_RFO.L3_HIT_F.ANY_SNOOP", 7174ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 7175ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7176ecd94f1bSKan Liang "SampleAfterValue": "100003", 7177ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 7178ecd94f1bSKan Liang }, 7179ecd94f1bSKan Liang { 7180ecd94f1bSKan Liang "Offcore": "1", 7181ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 7182ecd94f1bSKan Liang "UMask": "0x1", 7183ecd94f1bSKan Liang "BriefDescription": "TBD TBD", 7184ecd94f1bSKan Liang "MSRValue": "0x00803C0122", 7185ecd94f1bSKan Liang "Counter": "0,1,2,3", 7186ecd94f1bSKan Liang "EventName": "OCR.ALL_RFO.L3_HIT.SNOOP_NONE", 7187ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 7188ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7189ecd94f1bSKan Liang "SampleAfterValue": "100003", 7190ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 7191ecd94f1bSKan Liang }, 7192ecd94f1bSKan Liang { 7193ecd94f1bSKan Liang "Offcore": "1", 7194ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 7195ecd94f1bSKan Liang "UMask": "0x1", 7196ecd94f1bSKan Liang "BriefDescription": "TBD TBD TBD", 7197ecd94f1bSKan Liang "MSRValue": "0x01003C0122", 7198ecd94f1bSKan Liang "Counter": "0,1,2,3", 7199ecd94f1bSKan Liang "EventName": "OCR.ALL_RFO.L3_HIT.NO_SNOOP_NEEDED", 7200ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 7201ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7202ecd94f1bSKan Liang "SampleAfterValue": "100003", 7203ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 7204ecd94f1bSKan Liang }, 7205ecd94f1bSKan Liang { 7206ecd94f1bSKan Liang "Offcore": "1", 7207ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 7208ecd94f1bSKan Liang "UMask": "0x1", 7209ecd94f1bSKan Liang "BriefDescription": "TBD TBD", 7210ecd94f1bSKan Liang "MSRValue": "0x02003C0122", 7211ecd94f1bSKan Liang "Counter": "0,1,2,3", 7212ecd94f1bSKan Liang "EventName": "OCR.ALL_RFO.L3_HIT.SNOOP_MISS", 7213ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 7214ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7215ecd94f1bSKan Liang "SampleAfterValue": "100003", 7216ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 7217ecd94f1bSKan Liang }, 7218ecd94f1bSKan Liang { 7219ecd94f1bSKan Liang "Offcore": "1", 7220ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 7221ecd94f1bSKan Liang "UMask": "0x1", 7222ecd94f1bSKan Liang "BriefDescription": "TBD TBD TBD", 7223ecd94f1bSKan Liang "MSRValue": "0x04003C0122", 7224ecd94f1bSKan Liang "Counter": "0,1,2,3", 7225ecd94f1bSKan Liang "EventName": "OCR.ALL_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD", 7226ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 7227ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7228ecd94f1bSKan Liang "SampleAfterValue": "100003", 7229ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 7230ecd94f1bSKan Liang }, 7231ecd94f1bSKan Liang { 7232ecd94f1bSKan Liang "Offcore": "1", 7233ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 7234ecd94f1bSKan Liang "UMask": "0x1", 7235ecd94f1bSKan Liang "BriefDescription": "TBD TBD TBD", 7236ecd94f1bSKan Liang "MSRValue": "0x08003C0122", 7237ecd94f1bSKan Liang "Counter": "0,1,2,3", 7238ecd94f1bSKan Liang "EventName": "OCR.ALL_RFO.L3_HIT.HIT_OTHER_CORE_FWD", 7239ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 7240ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7241ecd94f1bSKan Liang "SampleAfterValue": "100003", 7242ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 7243ecd94f1bSKan Liang }, 7244ecd94f1bSKan Liang { 7245ecd94f1bSKan Liang "Offcore": "1", 7246ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 7247ecd94f1bSKan Liang "UMask": "0x1", 7248ecd94f1bSKan Liang "BriefDescription": "TBD TBD TBD", 7249ecd94f1bSKan Liang "MSRValue": "0x10003C0122", 7250ecd94f1bSKan Liang "Counter": "0,1,2,3", 7251ecd94f1bSKan Liang "EventName": "OCR.ALL_RFO.L3_HIT.HITM_OTHER_CORE", 7252ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 7253ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7254ecd94f1bSKan Liang "SampleAfterValue": "100003", 7255ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 7256ecd94f1bSKan Liang }, 7257ecd94f1bSKan Liang { 7258ecd94f1bSKan Liang "Offcore": "1", 7259ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 7260ecd94f1bSKan Liang "UMask": "0x1", 7261ecd94f1bSKan Liang "BriefDescription": "TBD TBD TBD", 7262ecd94f1bSKan Liang "MSRValue": "0x3F803C0122", 7263ecd94f1bSKan Liang "Counter": "0,1,2,3", 7264ecd94f1bSKan Liang "EventName": "OCR.ALL_RFO.L3_HIT.ANY_SNOOP", 7265ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 7266ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7267ecd94f1bSKan Liang "SampleAfterValue": "100003", 7268ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 7269ecd94f1bSKan Liang }, 7270ecd94f1bSKan Liang { 7271ecd94f1bSKan Liang "Offcore": "1", 7272ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 7273ecd94f1bSKan Liang "UMask": "0x1", 7274ecd94f1bSKan Liang "BriefDescription": "TBD", 7275ecd94f1bSKan Liang "MSRValue": "0x00800207F7", 7276ecd94f1bSKan Liang "Counter": "0,1,2,3", 7277ecd94f1bSKan Liang "EventName": "OCR.ALL_READS.SUPPLIER_NONE.SNOOP_NONE", 7278ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 7279ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7280ecd94f1bSKan Liang "SampleAfterValue": "100003", 7281ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 7282ecd94f1bSKan Liang }, 7283ecd94f1bSKan Liang { 7284ecd94f1bSKan Liang "Offcore": "1", 7285ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 7286ecd94f1bSKan Liang "UMask": "0x1", 7287ecd94f1bSKan Liang "BriefDescription": "TBD TBD", 7288ecd94f1bSKan Liang "MSRValue": "0x01000207F7", 7289ecd94f1bSKan Liang "Counter": "0,1,2,3", 7290ecd94f1bSKan Liang "EventName": "OCR.ALL_READS.SUPPLIER_NONE.NO_SNOOP_NEEDED", 7291ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 7292ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7293ecd94f1bSKan Liang "SampleAfterValue": "100003", 7294ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 7295ecd94f1bSKan Liang }, 7296ecd94f1bSKan Liang { 7297ecd94f1bSKan Liang "Offcore": "1", 7298ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 7299ecd94f1bSKan Liang "UMask": "0x1", 7300ecd94f1bSKan Liang "BriefDescription": "TBD", 7301ecd94f1bSKan Liang "MSRValue": "0x02000207F7", 7302ecd94f1bSKan Liang "Counter": "0,1,2,3", 7303ecd94f1bSKan Liang "EventName": "OCR.ALL_READS.SUPPLIER_NONE.SNOOP_MISS", 7304ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 7305ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7306ecd94f1bSKan Liang "SampleAfterValue": "100003", 7307ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 7308ecd94f1bSKan Liang }, 7309ecd94f1bSKan Liang { 7310ecd94f1bSKan Liang "Offcore": "1", 7311ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 7312ecd94f1bSKan Liang "UMask": "0x1", 7313ecd94f1bSKan Liang "BriefDescription": "TBD TBD", 7314ecd94f1bSKan Liang "MSRValue": "0x04000207F7", 7315ecd94f1bSKan Liang "Counter": "0,1,2,3", 7316ecd94f1bSKan Liang "EventName": "OCR.ALL_READS.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", 7317ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 7318ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7319ecd94f1bSKan Liang "SampleAfterValue": "100003", 7320ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 7321ecd94f1bSKan Liang }, 7322ecd94f1bSKan Liang { 7323ecd94f1bSKan Liang "Offcore": "1", 7324ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 7325ecd94f1bSKan Liang "UMask": "0x1", 7326ecd94f1bSKan Liang "BriefDescription": "TBD TBD", 7327ecd94f1bSKan Liang "MSRValue": "0x08000207F7", 7328ecd94f1bSKan Liang "Counter": "0,1,2,3", 7329ecd94f1bSKan Liang "EventName": "OCR.ALL_READS.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", 7330ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 7331ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7332ecd94f1bSKan Liang "SampleAfterValue": "100003", 7333ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 7334ecd94f1bSKan Liang }, 7335ecd94f1bSKan Liang { 7336ecd94f1bSKan Liang "Offcore": "1", 7337ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 7338ecd94f1bSKan Liang "UMask": "0x1", 7339ecd94f1bSKan Liang "BriefDescription": "TBD TBD", 7340ecd94f1bSKan Liang "MSRValue": "0x10000207F7", 7341ecd94f1bSKan Liang "Counter": "0,1,2,3", 7342ecd94f1bSKan Liang "EventName": "OCR.ALL_READS.SUPPLIER_NONE.HITM_OTHER_CORE", 7343ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 7344ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7345ecd94f1bSKan Liang "SampleAfterValue": "100003", 7346ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 7347ecd94f1bSKan Liang }, 7348ecd94f1bSKan Liang { 7349ecd94f1bSKan Liang "Offcore": "1", 7350ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 7351ecd94f1bSKan Liang "UMask": "0x1", 7352ecd94f1bSKan Liang "BriefDescription": "TBD TBD", 7353ecd94f1bSKan Liang "MSRValue": "0x3F800207F7", 7354ecd94f1bSKan Liang "Counter": "0,1,2,3", 7355ecd94f1bSKan Liang "EventName": "OCR.ALL_READS.SUPPLIER_NONE.ANY_SNOOP", 7356ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 7357ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7358ecd94f1bSKan Liang "SampleAfterValue": "100003", 7359ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 7360ecd94f1bSKan Liang }, 7361ecd94f1bSKan Liang { 7362ecd94f1bSKan Liang "Offcore": "1", 7363ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 7364ecd94f1bSKan Liang "UMask": "0x1", 7365ecd94f1bSKan Liang "BriefDescription": "TBD", 7366ecd94f1bSKan Liang "MSRValue": "0x00800407F7", 7367ecd94f1bSKan Liang "Counter": "0,1,2,3", 7368ecd94f1bSKan Liang "EventName": "OCR.ALL_READS.L3_HIT_M.SNOOP_NONE", 7369ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 7370ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7371ecd94f1bSKan Liang "SampleAfterValue": "100003", 7372ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 7373ecd94f1bSKan Liang }, 7374ecd94f1bSKan Liang { 7375ecd94f1bSKan Liang "Offcore": "1", 7376ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 7377ecd94f1bSKan Liang "UMask": "0x1", 7378ecd94f1bSKan Liang "BriefDescription": "TBD TBD", 7379ecd94f1bSKan Liang "MSRValue": "0x01000407F7", 7380ecd94f1bSKan Liang "Counter": "0,1,2,3", 7381ecd94f1bSKan Liang "EventName": "OCR.ALL_READS.L3_HIT_M.NO_SNOOP_NEEDED", 7382ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 7383ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7384ecd94f1bSKan Liang "SampleAfterValue": "100003", 7385ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 7386ecd94f1bSKan Liang }, 7387ecd94f1bSKan Liang { 7388ecd94f1bSKan Liang "Offcore": "1", 7389ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 7390ecd94f1bSKan Liang "UMask": "0x1", 7391ecd94f1bSKan Liang "BriefDescription": "TBD", 7392ecd94f1bSKan Liang "MSRValue": "0x02000407F7", 7393ecd94f1bSKan Liang "Counter": "0,1,2,3", 7394ecd94f1bSKan Liang "EventName": "OCR.ALL_READS.L3_HIT_M.SNOOP_MISS", 7395ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 7396ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7397ecd94f1bSKan Liang "SampleAfterValue": "100003", 7398ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 7399ecd94f1bSKan Liang }, 7400ecd94f1bSKan Liang { 7401ecd94f1bSKan Liang "Offcore": "1", 7402ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 7403ecd94f1bSKan Liang "UMask": "0x1", 7404ecd94f1bSKan Liang "BriefDescription": "TBD TBD", 7405ecd94f1bSKan Liang "MSRValue": "0x04000407F7", 7406ecd94f1bSKan Liang "Counter": "0,1,2,3", 7407ecd94f1bSKan Liang "EventName": "OCR.ALL_READS.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", 7408ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 7409ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7410ecd94f1bSKan Liang "SampleAfterValue": "100003", 7411ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 7412ecd94f1bSKan Liang }, 7413ecd94f1bSKan Liang { 7414ecd94f1bSKan Liang "Offcore": "1", 7415ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 7416ecd94f1bSKan Liang "UMask": "0x1", 7417ecd94f1bSKan Liang "BriefDescription": "TBD TBD", 7418ecd94f1bSKan Liang "MSRValue": "0x08000407F7", 7419ecd94f1bSKan Liang "Counter": "0,1,2,3", 7420ecd94f1bSKan Liang "EventName": "OCR.ALL_READS.L3_HIT_M.HIT_OTHER_CORE_FWD", 7421ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 7422ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7423ecd94f1bSKan Liang "SampleAfterValue": "100003", 7424ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 7425ecd94f1bSKan Liang }, 7426ecd94f1bSKan Liang { 7427ecd94f1bSKan Liang "Offcore": "1", 7428ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 7429ecd94f1bSKan Liang "UMask": "0x1", 7430ecd94f1bSKan Liang "BriefDescription": "TBD TBD", 7431ecd94f1bSKan Liang "MSRValue": "0x10000407F7", 7432ecd94f1bSKan Liang "Counter": "0,1,2,3", 7433ecd94f1bSKan Liang "EventName": "OCR.ALL_READS.L3_HIT_M.HITM_OTHER_CORE", 7434ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 7435ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7436ecd94f1bSKan Liang "SampleAfterValue": "100003", 7437ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 7438ecd94f1bSKan Liang }, 7439ecd94f1bSKan Liang { 7440ecd94f1bSKan Liang "Offcore": "1", 7441ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 7442ecd94f1bSKan Liang "UMask": "0x1", 7443ecd94f1bSKan Liang "BriefDescription": "TBD TBD", 7444ecd94f1bSKan Liang "MSRValue": "0x3F800407F7", 7445ecd94f1bSKan Liang "Counter": "0,1,2,3", 7446ecd94f1bSKan Liang "EventName": "OCR.ALL_READS.L3_HIT_M.ANY_SNOOP", 7447ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 7448ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7449ecd94f1bSKan Liang "SampleAfterValue": "100003", 7450ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 7451ecd94f1bSKan Liang }, 7452ecd94f1bSKan Liang { 7453ecd94f1bSKan Liang "Offcore": "1", 7454ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 7455ecd94f1bSKan Liang "UMask": "0x1", 7456ecd94f1bSKan Liang "BriefDescription": "TBD", 7457ecd94f1bSKan Liang "MSRValue": "0x00800807F7", 7458ecd94f1bSKan Liang "Counter": "0,1,2,3", 7459ecd94f1bSKan Liang "EventName": "OCR.ALL_READS.L3_HIT_E.SNOOP_NONE", 7460ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 7461ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7462ecd94f1bSKan Liang "SampleAfterValue": "100003", 7463ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 7464ecd94f1bSKan Liang }, 7465ecd94f1bSKan Liang { 7466ecd94f1bSKan Liang "Offcore": "1", 7467ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 7468ecd94f1bSKan Liang "UMask": "0x1", 7469ecd94f1bSKan Liang "BriefDescription": "TBD TBD", 7470ecd94f1bSKan Liang "MSRValue": "0x01000807F7", 7471ecd94f1bSKan Liang "Counter": "0,1,2,3", 7472ecd94f1bSKan Liang "EventName": "OCR.ALL_READS.L3_HIT_E.NO_SNOOP_NEEDED", 7473ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 7474ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7475ecd94f1bSKan Liang "SampleAfterValue": "100003", 7476ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 7477ecd94f1bSKan Liang }, 7478ecd94f1bSKan Liang { 7479ecd94f1bSKan Liang "Offcore": "1", 7480ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 7481ecd94f1bSKan Liang "UMask": "0x1", 7482ecd94f1bSKan Liang "BriefDescription": "TBD", 7483ecd94f1bSKan Liang "MSRValue": "0x02000807F7", 7484ecd94f1bSKan Liang "Counter": "0,1,2,3", 7485ecd94f1bSKan Liang "EventName": "OCR.ALL_READS.L3_HIT_E.SNOOP_MISS", 7486ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 7487ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7488ecd94f1bSKan Liang "SampleAfterValue": "100003", 7489ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 7490ecd94f1bSKan Liang }, 7491ecd94f1bSKan Liang { 7492ecd94f1bSKan Liang "Offcore": "1", 7493ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 7494ecd94f1bSKan Liang "UMask": "0x1", 7495ecd94f1bSKan Liang "BriefDescription": "TBD TBD", 7496ecd94f1bSKan Liang "MSRValue": "0x04000807F7", 7497ecd94f1bSKan Liang "Counter": "0,1,2,3", 7498ecd94f1bSKan Liang "EventName": "OCR.ALL_READS.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", 7499ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 7500ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7501ecd94f1bSKan Liang "SampleAfterValue": "100003", 7502ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 7503ecd94f1bSKan Liang }, 7504ecd94f1bSKan Liang { 7505ecd94f1bSKan Liang "Offcore": "1", 7506ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 7507ecd94f1bSKan Liang "UMask": "0x1", 7508ecd94f1bSKan Liang "BriefDescription": "TBD TBD", 7509ecd94f1bSKan Liang "MSRValue": "0x08000807F7", 7510ecd94f1bSKan Liang "Counter": "0,1,2,3", 7511ecd94f1bSKan Liang "EventName": "OCR.ALL_READS.L3_HIT_E.HIT_OTHER_CORE_FWD", 7512ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 7513ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7514ecd94f1bSKan Liang "SampleAfterValue": "100003", 7515ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 7516ecd94f1bSKan Liang }, 7517ecd94f1bSKan Liang { 7518ecd94f1bSKan Liang "Offcore": "1", 7519ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 7520ecd94f1bSKan Liang "UMask": "0x1", 7521ecd94f1bSKan Liang "BriefDescription": "TBD TBD", 7522ecd94f1bSKan Liang "MSRValue": "0x10000807F7", 7523ecd94f1bSKan Liang "Counter": "0,1,2,3", 7524ecd94f1bSKan Liang "EventName": "OCR.ALL_READS.L3_HIT_E.HITM_OTHER_CORE", 7525ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 7526ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7527ecd94f1bSKan Liang "SampleAfterValue": "100003", 7528ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 7529ecd94f1bSKan Liang }, 7530ecd94f1bSKan Liang { 7531ecd94f1bSKan Liang "Offcore": "1", 7532ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 7533ecd94f1bSKan Liang "UMask": "0x1", 7534ecd94f1bSKan Liang "BriefDescription": "TBD TBD", 7535ecd94f1bSKan Liang "MSRValue": "0x3F800807F7", 7536ecd94f1bSKan Liang "Counter": "0,1,2,3", 7537ecd94f1bSKan Liang "EventName": "OCR.ALL_READS.L3_HIT_E.ANY_SNOOP", 7538ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 7539ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7540ecd94f1bSKan Liang "SampleAfterValue": "100003", 7541ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 7542ecd94f1bSKan Liang }, 7543ecd94f1bSKan Liang { 7544ecd94f1bSKan Liang "Offcore": "1", 7545ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 7546ecd94f1bSKan Liang "UMask": "0x1", 7547ecd94f1bSKan Liang "BriefDescription": "TBD", 7548ecd94f1bSKan Liang "MSRValue": "0x00801007F7", 7549ecd94f1bSKan Liang "Counter": "0,1,2,3", 7550ecd94f1bSKan Liang "EventName": "OCR.ALL_READS.L3_HIT_S.SNOOP_NONE", 7551ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 7552ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7553ecd94f1bSKan Liang "SampleAfterValue": "100003", 7554ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 7555ecd94f1bSKan Liang }, 7556ecd94f1bSKan Liang { 7557ecd94f1bSKan Liang "Offcore": "1", 7558ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 7559ecd94f1bSKan Liang "UMask": "0x1", 7560ecd94f1bSKan Liang "BriefDescription": "TBD TBD", 7561ecd94f1bSKan Liang "MSRValue": "0x01001007F7", 7562ecd94f1bSKan Liang "Counter": "0,1,2,3", 7563ecd94f1bSKan Liang "EventName": "OCR.ALL_READS.L3_HIT_S.NO_SNOOP_NEEDED", 7564ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 7565ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7566ecd94f1bSKan Liang "SampleAfterValue": "100003", 7567ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 7568ecd94f1bSKan Liang }, 7569ecd94f1bSKan Liang { 7570ecd94f1bSKan Liang "Offcore": "1", 7571ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 7572ecd94f1bSKan Liang "UMask": "0x1", 7573ecd94f1bSKan Liang "BriefDescription": "TBD", 7574ecd94f1bSKan Liang "MSRValue": "0x02001007F7", 7575ecd94f1bSKan Liang "Counter": "0,1,2,3", 7576ecd94f1bSKan Liang "EventName": "OCR.ALL_READS.L3_HIT_S.SNOOP_MISS", 7577ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 7578ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7579ecd94f1bSKan Liang "SampleAfterValue": "100003", 7580ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 7581ecd94f1bSKan Liang }, 7582ecd94f1bSKan Liang { 7583ecd94f1bSKan Liang "Offcore": "1", 7584ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 7585ecd94f1bSKan Liang "UMask": "0x1", 7586ecd94f1bSKan Liang "BriefDescription": "TBD TBD", 7587ecd94f1bSKan Liang "MSRValue": "0x04001007F7", 7588ecd94f1bSKan Liang "Counter": "0,1,2,3", 7589ecd94f1bSKan Liang "EventName": "OCR.ALL_READS.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", 7590ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 7591ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7592ecd94f1bSKan Liang "SampleAfterValue": "100003", 7593ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 7594ecd94f1bSKan Liang }, 7595ecd94f1bSKan Liang { 7596ecd94f1bSKan Liang "Offcore": "1", 7597ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 7598ecd94f1bSKan Liang "UMask": "0x1", 7599ecd94f1bSKan Liang "BriefDescription": "TBD TBD", 7600ecd94f1bSKan Liang "MSRValue": "0x08001007F7", 7601ecd94f1bSKan Liang "Counter": "0,1,2,3", 7602ecd94f1bSKan Liang "EventName": "OCR.ALL_READS.L3_HIT_S.HIT_OTHER_CORE_FWD", 7603ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 7604ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7605ecd94f1bSKan Liang "SampleAfterValue": "100003", 7606ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 7607ecd94f1bSKan Liang }, 7608ecd94f1bSKan Liang { 7609ecd94f1bSKan Liang "Offcore": "1", 7610ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 7611ecd94f1bSKan Liang "UMask": "0x1", 7612ecd94f1bSKan Liang "BriefDescription": "TBD TBD", 7613ecd94f1bSKan Liang "MSRValue": "0x10001007F7", 7614ecd94f1bSKan Liang "Counter": "0,1,2,3", 7615ecd94f1bSKan Liang "EventName": "OCR.ALL_READS.L3_HIT_S.HITM_OTHER_CORE", 7616ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 7617ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7618ecd94f1bSKan Liang "SampleAfterValue": "100003", 7619ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 7620ecd94f1bSKan Liang }, 7621ecd94f1bSKan Liang { 7622ecd94f1bSKan Liang "Offcore": "1", 7623ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 7624ecd94f1bSKan Liang "UMask": "0x1", 7625ecd94f1bSKan Liang "BriefDescription": "TBD TBD", 7626ecd94f1bSKan Liang "MSRValue": "0x3F801007F7", 7627ecd94f1bSKan Liang "Counter": "0,1,2,3", 7628ecd94f1bSKan Liang "EventName": "OCR.ALL_READS.L3_HIT_S.ANY_SNOOP", 7629ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 7630ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7631ecd94f1bSKan Liang "SampleAfterValue": "100003", 7632ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 7633ecd94f1bSKan Liang }, 7634ecd94f1bSKan Liang { 7635ecd94f1bSKan Liang "Offcore": "1", 7636ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 7637ecd94f1bSKan Liang "UMask": "0x1", 7638ecd94f1bSKan Liang "BriefDescription": "TBD", 7639ecd94f1bSKan Liang "MSRValue": "0x00802007F7", 7640ecd94f1bSKan Liang "Counter": "0,1,2,3", 7641ecd94f1bSKan Liang "EventName": "OCR.ALL_READS.L3_HIT_F.SNOOP_NONE", 7642ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 7643ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7644ecd94f1bSKan Liang "SampleAfterValue": "100003", 7645ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 7646ecd94f1bSKan Liang }, 7647ecd94f1bSKan Liang { 7648ecd94f1bSKan Liang "Offcore": "1", 7649ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 7650ecd94f1bSKan Liang "UMask": "0x1", 7651ecd94f1bSKan Liang "BriefDescription": "TBD TBD", 7652ecd94f1bSKan Liang "MSRValue": "0x01002007F7", 7653ecd94f1bSKan Liang "Counter": "0,1,2,3", 7654ecd94f1bSKan Liang "EventName": "OCR.ALL_READS.L3_HIT_F.NO_SNOOP_NEEDED", 7655ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 7656ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7657ecd94f1bSKan Liang "SampleAfterValue": "100003", 7658ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 7659ecd94f1bSKan Liang }, 7660ecd94f1bSKan Liang { 7661ecd94f1bSKan Liang "Offcore": "1", 7662ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 7663ecd94f1bSKan Liang "UMask": "0x1", 7664ecd94f1bSKan Liang "BriefDescription": "TBD", 7665ecd94f1bSKan Liang "MSRValue": "0x02002007F7", 7666ecd94f1bSKan Liang "Counter": "0,1,2,3", 7667ecd94f1bSKan Liang "EventName": "OCR.ALL_READS.L3_HIT_F.SNOOP_MISS", 7668ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 7669ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7670ecd94f1bSKan Liang "SampleAfterValue": "100003", 7671ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 7672ecd94f1bSKan Liang }, 7673ecd94f1bSKan Liang { 7674ecd94f1bSKan Liang "Offcore": "1", 7675ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 7676ecd94f1bSKan Liang "UMask": "0x1", 7677ecd94f1bSKan Liang "BriefDescription": "TBD TBD", 7678ecd94f1bSKan Liang "MSRValue": "0x04002007F7", 7679ecd94f1bSKan Liang "Counter": "0,1,2,3", 7680ecd94f1bSKan Liang "EventName": "OCR.ALL_READS.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", 7681ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 7682ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7683ecd94f1bSKan Liang "SampleAfterValue": "100003", 7684ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 7685ecd94f1bSKan Liang }, 7686ecd94f1bSKan Liang { 7687ecd94f1bSKan Liang "Offcore": "1", 7688ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 7689ecd94f1bSKan Liang "UMask": "0x1", 7690ecd94f1bSKan Liang "BriefDescription": "TBD TBD", 7691ecd94f1bSKan Liang "MSRValue": "0x08002007F7", 7692ecd94f1bSKan Liang "Counter": "0,1,2,3", 7693ecd94f1bSKan Liang "EventName": "OCR.ALL_READS.L3_HIT_F.HIT_OTHER_CORE_FWD", 7694ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 7695ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7696ecd94f1bSKan Liang "SampleAfterValue": "100003", 7697ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 7698ecd94f1bSKan Liang }, 7699ecd94f1bSKan Liang { 7700ecd94f1bSKan Liang "Offcore": "1", 7701ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 7702ecd94f1bSKan Liang "UMask": "0x1", 7703ecd94f1bSKan Liang "BriefDescription": "TBD TBD", 7704ecd94f1bSKan Liang "MSRValue": "0x10002007F7", 7705ecd94f1bSKan Liang "Counter": "0,1,2,3", 7706ecd94f1bSKan Liang "EventName": "OCR.ALL_READS.L3_HIT_F.HITM_OTHER_CORE", 7707ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 7708ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7709ecd94f1bSKan Liang "SampleAfterValue": "100003", 7710ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 7711ecd94f1bSKan Liang }, 7712ecd94f1bSKan Liang { 7713ecd94f1bSKan Liang "Offcore": "1", 7714ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 7715ecd94f1bSKan Liang "UMask": "0x1", 7716ecd94f1bSKan Liang "BriefDescription": "TBD TBD", 7717ecd94f1bSKan Liang "MSRValue": "0x3F802007F7", 7718ecd94f1bSKan Liang "Counter": "0,1,2,3", 7719ecd94f1bSKan Liang "EventName": "OCR.ALL_READS.L3_HIT_F.ANY_SNOOP", 7720ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 7721ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7722ecd94f1bSKan Liang "SampleAfterValue": "100003", 7723ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 7724ecd94f1bSKan Liang }, 7725ecd94f1bSKan Liang { 7726ecd94f1bSKan Liang "Offcore": "1", 7727ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 7728ecd94f1bSKan Liang "UMask": "0x1", 7729ecd94f1bSKan Liang "BriefDescription": "TBD TBD", 7730ecd94f1bSKan Liang "MSRValue": "0x00803C07F7", 7731ecd94f1bSKan Liang "Counter": "0,1,2,3", 7732ecd94f1bSKan Liang "EventName": "OCR.ALL_READS.L3_HIT.SNOOP_NONE", 7733ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 7734ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7735ecd94f1bSKan Liang "SampleAfterValue": "100003", 7736ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 7737ecd94f1bSKan Liang }, 7738ecd94f1bSKan Liang { 7739ecd94f1bSKan Liang "Offcore": "1", 7740ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 7741ecd94f1bSKan Liang "UMask": "0x1", 7742ecd94f1bSKan Liang "BriefDescription": "TBD TBD TBD", 7743ecd94f1bSKan Liang "MSRValue": "0x01003C07F7", 7744ecd94f1bSKan Liang "Counter": "0,1,2,3", 7745ecd94f1bSKan Liang "EventName": "OCR.ALL_READS.L3_HIT.NO_SNOOP_NEEDED", 7746ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 7747ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7748ecd94f1bSKan Liang "SampleAfterValue": "100003", 7749ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 7750ecd94f1bSKan Liang }, 7751ecd94f1bSKan Liang { 7752ecd94f1bSKan Liang "Offcore": "1", 7753ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 7754ecd94f1bSKan Liang "UMask": "0x1", 7755ecd94f1bSKan Liang "BriefDescription": "TBD TBD", 7756ecd94f1bSKan Liang "MSRValue": "0x02003C07F7", 7757ecd94f1bSKan Liang "Counter": "0,1,2,3", 7758ecd94f1bSKan Liang "EventName": "OCR.ALL_READS.L3_HIT.SNOOP_MISS", 7759ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 7760ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7761ecd94f1bSKan Liang "SampleAfterValue": "100003", 7762ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 7763ecd94f1bSKan Liang }, 7764ecd94f1bSKan Liang { 7765ecd94f1bSKan Liang "Offcore": "1", 7766ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 7767ecd94f1bSKan Liang "UMask": "0x1", 7768ecd94f1bSKan Liang "BriefDescription": "TBD TBD TBD", 7769ecd94f1bSKan Liang "MSRValue": "0x04003C07F7", 7770ecd94f1bSKan Liang "Counter": "0,1,2,3", 7771ecd94f1bSKan Liang "EventName": "OCR.ALL_READS.L3_HIT.HIT_OTHER_CORE_NO_FWD", 7772ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 7773ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7774ecd94f1bSKan Liang "SampleAfterValue": "100003", 7775ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 7776ecd94f1bSKan Liang }, 7777ecd94f1bSKan Liang { 7778ecd94f1bSKan Liang "Offcore": "1", 7779ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 7780ecd94f1bSKan Liang "UMask": "0x1", 7781ecd94f1bSKan Liang "BriefDescription": "TBD TBD TBD", 7782ecd94f1bSKan Liang "MSRValue": "0x08003C07F7", 7783ecd94f1bSKan Liang "Counter": "0,1,2,3", 7784ecd94f1bSKan Liang "EventName": "OCR.ALL_READS.L3_HIT.HIT_OTHER_CORE_FWD", 7785ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 7786ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7787ecd94f1bSKan Liang "SampleAfterValue": "100003", 7788ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 7789ecd94f1bSKan Liang }, 7790ecd94f1bSKan Liang { 7791ecd94f1bSKan Liang "Offcore": "1", 7792ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 7793ecd94f1bSKan Liang "UMask": "0x1", 7794ecd94f1bSKan Liang "BriefDescription": "TBD TBD TBD", 7795ecd94f1bSKan Liang "MSRValue": "0x10003C07F7", 7796ecd94f1bSKan Liang "Counter": "0,1,2,3", 7797ecd94f1bSKan Liang "EventName": "OCR.ALL_READS.L3_HIT.HITM_OTHER_CORE", 7798ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 7799ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7800ecd94f1bSKan Liang "SampleAfterValue": "100003", 7801ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 7802ecd94f1bSKan Liang }, 7803ecd94f1bSKan Liang { 7804ecd94f1bSKan Liang "Offcore": "1", 7805ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 7806ecd94f1bSKan Liang "UMask": "0x1", 7807ecd94f1bSKan Liang "BriefDescription": "TBD TBD TBD", 7808ecd94f1bSKan Liang "MSRValue": "0x3F803C07F7", 7809ecd94f1bSKan Liang "Counter": "0,1,2,3", 7810ecd94f1bSKan Liang "EventName": "OCR.ALL_READS.L3_HIT.ANY_SNOOP", 7811ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 7812ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7813ecd94f1bSKan Liang "SampleAfterValue": "100003", 7814ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 7815ecd94f1bSKan Liang }, 7816ecd94f1bSKan Liang { 7817ecd94f1bSKan Liang "Offcore": "1", 7818ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 7819ecd94f1bSKan Liang "UMask": "0x1", 7820ecd94f1bSKan Liang "BriefDescription": "Counts demand data reads have any response type.", 7821ecd94f1bSKan Liang "MSRValue": "0x0000010001", 7822ecd94f1bSKan Liang "Counter": "0,1,2,3", 7823ecd94f1bSKan Liang "EventName": "OCR.DEMAND_DATA_RD.ANY_RESPONSE", 7824ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 7825ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7826ecd94f1bSKan Liang "SampleAfterValue": "100003", 7827ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 7828ecd94f1bSKan Liang }, 7829ecd94f1bSKan Liang { 7830ecd94f1bSKan Liang "Offcore": "1", 7831ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 7832ecd94f1bSKan Liang "UMask": "0x1", 7833ecd94f1bSKan Liang "BriefDescription": "Counts demand data reads hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.", 7834ecd94f1bSKan Liang "MSRValue": "0x01003C0001", 7835ecd94f1bSKan Liang "Counter": "0,1,2,3", 7836ecd94f1bSKan Liang "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.NO_SNOOP_NEEDED", 7837ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 7838ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7839ecd94f1bSKan Liang "SampleAfterValue": "100003", 7840ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 7841ecd94f1bSKan Liang }, 7842ecd94f1bSKan Liang { 7843ecd94f1bSKan Liang "Offcore": "1", 7844ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 7845ecd94f1bSKan Liang "UMask": "0x1", 7846ecd94f1bSKan Liang "BriefDescription": "Counts demand data reads", 7847ecd94f1bSKan Liang "MSRValue": "0x08007C0001", 7848ecd94f1bSKan Liang "Counter": "0,1,2,3", 7849ecd94f1bSKan Liang "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD", 7850ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 7851ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7852ecd94f1bSKan Liang "SampleAfterValue": "100003", 7853ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 7854ecd94f1bSKan Liang }, 7855ecd94f1bSKan Liang { 7856ecd94f1bSKan Liang "Offcore": "1", 7857ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 7858ecd94f1bSKan Liang "UMask": "0x1", 7859ecd94f1bSKan Liang "BriefDescription": "Counts all demand data writes (RFOs) have any response type.", 7860ecd94f1bSKan Liang "MSRValue": "0x0000010002", 7861ecd94f1bSKan Liang "Counter": "0,1,2,3", 7862ecd94f1bSKan Liang "EventName": "OCR.DEMAND_RFO.ANY_RESPONSE", 7863ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 7864ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7865ecd94f1bSKan Liang "SampleAfterValue": "100003", 7866ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 7867ecd94f1bSKan Liang }, 7868ecd94f1bSKan Liang { 7869ecd94f1bSKan Liang "Offcore": "1", 7870ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 7871ecd94f1bSKan Liang "UMask": "0x1", 7872ecd94f1bSKan Liang "BriefDescription": "Counts all demand data writes (RFOs) hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.", 7873ecd94f1bSKan Liang "MSRValue": "0x01003C0002", 7874ecd94f1bSKan Liang "Counter": "0,1,2,3", 7875ecd94f1bSKan Liang "EventName": "OCR.DEMAND_RFO.L3_HIT.NO_SNOOP_NEEDED", 7876ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 7877ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7878ecd94f1bSKan Liang "SampleAfterValue": "100003", 7879ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 7880ecd94f1bSKan Liang }, 7881ecd94f1bSKan Liang { 7882ecd94f1bSKan Liang "Offcore": "1", 7883ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 7884ecd94f1bSKan Liang "UMask": "0x1", 7885ecd94f1bSKan Liang "BriefDescription": "Counts all demand data writes (RFOs)", 7886ecd94f1bSKan Liang "MSRValue": "0x08007C0002", 7887ecd94f1bSKan Liang "Counter": "0,1,2,3", 7888ecd94f1bSKan Liang "EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_HIT_WITH_FWD", 7889ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 7890ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7891ecd94f1bSKan Liang "SampleAfterValue": "100003", 7892ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 7893ecd94f1bSKan Liang }, 7894ecd94f1bSKan Liang { 7895ecd94f1bSKan Liang "Offcore": "1", 7896ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 7897ecd94f1bSKan Liang "UMask": "0x1", 7898ecd94f1bSKan Liang "BriefDescription": "Counts all demand code reads have any response type.", 7899ecd94f1bSKan Liang "MSRValue": "0x0000010004", 7900ecd94f1bSKan Liang "Counter": "0,1,2,3", 7901ecd94f1bSKan Liang "EventName": "OCR.DEMAND_CODE_RD.ANY_RESPONSE", 7902ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 7903ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7904ecd94f1bSKan Liang "SampleAfterValue": "100003", 7905ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 7906ecd94f1bSKan Liang }, 7907ecd94f1bSKan Liang { 7908ecd94f1bSKan Liang "Offcore": "1", 7909ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 7910ecd94f1bSKan Liang "UMask": "0x1", 7911ecd94f1bSKan Liang "BriefDescription": "Counts all demand code reads hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.", 7912ecd94f1bSKan Liang "MSRValue": "0x01003C0004", 7913ecd94f1bSKan Liang "Counter": "0,1,2,3", 7914ecd94f1bSKan Liang "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.NO_SNOOP_NEEDED", 7915ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 7916ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7917ecd94f1bSKan Liang "SampleAfterValue": "100003", 7918ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 7919ecd94f1bSKan Liang }, 7920ecd94f1bSKan Liang { 7921ecd94f1bSKan Liang "Offcore": "1", 7922ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 7923ecd94f1bSKan Liang "UMask": "0x1", 7924ecd94f1bSKan Liang "BriefDescription": "Counts all demand code reads", 7925ecd94f1bSKan Liang "MSRValue": "0x08007C0004", 7926ecd94f1bSKan Liang "Counter": "0,1,2,3", 7927ecd94f1bSKan Liang "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_HIT_WITH_FWD", 7928ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 7929ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7930ecd94f1bSKan Liang "SampleAfterValue": "100003", 7931ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 7932ecd94f1bSKan Liang }, 7933ecd94f1bSKan Liang { 7934ecd94f1bSKan Liang "Offcore": "1", 7935ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 7936ecd94f1bSKan Liang "UMask": "0x1", 7937ecd94f1bSKan Liang "BriefDescription": "Counts prefetch (that bring data to L2) data reads have any response type.", 7938ecd94f1bSKan Liang "MSRValue": "0x0000010010", 7939ecd94f1bSKan Liang "Counter": "0,1,2,3", 7940ecd94f1bSKan Liang "EventName": "OCR.PF_L2_DATA_RD.ANY_RESPONSE", 7941ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 7942ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7943ecd94f1bSKan Liang "SampleAfterValue": "100003", 7944ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 7945ecd94f1bSKan Liang }, 7946ecd94f1bSKan Liang { 7947ecd94f1bSKan Liang "Offcore": "1", 7948ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 7949ecd94f1bSKan Liang "UMask": "0x1", 7950ecd94f1bSKan Liang "BriefDescription": "Counts prefetch (that bring data to L2) data reads hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.", 7951ecd94f1bSKan Liang "MSRValue": "0x01003C0010", 7952ecd94f1bSKan Liang "Counter": "0,1,2,3", 7953ecd94f1bSKan Liang "EventName": "OCR.PF_L2_DATA_RD.L3_HIT.NO_SNOOP_NEEDED", 7954ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 7955ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7956ecd94f1bSKan Liang "SampleAfterValue": "100003", 7957ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 7958ecd94f1bSKan Liang }, 7959ecd94f1bSKan Liang { 7960ecd94f1bSKan Liang "Offcore": "1", 7961ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 7962ecd94f1bSKan Liang "UMask": "0x1", 7963ecd94f1bSKan Liang "BriefDescription": "Counts prefetch (that bring data to L2) data reads", 7964ecd94f1bSKan Liang "MSRValue": "0x08007C0010", 7965ecd94f1bSKan Liang "Counter": "0,1,2,3", 7966ecd94f1bSKan Liang "EventName": "OCR.PF_L2_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD", 7967ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 7968ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7969ecd94f1bSKan Liang "SampleAfterValue": "100003", 7970ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 7971ecd94f1bSKan Liang }, 7972ecd94f1bSKan Liang { 7973ecd94f1bSKan Liang "Offcore": "1", 7974ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 7975ecd94f1bSKan Liang "UMask": "0x1", 7976ecd94f1bSKan Liang "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs have any response type.", 7977ecd94f1bSKan Liang "MSRValue": "0x0000010020", 7978ecd94f1bSKan Liang "Counter": "0,1,2,3", 7979ecd94f1bSKan Liang "EventName": "OCR.PF_L2_RFO.ANY_RESPONSE", 7980ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 7981ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7982ecd94f1bSKan Liang "SampleAfterValue": "100003", 7983ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 7984ecd94f1bSKan Liang }, 7985ecd94f1bSKan Liang { 7986ecd94f1bSKan Liang "Offcore": "1", 7987ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 7988ecd94f1bSKan Liang "UMask": "0x1", 7989ecd94f1bSKan Liang "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.", 7990ecd94f1bSKan Liang "MSRValue": "0x01003C0020", 7991ecd94f1bSKan Liang "Counter": "0,1,2,3", 7992ecd94f1bSKan Liang "EventName": "OCR.PF_L2_RFO.L3_HIT.NO_SNOOP_NEEDED", 7993ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 7994ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7995ecd94f1bSKan Liang "SampleAfterValue": "100003", 7996ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 7997ecd94f1bSKan Liang }, 7998ecd94f1bSKan Liang { 7999ecd94f1bSKan Liang "Offcore": "1", 8000ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 8001ecd94f1bSKan Liang "UMask": "0x1", 8002ecd94f1bSKan Liang "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs", 8003ecd94f1bSKan Liang "MSRValue": "0x08007C0020", 8004ecd94f1bSKan Liang "Counter": "0,1,2,3", 8005ecd94f1bSKan Liang "EventName": "OCR.PF_L2_RFO.L3_HIT.SNOOP_HIT_WITH_FWD", 8006ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 8007ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8008ecd94f1bSKan Liang "SampleAfterValue": "100003", 8009ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 8010ecd94f1bSKan Liang }, 8011ecd94f1bSKan Liang { 8012ecd94f1bSKan Liang "Offcore": "1", 8013ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 8014ecd94f1bSKan Liang "UMask": "0x1", 8015ecd94f1bSKan Liang "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads have any response type.", 8016ecd94f1bSKan Liang "MSRValue": "0x0000010080", 8017ecd94f1bSKan Liang "Counter": "0,1,2,3", 8018ecd94f1bSKan Liang "EventName": "OCR.PF_L3_DATA_RD.ANY_RESPONSE", 8019ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 8020ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8021ecd94f1bSKan Liang "SampleAfterValue": "100003", 8022ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 8023ecd94f1bSKan Liang }, 8024ecd94f1bSKan Liang { 8025ecd94f1bSKan Liang "Offcore": "1", 8026ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 8027ecd94f1bSKan Liang "UMask": "0x1", 8028ecd94f1bSKan Liang "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.", 8029ecd94f1bSKan Liang "MSRValue": "0x01003C0080", 8030ecd94f1bSKan Liang "Counter": "0,1,2,3", 8031ecd94f1bSKan Liang "EventName": "OCR.PF_L3_DATA_RD.L3_HIT.NO_SNOOP_NEEDED", 8032ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 8033ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8034ecd94f1bSKan Liang "SampleAfterValue": "100003", 8035ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 8036ecd94f1bSKan Liang }, 8037ecd94f1bSKan Liang { 8038ecd94f1bSKan Liang "Offcore": "1", 8039ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 8040ecd94f1bSKan Liang "UMask": "0x1", 8041ecd94f1bSKan Liang "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads", 8042ecd94f1bSKan Liang "MSRValue": "0x08007C0080", 8043ecd94f1bSKan Liang "Counter": "0,1,2,3", 8044ecd94f1bSKan Liang "EventName": "OCR.PF_L3_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD", 8045ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 8046ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8047ecd94f1bSKan Liang "SampleAfterValue": "100003", 8048ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 8049ecd94f1bSKan Liang }, 8050ecd94f1bSKan Liang { 8051ecd94f1bSKan Liang "Offcore": "1", 8052ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 8053ecd94f1bSKan Liang "UMask": "0x1", 8054ecd94f1bSKan Liang "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs have any response type.", 8055ecd94f1bSKan Liang "MSRValue": "0x0000010100", 8056ecd94f1bSKan Liang "Counter": "0,1,2,3", 8057ecd94f1bSKan Liang "EventName": "OCR.PF_L3_RFO.ANY_RESPONSE", 8058ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 8059ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8060ecd94f1bSKan Liang "SampleAfterValue": "100003", 8061ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 8062ecd94f1bSKan Liang }, 8063ecd94f1bSKan Liang { 8064ecd94f1bSKan Liang "Offcore": "1", 8065ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 8066ecd94f1bSKan Liang "UMask": "0x1", 8067ecd94f1bSKan Liang "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.", 8068ecd94f1bSKan Liang "MSRValue": "0x01003C0100", 8069ecd94f1bSKan Liang "Counter": "0,1,2,3", 8070ecd94f1bSKan Liang "EventName": "OCR.PF_L3_RFO.L3_HIT.NO_SNOOP_NEEDED", 8071ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 8072ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8073ecd94f1bSKan Liang "SampleAfterValue": "100003", 8074ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 8075ecd94f1bSKan Liang }, 8076ecd94f1bSKan Liang { 8077ecd94f1bSKan Liang "Offcore": "1", 8078ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 8079ecd94f1bSKan Liang "UMask": "0x1", 8080ecd94f1bSKan Liang "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs", 8081ecd94f1bSKan Liang "MSRValue": "0x08007C0100", 8082ecd94f1bSKan Liang "Counter": "0,1,2,3", 8083ecd94f1bSKan Liang "EventName": "OCR.PF_L3_RFO.L3_HIT.SNOOP_HIT_WITH_FWD", 8084ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 8085ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8086ecd94f1bSKan Liang "SampleAfterValue": "100003", 8087ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 8088ecd94f1bSKan Liang }, 8089ecd94f1bSKan Liang { 8090ecd94f1bSKan Liang "Offcore": "1", 8091ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 8092ecd94f1bSKan Liang "UMask": "0x1", 8093ecd94f1bSKan Liang "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests have any response type.", 8094ecd94f1bSKan Liang "MSRValue": "0x0000010400", 8095ecd94f1bSKan Liang "Counter": "0,1,2,3", 8096ecd94f1bSKan Liang "EventName": "OCR.PF_L1D_AND_SW.ANY_RESPONSE", 8097ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 8098ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8099ecd94f1bSKan Liang "SampleAfterValue": "100003", 8100ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 8101ecd94f1bSKan Liang }, 8102ecd94f1bSKan Liang { 8103ecd94f1bSKan Liang "Offcore": "1", 8104ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 8105ecd94f1bSKan Liang "UMask": "0x1", 8106ecd94f1bSKan Liang "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.", 8107ecd94f1bSKan Liang "MSRValue": "0x01003C0400", 8108ecd94f1bSKan Liang "Counter": "0,1,2,3", 8109ecd94f1bSKan Liang "EventName": "OCR.PF_L1D_AND_SW.L3_HIT.NO_SNOOP_NEEDED", 8110ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 8111ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8112ecd94f1bSKan Liang "SampleAfterValue": "100003", 8113ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 8114ecd94f1bSKan Liang }, 8115ecd94f1bSKan Liang { 8116ecd94f1bSKan Liang "Offcore": "1", 8117ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 8118ecd94f1bSKan Liang "UMask": "0x1", 8119ecd94f1bSKan Liang "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests", 8120ecd94f1bSKan Liang "MSRValue": "0x08007C0400", 8121ecd94f1bSKan Liang "Counter": "0,1,2,3", 8122ecd94f1bSKan Liang "EventName": "OCR.PF_L1D_AND_SW.L3_HIT.SNOOP_HIT_WITH_FWD", 8123ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 8124ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8125ecd94f1bSKan Liang "SampleAfterValue": "100003", 8126ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 8127ecd94f1bSKan Liang }, 8128ecd94f1bSKan Liang { 8129ecd94f1bSKan Liang "Offcore": "1", 8130ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 8131ecd94f1bSKan Liang "UMask": "0x1", 8132ecd94f1bSKan Liang "BriefDescription": "Counts any other requests have any response type.", 8133ecd94f1bSKan Liang "MSRValue": "0x0000018000", 8134ecd94f1bSKan Liang "Counter": "0,1,2,3", 8135ecd94f1bSKan Liang "EventName": "OCR.OTHER.ANY_RESPONSE", 8136ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 8137ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8138ecd94f1bSKan Liang "SampleAfterValue": "100003", 8139ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 8140ecd94f1bSKan Liang }, 8141ecd94f1bSKan Liang { 8142ecd94f1bSKan Liang "Offcore": "1", 8143ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 8144ecd94f1bSKan Liang "UMask": "0x1", 8145ecd94f1bSKan Liang "BriefDescription": "Counts any other requests hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.", 8146ecd94f1bSKan Liang "MSRValue": "0x01003C8000", 8147ecd94f1bSKan Liang "Counter": "0,1,2,3", 8148ecd94f1bSKan Liang "EventName": "OCR.OTHER.L3_HIT.NO_SNOOP_NEEDED", 8149ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 8150ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8151ecd94f1bSKan Liang "SampleAfterValue": "100003", 8152ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 8153ecd94f1bSKan Liang }, 8154ecd94f1bSKan Liang { 8155ecd94f1bSKan Liang "Offcore": "1", 8156ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 8157ecd94f1bSKan Liang "UMask": "0x1", 8158ecd94f1bSKan Liang "BriefDescription": "Counts any other requests", 8159ecd94f1bSKan Liang "MSRValue": "0x08007C8000", 8160ecd94f1bSKan Liang "Counter": "0,1,2,3", 8161ecd94f1bSKan Liang "EventName": "OCR.OTHER.L3_HIT.SNOOP_HIT_WITH_FWD", 8162ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 8163ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8164ecd94f1bSKan Liang "SampleAfterValue": "100003", 8165ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 8166ecd94f1bSKan Liang }, 8167ecd94f1bSKan Liang { 8168ecd94f1bSKan Liang "Offcore": "1", 8169ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 8170ecd94f1bSKan Liang "UMask": "0x1", 8171ecd94f1bSKan Liang "BriefDescription": "TBD have any response type.", 8172ecd94f1bSKan Liang "MSRValue": "0x0000010490", 8173ecd94f1bSKan Liang "Counter": "0,1,2,3", 8174ecd94f1bSKan Liang "EventName": "OCR.ALL_PF_DATA_RD.ANY_RESPONSE", 8175ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 8176ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8177ecd94f1bSKan Liang "SampleAfterValue": "100003", 8178ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 8179ecd94f1bSKan Liang }, 8180ecd94f1bSKan Liang { 8181ecd94f1bSKan Liang "Offcore": "1", 8182ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 8183ecd94f1bSKan Liang "UMask": "0x1", 8184ecd94f1bSKan Liang "BriefDescription": "TBD hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.", 8185ecd94f1bSKan Liang "MSRValue": "0x01003C0490", 8186ecd94f1bSKan Liang "Counter": "0,1,2,3", 8187ecd94f1bSKan Liang "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT.NO_SNOOP_NEEDED", 8188ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 8189ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8190ecd94f1bSKan Liang "SampleAfterValue": "100003", 8191ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 8192ecd94f1bSKan Liang }, 8193ecd94f1bSKan Liang { 8194ecd94f1bSKan Liang "Offcore": "1", 8195ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 8196ecd94f1bSKan Liang "UMask": "0x1", 8197ecd94f1bSKan Liang "BriefDescription": "TBD", 8198ecd94f1bSKan Liang "MSRValue": "0x08007C0490", 8199ecd94f1bSKan Liang "Counter": "0,1,2,3", 8200ecd94f1bSKan Liang "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD", 8201ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 8202ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8203ecd94f1bSKan Liang "SampleAfterValue": "100003", 8204ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 8205ecd94f1bSKan Liang }, 8206ecd94f1bSKan Liang { 8207ecd94f1bSKan Liang "Offcore": "1", 8208ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 8209ecd94f1bSKan Liang "UMask": "0x1", 8210ecd94f1bSKan Liang "BriefDescription": "TBD have any response type.", 8211ecd94f1bSKan Liang "MSRValue": "0x0000010120", 8212ecd94f1bSKan Liang "Counter": "0,1,2,3", 8213ecd94f1bSKan Liang "EventName": "OCR.ALL_PF_RFO.ANY_RESPONSE", 8214ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 8215ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8216ecd94f1bSKan Liang "SampleAfterValue": "100003", 8217ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 8218ecd94f1bSKan Liang }, 8219ecd94f1bSKan Liang { 8220ecd94f1bSKan Liang "Offcore": "1", 8221ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 8222ecd94f1bSKan Liang "UMask": "0x1", 8223ecd94f1bSKan Liang "BriefDescription": "TBD hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.", 8224ecd94f1bSKan Liang "MSRValue": "0x01003C0120", 8225ecd94f1bSKan Liang "Counter": "0,1,2,3", 8226ecd94f1bSKan Liang "EventName": "OCR.ALL_PF_RFO.L3_HIT.NO_SNOOP_NEEDED", 8227ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 8228ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8229ecd94f1bSKan Liang "SampleAfterValue": "100003", 8230ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 8231ecd94f1bSKan Liang }, 8232ecd94f1bSKan Liang { 8233ecd94f1bSKan Liang "Offcore": "1", 8234ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 8235ecd94f1bSKan Liang "UMask": "0x1", 8236ecd94f1bSKan Liang "BriefDescription": "TBD", 8237ecd94f1bSKan Liang "MSRValue": "0x08007C0120", 8238ecd94f1bSKan Liang "Counter": "0,1,2,3", 8239ecd94f1bSKan Liang "EventName": "OCR.ALL_PF_RFO.L3_HIT.SNOOP_HIT_WITH_FWD", 8240ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 8241ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8242ecd94f1bSKan Liang "SampleAfterValue": "100003", 8243ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 8244ecd94f1bSKan Liang }, 8245ecd94f1bSKan Liang { 8246ecd94f1bSKan Liang "Offcore": "1", 8247ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 8248ecd94f1bSKan Liang "UMask": "0x1", 8249ecd94f1bSKan Liang "BriefDescription": "TBD have any response type.", 8250ecd94f1bSKan Liang "MSRValue": "0x0000010491", 8251ecd94f1bSKan Liang "Counter": "0,1,2,3", 8252ecd94f1bSKan Liang "EventName": "OCR.ALL_DATA_RD.ANY_RESPONSE", 8253ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 8254ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8255ecd94f1bSKan Liang "SampleAfterValue": "100003", 8256ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 8257ecd94f1bSKan Liang }, 8258ecd94f1bSKan Liang { 8259ecd94f1bSKan Liang "Offcore": "1", 8260ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 8261ecd94f1bSKan Liang "UMask": "0x1", 8262ecd94f1bSKan Liang "BriefDescription": "TBD hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.", 8263ecd94f1bSKan Liang "MSRValue": "0x01003C0491", 8264ecd94f1bSKan Liang "Counter": "0,1,2,3", 8265ecd94f1bSKan Liang "EventName": "OCR.ALL_DATA_RD.L3_HIT.NO_SNOOP_NEEDED", 8266ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 8267ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8268ecd94f1bSKan Liang "SampleAfterValue": "100003", 8269ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 8270ecd94f1bSKan Liang }, 8271ecd94f1bSKan Liang { 8272ecd94f1bSKan Liang "Offcore": "1", 8273ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 8274ecd94f1bSKan Liang "UMask": "0x1", 8275ecd94f1bSKan Liang "BriefDescription": "TBD", 8276ecd94f1bSKan Liang "MSRValue": "0x08007C0491", 8277ecd94f1bSKan Liang "Counter": "0,1,2,3", 8278ecd94f1bSKan Liang "EventName": "OCR.ALL_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD", 8279ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 8280ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8281ecd94f1bSKan Liang "SampleAfterValue": "100003", 8282ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 8283ecd94f1bSKan Liang }, 8284ecd94f1bSKan Liang { 8285ecd94f1bSKan Liang "Offcore": "1", 8286ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 8287ecd94f1bSKan Liang "UMask": "0x1", 8288ecd94f1bSKan Liang "BriefDescription": "TBD have any response type.", 8289ecd94f1bSKan Liang "MSRValue": "0x0000010122", 8290ecd94f1bSKan Liang "Counter": "0,1,2,3", 8291ecd94f1bSKan Liang "EventName": "OCR.ALL_RFO.ANY_RESPONSE", 8292ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 8293ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8294ecd94f1bSKan Liang "SampleAfterValue": "100003", 8295ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 8296ecd94f1bSKan Liang }, 8297ecd94f1bSKan Liang { 8298ecd94f1bSKan Liang "Offcore": "1", 8299ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 8300ecd94f1bSKan Liang "UMask": "0x1", 8301ecd94f1bSKan Liang "BriefDescription": "TBD hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.", 8302ecd94f1bSKan Liang "MSRValue": "0x01003C0122", 8303ecd94f1bSKan Liang "Counter": "0,1,2,3", 8304ecd94f1bSKan Liang "EventName": "OCR.ALL_RFO.L3_HIT.NO_SNOOP_NEEDED", 8305ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 8306ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8307ecd94f1bSKan Liang "SampleAfterValue": "100003", 8308ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 8309ecd94f1bSKan Liang }, 8310ecd94f1bSKan Liang { 8311ecd94f1bSKan Liang "Offcore": "1", 8312ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 8313ecd94f1bSKan Liang "UMask": "0x1", 8314ecd94f1bSKan Liang "BriefDescription": "TBD", 8315ecd94f1bSKan Liang "MSRValue": "0x08007C0122", 8316ecd94f1bSKan Liang "Counter": "0,1,2,3", 8317ecd94f1bSKan Liang "EventName": "OCR.ALL_RFO.L3_HIT.SNOOP_HIT_WITH_FWD", 8318ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 8319ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8320ecd94f1bSKan Liang "SampleAfterValue": "100003", 8321ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 8322ecd94f1bSKan Liang }, 8323ecd94f1bSKan Liang { 8324ecd94f1bSKan Liang "Offcore": "1", 8325ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 8326ecd94f1bSKan Liang "UMask": "0x1", 8327ecd94f1bSKan Liang "BriefDescription": "TBD have any response type.", 8328ecd94f1bSKan Liang "MSRValue": "0x00000107F7", 8329ecd94f1bSKan Liang "Counter": "0,1,2,3", 8330ecd94f1bSKan Liang "EventName": "OCR.ALL_READS.ANY_RESPONSE", 8331ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 8332ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8333ecd94f1bSKan Liang "SampleAfterValue": "100003", 8334ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 8335ecd94f1bSKan Liang }, 8336ecd94f1bSKan Liang { 8337ecd94f1bSKan Liang "Offcore": "1", 8338ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 8339ecd94f1bSKan Liang "UMask": "0x1", 8340ecd94f1bSKan Liang "BriefDescription": "TBD hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.", 8341ecd94f1bSKan Liang "MSRValue": "0x01003C07F7", 8342ecd94f1bSKan Liang "Counter": "0,1,2,3", 8343ecd94f1bSKan Liang "EventName": "OCR.ALL_READS.L3_HIT.NO_SNOOP_NEEDED", 8344ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 8345ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8346ecd94f1bSKan Liang "SampleAfterValue": "100003", 8347ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 8348ecd94f1bSKan Liang }, 8349ecd94f1bSKan Liang { 8350ecd94f1bSKan Liang "Offcore": "1", 8351ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 8352ecd94f1bSKan Liang "UMask": "0x1", 8353ecd94f1bSKan Liang "BriefDescription": "TBD", 8354ecd94f1bSKan Liang "MSRValue": "0x08007C07F7", 8355ecd94f1bSKan Liang "Counter": "0,1,2,3", 8356ecd94f1bSKan Liang "EventName": "OCR.ALL_READS.L3_HIT.SNOOP_HIT_WITH_FWD", 8357ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 8358ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8359ecd94f1bSKan Liang "SampleAfterValue": "100003", 8360ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 8361ecd94f1bSKan Liang }, 8362ecd94f1bSKan Liang { 8363ecd94f1bSKan Liang "Offcore": "1", 8364ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 8365ecd94f1bSKan Liang "UMask": "0x1", 8366ecd94f1bSKan Liang "BriefDescription": "Counts demand data reads TBD", 8367ecd94f1bSKan Liang "MSRValue": "0x0100400001", 8368ecd94f1bSKan Liang "Counter": "0,1,2,3", 8369ecd94f1bSKan Liang "EventName": "OCR.DEMAND_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", 8370ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 8371ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8372ecd94f1bSKan Liang "SampleAfterValue": "100003", 8373ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 8374ecd94f1bSKan Liang }, 8375ecd94f1bSKan Liang { 8376ecd94f1bSKan Liang "Offcore": "1", 8377ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 8378ecd94f1bSKan Liang "UMask": "0x1", 8379ecd94f1bSKan Liang "BriefDescription": "Counts demand data reads TBD", 8380ecd94f1bSKan Liang "MSRValue": "0x0080400001", 8381ecd94f1bSKan Liang "Counter": "0,1,2,3", 8382ecd94f1bSKan Liang "EventName": "OCR.DEMAND_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE", 8383ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 8384ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8385ecd94f1bSKan Liang "SampleAfterValue": "100003", 8386ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 8387ecd94f1bSKan Liang }, 8388ecd94f1bSKan Liang { 8389ecd94f1bSKan Liang "Offcore": "1", 8390ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 8391ecd94f1bSKan Liang "UMask": "0x1", 8392ecd94f1bSKan Liang "BriefDescription": "Counts all demand data writes (RFOs) TBD", 8393ecd94f1bSKan Liang "MSRValue": "0x0100400002", 8394ecd94f1bSKan Liang "Counter": "0,1,2,3", 8395ecd94f1bSKan Liang "EventName": "OCR.DEMAND_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", 8396ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 8397ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8398ecd94f1bSKan Liang "SampleAfterValue": "100003", 8399ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 8400ecd94f1bSKan Liang }, 8401ecd94f1bSKan Liang { 8402ecd94f1bSKan Liang "Offcore": "1", 8403ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 8404ecd94f1bSKan Liang "UMask": "0x1", 8405ecd94f1bSKan Liang "BriefDescription": "Counts all demand data writes (RFOs) TBD", 8406ecd94f1bSKan Liang "MSRValue": "0x0080400002", 8407ecd94f1bSKan Liang "Counter": "0,1,2,3", 8408ecd94f1bSKan Liang "EventName": "OCR.DEMAND_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NONE", 8409ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 8410ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8411ecd94f1bSKan Liang "SampleAfterValue": "100003", 8412ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 8413ecd94f1bSKan Liang }, 8414ecd94f1bSKan Liang { 8415ecd94f1bSKan Liang "Offcore": "1", 8416ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 8417ecd94f1bSKan Liang "UMask": "0x1", 8418ecd94f1bSKan Liang "BriefDescription": "Counts all demand code reads TBD", 8419ecd94f1bSKan Liang "MSRValue": "0x0100400004", 8420ecd94f1bSKan Liang "Counter": "0,1,2,3", 8421ecd94f1bSKan Liang "EventName": "OCR.DEMAND_CODE_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", 8422ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 8423ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8424ecd94f1bSKan Liang "SampleAfterValue": "100003", 8425ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 8426ecd94f1bSKan Liang }, 8427ecd94f1bSKan Liang { 8428ecd94f1bSKan Liang "Offcore": "1", 8429ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 8430ecd94f1bSKan Liang "UMask": "0x1", 8431ecd94f1bSKan Liang "BriefDescription": "Counts all demand code reads TBD", 8432ecd94f1bSKan Liang "MSRValue": "0x0080400004", 8433ecd94f1bSKan Liang "Counter": "0,1,2,3", 8434ecd94f1bSKan Liang "EventName": "OCR.DEMAND_CODE_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE", 8435ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 8436ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8437ecd94f1bSKan Liang "SampleAfterValue": "100003", 8438ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 8439ecd94f1bSKan Liang }, 8440ecd94f1bSKan Liang { 8441ecd94f1bSKan Liang "Offcore": "1", 8442ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 8443ecd94f1bSKan Liang "UMask": "0x1", 8444ecd94f1bSKan Liang "BriefDescription": "Counts prefetch (that bring data to L2) data reads TBD", 8445ecd94f1bSKan Liang "MSRValue": "0x0100400010", 8446ecd94f1bSKan Liang "Counter": "0,1,2,3", 8447ecd94f1bSKan Liang "EventName": "OCR.PF_L2_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", 8448ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 8449ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8450ecd94f1bSKan Liang "SampleAfterValue": "100003", 8451ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 8452ecd94f1bSKan Liang }, 8453ecd94f1bSKan Liang { 8454ecd94f1bSKan Liang "Offcore": "1", 8455ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 8456ecd94f1bSKan Liang "UMask": "0x1", 8457ecd94f1bSKan Liang "BriefDescription": "Counts prefetch (that bring data to L2) data reads TBD", 8458ecd94f1bSKan Liang "MSRValue": "0x0080400010", 8459ecd94f1bSKan Liang "Counter": "0,1,2,3", 8460ecd94f1bSKan Liang "EventName": "OCR.PF_L2_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE", 8461ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 8462ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8463ecd94f1bSKan Liang "SampleAfterValue": "100003", 8464ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 8465ecd94f1bSKan Liang }, 8466ecd94f1bSKan Liang { 8467ecd94f1bSKan Liang "Offcore": "1", 8468ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 8469ecd94f1bSKan Liang "UMask": "0x1", 8470ecd94f1bSKan Liang "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs TBD", 8471ecd94f1bSKan Liang "MSRValue": "0x0100400020", 8472ecd94f1bSKan Liang "Counter": "0,1,2,3", 8473ecd94f1bSKan Liang "EventName": "OCR.PF_L2_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", 8474ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 8475ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8476ecd94f1bSKan Liang "SampleAfterValue": "100003", 8477ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 8478ecd94f1bSKan Liang }, 8479ecd94f1bSKan Liang { 8480ecd94f1bSKan Liang "Offcore": "1", 8481ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 8482ecd94f1bSKan Liang "UMask": "0x1", 8483ecd94f1bSKan Liang "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs TBD", 8484ecd94f1bSKan Liang "MSRValue": "0x0080400020", 8485ecd94f1bSKan Liang "Counter": "0,1,2,3", 8486ecd94f1bSKan Liang "EventName": "OCR.PF_L2_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NONE", 8487ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 8488ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8489ecd94f1bSKan Liang "SampleAfterValue": "100003", 8490ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 8491ecd94f1bSKan Liang }, 8492ecd94f1bSKan Liang { 8493ecd94f1bSKan Liang "Offcore": "1", 8494ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 8495ecd94f1bSKan Liang "UMask": "0x1", 8496ecd94f1bSKan Liang "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads TBD", 8497ecd94f1bSKan Liang "MSRValue": "0x0100400080", 8498ecd94f1bSKan Liang "Counter": "0,1,2,3", 8499ecd94f1bSKan Liang "EventName": "OCR.PF_L3_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", 8500ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 8501ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8502ecd94f1bSKan Liang "SampleAfterValue": "100003", 8503ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 8504ecd94f1bSKan Liang }, 8505ecd94f1bSKan Liang { 8506ecd94f1bSKan Liang "Offcore": "1", 8507ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 8508ecd94f1bSKan Liang "UMask": "0x1", 8509ecd94f1bSKan Liang "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads TBD", 8510ecd94f1bSKan Liang "MSRValue": "0x0080400080", 8511ecd94f1bSKan Liang "Counter": "0,1,2,3", 8512ecd94f1bSKan Liang "EventName": "OCR.PF_L3_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE", 8513ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 8514ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8515ecd94f1bSKan Liang "SampleAfterValue": "100003", 8516ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 8517ecd94f1bSKan Liang }, 8518ecd94f1bSKan Liang { 8519ecd94f1bSKan Liang "Offcore": "1", 8520ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 8521ecd94f1bSKan Liang "UMask": "0x1", 8522ecd94f1bSKan Liang "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs TBD", 8523ecd94f1bSKan Liang "MSRValue": "0x0100400100", 8524ecd94f1bSKan Liang "Counter": "0,1,2,3", 8525ecd94f1bSKan Liang "EventName": "OCR.PF_L3_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", 8526ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 8527ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8528ecd94f1bSKan Liang "SampleAfterValue": "100003", 8529ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 8530ecd94f1bSKan Liang }, 8531ecd94f1bSKan Liang { 8532ecd94f1bSKan Liang "Offcore": "1", 8533ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 8534ecd94f1bSKan Liang "UMask": "0x1", 8535ecd94f1bSKan Liang "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs TBD", 8536ecd94f1bSKan Liang "MSRValue": "0x0080400100", 8537ecd94f1bSKan Liang "Counter": "0,1,2,3", 8538ecd94f1bSKan Liang "EventName": "OCR.PF_L3_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NONE", 8539ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 8540ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8541ecd94f1bSKan Liang "SampleAfterValue": "100003", 8542ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 8543ecd94f1bSKan Liang }, 8544ecd94f1bSKan Liang { 8545ecd94f1bSKan Liang "Offcore": "1", 8546ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 8547ecd94f1bSKan Liang "UMask": "0x1", 8548ecd94f1bSKan Liang "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests TBD", 8549ecd94f1bSKan Liang "MSRValue": "0x0100400400", 8550ecd94f1bSKan Liang "Counter": "0,1,2,3", 8551ecd94f1bSKan Liang "EventName": "OCR.PF_L1D_AND_SW.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", 8552ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 8553ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8554ecd94f1bSKan Liang "SampleAfterValue": "100003", 8555ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 8556ecd94f1bSKan Liang }, 8557ecd94f1bSKan Liang { 8558ecd94f1bSKan Liang "Offcore": "1", 8559ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 8560ecd94f1bSKan Liang "UMask": "0x1", 8561ecd94f1bSKan Liang "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests TBD", 8562ecd94f1bSKan Liang "MSRValue": "0x0080400400", 8563ecd94f1bSKan Liang "Counter": "0,1,2,3", 8564ecd94f1bSKan Liang "EventName": "OCR.PF_L1D_AND_SW.PMM_HIT_LOCAL_PMM.SNOOP_NONE", 8565ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 8566ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8567ecd94f1bSKan Liang "SampleAfterValue": "100003", 8568ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 8569ecd94f1bSKan Liang }, 8570ecd94f1bSKan Liang { 8571ecd94f1bSKan Liang "Offcore": "1", 8572ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 8573ecd94f1bSKan Liang "UMask": "0x1", 8574ecd94f1bSKan Liang "BriefDescription": "Counts any other requests TBD", 8575ecd94f1bSKan Liang "MSRValue": "0x0100408000", 8576ecd94f1bSKan Liang "Counter": "0,1,2,3", 8577ecd94f1bSKan Liang "EventName": "OCR.OTHER.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", 8578ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 8579ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8580ecd94f1bSKan Liang "SampleAfterValue": "100003", 8581ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 8582ecd94f1bSKan Liang }, 8583ecd94f1bSKan Liang { 8584ecd94f1bSKan Liang "Offcore": "1", 8585ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 8586ecd94f1bSKan Liang "UMask": "0x1", 8587ecd94f1bSKan Liang "BriefDescription": "Counts any other requests TBD", 8588ecd94f1bSKan Liang "MSRValue": "0x0080408000", 8589ecd94f1bSKan Liang "Counter": "0,1,2,3", 8590ecd94f1bSKan Liang "EventName": "OCR.OTHER.PMM_HIT_LOCAL_PMM.SNOOP_NONE", 8591ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 8592ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8593ecd94f1bSKan Liang "SampleAfterValue": "100003", 8594ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 8595ecd94f1bSKan Liang }, 8596ecd94f1bSKan Liang { 8597ecd94f1bSKan Liang "Offcore": "1", 8598ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 8599ecd94f1bSKan Liang "UMask": "0x1", 8600ecd94f1bSKan Liang "BriefDescription": "TBD TBD", 8601ecd94f1bSKan Liang "MSRValue": "0x0100400490", 8602ecd94f1bSKan Liang "Counter": "0,1,2,3", 8603ecd94f1bSKan Liang "EventName": "OCR.ALL_PF_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", 8604ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 8605ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8606ecd94f1bSKan Liang "SampleAfterValue": "100003", 8607ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 8608ecd94f1bSKan Liang }, 8609ecd94f1bSKan Liang { 8610ecd94f1bSKan Liang "Offcore": "1", 8611ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 8612ecd94f1bSKan Liang "UMask": "0x1", 8613ecd94f1bSKan Liang "BriefDescription": "TBD TBD", 8614ecd94f1bSKan Liang "MSRValue": "0x0080400490", 8615ecd94f1bSKan Liang "Counter": "0,1,2,3", 8616ecd94f1bSKan Liang "EventName": "OCR.ALL_PF_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE", 8617ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 8618ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8619ecd94f1bSKan Liang "SampleAfterValue": "100003", 8620ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 8621ecd94f1bSKan Liang }, 8622ecd94f1bSKan Liang { 8623ecd94f1bSKan Liang "Offcore": "1", 8624ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 8625ecd94f1bSKan Liang "UMask": "0x1", 8626ecd94f1bSKan Liang "BriefDescription": "TBD TBD", 8627ecd94f1bSKan Liang "MSRValue": "0x0100400120", 8628ecd94f1bSKan Liang "Counter": "0,1,2,3", 8629ecd94f1bSKan Liang "EventName": "OCR.ALL_PF_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", 8630ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 8631ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8632ecd94f1bSKan Liang "SampleAfterValue": "100003", 8633ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 8634ecd94f1bSKan Liang }, 8635ecd94f1bSKan Liang { 8636ecd94f1bSKan Liang "Offcore": "1", 8637ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 8638ecd94f1bSKan Liang "UMask": "0x1", 8639ecd94f1bSKan Liang "BriefDescription": "TBD TBD", 8640ecd94f1bSKan Liang "MSRValue": "0x0080400120", 8641ecd94f1bSKan Liang "Counter": "0,1,2,3", 8642ecd94f1bSKan Liang "EventName": "OCR.ALL_PF_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NONE", 8643ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 8644ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8645ecd94f1bSKan Liang "SampleAfterValue": "100003", 8646ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 8647ecd94f1bSKan Liang }, 8648ecd94f1bSKan Liang { 8649ecd94f1bSKan Liang "Offcore": "1", 8650ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 8651ecd94f1bSKan Liang "UMask": "0x1", 8652ecd94f1bSKan Liang "BriefDescription": "TBD TBD", 8653ecd94f1bSKan Liang "MSRValue": "0x0100400491", 8654ecd94f1bSKan Liang "Counter": "0,1,2,3", 8655ecd94f1bSKan Liang "EventName": "OCR.ALL_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", 8656ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 8657ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8658ecd94f1bSKan Liang "SampleAfterValue": "100003", 8659ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 8660ecd94f1bSKan Liang }, 8661ecd94f1bSKan Liang { 8662ecd94f1bSKan Liang "Offcore": "1", 8663ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 8664ecd94f1bSKan Liang "UMask": "0x1", 8665ecd94f1bSKan Liang "BriefDescription": "TBD TBD", 8666ecd94f1bSKan Liang "MSRValue": "0x0080400491", 8667ecd94f1bSKan Liang "Counter": "0,1,2,3", 8668ecd94f1bSKan Liang "EventName": "OCR.ALL_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE", 8669ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 8670ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8671ecd94f1bSKan Liang "SampleAfterValue": "100003", 8672ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 8673ecd94f1bSKan Liang }, 8674ecd94f1bSKan Liang { 8675ecd94f1bSKan Liang "Offcore": "1", 8676ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 8677ecd94f1bSKan Liang "UMask": "0x1", 8678ecd94f1bSKan Liang "BriefDescription": "TBD TBD", 8679ecd94f1bSKan Liang "MSRValue": "0x0100400122", 8680ecd94f1bSKan Liang "Counter": "0,1,2,3", 8681ecd94f1bSKan Liang "EventName": "OCR.ALL_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", 8682ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 8683ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8684ecd94f1bSKan Liang "SampleAfterValue": "100003", 8685ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 8686ecd94f1bSKan Liang }, 8687ecd94f1bSKan Liang { 8688ecd94f1bSKan Liang "Offcore": "1", 8689ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 8690ecd94f1bSKan Liang "UMask": "0x1", 8691ecd94f1bSKan Liang "BriefDescription": "TBD TBD", 8692ecd94f1bSKan Liang "MSRValue": "0x0080400122", 8693ecd94f1bSKan Liang "Counter": "0,1,2,3", 8694ecd94f1bSKan Liang "EventName": "OCR.ALL_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NONE", 8695ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 8696ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8697ecd94f1bSKan Liang "SampleAfterValue": "100003", 8698ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 8699ecd94f1bSKan Liang }, 8700ecd94f1bSKan Liang { 8701ecd94f1bSKan Liang "Offcore": "1", 8702ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 8703ecd94f1bSKan Liang "UMask": "0x1", 8704ecd94f1bSKan Liang "BriefDescription": "TBD TBD", 8705ecd94f1bSKan Liang "MSRValue": "0x01004007F7", 8706ecd94f1bSKan Liang "Counter": "0,1,2,3", 8707ecd94f1bSKan Liang "EventName": "OCR.ALL_READS.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", 8708ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 8709ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8710ecd94f1bSKan Liang "SampleAfterValue": "100003", 8711ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 8712ecd94f1bSKan Liang }, 8713ecd94f1bSKan Liang { 8714ecd94f1bSKan Liang "Offcore": "1", 8715ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 8716ecd94f1bSKan Liang "UMask": "0x1", 8717ecd94f1bSKan Liang "BriefDescription": "TBD TBD", 8718ecd94f1bSKan Liang "MSRValue": "0x00804007F7", 8719ecd94f1bSKan Liang "Counter": "0,1,2,3", 8720ecd94f1bSKan Liang "EventName": "OCR.ALL_READS.PMM_HIT_LOCAL_PMM.SNOOP_NONE", 8721ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 8722ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8723ecd94f1bSKan Liang "SampleAfterValue": "100003", 8724ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 8725ecd94f1bSKan Liang }, 8726ecd94f1bSKan Liang { 8727ecd94f1bSKan Liang "Offcore": "1", 8728ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 8729ecd94f1bSKan Liang "UMask": "0x1", 8730ecd94f1bSKan Liang "BriefDescription": "Counts demand data reads TBD", 8731ecd94f1bSKan Liang "MSRValue": "0x3F80400001", 8732ecd94f1bSKan Liang "Counter": "0,1,2,3", 8733ecd94f1bSKan Liang "EventName": "OCR.DEMAND_DATA_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOP", 8734ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 8735ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8736ecd94f1bSKan Liang "SampleAfterValue": "100003", 8737ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 8738ecd94f1bSKan Liang }, 8739ecd94f1bSKan Liang { 8740ecd94f1bSKan Liang "Offcore": "1", 8741ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 8742ecd94f1bSKan Liang "UMask": "0x1", 8743ecd94f1bSKan Liang "BriefDescription": "Counts all demand data writes (RFOs) TBD", 8744ecd94f1bSKan Liang "MSRValue": "0x3F80400002", 8745ecd94f1bSKan Liang "Counter": "0,1,2,3", 8746ecd94f1bSKan Liang "EventName": "OCR.DEMAND_RFO.PMM_HIT_LOCAL_PMM.ANY_SNOOP", 8747ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 8748ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8749ecd94f1bSKan Liang "SampleAfterValue": "100003", 8750ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 8751ecd94f1bSKan Liang }, 8752ecd94f1bSKan Liang { 8753ecd94f1bSKan Liang "Offcore": "1", 8754ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 8755ecd94f1bSKan Liang "UMask": "0x1", 8756ecd94f1bSKan Liang "BriefDescription": "Counts all demand code reads TBD", 8757ecd94f1bSKan Liang "MSRValue": "0x3F80400004", 8758ecd94f1bSKan Liang "Counter": "0,1,2,3", 8759ecd94f1bSKan Liang "EventName": "OCR.DEMAND_CODE_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOP", 8760ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 8761ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8762ecd94f1bSKan Liang "SampleAfterValue": "100003", 8763ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 8764ecd94f1bSKan Liang }, 8765ecd94f1bSKan Liang { 8766ecd94f1bSKan Liang "Offcore": "1", 8767ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 8768ecd94f1bSKan Liang "UMask": "0x1", 8769ecd94f1bSKan Liang "BriefDescription": "Counts prefetch (that bring data to L2) data reads TBD", 8770ecd94f1bSKan Liang "MSRValue": "0x3F80400010", 8771ecd94f1bSKan Liang "Counter": "0,1,2,3", 8772ecd94f1bSKan Liang "EventName": "OCR.PF_L2_DATA_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOP", 8773ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 8774ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8775ecd94f1bSKan Liang "SampleAfterValue": "100003", 8776ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 8777ecd94f1bSKan Liang }, 8778ecd94f1bSKan Liang { 8779ecd94f1bSKan Liang "Offcore": "1", 8780ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 8781ecd94f1bSKan Liang "UMask": "0x1", 8782ecd94f1bSKan Liang "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs TBD", 8783ecd94f1bSKan Liang "MSRValue": "0x3F80400020", 8784ecd94f1bSKan Liang "Counter": "0,1,2,3", 8785ecd94f1bSKan Liang "EventName": "OCR.PF_L2_RFO.PMM_HIT_LOCAL_PMM.ANY_SNOOP", 8786ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 8787ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8788ecd94f1bSKan Liang "SampleAfterValue": "100003", 8789ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 8790ecd94f1bSKan Liang }, 8791ecd94f1bSKan Liang { 8792ecd94f1bSKan Liang "Offcore": "1", 8793ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 8794ecd94f1bSKan Liang "UMask": "0x1", 8795ecd94f1bSKan Liang "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads TBD", 8796ecd94f1bSKan Liang "MSRValue": "0x3F80400080", 8797ecd94f1bSKan Liang "Counter": "0,1,2,3", 8798ecd94f1bSKan Liang "EventName": "OCR.PF_L3_DATA_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOP", 8799ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 8800ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8801ecd94f1bSKan Liang "SampleAfterValue": "100003", 8802ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 8803ecd94f1bSKan Liang }, 8804ecd94f1bSKan Liang { 8805ecd94f1bSKan Liang "Offcore": "1", 8806ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 8807ecd94f1bSKan Liang "UMask": "0x1", 8808ecd94f1bSKan Liang "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs TBD", 8809ecd94f1bSKan Liang "MSRValue": "0x3F80400100", 8810ecd94f1bSKan Liang "Counter": "0,1,2,3", 8811ecd94f1bSKan Liang "EventName": "OCR.PF_L3_RFO.PMM_HIT_LOCAL_PMM.ANY_SNOOP", 8812ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 8813ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8814ecd94f1bSKan Liang "SampleAfterValue": "100003", 8815ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 8816ecd94f1bSKan Liang }, 8817ecd94f1bSKan Liang { 8818ecd94f1bSKan Liang "Offcore": "1", 8819ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 8820ecd94f1bSKan Liang "UMask": "0x1", 8821ecd94f1bSKan Liang "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests TBD", 8822ecd94f1bSKan Liang "MSRValue": "0x3F80400400", 8823ecd94f1bSKan Liang "Counter": "0,1,2,3", 8824ecd94f1bSKan Liang "EventName": "OCR.PF_L1D_AND_SW.PMM_HIT_LOCAL_PMM.ANY_SNOOP", 8825ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 8826ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8827ecd94f1bSKan Liang "SampleAfterValue": "100003", 8828ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 8829ecd94f1bSKan Liang }, 8830ecd94f1bSKan Liang { 8831ecd94f1bSKan Liang "Offcore": "1", 8832ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 8833ecd94f1bSKan Liang "UMask": "0x1", 8834ecd94f1bSKan Liang "BriefDescription": "Counts any other requests TBD", 8835ecd94f1bSKan Liang "MSRValue": "0x3F80408000", 8836ecd94f1bSKan Liang "Counter": "0,1,2,3", 8837ecd94f1bSKan Liang "EventName": "OCR.OTHER.PMM_HIT_LOCAL_PMM.ANY_SNOOP", 8838ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 8839ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8840ecd94f1bSKan Liang "SampleAfterValue": "100003", 8841ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 8842ecd94f1bSKan Liang }, 8843ecd94f1bSKan Liang { 8844ecd94f1bSKan Liang "Offcore": "1", 8845ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 8846ecd94f1bSKan Liang "UMask": "0x1", 8847ecd94f1bSKan Liang "BriefDescription": "TBD TBD", 8848ecd94f1bSKan Liang "MSRValue": "0x3F80400490", 8849ecd94f1bSKan Liang "Counter": "0,1,2,3", 8850ecd94f1bSKan Liang "EventName": "OCR.ALL_PF_DATA_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOP", 8851ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 8852ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8853ecd94f1bSKan Liang "SampleAfterValue": "100003", 8854ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 8855ecd94f1bSKan Liang }, 8856ecd94f1bSKan Liang { 8857ecd94f1bSKan Liang "Offcore": "1", 8858ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 8859ecd94f1bSKan Liang "UMask": "0x1", 8860ecd94f1bSKan Liang "BriefDescription": "TBD TBD", 8861ecd94f1bSKan Liang "MSRValue": "0x3F80400120", 8862ecd94f1bSKan Liang "Counter": "0,1,2,3", 8863ecd94f1bSKan Liang "EventName": "OCR.ALL_PF_RFO.PMM_HIT_LOCAL_PMM.ANY_SNOOP", 8864ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 8865ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8866ecd94f1bSKan Liang "SampleAfterValue": "100003", 8867ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 8868ecd94f1bSKan Liang }, 8869ecd94f1bSKan Liang { 8870ecd94f1bSKan Liang "Offcore": "1", 8871ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 8872ecd94f1bSKan Liang "UMask": "0x1", 8873ecd94f1bSKan Liang "BriefDescription": "TBD TBD", 8874ecd94f1bSKan Liang "MSRValue": "0x3F80400491", 8875ecd94f1bSKan Liang "Counter": "0,1,2,3", 8876ecd94f1bSKan Liang "EventName": "OCR.ALL_DATA_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOP", 8877ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 8878ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8879ecd94f1bSKan Liang "SampleAfterValue": "100003", 8880ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 8881ecd94f1bSKan Liang }, 8882ecd94f1bSKan Liang { 8883ecd94f1bSKan Liang "Offcore": "1", 8884ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 8885ecd94f1bSKan Liang "UMask": "0x1", 8886ecd94f1bSKan Liang "BriefDescription": "TBD TBD", 8887ecd94f1bSKan Liang "MSRValue": "0x3F80400122", 8888ecd94f1bSKan Liang "Counter": "0,1,2,3", 8889ecd94f1bSKan Liang "EventName": "OCR.ALL_RFO.PMM_HIT_LOCAL_PMM.ANY_SNOOP", 8890ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 8891ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8892ecd94f1bSKan Liang "SampleAfterValue": "100003", 8893ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 8894ecd94f1bSKan Liang }, 8895ecd94f1bSKan Liang { 8896ecd94f1bSKan Liang "Offcore": "1", 8897ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 8898ecd94f1bSKan Liang "UMask": "0x1", 8899ecd94f1bSKan Liang "BriefDescription": "TBD TBD", 8900ecd94f1bSKan Liang "MSRValue": "0x3F804007F7", 8901ecd94f1bSKan Liang "Counter": "0,1,2,3", 8902ecd94f1bSKan Liang "EventName": "OCR.ALL_READS.PMM_HIT_LOCAL_PMM.ANY_SNOOP", 8903ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 8904ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8905ecd94f1bSKan Liang "SampleAfterValue": "100003", 8906ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 8907ecd94f1bSKan Liang } 8908ecd94f1bSKan Liang]