1[ 2 { 3 "EventCode": "0x54", 4 "UMask": "0x1", 5 "BriefDescription": "Number of times a transactional abort was signaled due to a data conflict on a transactionally accessed address", 6 "Counter": "0,1,2,3", 7 "EventName": "TX_MEM.ABORT_CONFLICT", 8 "PublicDescription": "Number of times a TSX line had a cache conflict.", 9 "SampleAfterValue": "2000003", 10 "CounterHTOff": "0,1,2,3,4,5,6,7" 11 }, 12 { 13 "EventCode": "0x54", 14 "UMask": "0x2", 15 "BriefDescription": "Number of times a transactional abort was signaled due to a data capacity limitation for transactional reads or writes.", 16 "Counter": "0,1,2,3", 17 "EventName": "TX_MEM.ABORT_CAPACITY", 18 "SampleAfterValue": "2000003", 19 "CounterHTOff": "0,1,2,3,4,5,6,7" 20 }, 21 { 22 "EventCode": "0x54", 23 "UMask": "0x4", 24 "BriefDescription": "Number of times a HLE transactional region aborted due to a non XRELEASE prefixed instruction writing to an elided lock in the elision buffer", 25 "Counter": "0,1,2,3", 26 "EventName": "TX_MEM.ABORT_HLE_STORE_TO_ELIDED_LOCK", 27 "PublicDescription": "Number of times a TSX Abort was triggered due to a non-release/commit store to lock.", 28 "SampleAfterValue": "2000003", 29 "CounterHTOff": "0,1,2,3,4,5,6,7" 30 }, 31 { 32 "EventCode": "0x54", 33 "UMask": "0x8", 34 "BriefDescription": "Number of times an HLE transactional execution aborted due to NoAllocatedElisionBuffer being non-zero.", 35 "Counter": "0,1,2,3", 36 "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_NOT_EMPTY", 37 "PublicDescription": "Number of times a TSX Abort was triggered due to commit but Lock Buffer not empty.", 38 "SampleAfterValue": "2000003", 39 "CounterHTOff": "0,1,2,3,4,5,6,7" 40 }, 41 { 42 "EventCode": "0x54", 43 "UMask": "0x10", 44 "BriefDescription": "Number of times an HLE transactional execution aborted due to XRELEASE lock not satisfying the address and value requirements in the elision buffer", 45 "Counter": "0,1,2,3", 46 "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_MISMATCH", 47 "PublicDescription": "Number of times a TSX Abort was triggered due to release/commit but data and address mismatch.", 48 "SampleAfterValue": "2000003", 49 "CounterHTOff": "0,1,2,3,4,5,6,7" 50 }, 51 { 52 "EventCode": "0x54", 53 "UMask": "0x20", 54 "BriefDescription": "Number of times an HLE transactional execution aborted due to an unsupported read alignment from the elision buffer.", 55 "Counter": "0,1,2,3", 56 "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_UNSUPPORTED_ALIGNMENT", 57 "PublicDescription": "Number of times a TSX Abort was triggered due to attempting an unsupported alignment from Lock Buffer.", 58 "SampleAfterValue": "2000003", 59 "CounterHTOff": "0,1,2,3,4,5,6,7" 60 }, 61 { 62 "EventCode": "0x54", 63 "UMask": "0x40", 64 "BriefDescription": "Number of times HLE lock could not be elided due to ElisionBufferAvailable being zero.", 65 "Counter": "0,1,2,3", 66 "EventName": "TX_MEM.HLE_ELISION_BUFFER_FULL", 67 "PublicDescription": "Number of times we could not allocate Lock Buffer.", 68 "SampleAfterValue": "2000003", 69 "CounterHTOff": "0,1,2,3,4,5,6,7" 70 }, 71 { 72 "EventCode": "0x5d", 73 "UMask": "0x1", 74 "BriefDescription": "Counts the number of times a class of instructions that may cause a transactional abort was executed. Since this is the count of execution, it may not always cause a transactional abort.", 75 "Counter": "0,1,2,3", 76 "EventName": "TX_EXEC.MISC1", 77 "SampleAfterValue": "2000003", 78 "CounterHTOff": "0,1,2,3,4,5,6,7" 79 }, 80 { 81 "EventCode": "0x5d", 82 "UMask": "0x2", 83 "BriefDescription": "Counts the number of times a class of instructions (e.g., vzeroupper) that may cause a transactional abort was executed inside a transactional region", 84 "Counter": "0,1,2,3", 85 "EventName": "TX_EXEC.MISC2", 86 "PublicDescription": "Unfriendly TSX abort triggered by a vzeroupper instruction.", 87 "SampleAfterValue": "2000003", 88 "CounterHTOff": "0,1,2,3,4,5,6,7" 89 }, 90 { 91 "EventCode": "0x5d", 92 "UMask": "0x4", 93 "BriefDescription": "Counts the number of times an instruction execution caused the transactional nest count supported to be exceeded", 94 "Counter": "0,1,2,3", 95 "EventName": "TX_EXEC.MISC3", 96 "PublicDescription": "Unfriendly TSX abort triggered by a nest count that is too deep.", 97 "SampleAfterValue": "2000003", 98 "CounterHTOff": "0,1,2,3,4,5,6,7" 99 }, 100 { 101 "EventCode": "0x5d", 102 "UMask": "0x8", 103 "BriefDescription": "Counts the number of times a XBEGIN instruction was executed inside an HLE transactional region.", 104 "Counter": "0,1,2,3", 105 "EventName": "TX_EXEC.MISC4", 106 "PublicDescription": "RTM region detected inside HLE.", 107 "SampleAfterValue": "2000003", 108 "CounterHTOff": "0,1,2,3,4,5,6,7" 109 }, 110 { 111 "EventCode": "0x5d", 112 "UMask": "0x10", 113 "BriefDescription": "Counts the number of times an HLE XACQUIRE instruction was executed inside an RTM transactional region", 114 "Counter": "0,1,2,3", 115 "EventName": "TX_EXEC.MISC5", 116 "PublicDescription": "Counts the number of times an HLE XACQUIRE instruction was executed inside an RTM transactional region.", 117 "SampleAfterValue": "2000003", 118 "CounterHTOff": "0,1,2,3,4,5,6,7" 119 }, 120 { 121 "EventCode": "0x60", 122 "UMask": "0x10", 123 "BriefDescription": "Counts number of Offcore outstanding Demand Data Read requests that miss L3 cache in the superQ every cycle.", 124 "Counter": "0,1,2,3", 125 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.L3_MISS_DEMAND_DATA_RD", 126 "SampleAfterValue": "2000003", 127 "CounterHTOff": "0,1,2,3,4,5,6,7" 128 }, 129 { 130 "EventCode": "0x60", 131 "UMask": "0x10", 132 "BriefDescription": "Cycles with at least 6 Demand Data Read requests that miss L3 cache in the superQ.", 133 "Counter": "0,1,2,3", 134 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.L3_MISS_DEMAND_DATA_RD_GE_6", 135 "CounterMask": "6", 136 "SampleAfterValue": "2000003", 137 "CounterHTOff": "0,1,2,3,4,5,6,7" 138 }, 139 { 140 "EventCode": "0x60", 141 "UMask": "0x10", 142 "BriefDescription": "Cycles with at least 1 Demand Data Read requests who miss L3 cache in the superQ.", 143 "Counter": "0,1,2,3", 144 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_L3_MISS_DEMAND_DATA_RD", 145 "CounterMask": "1", 146 "SampleAfterValue": "2000003", 147 "CounterHTOff": "0,1,2,3,4,5,6,7" 148 }, 149 { 150 "EventCode": "0xA3", 151 "UMask": "0x2", 152 "BriefDescription": "Cycles while L3 cache miss demand load is outstanding.", 153 "Counter": "0,1,2,3", 154 "EventName": "CYCLE_ACTIVITY.CYCLES_L3_MISS", 155 "CounterMask": "2", 156 "SampleAfterValue": "2000003", 157 "CounterHTOff": "0,1,2,3,4,5,6,7" 158 }, 159 { 160 "EventCode": "0xA3", 161 "UMask": "0x6", 162 "BriefDescription": "Execution stalls while L3 cache miss demand load is outstanding.", 163 "Counter": "0,1,2,3", 164 "EventName": "CYCLE_ACTIVITY.STALLS_L3_MISS", 165 "CounterMask": "6", 166 "SampleAfterValue": "2000003", 167 "CounterHTOff": "0,1,2,3,4,5,6,7" 168 }, 169 { 170 "EventCode": "0xB0", 171 "UMask": "0x10", 172 "BriefDescription": "Demand Data Read requests who miss L3 cache", 173 "Counter": "0,1,2,3", 174 "EventName": "OFFCORE_REQUESTS.L3_MISS_DEMAND_DATA_RD", 175 "PublicDescription": "Demand Data Read requests who miss L3 cache.", 176 "SampleAfterValue": "100003", 177 "CounterHTOff": "0,1,2,3,4,5,6,7" 178 }, 179 { 180 "EventCode": "0xC3", 181 "UMask": "0x2", 182 "BriefDescription": "Counts the number of machine clears due to memory order conflicts.", 183 "Counter": "0,1,2,3", 184 "EventName": "MACHINE_CLEARS.MEMORY_ORDERING", 185 "Errata": "SKL089", 186 "PublicDescription": "Counts the number of memory ordering Machine Clears detected. Memory Ordering Machine Clears can result from one of the following:a. memory disambiguation,b. external snoop, orc. cross SMT-HW-thread snoop (stores) hitting load buffer.", 187 "SampleAfterValue": "100003", 188 "CounterHTOff": "0,1,2,3,4,5,6,7" 189 }, 190 { 191 "EventCode": "0xC8", 192 "UMask": "0x1", 193 "BriefDescription": "Number of times an HLE execution started.", 194 "Counter": "0,1,2,3", 195 "EventName": "HLE_RETIRED.START", 196 "PublicDescription": "Number of times we entered an HLE region. Does not count nested transactions.", 197 "SampleAfterValue": "2000003", 198 "CounterHTOff": "0,1,2,3,4,5,6,7" 199 }, 200 { 201 "EventCode": "0xC8", 202 "UMask": "0x2", 203 "BriefDescription": "Number of times an HLE execution successfully committed", 204 "Counter": "0,1,2,3", 205 "EventName": "HLE_RETIRED.COMMIT", 206 "PublicDescription": "Number of times HLE commit succeeded.", 207 "SampleAfterValue": "2000003", 208 "CounterHTOff": "0,1,2,3,4,5,6,7" 209 }, 210 { 211 "EventCode": "0xC8", 212 "UMask": "0x4", 213 "BriefDescription": "Number of times an HLE execution aborted due to any reasons (multiple categories may count as one). ", 214 "PEBS": "1", 215 "Counter": "0,1,2,3", 216 "EventName": "HLE_RETIRED.ABORTED", 217 "PublicDescription": "Number of times HLE abort was triggered.", 218 "SampleAfterValue": "2000003", 219 "CounterHTOff": "0,1,2,3,4,5,6,7" 220 }, 221 { 222 "EventCode": "0xC8", 223 "UMask": "0x8", 224 "BriefDescription": "Number of times an HLE execution aborted due to various memory events (e.g., read/write capacity and conflicts).", 225 "Counter": "0,1,2,3", 226 "EventName": "HLE_RETIRED.ABORTED_MEM", 227 "SampleAfterValue": "2000003", 228 "CounterHTOff": "0,1,2,3,4,5,6,7" 229 }, 230 { 231 "EventCode": "0xC8", 232 "UMask": "0x10", 233 "BriefDescription": "Number of times an HLE execution aborted due to hardware timer expiration.", 234 "Counter": "0,1,2,3", 235 "EventName": "HLE_RETIRED.ABORTED_TIMER", 236 "SampleAfterValue": "2000003", 237 "CounterHTOff": "0,1,2,3,4,5,6,7" 238 }, 239 { 240 "EventCode": "0xC8", 241 "UMask": "0x20", 242 "BriefDescription": "Number of times an HLE execution aborted due to HLE-unfriendly instructions and certain unfriendly events (such as AD assists etc.).", 243 "Counter": "0,1,2,3", 244 "EventName": "HLE_RETIRED.ABORTED_UNFRIENDLY", 245 "SampleAfterValue": "2000003", 246 "CounterHTOff": "0,1,2,3,4,5,6,7" 247 }, 248 { 249 "EventCode": "0xC8", 250 "UMask": "0x40", 251 "BriefDescription": "Number of times an HLE execution aborted due to incompatible memory type", 252 "Counter": "0,1,2,3", 253 "EventName": "HLE_RETIRED.ABORTED_MEMTYPE", 254 "PublicDescription": "Number of times an HLE execution aborted due to incompatible memory type.", 255 "SampleAfterValue": "2000003", 256 "CounterHTOff": "0,1,2,3,4,5,6,7" 257 }, 258 { 259 "EventCode": "0xC8", 260 "UMask": "0x80", 261 "BriefDescription": "Number of times an HLE execution aborted due to unfriendly events (such as interrupts).", 262 "Counter": "0,1,2,3", 263 "EventName": "HLE_RETIRED.ABORTED_EVENTS", 264 "SampleAfterValue": "2000003", 265 "CounterHTOff": "0,1,2,3,4,5,6,7" 266 }, 267 { 268 "EventCode": "0xC9", 269 "UMask": "0x1", 270 "BriefDescription": "Number of times an RTM execution started.", 271 "Counter": "0,1,2,3", 272 "EventName": "RTM_RETIRED.START", 273 "PublicDescription": "Number of times we entered an RTM region. Does not count nested transactions.", 274 "SampleAfterValue": "2000003", 275 "CounterHTOff": "0,1,2,3,4,5,6,7" 276 }, 277 { 278 "EventCode": "0xC9", 279 "UMask": "0x2", 280 "BriefDescription": "Number of times an RTM execution successfully committed", 281 "Counter": "0,1,2,3", 282 "EventName": "RTM_RETIRED.COMMIT", 283 "PublicDescription": "Number of times RTM commit succeeded.", 284 "SampleAfterValue": "2000003", 285 "CounterHTOff": "0,1,2,3,4,5,6,7" 286 }, 287 { 288 "EventCode": "0xC9", 289 "UMask": "0x4", 290 "BriefDescription": "Number of times an RTM execution aborted due to any reasons (multiple categories may count as one). ", 291 "PEBS": "1", 292 "Counter": "0,1,2,3", 293 "EventName": "RTM_RETIRED.ABORTED", 294 "PublicDescription": "Number of times RTM abort was triggered.", 295 "SampleAfterValue": "2000003", 296 "CounterHTOff": "0,1,2,3,4,5,6,7" 297 }, 298 { 299 "EventCode": "0xC9", 300 "UMask": "0x8", 301 "BriefDescription": "Number of times an RTM execution aborted due to various memory events (e.g. read/write capacity and conflicts)", 302 "Counter": "0,1,2,3", 303 "EventName": "RTM_RETIRED.ABORTED_MEM", 304 "PublicDescription": "Number of times an RTM execution aborted due to various memory events (e.g. read/write capacity and conflicts).", 305 "SampleAfterValue": "2000003", 306 "CounterHTOff": "0,1,2,3,4,5,6,7" 307 }, 308 { 309 "EventCode": "0xC9", 310 "UMask": "0x10", 311 "BriefDescription": "Number of times an RTM execution aborted due to uncommon conditions.", 312 "Counter": "0,1,2,3", 313 "EventName": "RTM_RETIRED.ABORTED_TIMER", 314 "SampleAfterValue": "2000003", 315 "CounterHTOff": "0,1,2,3,4,5,6,7" 316 }, 317 { 318 "EventCode": "0xC9", 319 "UMask": "0x20", 320 "BriefDescription": "Number of times an RTM execution aborted due to HLE-unfriendly instructions", 321 "Counter": "0,1,2,3", 322 "EventName": "RTM_RETIRED.ABORTED_UNFRIENDLY", 323 "PublicDescription": "Number of times an RTM execution aborted due to HLE-unfriendly instructions.", 324 "SampleAfterValue": "2000003", 325 "CounterHTOff": "0,1,2,3,4,5,6,7" 326 }, 327 { 328 "EventCode": "0xC9", 329 "UMask": "0x40", 330 "BriefDescription": "Number of times an RTM execution aborted due to incompatible memory type", 331 "Counter": "0,1,2,3", 332 "EventName": "RTM_RETIRED.ABORTED_MEMTYPE", 333 "PublicDescription": "Number of times an RTM execution aborted due to incompatible memory type.", 334 "SampleAfterValue": "2000003", 335 "CounterHTOff": "0,1,2,3,4,5,6,7" 336 }, 337 { 338 "EventCode": "0xC9", 339 "UMask": "0x80", 340 "BriefDescription": "Number of times an RTM execution aborted due to none of the previous 4 categories (e.g. interrupt)", 341 "Counter": "0,1,2,3", 342 "EventName": "RTM_RETIRED.ABORTED_EVENTS", 343 "PublicDescription": "Number of times an RTM execution aborted due to none of the previous 4 categories (e.g. interrupt).", 344 "SampleAfterValue": "2000003", 345 "CounterHTOff": "0,1,2,3,4,5,6,7" 346 }, 347 { 348 "EventCode": "0xCD", 349 "UMask": "0x1", 350 "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 512 cycles.", 351 "PEBS": "2", 352 "MSRValue": "0x200", 353 "Counter": "0,1,2,3", 354 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_512", 355 "MSRIndex": "0x3F6", 356 "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 512 cycles. Reported latency may be longer than just the memory latency.", 357 "TakenAlone": "1", 358 "SampleAfterValue": "101", 359 "CounterHTOff": "0,1,2,3" 360 }, 361 { 362 "EventCode": "0xCD", 363 "UMask": "0x1", 364 "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 256 cycles.", 365 "PEBS": "2", 366 "MSRValue": "0x100", 367 "Counter": "0,1,2,3", 368 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_256", 369 "MSRIndex": "0x3F6", 370 "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 256 cycles. Reported latency may be longer than just the memory latency.", 371 "TakenAlone": "1", 372 "SampleAfterValue": "503", 373 "CounterHTOff": "0,1,2,3" 374 }, 375 { 376 "EventCode": "0xCD", 377 "UMask": "0x1", 378 "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 128 cycles.", 379 "PEBS": "2", 380 "MSRValue": "0x80", 381 "Counter": "0,1,2,3", 382 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_128", 383 "MSRIndex": "0x3F6", 384 "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 128 cycles. Reported latency may be longer than just the memory latency.", 385 "TakenAlone": "1", 386 "SampleAfterValue": "1009", 387 "CounterHTOff": "0,1,2,3" 388 }, 389 { 390 "EventCode": "0xCD", 391 "UMask": "0x1", 392 "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 64 cycles.", 393 "PEBS": "2", 394 "MSRValue": "0x40", 395 "Counter": "0,1,2,3", 396 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_64", 397 "MSRIndex": "0x3F6", 398 "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 64 cycles. Reported latency may be longer than just the memory latency.", 399 "TakenAlone": "1", 400 "SampleAfterValue": "2003", 401 "CounterHTOff": "0,1,2,3" 402 }, 403 { 404 "EventCode": "0xCD", 405 "UMask": "0x1", 406 "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 32 cycles.", 407 "PEBS": "2", 408 "MSRValue": "0x20", 409 "Counter": "0,1,2,3", 410 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_32", 411 "MSRIndex": "0x3F6", 412 "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 32 cycles. Reported latency may be longer than just the memory latency.", 413 "TakenAlone": "1", 414 "SampleAfterValue": "100007", 415 "CounterHTOff": "0,1,2,3" 416 }, 417 { 418 "EventCode": "0xCD", 419 "UMask": "0x1", 420 "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 16 cycles.", 421 "PEBS": "2", 422 "MSRValue": "0x10", 423 "Counter": "0,1,2,3", 424 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_16", 425 "MSRIndex": "0x3F6", 426 "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 16 cycles. Reported latency may be longer than just the memory latency.", 427 "TakenAlone": "1", 428 "SampleAfterValue": "20011", 429 "CounterHTOff": "0,1,2,3" 430 }, 431 { 432 "EventCode": "0xCD", 433 "UMask": "0x1", 434 "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 8 cycles.", 435 "PEBS": "2", 436 "MSRValue": "0x8", 437 "Counter": "0,1,2,3", 438 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_8", 439 "MSRIndex": "0x3F6", 440 "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 8 cycles. Reported latency may be longer than just the memory latency.", 441 "TakenAlone": "1", 442 "SampleAfterValue": "50021", 443 "CounterHTOff": "0,1,2,3" 444 }, 445 { 446 "EventCode": "0xCD", 447 "UMask": "0x1", 448 "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 4 cycles.", 449 "PEBS": "2", 450 "MSRValue": "0x4", 451 "Counter": "0,1,2,3", 452 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_4", 453 "MSRIndex": "0x3F6", 454 "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 4 cycles. Reported latency may be longer than just the memory latency.", 455 "TakenAlone": "1", 456 "SampleAfterValue": "100003", 457 "CounterHTOff": "0,1,2,3" 458 }, 459 { 460 "Offcore": "1", 461 "EventCode": "0xB7, 0xBB", 462 "UMask": "0x1", 463 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NONE", 464 "Deprecated": "1", 465 "MSRValue": "0x0084000001", 466 "Counter": "0,1,2,3", 467 "EventName": "OFFCORE_RESPONSE:request=DEMAND_DATA_RD:response=L3_MISS_LOCAL_DRAM.SNOOP_NONE", 468 "MSRIndex": "0x1a6,0x1a7", 469 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 470 "SampleAfterValue": "100003", 471 "CounterHTOff": "0,1,2,3" 472 }, 473 { 474 "Offcore": "1", 475 "EventCode": "0xB7, 0xBB", 476 "UMask": "0x1", 477 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED", 478 "Deprecated": "1", 479 "MSRValue": "0x0104000001", 480 "Counter": "0,1,2,3", 481 "EventName": "OFFCORE_RESPONSE:request=DEMAND_DATA_RD:response=L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED", 482 "MSRIndex": "0x1a6,0x1a7", 483 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 484 "SampleAfterValue": "100003", 485 "CounterHTOff": "0,1,2,3" 486 }, 487 { 488 "Offcore": "1", 489 "EventCode": "0xB7, 0xBB", 490 "UMask": "0x1", 491 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS", 492 "Deprecated": "1", 493 "MSRValue": "0x0204000001", 494 "Counter": "0,1,2,3", 495 "EventName": "OFFCORE_RESPONSE:request=DEMAND_DATA_RD:response=L3_MISS_LOCAL_DRAM.SNOOP_MISS", 496 "MSRIndex": "0x1a6,0x1a7", 497 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 498 "SampleAfterValue": "100003", 499 "CounterHTOff": "0,1,2,3" 500 }, 501 { 502 "Offcore": "1", 503 "EventCode": "0xB7, 0xBB", 504 "UMask": "0x1", 505 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD", 506 "Deprecated": "1", 507 "MSRValue": "0x0404000001", 508 "Counter": "0,1,2,3", 509 "EventName": "OFFCORE_RESPONSE:request=DEMAND_DATA_RD:response=L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD", 510 "MSRIndex": "0x1a6,0x1a7", 511 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 512 "SampleAfterValue": "100003", 513 "CounterHTOff": "0,1,2,3" 514 }, 515 { 516 "Offcore": "1", 517 "EventCode": "0xB7, 0xBB", 518 "UMask": "0x1", 519 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD", 520 "Deprecated": "1", 521 "MSRValue": "0x0804000001", 522 "Counter": "0,1,2,3", 523 "EventName": "OFFCORE_RESPONSE:request=DEMAND_DATA_RD:response=L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD", 524 "MSRIndex": "0x1a6,0x1a7", 525 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 526 "SampleAfterValue": "100003", 527 "CounterHTOff": "0,1,2,3" 528 }, 529 { 530 "Offcore": "1", 531 "EventCode": "0xB7, 0xBB", 532 "UMask": "0x1", 533 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE", 534 "Deprecated": "1", 535 "MSRValue": "0x1004000001", 536 "Counter": "0,1,2,3", 537 "EventName": "OFFCORE_RESPONSE:request=DEMAND_DATA_RD:response=L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE", 538 "MSRIndex": "0x1a6,0x1a7", 539 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 540 "SampleAfterValue": "100003", 541 "CounterHTOff": "0,1,2,3" 542 }, 543 { 544 "Offcore": "1", 545 "EventCode": "0xB7, 0xBB", 546 "UMask": "0x1", 547 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP", 548 "Deprecated": "1", 549 "MSRValue": "0x3F84000001", 550 "Counter": "0,1,2,3", 551 "EventName": "OFFCORE_RESPONSE:request=DEMAND_DATA_RD:response=L3_MISS_LOCAL_DRAM.ANY_SNOOP", 552 "MSRIndex": "0x1a6,0x1a7", 553 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 554 "SampleAfterValue": "100003", 555 "CounterHTOff": "0,1,2,3" 556 }, 557 { 558 "Offcore": "1", 559 "EventCode": "0xB7, 0xBB", 560 "UMask": "0x1", 561 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE", 562 "Deprecated": "1", 563 "MSRValue": "0x0090000001", 564 "Counter": "0,1,2,3", 565 "EventName": "OFFCORE_RESPONSE:request=DEMAND_DATA_RD:response=L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE", 566 "MSRIndex": "0x1a6,0x1a7", 567 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 568 "SampleAfterValue": "100003", 569 "CounterHTOff": "0,1,2,3" 570 }, 571 { 572 "Offcore": "1", 573 "EventCode": "0xB7, 0xBB", 574 "UMask": "0x1", 575 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED", 576 "Deprecated": "1", 577 "MSRValue": "0x0110000001", 578 "Counter": "0,1,2,3", 579 "EventName": "OFFCORE_RESPONSE:request=DEMAND_DATA_RD:response=L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED", 580 "MSRIndex": "0x1a6,0x1a7", 581 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 582 "SampleAfterValue": "100003", 583 "CounterHTOff": "0,1,2,3" 584 }, 585 { 586 "Offcore": "1", 587 "EventCode": "0xB7, 0xBB", 588 "UMask": "0x1", 589 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS", 590 "Deprecated": "1", 591 "MSRValue": "0x0210000001", 592 "Counter": "0,1,2,3", 593 "EventName": "OFFCORE_RESPONSE:request=DEMAND_DATA_RD:response=L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS", 594 "MSRIndex": "0x1a6,0x1a7", 595 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 596 "SampleAfterValue": "100003", 597 "CounterHTOff": "0,1,2,3" 598 }, 599 { 600 "Offcore": "1", 601 "EventCode": "0xB7, 0xBB", 602 "UMask": "0x1", 603 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD", 604 "Deprecated": "1", 605 "MSRValue": "0x0410000001", 606 "Counter": "0,1,2,3", 607 "EventName": "OFFCORE_RESPONSE:request=DEMAND_DATA_RD:response=L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD", 608 "MSRIndex": "0x1a6,0x1a7", 609 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 610 "SampleAfterValue": "100003", 611 "CounterHTOff": "0,1,2,3" 612 }, 613 { 614 "Offcore": "1", 615 "EventCode": "0xB7, 0xBB", 616 "UMask": "0x1", 617 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD", 618 "Deprecated": "1", 619 "MSRValue": "0x0810000001", 620 "Counter": "0,1,2,3", 621 "EventName": "OFFCORE_RESPONSE:request=DEMAND_DATA_RD:response=L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD", 622 "MSRIndex": "0x1a6,0x1a7", 623 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 624 "SampleAfterValue": "100003", 625 "CounterHTOff": "0,1,2,3" 626 }, 627 { 628 "Offcore": "1", 629 "EventCode": "0xB7, 0xBB", 630 "UMask": "0x1", 631 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE", 632 "Deprecated": "1", 633 "MSRValue": "0x1010000001", 634 "Counter": "0,1,2,3", 635 "EventName": "OFFCORE_RESPONSE:request=DEMAND_DATA_RD:response=L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE", 636 "MSRIndex": "0x1a6,0x1a7", 637 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 638 "SampleAfterValue": "100003", 639 "CounterHTOff": "0,1,2,3" 640 }, 641 { 642 "Offcore": "1", 643 "EventCode": "0xB7, 0xBB", 644 "UMask": "0x1", 645 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP", 646 "Deprecated": "1", 647 "MSRValue": "0x3F90000001", 648 "Counter": "0,1,2,3", 649 "EventName": "OFFCORE_RESPONSE:request=DEMAND_DATA_RD:response=L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP", 650 "MSRIndex": "0x1a6,0x1a7", 651 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 652 "SampleAfterValue": "100003", 653 "CounterHTOff": "0,1,2,3" 654 }, 655 { 656 "Offcore": "1", 657 "EventCode": "0xB7, 0xBB", 658 "UMask": "0x1", 659 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS.SNOOP_NONE", 660 "Deprecated": "1", 661 "MSRValue": "0x00BC000001", 662 "Counter": "0,1,2,3", 663 "EventName": "OFFCORE_RESPONSE:request=DEMAND_DATA_RD:response=L3_MISS.SNOOP_NONE", 664 "MSRIndex": "0x1a6,0x1a7", 665 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 666 "SampleAfterValue": "100003", 667 "CounterHTOff": "0,1,2,3" 668 }, 669 { 670 "Offcore": "1", 671 "EventCode": "0xB7, 0xBB", 672 "UMask": "0x1", 673 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS.NO_SNOOP_NEEDED", 674 "Deprecated": "1", 675 "MSRValue": "0x013C000001", 676 "Counter": "0,1,2,3", 677 "EventName": "OFFCORE_RESPONSE:request=DEMAND_DATA_RD:response=L3_MISS.NO_SNOOP_NEEDED", 678 "MSRIndex": "0x1a6,0x1a7", 679 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 680 "SampleAfterValue": "100003", 681 "CounterHTOff": "0,1,2,3" 682 }, 683 { 684 "Offcore": "1", 685 "EventCode": "0xB7, 0xBB", 686 "UMask": "0x1", 687 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS.SNOOP_MISS", 688 "Deprecated": "1", 689 "MSRValue": "0x023C000001", 690 "Counter": "0,1,2,3", 691 "EventName": "OFFCORE_RESPONSE:request=DEMAND_DATA_RD:response=L3_MISS.SNOOP_MISS", 692 "MSRIndex": "0x1a6,0x1a7", 693 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 694 "SampleAfterValue": "100003", 695 "CounterHTOff": "0,1,2,3" 696 }, 697 { 698 "Offcore": "1", 699 "EventCode": "0xB7, 0xBB", 700 "UMask": "0x1", 701 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS.HIT_OTHER_CORE_NO_FWD", 702 "Deprecated": "1", 703 "MSRValue": "0x043C000001", 704 "Counter": "0,1,2,3", 705 "EventName": "OFFCORE_RESPONSE:request=DEMAND_DATA_RD:response=L3_MISS.HIT_OTHER_CORE_NO_FWD", 706 "MSRIndex": "0x1a6,0x1a7", 707 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 708 "SampleAfterValue": "100003", 709 "CounterHTOff": "0,1,2,3" 710 }, 711 { 712 "Offcore": "1", 713 "EventCode": "0xB7, 0xBB", 714 "UMask": "0x1", 715 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS.HIT_OTHER_CORE_FWD", 716 "Deprecated": "1", 717 "MSRValue": "0x083C000001", 718 "Counter": "0,1,2,3", 719 "EventName": "OFFCORE_RESPONSE:request=DEMAND_DATA_RD:response=L3_MISS.HIT_OTHER_CORE_FWD", 720 "MSRIndex": "0x1a6,0x1a7", 721 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 722 "SampleAfterValue": "100003", 723 "CounterHTOff": "0,1,2,3" 724 }, 725 { 726 "Offcore": "1", 727 "EventCode": "0xB7, 0xBB", 728 "UMask": "0x1", 729 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS.HITM_OTHER_CORE", 730 "Deprecated": "1", 731 "MSRValue": "0x103C000001", 732 "Counter": "0,1,2,3", 733 "EventName": "OFFCORE_RESPONSE:request=DEMAND_DATA_RD:response=L3_MISS.HITM_OTHER_CORE", 734 "MSRIndex": "0x1a6,0x1a7", 735 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 736 "SampleAfterValue": "100003", 737 "CounterHTOff": "0,1,2,3" 738 }, 739 { 740 "Offcore": "1", 741 "EventCode": "0xB7, 0xBB", 742 "UMask": "0x1", 743 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS.ANY_SNOOP", 744 "Deprecated": "1", 745 "MSRValue": "0x3FBC000001", 746 "Counter": "0,1,2,3", 747 "EventName": "OFFCORE_RESPONSE:request=DEMAND_DATA_RD:response=L3_MISS.ANY_SNOOP", 748 "MSRIndex": "0x1a6,0x1a7", 749 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 750 "SampleAfterValue": "100003", 751 "CounterHTOff": "0,1,2,3" 752 }, 753 { 754 "Offcore": "1", 755 "EventCode": "0xB7, 0xBB", 756 "UMask": "0x1", 757 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NONE", 758 "Deprecated": "1", 759 "MSRValue": "0x0084000002", 760 "Counter": "0,1,2,3", 761 "EventName": "OFFCORE_RESPONSE:request=DEMAND_RFO:response=L3_MISS_LOCAL_DRAM.SNOOP_NONE", 762 "MSRIndex": "0x1a6,0x1a7", 763 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 764 "SampleAfterValue": "100003", 765 "CounterHTOff": "0,1,2,3" 766 }, 767 { 768 "Offcore": "1", 769 "EventCode": "0xB7, 0xBB", 770 "UMask": "0x1", 771 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED", 772 "Deprecated": "1", 773 "MSRValue": "0x0104000002", 774 "Counter": "0,1,2,3", 775 "EventName": "OFFCORE_RESPONSE:request=DEMAND_RFO:response=L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED", 776 "MSRIndex": "0x1a6,0x1a7", 777 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 778 "SampleAfterValue": "100003", 779 "CounterHTOff": "0,1,2,3" 780 }, 781 { 782 "Offcore": "1", 783 "EventCode": "0xB7, 0xBB", 784 "UMask": "0x1", 785 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS", 786 "Deprecated": "1", 787 "MSRValue": "0x0204000002", 788 "Counter": "0,1,2,3", 789 "EventName": "OFFCORE_RESPONSE:request=DEMAND_RFO:response=L3_MISS_LOCAL_DRAM.SNOOP_MISS", 790 "MSRIndex": "0x1a6,0x1a7", 791 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 792 "SampleAfterValue": "100003", 793 "CounterHTOff": "0,1,2,3" 794 }, 795 { 796 "Offcore": "1", 797 "EventCode": "0xB7, 0xBB", 798 "UMask": "0x1", 799 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD", 800 "Deprecated": "1", 801 "MSRValue": "0x0404000002", 802 "Counter": "0,1,2,3", 803 "EventName": "OFFCORE_RESPONSE:request=DEMAND_RFO:response=L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD", 804 "MSRIndex": "0x1a6,0x1a7", 805 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 806 "SampleAfterValue": "100003", 807 "CounterHTOff": "0,1,2,3" 808 }, 809 { 810 "Offcore": "1", 811 "EventCode": "0xB7, 0xBB", 812 "UMask": "0x1", 813 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD", 814 "Deprecated": "1", 815 "MSRValue": "0x0804000002", 816 "Counter": "0,1,2,3", 817 "EventName": "OFFCORE_RESPONSE:request=DEMAND_RFO:response=L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD", 818 "MSRIndex": "0x1a6,0x1a7", 819 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 820 "SampleAfterValue": "100003", 821 "CounterHTOff": "0,1,2,3" 822 }, 823 { 824 "Offcore": "1", 825 "EventCode": "0xB7, 0xBB", 826 "UMask": "0x1", 827 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE", 828 "Deprecated": "1", 829 "MSRValue": "0x1004000002", 830 "Counter": "0,1,2,3", 831 "EventName": "OFFCORE_RESPONSE:request=DEMAND_RFO:response=L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE", 832 "MSRIndex": "0x1a6,0x1a7", 833 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 834 "SampleAfterValue": "100003", 835 "CounterHTOff": "0,1,2,3" 836 }, 837 { 838 "Offcore": "1", 839 "EventCode": "0xB7, 0xBB", 840 "UMask": "0x1", 841 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS_LOCAL_DRAM.ANY_SNOOP", 842 "Deprecated": "1", 843 "MSRValue": "0x3F84000002", 844 "Counter": "0,1,2,3", 845 "EventName": "OFFCORE_RESPONSE:request=DEMAND_RFO:response=L3_MISS_LOCAL_DRAM.ANY_SNOOP", 846 "MSRIndex": "0x1a6,0x1a7", 847 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 848 "SampleAfterValue": "100003", 849 "CounterHTOff": "0,1,2,3" 850 }, 851 { 852 "Offcore": "1", 853 "EventCode": "0xB7, 0xBB", 854 "UMask": "0x1", 855 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE", 856 "Deprecated": "1", 857 "MSRValue": "0x0090000002", 858 "Counter": "0,1,2,3", 859 "EventName": "OFFCORE_RESPONSE:request=DEMAND_RFO:response=L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE", 860 "MSRIndex": "0x1a6,0x1a7", 861 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 862 "SampleAfterValue": "100003", 863 "CounterHTOff": "0,1,2,3" 864 }, 865 { 866 "Offcore": "1", 867 "EventCode": "0xB7, 0xBB", 868 "UMask": "0x1", 869 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED", 870 "Deprecated": "1", 871 "MSRValue": "0x0110000002", 872 "Counter": "0,1,2,3", 873 "EventName": "OFFCORE_RESPONSE:request=DEMAND_RFO:response=L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED", 874 "MSRIndex": "0x1a6,0x1a7", 875 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 876 "SampleAfterValue": "100003", 877 "CounterHTOff": "0,1,2,3" 878 }, 879 { 880 "Offcore": "1", 881 "EventCode": "0xB7, 0xBB", 882 "UMask": "0x1", 883 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS", 884 "Deprecated": "1", 885 "MSRValue": "0x0210000002", 886 "Counter": "0,1,2,3", 887 "EventName": "OFFCORE_RESPONSE:request=DEMAND_RFO:response=L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS", 888 "MSRIndex": "0x1a6,0x1a7", 889 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 890 "SampleAfterValue": "100003", 891 "CounterHTOff": "0,1,2,3" 892 }, 893 { 894 "Offcore": "1", 895 "EventCode": "0xB7, 0xBB", 896 "UMask": "0x1", 897 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD", 898 "Deprecated": "1", 899 "MSRValue": "0x0410000002", 900 "Counter": "0,1,2,3", 901 "EventName": "OFFCORE_RESPONSE:request=DEMAND_RFO:response=L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD", 902 "MSRIndex": "0x1a6,0x1a7", 903 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 904 "SampleAfterValue": "100003", 905 "CounterHTOff": "0,1,2,3" 906 }, 907 { 908 "Offcore": "1", 909 "EventCode": "0xB7, 0xBB", 910 "UMask": "0x1", 911 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD", 912 "Deprecated": "1", 913 "MSRValue": "0x0810000002", 914 "Counter": "0,1,2,3", 915 "EventName": "OFFCORE_RESPONSE:request=DEMAND_RFO:response=L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD", 916 "MSRIndex": "0x1a6,0x1a7", 917 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 918 "SampleAfterValue": "100003", 919 "CounterHTOff": "0,1,2,3" 920 }, 921 { 922 "Offcore": "1", 923 "EventCode": "0xB7, 0xBB", 924 "UMask": "0x1", 925 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE", 926 "Deprecated": "1", 927 "MSRValue": "0x1010000002", 928 "Counter": "0,1,2,3", 929 "EventName": "OFFCORE_RESPONSE:request=DEMAND_RFO:response=L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE", 930 "MSRIndex": "0x1a6,0x1a7", 931 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 932 "SampleAfterValue": "100003", 933 "CounterHTOff": "0,1,2,3" 934 }, 935 { 936 "Offcore": "1", 937 "EventCode": "0xB7, 0xBB", 938 "UMask": "0x1", 939 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP", 940 "Deprecated": "1", 941 "MSRValue": "0x3F90000002", 942 "Counter": "0,1,2,3", 943 "EventName": "OFFCORE_RESPONSE:request=DEMAND_RFO:response=L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP", 944 "MSRIndex": "0x1a6,0x1a7", 945 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 946 "SampleAfterValue": "100003", 947 "CounterHTOff": "0,1,2,3" 948 }, 949 { 950 "Offcore": "1", 951 "EventCode": "0xB7, 0xBB", 952 "UMask": "0x1", 953 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS.SNOOP_NONE", 954 "Deprecated": "1", 955 "MSRValue": "0x00BC000002", 956 "Counter": "0,1,2,3", 957 "EventName": "OFFCORE_RESPONSE:request=DEMAND_RFO:response=L3_MISS.SNOOP_NONE", 958 "MSRIndex": "0x1a6,0x1a7", 959 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 960 "SampleAfterValue": "100003", 961 "CounterHTOff": "0,1,2,3" 962 }, 963 { 964 "Offcore": "1", 965 "EventCode": "0xB7, 0xBB", 966 "UMask": "0x1", 967 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS.NO_SNOOP_NEEDED", 968 "Deprecated": "1", 969 "MSRValue": "0x013C000002", 970 "Counter": "0,1,2,3", 971 "EventName": "OFFCORE_RESPONSE:request=DEMAND_RFO:response=L3_MISS.NO_SNOOP_NEEDED", 972 "MSRIndex": "0x1a6,0x1a7", 973 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 974 "SampleAfterValue": "100003", 975 "CounterHTOff": "0,1,2,3" 976 }, 977 { 978 "Offcore": "1", 979 "EventCode": "0xB7, 0xBB", 980 "UMask": "0x1", 981 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS.SNOOP_MISS", 982 "Deprecated": "1", 983 "MSRValue": "0x023C000002", 984 "Counter": "0,1,2,3", 985 "EventName": "OFFCORE_RESPONSE:request=DEMAND_RFO:response=L3_MISS.SNOOP_MISS", 986 "MSRIndex": "0x1a6,0x1a7", 987 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 988 "SampleAfterValue": "100003", 989 "CounterHTOff": "0,1,2,3" 990 }, 991 { 992 "Offcore": "1", 993 "EventCode": "0xB7, 0xBB", 994 "UMask": "0x1", 995 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS.HIT_OTHER_CORE_NO_FWD", 996 "Deprecated": "1", 997 "MSRValue": "0x043C000002", 998 "Counter": "0,1,2,3", 999 "EventName": "OFFCORE_RESPONSE:request=DEMAND_RFO:response=L3_MISS.HIT_OTHER_CORE_NO_FWD", 1000 "MSRIndex": "0x1a6,0x1a7", 1001 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1002 "SampleAfterValue": "100003", 1003 "CounterHTOff": "0,1,2,3" 1004 }, 1005 { 1006 "Offcore": "1", 1007 "EventCode": "0xB7, 0xBB", 1008 "UMask": "0x1", 1009 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS.HIT_OTHER_CORE_FWD", 1010 "Deprecated": "1", 1011 "MSRValue": "0x083C000002", 1012 "Counter": "0,1,2,3", 1013 "EventName": "OFFCORE_RESPONSE:request=DEMAND_RFO:response=L3_MISS.HIT_OTHER_CORE_FWD", 1014 "MSRIndex": "0x1a6,0x1a7", 1015 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1016 "SampleAfterValue": "100003", 1017 "CounterHTOff": "0,1,2,3" 1018 }, 1019 { 1020 "Offcore": "1", 1021 "EventCode": "0xB7, 0xBB", 1022 "UMask": "0x1", 1023 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS.HITM_OTHER_CORE", 1024 "Deprecated": "1", 1025 "MSRValue": "0x103C000002", 1026 "Counter": "0,1,2,3", 1027 "EventName": "OFFCORE_RESPONSE:request=DEMAND_RFO:response=L3_MISS.HITM_OTHER_CORE", 1028 "MSRIndex": "0x1a6,0x1a7", 1029 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1030 "SampleAfterValue": "100003", 1031 "CounterHTOff": "0,1,2,3" 1032 }, 1033 { 1034 "Offcore": "1", 1035 "EventCode": "0xB7, 0xBB", 1036 "UMask": "0x1", 1037 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS.ANY_SNOOP", 1038 "Deprecated": "1", 1039 "MSRValue": "0x3FBC000002", 1040 "Counter": "0,1,2,3", 1041 "EventName": "OFFCORE_RESPONSE:request=DEMAND_RFO:response=L3_MISS.ANY_SNOOP", 1042 "MSRIndex": "0x1a6,0x1a7", 1043 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1044 "SampleAfterValue": "100003", 1045 "CounterHTOff": "0,1,2,3" 1046 }, 1047 { 1048 "Offcore": "1", 1049 "EventCode": "0xB7, 0xBB", 1050 "UMask": "0x1", 1051 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_NONE", 1052 "Deprecated": "1", 1053 "MSRValue": "0x0084000004", 1054 "Counter": "0,1,2,3", 1055 "EventName": "OFFCORE_RESPONSE:request=DEMAND_CODE_RD:response=L3_MISS_LOCAL_DRAM.SNOOP_NONE", 1056 "MSRIndex": "0x1a6,0x1a7", 1057 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1058 "SampleAfterValue": "100003", 1059 "CounterHTOff": "0,1,2,3" 1060 }, 1061 { 1062 "Offcore": "1", 1063 "EventCode": "0xB7, 0xBB", 1064 "UMask": "0x1", 1065 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED", 1066 "Deprecated": "1", 1067 "MSRValue": "0x0104000004", 1068 "Counter": "0,1,2,3", 1069 "EventName": "OFFCORE_RESPONSE:request=DEMAND_CODE_RD:response=L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED", 1070 "MSRIndex": "0x1a6,0x1a7", 1071 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1072 "SampleAfterValue": "100003", 1073 "CounterHTOff": "0,1,2,3" 1074 }, 1075 { 1076 "Offcore": "1", 1077 "EventCode": "0xB7, 0xBB", 1078 "UMask": "0x1", 1079 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS", 1080 "Deprecated": "1", 1081 "MSRValue": "0x0204000004", 1082 "Counter": "0,1,2,3", 1083 "EventName": "OFFCORE_RESPONSE:request=DEMAND_CODE_RD:response=L3_MISS_LOCAL_DRAM.SNOOP_MISS", 1084 "MSRIndex": "0x1a6,0x1a7", 1085 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1086 "SampleAfterValue": "100003", 1087 "CounterHTOff": "0,1,2,3" 1088 }, 1089 { 1090 "Offcore": "1", 1091 "EventCode": "0xB7, 0xBB", 1092 "UMask": "0x1", 1093 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD", 1094 "Deprecated": "1", 1095 "MSRValue": "0x0404000004", 1096 "Counter": "0,1,2,3", 1097 "EventName": "OFFCORE_RESPONSE:request=DEMAND_CODE_RD:response=L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD", 1098 "MSRIndex": "0x1a6,0x1a7", 1099 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1100 "SampleAfterValue": "100003", 1101 "CounterHTOff": "0,1,2,3" 1102 }, 1103 { 1104 "Offcore": "1", 1105 "EventCode": "0xB7, 0xBB", 1106 "UMask": "0x1", 1107 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD", 1108 "Deprecated": "1", 1109 "MSRValue": "0x0804000004", 1110 "Counter": "0,1,2,3", 1111 "EventName": "OFFCORE_RESPONSE:request=DEMAND_CODE_RD:response=L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD", 1112 "MSRIndex": "0x1a6,0x1a7", 1113 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1114 "SampleAfterValue": "100003", 1115 "CounterHTOff": "0,1,2,3" 1116 }, 1117 { 1118 "Offcore": "1", 1119 "EventCode": "0xB7, 0xBB", 1120 "UMask": "0x1", 1121 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE", 1122 "Deprecated": "1", 1123 "MSRValue": "0x1004000004", 1124 "Counter": "0,1,2,3", 1125 "EventName": "OFFCORE_RESPONSE:request=DEMAND_CODE_RD:response=L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE", 1126 "MSRIndex": "0x1a6,0x1a7", 1127 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1128 "SampleAfterValue": "100003", 1129 "CounterHTOff": "0,1,2,3" 1130 }, 1131 { 1132 "Offcore": "1", 1133 "EventCode": "0xB7, 0xBB", 1134 "UMask": "0x1", 1135 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP", 1136 "Deprecated": "1", 1137 "MSRValue": "0x3F84000004", 1138 "Counter": "0,1,2,3", 1139 "EventName": "OFFCORE_RESPONSE:request=DEMAND_CODE_RD:response=L3_MISS_LOCAL_DRAM.ANY_SNOOP", 1140 "MSRIndex": "0x1a6,0x1a7", 1141 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1142 "SampleAfterValue": "100003", 1143 "CounterHTOff": "0,1,2,3" 1144 }, 1145 { 1146 "Offcore": "1", 1147 "EventCode": "0xB7, 0xBB", 1148 "UMask": "0x1", 1149 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE", 1150 "Deprecated": "1", 1151 "MSRValue": "0x0090000004", 1152 "Counter": "0,1,2,3", 1153 "EventName": "OFFCORE_RESPONSE:request=DEMAND_CODE_RD:response=L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE", 1154 "MSRIndex": "0x1a6,0x1a7", 1155 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1156 "SampleAfterValue": "100003", 1157 "CounterHTOff": "0,1,2,3" 1158 }, 1159 { 1160 "Offcore": "1", 1161 "EventCode": "0xB7, 0xBB", 1162 "UMask": "0x1", 1163 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED", 1164 "Deprecated": "1", 1165 "MSRValue": "0x0110000004", 1166 "Counter": "0,1,2,3", 1167 "EventName": "OFFCORE_RESPONSE:request=DEMAND_CODE_RD:response=L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED", 1168 "MSRIndex": "0x1a6,0x1a7", 1169 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1170 "SampleAfterValue": "100003", 1171 "CounterHTOff": "0,1,2,3" 1172 }, 1173 { 1174 "Offcore": "1", 1175 "EventCode": "0xB7, 0xBB", 1176 "UMask": "0x1", 1177 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS", 1178 "Deprecated": "1", 1179 "MSRValue": "0x0210000004", 1180 "Counter": "0,1,2,3", 1181 "EventName": "OFFCORE_RESPONSE:request=DEMAND_CODE_RD:response=L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS", 1182 "MSRIndex": "0x1a6,0x1a7", 1183 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1184 "SampleAfterValue": "100003", 1185 "CounterHTOff": "0,1,2,3" 1186 }, 1187 { 1188 "Offcore": "1", 1189 "EventCode": "0xB7, 0xBB", 1190 "UMask": "0x1", 1191 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD", 1192 "Deprecated": "1", 1193 "MSRValue": "0x0410000004", 1194 "Counter": "0,1,2,3", 1195 "EventName": "OFFCORE_RESPONSE:request=DEMAND_CODE_RD:response=L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD", 1196 "MSRIndex": "0x1a6,0x1a7", 1197 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1198 "SampleAfterValue": "100003", 1199 "CounterHTOff": "0,1,2,3" 1200 }, 1201 { 1202 "Offcore": "1", 1203 "EventCode": "0xB7, 0xBB", 1204 "UMask": "0x1", 1205 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD", 1206 "Deprecated": "1", 1207 "MSRValue": "0x0810000004", 1208 "Counter": "0,1,2,3", 1209 "EventName": "OFFCORE_RESPONSE:request=DEMAND_CODE_RD:response=L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD", 1210 "MSRIndex": "0x1a6,0x1a7", 1211 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1212 "SampleAfterValue": "100003", 1213 "CounterHTOff": "0,1,2,3" 1214 }, 1215 { 1216 "Offcore": "1", 1217 "EventCode": "0xB7, 0xBB", 1218 "UMask": "0x1", 1219 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE", 1220 "Deprecated": "1", 1221 "MSRValue": "0x1010000004", 1222 "Counter": "0,1,2,3", 1223 "EventName": "OFFCORE_RESPONSE:request=DEMAND_CODE_RD:response=L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE", 1224 "MSRIndex": "0x1a6,0x1a7", 1225 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1226 "SampleAfterValue": "100003", 1227 "CounterHTOff": "0,1,2,3" 1228 }, 1229 { 1230 "Offcore": "1", 1231 "EventCode": "0xB7, 0xBB", 1232 "UMask": "0x1", 1233 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP", 1234 "Deprecated": "1", 1235 "MSRValue": "0x3F90000004", 1236 "Counter": "0,1,2,3", 1237 "EventName": "OFFCORE_RESPONSE:request=DEMAND_CODE_RD:response=L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP", 1238 "MSRIndex": "0x1a6,0x1a7", 1239 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1240 "SampleAfterValue": "100003", 1241 "CounterHTOff": "0,1,2,3" 1242 }, 1243 { 1244 "Offcore": "1", 1245 "EventCode": "0xB7, 0xBB", 1246 "UMask": "0x1", 1247 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS.SNOOP_NONE", 1248 "Deprecated": "1", 1249 "MSRValue": "0x00BC000004", 1250 "Counter": "0,1,2,3", 1251 "EventName": "OFFCORE_RESPONSE:request=DEMAND_CODE_RD:response=L3_MISS.SNOOP_NONE", 1252 "MSRIndex": "0x1a6,0x1a7", 1253 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1254 "SampleAfterValue": "100003", 1255 "CounterHTOff": "0,1,2,3" 1256 }, 1257 { 1258 "Offcore": "1", 1259 "EventCode": "0xB7, 0xBB", 1260 "UMask": "0x1", 1261 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS.NO_SNOOP_NEEDED", 1262 "Deprecated": "1", 1263 "MSRValue": "0x013C000004", 1264 "Counter": "0,1,2,3", 1265 "EventName": "OFFCORE_RESPONSE:request=DEMAND_CODE_RD:response=L3_MISS.NO_SNOOP_NEEDED", 1266 "MSRIndex": "0x1a6,0x1a7", 1267 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1268 "SampleAfterValue": "100003", 1269 "CounterHTOff": "0,1,2,3" 1270 }, 1271 { 1272 "Offcore": "1", 1273 "EventCode": "0xB7, 0xBB", 1274 "UMask": "0x1", 1275 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS.SNOOP_MISS", 1276 "Deprecated": "1", 1277 "MSRValue": "0x023C000004", 1278 "Counter": "0,1,2,3", 1279 "EventName": "OFFCORE_RESPONSE:request=DEMAND_CODE_RD:response=L3_MISS.SNOOP_MISS", 1280 "MSRIndex": "0x1a6,0x1a7", 1281 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1282 "SampleAfterValue": "100003", 1283 "CounterHTOff": "0,1,2,3" 1284 }, 1285 { 1286 "Offcore": "1", 1287 "EventCode": "0xB7, 0xBB", 1288 "UMask": "0x1", 1289 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS.HIT_OTHER_CORE_NO_FWD", 1290 "Deprecated": "1", 1291 "MSRValue": "0x043C000004", 1292 "Counter": "0,1,2,3", 1293 "EventName": "OFFCORE_RESPONSE:request=DEMAND_CODE_RD:response=L3_MISS.HIT_OTHER_CORE_NO_FWD", 1294 "MSRIndex": "0x1a6,0x1a7", 1295 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1296 "SampleAfterValue": "100003", 1297 "CounterHTOff": "0,1,2,3" 1298 }, 1299 { 1300 "Offcore": "1", 1301 "EventCode": "0xB7, 0xBB", 1302 "UMask": "0x1", 1303 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS.HIT_OTHER_CORE_FWD", 1304 "Deprecated": "1", 1305 "MSRValue": "0x083C000004", 1306 "Counter": "0,1,2,3", 1307 "EventName": "OFFCORE_RESPONSE:request=DEMAND_CODE_RD:response=L3_MISS.HIT_OTHER_CORE_FWD", 1308 "MSRIndex": "0x1a6,0x1a7", 1309 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1310 "SampleAfterValue": "100003", 1311 "CounterHTOff": "0,1,2,3" 1312 }, 1313 { 1314 "Offcore": "1", 1315 "EventCode": "0xB7, 0xBB", 1316 "UMask": "0x1", 1317 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS.HITM_OTHER_CORE", 1318 "Deprecated": "1", 1319 "MSRValue": "0x103C000004", 1320 "Counter": "0,1,2,3", 1321 "EventName": "OFFCORE_RESPONSE:request=DEMAND_CODE_RD:response=L3_MISS.HITM_OTHER_CORE", 1322 "MSRIndex": "0x1a6,0x1a7", 1323 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1324 "SampleAfterValue": "100003", 1325 "CounterHTOff": "0,1,2,3" 1326 }, 1327 { 1328 "Offcore": "1", 1329 "EventCode": "0xB7, 0xBB", 1330 "UMask": "0x1", 1331 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS.ANY_SNOOP", 1332 "Deprecated": "1", 1333 "MSRValue": "0x3FBC000004", 1334 "Counter": "0,1,2,3", 1335 "EventName": "OFFCORE_RESPONSE:request=DEMAND_CODE_RD:response=L3_MISS.ANY_SNOOP", 1336 "MSRIndex": "0x1a6,0x1a7", 1337 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1338 "SampleAfterValue": "100003", 1339 "CounterHTOff": "0,1,2,3" 1340 }, 1341 { 1342 "Offcore": "1", 1343 "EventCode": "0xB7, 0xBB", 1344 "UMask": "0x1", 1345 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NONE", 1346 "Deprecated": "1", 1347 "MSRValue": "0x0084000010", 1348 "Counter": "0,1,2,3", 1349 "EventName": "OFFCORE_RESPONSE:request=PF_L2_DATA_RD:response=L3_MISS_LOCAL_DRAM.SNOOP_NONE", 1350 "MSRIndex": "0x1a6,0x1a7", 1351 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1352 "SampleAfterValue": "100003", 1353 "CounterHTOff": "0,1,2,3" 1354 }, 1355 { 1356 "Offcore": "1", 1357 "EventCode": "0xB7, 0xBB", 1358 "UMask": "0x1", 1359 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED", 1360 "Deprecated": "1", 1361 "MSRValue": "0x0104000010", 1362 "Counter": "0,1,2,3", 1363 "EventName": "OFFCORE_RESPONSE:request=PF_L2_DATA_RD:response=L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED", 1364 "MSRIndex": "0x1a6,0x1a7", 1365 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1366 "SampleAfterValue": "100003", 1367 "CounterHTOff": "0,1,2,3" 1368 }, 1369 { 1370 "Offcore": "1", 1371 "EventCode": "0xB7, 0xBB", 1372 "UMask": "0x1", 1373 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS", 1374 "Deprecated": "1", 1375 "MSRValue": "0x0204000010", 1376 "Counter": "0,1,2,3", 1377 "EventName": "OFFCORE_RESPONSE:request=PF_L2_DATA_RD:response=L3_MISS_LOCAL_DRAM.SNOOP_MISS", 1378 "MSRIndex": "0x1a6,0x1a7", 1379 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1380 "SampleAfterValue": "100003", 1381 "CounterHTOff": "0,1,2,3" 1382 }, 1383 { 1384 "Offcore": "1", 1385 "EventCode": "0xB7, 0xBB", 1386 "UMask": "0x1", 1387 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD", 1388 "Deprecated": "1", 1389 "MSRValue": "0x0404000010", 1390 "Counter": "0,1,2,3", 1391 "EventName": "OFFCORE_RESPONSE:request=PF_L2_DATA_RD:response=L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD", 1392 "MSRIndex": "0x1a6,0x1a7", 1393 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1394 "SampleAfterValue": "100003", 1395 "CounterHTOff": "0,1,2,3" 1396 }, 1397 { 1398 "Offcore": "1", 1399 "EventCode": "0xB7, 0xBB", 1400 "UMask": "0x1", 1401 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD", 1402 "Deprecated": "1", 1403 "MSRValue": "0x0804000010", 1404 "Counter": "0,1,2,3", 1405 "EventName": "OFFCORE_RESPONSE:request=PF_L2_DATA_RD:response=L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD", 1406 "MSRIndex": "0x1a6,0x1a7", 1407 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1408 "SampleAfterValue": "100003", 1409 "CounterHTOff": "0,1,2,3" 1410 }, 1411 { 1412 "Offcore": "1", 1413 "EventCode": "0xB7, 0xBB", 1414 "UMask": "0x1", 1415 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE", 1416 "Deprecated": "1", 1417 "MSRValue": "0x1004000010", 1418 "Counter": "0,1,2,3", 1419 "EventName": "OFFCORE_RESPONSE:request=PF_L2_DATA_RD:response=L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE", 1420 "MSRIndex": "0x1a6,0x1a7", 1421 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1422 "SampleAfterValue": "100003", 1423 "CounterHTOff": "0,1,2,3" 1424 }, 1425 { 1426 "Offcore": "1", 1427 "EventCode": "0xB7, 0xBB", 1428 "UMask": "0x1", 1429 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP", 1430 "Deprecated": "1", 1431 "MSRValue": "0x3F84000010", 1432 "Counter": "0,1,2,3", 1433 "EventName": "OFFCORE_RESPONSE:request=PF_L2_DATA_RD:response=L3_MISS_LOCAL_DRAM.ANY_SNOOP", 1434 "MSRIndex": "0x1a6,0x1a7", 1435 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1436 "SampleAfterValue": "100003", 1437 "CounterHTOff": "0,1,2,3" 1438 }, 1439 { 1440 "Offcore": "1", 1441 "EventCode": "0xB7, 0xBB", 1442 "UMask": "0x1", 1443 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE", 1444 "Deprecated": "1", 1445 "MSRValue": "0x0090000010", 1446 "Counter": "0,1,2,3", 1447 "EventName": "OFFCORE_RESPONSE:request=PF_L2_DATA_RD:response=L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE", 1448 "MSRIndex": "0x1a6,0x1a7", 1449 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1450 "SampleAfterValue": "100003", 1451 "CounterHTOff": "0,1,2,3" 1452 }, 1453 { 1454 "Offcore": "1", 1455 "EventCode": "0xB7, 0xBB", 1456 "UMask": "0x1", 1457 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED", 1458 "Deprecated": "1", 1459 "MSRValue": "0x0110000010", 1460 "Counter": "0,1,2,3", 1461 "EventName": "OFFCORE_RESPONSE:request=PF_L2_DATA_RD:response=L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED", 1462 "MSRIndex": "0x1a6,0x1a7", 1463 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1464 "SampleAfterValue": "100003", 1465 "CounterHTOff": "0,1,2,3" 1466 }, 1467 { 1468 "Offcore": "1", 1469 "EventCode": "0xB7, 0xBB", 1470 "UMask": "0x1", 1471 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS", 1472 "Deprecated": "1", 1473 "MSRValue": "0x0210000010", 1474 "Counter": "0,1,2,3", 1475 "EventName": "OFFCORE_RESPONSE:request=PF_L2_DATA_RD:response=L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS", 1476 "MSRIndex": "0x1a6,0x1a7", 1477 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1478 "SampleAfterValue": "100003", 1479 "CounterHTOff": "0,1,2,3" 1480 }, 1481 { 1482 "Offcore": "1", 1483 "EventCode": "0xB7, 0xBB", 1484 "UMask": "0x1", 1485 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD", 1486 "Deprecated": "1", 1487 "MSRValue": "0x0410000010", 1488 "Counter": "0,1,2,3", 1489 "EventName": "OFFCORE_RESPONSE:request=PF_L2_DATA_RD:response=L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD", 1490 "MSRIndex": "0x1a6,0x1a7", 1491 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1492 "SampleAfterValue": "100003", 1493 "CounterHTOff": "0,1,2,3" 1494 }, 1495 { 1496 "Offcore": "1", 1497 "EventCode": "0xB7, 0xBB", 1498 "UMask": "0x1", 1499 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD", 1500 "Deprecated": "1", 1501 "MSRValue": "0x0810000010", 1502 "Counter": "0,1,2,3", 1503 "EventName": "OFFCORE_RESPONSE:request=PF_L2_DATA_RD:response=L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD", 1504 "MSRIndex": "0x1a6,0x1a7", 1505 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1506 "SampleAfterValue": "100003", 1507 "CounterHTOff": "0,1,2,3" 1508 }, 1509 { 1510 "Offcore": "1", 1511 "EventCode": "0xB7, 0xBB", 1512 "UMask": "0x1", 1513 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE", 1514 "Deprecated": "1", 1515 "MSRValue": "0x1010000010", 1516 "Counter": "0,1,2,3", 1517 "EventName": "OFFCORE_RESPONSE:request=PF_L2_DATA_RD:response=L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE", 1518 "MSRIndex": "0x1a6,0x1a7", 1519 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1520 "SampleAfterValue": "100003", 1521 "CounterHTOff": "0,1,2,3" 1522 }, 1523 { 1524 "Offcore": "1", 1525 "EventCode": "0xB7, 0xBB", 1526 "UMask": "0x1", 1527 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP", 1528 "Deprecated": "1", 1529 "MSRValue": "0x3F90000010", 1530 "Counter": "0,1,2,3", 1531 "EventName": "OFFCORE_RESPONSE:request=PF_L2_DATA_RD:response=L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP", 1532 "MSRIndex": "0x1a6,0x1a7", 1533 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1534 "SampleAfterValue": "100003", 1535 "CounterHTOff": "0,1,2,3" 1536 }, 1537 { 1538 "Offcore": "1", 1539 "EventCode": "0xB7, 0xBB", 1540 "UMask": "0x1", 1541 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS.SNOOP_NONE", 1542 "Deprecated": "1", 1543 "MSRValue": "0x00BC000010", 1544 "Counter": "0,1,2,3", 1545 "EventName": "OFFCORE_RESPONSE:request=PF_L2_DATA_RD:response=L3_MISS.SNOOP_NONE", 1546 "MSRIndex": "0x1a6,0x1a7", 1547 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1548 "SampleAfterValue": "100003", 1549 "CounterHTOff": "0,1,2,3" 1550 }, 1551 { 1552 "Offcore": "1", 1553 "EventCode": "0xB7, 0xBB", 1554 "UMask": "0x1", 1555 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS.NO_SNOOP_NEEDED", 1556 "Deprecated": "1", 1557 "MSRValue": "0x013C000010", 1558 "Counter": "0,1,2,3", 1559 "EventName": "OFFCORE_RESPONSE:request=PF_L2_DATA_RD:response=L3_MISS.NO_SNOOP_NEEDED", 1560 "MSRIndex": "0x1a6,0x1a7", 1561 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1562 "SampleAfterValue": "100003", 1563 "CounterHTOff": "0,1,2,3" 1564 }, 1565 { 1566 "Offcore": "1", 1567 "EventCode": "0xB7, 0xBB", 1568 "UMask": "0x1", 1569 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS.SNOOP_MISS", 1570 "Deprecated": "1", 1571 "MSRValue": "0x023C000010", 1572 "Counter": "0,1,2,3", 1573 "EventName": "OFFCORE_RESPONSE:request=PF_L2_DATA_RD:response=L3_MISS.SNOOP_MISS", 1574 "MSRIndex": "0x1a6,0x1a7", 1575 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1576 "SampleAfterValue": "100003", 1577 "CounterHTOff": "0,1,2,3" 1578 }, 1579 { 1580 "Offcore": "1", 1581 "EventCode": "0xB7, 0xBB", 1582 "UMask": "0x1", 1583 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS.HIT_OTHER_CORE_NO_FWD", 1584 "Deprecated": "1", 1585 "MSRValue": "0x043C000010", 1586 "Counter": "0,1,2,3", 1587 "EventName": "OFFCORE_RESPONSE:request=PF_L2_DATA_RD:response=L3_MISS.HIT_OTHER_CORE_NO_FWD", 1588 "MSRIndex": "0x1a6,0x1a7", 1589 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1590 "SampleAfterValue": "100003", 1591 "CounterHTOff": "0,1,2,3" 1592 }, 1593 { 1594 "Offcore": "1", 1595 "EventCode": "0xB7, 0xBB", 1596 "UMask": "0x1", 1597 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS.HIT_OTHER_CORE_FWD", 1598 "Deprecated": "1", 1599 "MSRValue": "0x083C000010", 1600 "Counter": "0,1,2,3", 1601 "EventName": "OFFCORE_RESPONSE:request=PF_L2_DATA_RD:response=L3_MISS.HIT_OTHER_CORE_FWD", 1602 "MSRIndex": "0x1a6,0x1a7", 1603 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1604 "SampleAfterValue": "100003", 1605 "CounterHTOff": "0,1,2,3" 1606 }, 1607 { 1608 "Offcore": "1", 1609 "EventCode": "0xB7, 0xBB", 1610 "UMask": "0x1", 1611 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS.HITM_OTHER_CORE", 1612 "Deprecated": "1", 1613 "MSRValue": "0x103C000010", 1614 "Counter": "0,1,2,3", 1615 "EventName": "OFFCORE_RESPONSE:request=PF_L2_DATA_RD:response=L3_MISS.HITM_OTHER_CORE", 1616 "MSRIndex": "0x1a6,0x1a7", 1617 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1618 "SampleAfterValue": "100003", 1619 "CounterHTOff": "0,1,2,3" 1620 }, 1621 { 1622 "Offcore": "1", 1623 "EventCode": "0xB7, 0xBB", 1624 "UMask": "0x1", 1625 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS.ANY_SNOOP", 1626 "Deprecated": "1", 1627 "MSRValue": "0x3FBC000010", 1628 "Counter": "0,1,2,3", 1629 "EventName": "OFFCORE_RESPONSE:request=PF_L2_DATA_RD:response=L3_MISS.ANY_SNOOP", 1630 "MSRIndex": "0x1a6,0x1a7", 1631 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1632 "SampleAfterValue": "100003", 1633 "CounterHTOff": "0,1,2,3" 1634 }, 1635 { 1636 "Offcore": "1", 1637 "EventCode": "0xB7, 0xBB", 1638 "UMask": "0x1", 1639 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NONE", 1640 "Deprecated": "1", 1641 "MSRValue": "0x0084000020", 1642 "Counter": "0,1,2,3", 1643 "EventName": "OFFCORE_RESPONSE:request=PF_L2_RFO:response=L3_MISS_LOCAL_DRAM.SNOOP_NONE", 1644 "MSRIndex": "0x1a6,0x1a7", 1645 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1646 "SampleAfterValue": "100003", 1647 "CounterHTOff": "0,1,2,3" 1648 }, 1649 { 1650 "Offcore": "1", 1651 "EventCode": "0xB7, 0xBB", 1652 "UMask": "0x1", 1653 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED", 1654 "Deprecated": "1", 1655 "MSRValue": "0x0104000020", 1656 "Counter": "0,1,2,3", 1657 "EventName": "OFFCORE_RESPONSE:request=PF_L2_RFO:response=L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED", 1658 "MSRIndex": "0x1a6,0x1a7", 1659 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1660 "SampleAfterValue": "100003", 1661 "CounterHTOff": "0,1,2,3" 1662 }, 1663 { 1664 "Offcore": "1", 1665 "EventCode": "0xB7, 0xBB", 1666 "UMask": "0x1", 1667 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS", 1668 "Deprecated": "1", 1669 "MSRValue": "0x0204000020", 1670 "Counter": "0,1,2,3", 1671 "EventName": "OFFCORE_RESPONSE:request=PF_L2_RFO:response=L3_MISS_LOCAL_DRAM.SNOOP_MISS", 1672 "MSRIndex": "0x1a6,0x1a7", 1673 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1674 "SampleAfterValue": "100003", 1675 "CounterHTOff": "0,1,2,3" 1676 }, 1677 { 1678 "Offcore": "1", 1679 "EventCode": "0xB7, 0xBB", 1680 "UMask": "0x1", 1681 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD", 1682 "Deprecated": "1", 1683 "MSRValue": "0x0404000020", 1684 "Counter": "0,1,2,3", 1685 "EventName": "OFFCORE_RESPONSE:request=PF_L2_RFO:response=L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD", 1686 "MSRIndex": "0x1a6,0x1a7", 1687 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1688 "SampleAfterValue": "100003", 1689 "CounterHTOff": "0,1,2,3" 1690 }, 1691 { 1692 "Offcore": "1", 1693 "EventCode": "0xB7, 0xBB", 1694 "UMask": "0x1", 1695 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD", 1696 "Deprecated": "1", 1697 "MSRValue": "0x0804000020", 1698 "Counter": "0,1,2,3", 1699 "EventName": "OFFCORE_RESPONSE:request=PF_L2_RFO:response=L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD", 1700 "MSRIndex": "0x1a6,0x1a7", 1701 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1702 "SampleAfterValue": "100003", 1703 "CounterHTOff": "0,1,2,3" 1704 }, 1705 { 1706 "Offcore": "1", 1707 "EventCode": "0xB7, 0xBB", 1708 "UMask": "0x1", 1709 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE", 1710 "Deprecated": "1", 1711 "MSRValue": "0x1004000020", 1712 "Counter": "0,1,2,3", 1713 "EventName": "OFFCORE_RESPONSE:request=PF_L2_RFO:response=L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE", 1714 "MSRIndex": "0x1a6,0x1a7", 1715 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1716 "SampleAfterValue": "100003", 1717 "CounterHTOff": "0,1,2,3" 1718 }, 1719 { 1720 "Offcore": "1", 1721 "EventCode": "0xB7, 0xBB", 1722 "UMask": "0x1", 1723 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS_LOCAL_DRAM.ANY_SNOOP", 1724 "Deprecated": "1", 1725 "MSRValue": "0x3F84000020", 1726 "Counter": "0,1,2,3", 1727 "EventName": "OFFCORE_RESPONSE:request=PF_L2_RFO:response=L3_MISS_LOCAL_DRAM.ANY_SNOOP", 1728 "MSRIndex": "0x1a6,0x1a7", 1729 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1730 "SampleAfterValue": "100003", 1731 "CounterHTOff": "0,1,2,3" 1732 }, 1733 { 1734 "Offcore": "1", 1735 "EventCode": "0xB7, 0xBB", 1736 "UMask": "0x1", 1737 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE", 1738 "Deprecated": "1", 1739 "MSRValue": "0x0090000020", 1740 "Counter": "0,1,2,3", 1741 "EventName": "OFFCORE_RESPONSE:request=PF_L2_RFO:response=L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE", 1742 "MSRIndex": "0x1a6,0x1a7", 1743 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1744 "SampleAfterValue": "100003", 1745 "CounterHTOff": "0,1,2,3" 1746 }, 1747 { 1748 "Offcore": "1", 1749 "EventCode": "0xB7, 0xBB", 1750 "UMask": "0x1", 1751 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED", 1752 "Deprecated": "1", 1753 "MSRValue": "0x0110000020", 1754 "Counter": "0,1,2,3", 1755 "EventName": "OFFCORE_RESPONSE:request=PF_L2_RFO:response=L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED", 1756 "MSRIndex": "0x1a6,0x1a7", 1757 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1758 "SampleAfterValue": "100003", 1759 "CounterHTOff": "0,1,2,3" 1760 }, 1761 { 1762 "Offcore": "1", 1763 "EventCode": "0xB7, 0xBB", 1764 "UMask": "0x1", 1765 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS", 1766 "Deprecated": "1", 1767 "MSRValue": "0x0210000020", 1768 "Counter": "0,1,2,3", 1769 "EventName": "OFFCORE_RESPONSE:request=PF_L2_RFO:response=L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS", 1770 "MSRIndex": "0x1a6,0x1a7", 1771 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1772 "SampleAfterValue": "100003", 1773 "CounterHTOff": "0,1,2,3" 1774 }, 1775 { 1776 "Offcore": "1", 1777 "EventCode": "0xB7, 0xBB", 1778 "UMask": "0x1", 1779 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD", 1780 "Deprecated": "1", 1781 "MSRValue": "0x0410000020", 1782 "Counter": "0,1,2,3", 1783 "EventName": "OFFCORE_RESPONSE:request=PF_L2_RFO:response=L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD", 1784 "MSRIndex": "0x1a6,0x1a7", 1785 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1786 "SampleAfterValue": "100003", 1787 "CounterHTOff": "0,1,2,3" 1788 }, 1789 { 1790 "Offcore": "1", 1791 "EventCode": "0xB7, 0xBB", 1792 "UMask": "0x1", 1793 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD", 1794 "Deprecated": "1", 1795 "MSRValue": "0x0810000020", 1796 "Counter": "0,1,2,3", 1797 "EventName": "OFFCORE_RESPONSE:request=PF_L2_RFO:response=L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD", 1798 "MSRIndex": "0x1a6,0x1a7", 1799 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1800 "SampleAfterValue": "100003", 1801 "CounterHTOff": "0,1,2,3" 1802 }, 1803 { 1804 "Offcore": "1", 1805 "EventCode": "0xB7, 0xBB", 1806 "UMask": "0x1", 1807 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE", 1808 "Deprecated": "1", 1809 "MSRValue": "0x1010000020", 1810 "Counter": "0,1,2,3", 1811 "EventName": "OFFCORE_RESPONSE:request=PF_L2_RFO:response=L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE", 1812 "MSRIndex": "0x1a6,0x1a7", 1813 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1814 "SampleAfterValue": "100003", 1815 "CounterHTOff": "0,1,2,3" 1816 }, 1817 { 1818 "Offcore": "1", 1819 "EventCode": "0xB7, 0xBB", 1820 "UMask": "0x1", 1821 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP", 1822 "Deprecated": "1", 1823 "MSRValue": "0x3F90000020", 1824 "Counter": "0,1,2,3", 1825 "EventName": "OFFCORE_RESPONSE:request=PF_L2_RFO:response=L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP", 1826 "MSRIndex": "0x1a6,0x1a7", 1827 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1828 "SampleAfterValue": "100003", 1829 "CounterHTOff": "0,1,2,3" 1830 }, 1831 { 1832 "Offcore": "1", 1833 "EventCode": "0xB7, 0xBB", 1834 "UMask": "0x1", 1835 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS.SNOOP_NONE", 1836 "Deprecated": "1", 1837 "MSRValue": "0x00BC000020", 1838 "Counter": "0,1,2,3", 1839 "EventName": "OFFCORE_RESPONSE:request=PF_L2_RFO:response=L3_MISS.SNOOP_NONE", 1840 "MSRIndex": "0x1a6,0x1a7", 1841 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1842 "SampleAfterValue": "100003", 1843 "CounterHTOff": "0,1,2,3" 1844 }, 1845 { 1846 "Offcore": "1", 1847 "EventCode": "0xB7, 0xBB", 1848 "UMask": "0x1", 1849 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS.NO_SNOOP_NEEDED", 1850 "Deprecated": "1", 1851 "MSRValue": "0x013C000020", 1852 "Counter": "0,1,2,3", 1853 "EventName": "OFFCORE_RESPONSE:request=PF_L2_RFO:response=L3_MISS.NO_SNOOP_NEEDED", 1854 "MSRIndex": "0x1a6,0x1a7", 1855 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1856 "SampleAfterValue": "100003", 1857 "CounterHTOff": "0,1,2,3" 1858 }, 1859 { 1860 "Offcore": "1", 1861 "EventCode": "0xB7, 0xBB", 1862 "UMask": "0x1", 1863 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS.SNOOP_MISS", 1864 "Deprecated": "1", 1865 "MSRValue": "0x023C000020", 1866 "Counter": "0,1,2,3", 1867 "EventName": "OFFCORE_RESPONSE:request=PF_L2_RFO:response=L3_MISS.SNOOP_MISS", 1868 "MSRIndex": "0x1a6,0x1a7", 1869 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1870 "SampleAfterValue": "100003", 1871 "CounterHTOff": "0,1,2,3" 1872 }, 1873 { 1874 "Offcore": "1", 1875 "EventCode": "0xB7, 0xBB", 1876 "UMask": "0x1", 1877 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS.HIT_OTHER_CORE_NO_FWD", 1878 "Deprecated": "1", 1879 "MSRValue": "0x043C000020", 1880 "Counter": "0,1,2,3", 1881 "EventName": "OFFCORE_RESPONSE:request=PF_L2_RFO:response=L3_MISS.HIT_OTHER_CORE_NO_FWD", 1882 "MSRIndex": "0x1a6,0x1a7", 1883 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1884 "SampleAfterValue": "100003", 1885 "CounterHTOff": "0,1,2,3" 1886 }, 1887 { 1888 "Offcore": "1", 1889 "EventCode": "0xB7, 0xBB", 1890 "UMask": "0x1", 1891 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS.HIT_OTHER_CORE_FWD", 1892 "Deprecated": "1", 1893 "MSRValue": "0x083C000020", 1894 "Counter": "0,1,2,3", 1895 "EventName": "OFFCORE_RESPONSE:request=PF_L2_RFO:response=L3_MISS.HIT_OTHER_CORE_FWD", 1896 "MSRIndex": "0x1a6,0x1a7", 1897 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1898 "SampleAfterValue": "100003", 1899 "CounterHTOff": "0,1,2,3" 1900 }, 1901 { 1902 "Offcore": "1", 1903 "EventCode": "0xB7, 0xBB", 1904 "UMask": "0x1", 1905 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS.HITM_OTHER_CORE", 1906 "Deprecated": "1", 1907 "MSRValue": "0x103C000020", 1908 "Counter": "0,1,2,3", 1909 "EventName": "OFFCORE_RESPONSE:request=PF_L2_RFO:response=L3_MISS.HITM_OTHER_CORE", 1910 "MSRIndex": "0x1a6,0x1a7", 1911 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1912 "SampleAfterValue": "100003", 1913 "CounterHTOff": "0,1,2,3" 1914 }, 1915 { 1916 "Offcore": "1", 1917 "EventCode": "0xB7, 0xBB", 1918 "UMask": "0x1", 1919 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS.ANY_SNOOP", 1920 "Deprecated": "1", 1921 "MSRValue": "0x3FBC000020", 1922 "Counter": "0,1,2,3", 1923 "EventName": "OFFCORE_RESPONSE:request=PF_L2_RFO:response=L3_MISS.ANY_SNOOP", 1924 "MSRIndex": "0x1a6,0x1a7", 1925 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1926 "SampleAfterValue": "100003", 1927 "CounterHTOff": "0,1,2,3" 1928 }, 1929 { 1930 "Offcore": "1", 1931 "EventCode": "0xB7, 0xBB", 1932 "UMask": "0x1", 1933 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NONE", 1934 "Deprecated": "1", 1935 "MSRValue": "0x0084000080", 1936 "Counter": "0,1,2,3", 1937 "EventName": "OFFCORE_RESPONSE:request=PF_L3_DATA_RD:response=L3_MISS_LOCAL_DRAM.SNOOP_NONE", 1938 "MSRIndex": "0x1a6,0x1a7", 1939 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1940 "SampleAfterValue": "100003", 1941 "CounterHTOff": "0,1,2,3" 1942 }, 1943 { 1944 "Offcore": "1", 1945 "EventCode": "0xB7, 0xBB", 1946 "UMask": "0x1", 1947 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED", 1948 "Deprecated": "1", 1949 "MSRValue": "0x0104000080", 1950 "Counter": "0,1,2,3", 1951 "EventName": "OFFCORE_RESPONSE:request=PF_L3_DATA_RD:response=L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED", 1952 "MSRIndex": "0x1a6,0x1a7", 1953 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1954 "SampleAfterValue": "100003", 1955 "CounterHTOff": "0,1,2,3" 1956 }, 1957 { 1958 "Offcore": "1", 1959 "EventCode": "0xB7, 0xBB", 1960 "UMask": "0x1", 1961 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS", 1962 "Deprecated": "1", 1963 "MSRValue": "0x0204000080", 1964 "Counter": "0,1,2,3", 1965 "EventName": "OFFCORE_RESPONSE:request=PF_L3_DATA_RD:response=L3_MISS_LOCAL_DRAM.SNOOP_MISS", 1966 "MSRIndex": "0x1a6,0x1a7", 1967 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1968 "SampleAfterValue": "100003", 1969 "CounterHTOff": "0,1,2,3" 1970 }, 1971 { 1972 "Offcore": "1", 1973 "EventCode": "0xB7, 0xBB", 1974 "UMask": "0x1", 1975 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD", 1976 "Deprecated": "1", 1977 "MSRValue": "0x0404000080", 1978 "Counter": "0,1,2,3", 1979 "EventName": "OFFCORE_RESPONSE:request=PF_L3_DATA_RD:response=L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD", 1980 "MSRIndex": "0x1a6,0x1a7", 1981 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1982 "SampleAfterValue": "100003", 1983 "CounterHTOff": "0,1,2,3" 1984 }, 1985 { 1986 "Offcore": "1", 1987 "EventCode": "0xB7, 0xBB", 1988 "UMask": "0x1", 1989 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD", 1990 "Deprecated": "1", 1991 "MSRValue": "0x0804000080", 1992 "Counter": "0,1,2,3", 1993 "EventName": "OFFCORE_RESPONSE:request=PF_L3_DATA_RD:response=L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD", 1994 "MSRIndex": "0x1a6,0x1a7", 1995 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1996 "SampleAfterValue": "100003", 1997 "CounterHTOff": "0,1,2,3" 1998 }, 1999 { 2000 "Offcore": "1", 2001 "EventCode": "0xB7, 0xBB", 2002 "UMask": "0x1", 2003 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE", 2004 "Deprecated": "1", 2005 "MSRValue": "0x1004000080", 2006 "Counter": "0,1,2,3", 2007 "EventName": "OFFCORE_RESPONSE:request=PF_L3_DATA_RD:response=L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE", 2008 "MSRIndex": "0x1a6,0x1a7", 2009 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2010 "SampleAfterValue": "100003", 2011 "CounterHTOff": "0,1,2,3" 2012 }, 2013 { 2014 "Offcore": "1", 2015 "EventCode": "0xB7, 0xBB", 2016 "UMask": "0x1", 2017 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP", 2018 "Deprecated": "1", 2019 "MSRValue": "0x3F84000080", 2020 "Counter": "0,1,2,3", 2021 "EventName": "OFFCORE_RESPONSE:request=PF_L3_DATA_RD:response=L3_MISS_LOCAL_DRAM.ANY_SNOOP", 2022 "MSRIndex": "0x1a6,0x1a7", 2023 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2024 "SampleAfterValue": "100003", 2025 "CounterHTOff": "0,1,2,3" 2026 }, 2027 { 2028 "Offcore": "1", 2029 "EventCode": "0xB7, 0xBB", 2030 "UMask": "0x1", 2031 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE", 2032 "Deprecated": "1", 2033 "MSRValue": "0x0090000080", 2034 "Counter": "0,1,2,3", 2035 "EventName": "OFFCORE_RESPONSE:request=PF_L3_DATA_RD:response=L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE", 2036 "MSRIndex": "0x1a6,0x1a7", 2037 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2038 "SampleAfterValue": "100003", 2039 "CounterHTOff": "0,1,2,3" 2040 }, 2041 { 2042 "Offcore": "1", 2043 "EventCode": "0xB7, 0xBB", 2044 "UMask": "0x1", 2045 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED", 2046 "Deprecated": "1", 2047 "MSRValue": "0x0110000080", 2048 "Counter": "0,1,2,3", 2049 "EventName": "OFFCORE_RESPONSE:request=PF_L3_DATA_RD:response=L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED", 2050 "MSRIndex": "0x1a6,0x1a7", 2051 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2052 "SampleAfterValue": "100003", 2053 "CounterHTOff": "0,1,2,3" 2054 }, 2055 { 2056 "Offcore": "1", 2057 "EventCode": "0xB7, 0xBB", 2058 "UMask": "0x1", 2059 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS", 2060 "Deprecated": "1", 2061 "MSRValue": "0x0210000080", 2062 "Counter": "0,1,2,3", 2063 "EventName": "OFFCORE_RESPONSE:request=PF_L3_DATA_RD:response=L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS", 2064 "MSRIndex": "0x1a6,0x1a7", 2065 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2066 "SampleAfterValue": "100003", 2067 "CounterHTOff": "0,1,2,3" 2068 }, 2069 { 2070 "Offcore": "1", 2071 "EventCode": "0xB7, 0xBB", 2072 "UMask": "0x1", 2073 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD", 2074 "Deprecated": "1", 2075 "MSRValue": "0x0410000080", 2076 "Counter": "0,1,2,3", 2077 "EventName": "OFFCORE_RESPONSE:request=PF_L3_DATA_RD:response=L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD", 2078 "MSRIndex": "0x1a6,0x1a7", 2079 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2080 "SampleAfterValue": "100003", 2081 "CounterHTOff": "0,1,2,3" 2082 }, 2083 { 2084 "Offcore": "1", 2085 "EventCode": "0xB7, 0xBB", 2086 "UMask": "0x1", 2087 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD", 2088 "Deprecated": "1", 2089 "MSRValue": "0x0810000080", 2090 "Counter": "0,1,2,3", 2091 "EventName": "OFFCORE_RESPONSE:request=PF_L3_DATA_RD:response=L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD", 2092 "MSRIndex": "0x1a6,0x1a7", 2093 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2094 "SampleAfterValue": "100003", 2095 "CounterHTOff": "0,1,2,3" 2096 }, 2097 { 2098 "Offcore": "1", 2099 "EventCode": "0xB7, 0xBB", 2100 "UMask": "0x1", 2101 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE", 2102 "Deprecated": "1", 2103 "MSRValue": "0x1010000080", 2104 "Counter": "0,1,2,3", 2105 "EventName": "OFFCORE_RESPONSE:request=PF_L3_DATA_RD:response=L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE", 2106 "MSRIndex": "0x1a6,0x1a7", 2107 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2108 "SampleAfterValue": "100003", 2109 "CounterHTOff": "0,1,2,3" 2110 }, 2111 { 2112 "Offcore": "1", 2113 "EventCode": "0xB7, 0xBB", 2114 "UMask": "0x1", 2115 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP", 2116 "Deprecated": "1", 2117 "MSRValue": "0x3F90000080", 2118 "Counter": "0,1,2,3", 2119 "EventName": "OFFCORE_RESPONSE:request=PF_L3_DATA_RD:response=L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP", 2120 "MSRIndex": "0x1a6,0x1a7", 2121 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2122 "SampleAfterValue": "100003", 2123 "CounterHTOff": "0,1,2,3" 2124 }, 2125 { 2126 "Offcore": "1", 2127 "EventCode": "0xB7, 0xBB", 2128 "UMask": "0x1", 2129 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS.SNOOP_NONE", 2130 "Deprecated": "1", 2131 "MSRValue": "0x00BC000080", 2132 "Counter": "0,1,2,3", 2133 "EventName": "OFFCORE_RESPONSE:request=PF_L3_DATA_RD:response=L3_MISS.SNOOP_NONE", 2134 "MSRIndex": "0x1a6,0x1a7", 2135 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2136 "SampleAfterValue": "100003", 2137 "CounterHTOff": "0,1,2,3" 2138 }, 2139 { 2140 "Offcore": "1", 2141 "EventCode": "0xB7, 0xBB", 2142 "UMask": "0x1", 2143 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS.NO_SNOOP_NEEDED", 2144 "Deprecated": "1", 2145 "MSRValue": "0x013C000080", 2146 "Counter": "0,1,2,3", 2147 "EventName": "OFFCORE_RESPONSE:request=PF_L3_DATA_RD:response=L3_MISS.NO_SNOOP_NEEDED", 2148 "MSRIndex": "0x1a6,0x1a7", 2149 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2150 "SampleAfterValue": "100003", 2151 "CounterHTOff": "0,1,2,3" 2152 }, 2153 { 2154 "Offcore": "1", 2155 "EventCode": "0xB7, 0xBB", 2156 "UMask": "0x1", 2157 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS.SNOOP_MISS", 2158 "Deprecated": "1", 2159 "MSRValue": "0x023C000080", 2160 "Counter": "0,1,2,3", 2161 "EventName": "OFFCORE_RESPONSE:request=PF_L3_DATA_RD:response=L3_MISS.SNOOP_MISS", 2162 "MSRIndex": "0x1a6,0x1a7", 2163 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2164 "SampleAfterValue": "100003", 2165 "CounterHTOff": "0,1,2,3" 2166 }, 2167 { 2168 "Offcore": "1", 2169 "EventCode": "0xB7, 0xBB", 2170 "UMask": "0x1", 2171 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS.HIT_OTHER_CORE_NO_FWD", 2172 "Deprecated": "1", 2173 "MSRValue": "0x043C000080", 2174 "Counter": "0,1,2,3", 2175 "EventName": "OFFCORE_RESPONSE:request=PF_L3_DATA_RD:response=L3_MISS.HIT_OTHER_CORE_NO_FWD", 2176 "MSRIndex": "0x1a6,0x1a7", 2177 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2178 "SampleAfterValue": "100003", 2179 "CounterHTOff": "0,1,2,3" 2180 }, 2181 { 2182 "Offcore": "1", 2183 "EventCode": "0xB7, 0xBB", 2184 "UMask": "0x1", 2185 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS.HIT_OTHER_CORE_FWD", 2186 "Deprecated": "1", 2187 "MSRValue": "0x083C000080", 2188 "Counter": "0,1,2,3", 2189 "EventName": "OFFCORE_RESPONSE:request=PF_L3_DATA_RD:response=L3_MISS.HIT_OTHER_CORE_FWD", 2190 "MSRIndex": "0x1a6,0x1a7", 2191 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2192 "SampleAfterValue": "100003", 2193 "CounterHTOff": "0,1,2,3" 2194 }, 2195 { 2196 "Offcore": "1", 2197 "EventCode": "0xB7, 0xBB", 2198 "UMask": "0x1", 2199 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS.HITM_OTHER_CORE", 2200 "Deprecated": "1", 2201 "MSRValue": "0x103C000080", 2202 "Counter": "0,1,2,3", 2203 "EventName": "OFFCORE_RESPONSE:request=PF_L3_DATA_RD:response=L3_MISS.HITM_OTHER_CORE", 2204 "MSRIndex": "0x1a6,0x1a7", 2205 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2206 "SampleAfterValue": "100003", 2207 "CounterHTOff": "0,1,2,3" 2208 }, 2209 { 2210 "Offcore": "1", 2211 "EventCode": "0xB7, 0xBB", 2212 "UMask": "0x1", 2213 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS.ANY_SNOOP", 2214 "Deprecated": "1", 2215 "MSRValue": "0x3FBC000080", 2216 "Counter": "0,1,2,3", 2217 "EventName": "OFFCORE_RESPONSE:request=PF_L3_DATA_RD:response=L3_MISS.ANY_SNOOP", 2218 "MSRIndex": "0x1a6,0x1a7", 2219 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2220 "SampleAfterValue": "100003", 2221 "CounterHTOff": "0,1,2,3" 2222 }, 2223 { 2224 "Offcore": "1", 2225 "EventCode": "0xB7, 0xBB", 2226 "UMask": "0x1", 2227 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NONE", 2228 "Deprecated": "1", 2229 "MSRValue": "0x0084000100", 2230 "Counter": "0,1,2,3", 2231 "EventName": "OFFCORE_RESPONSE:request=PF_L3_RFO:response=L3_MISS_LOCAL_DRAM.SNOOP_NONE", 2232 "MSRIndex": "0x1a6,0x1a7", 2233 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2234 "SampleAfterValue": "100003", 2235 "CounterHTOff": "0,1,2,3" 2236 }, 2237 { 2238 "Offcore": "1", 2239 "EventCode": "0xB7, 0xBB", 2240 "UMask": "0x1", 2241 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED", 2242 "Deprecated": "1", 2243 "MSRValue": "0x0104000100", 2244 "Counter": "0,1,2,3", 2245 "EventName": "OFFCORE_RESPONSE:request=PF_L3_RFO:response=L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED", 2246 "MSRIndex": "0x1a6,0x1a7", 2247 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2248 "SampleAfterValue": "100003", 2249 "CounterHTOff": "0,1,2,3" 2250 }, 2251 { 2252 "Offcore": "1", 2253 "EventCode": "0xB7, 0xBB", 2254 "UMask": "0x1", 2255 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS", 2256 "Deprecated": "1", 2257 "MSRValue": "0x0204000100", 2258 "Counter": "0,1,2,3", 2259 "EventName": "OFFCORE_RESPONSE:request=PF_L3_RFO:response=L3_MISS_LOCAL_DRAM.SNOOP_MISS", 2260 "MSRIndex": "0x1a6,0x1a7", 2261 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2262 "SampleAfterValue": "100003", 2263 "CounterHTOff": "0,1,2,3" 2264 }, 2265 { 2266 "Offcore": "1", 2267 "EventCode": "0xB7, 0xBB", 2268 "UMask": "0x1", 2269 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD", 2270 "Deprecated": "1", 2271 "MSRValue": "0x0404000100", 2272 "Counter": "0,1,2,3", 2273 "EventName": "OFFCORE_RESPONSE:request=PF_L3_RFO:response=L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD", 2274 "MSRIndex": "0x1a6,0x1a7", 2275 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2276 "SampleAfterValue": "100003", 2277 "CounterHTOff": "0,1,2,3" 2278 }, 2279 { 2280 "Offcore": "1", 2281 "EventCode": "0xB7, 0xBB", 2282 "UMask": "0x1", 2283 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD", 2284 "Deprecated": "1", 2285 "MSRValue": "0x0804000100", 2286 "Counter": "0,1,2,3", 2287 "EventName": "OFFCORE_RESPONSE:request=PF_L3_RFO:response=L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD", 2288 "MSRIndex": "0x1a6,0x1a7", 2289 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2290 "SampleAfterValue": "100003", 2291 "CounterHTOff": "0,1,2,3" 2292 }, 2293 { 2294 "Offcore": "1", 2295 "EventCode": "0xB7, 0xBB", 2296 "UMask": "0x1", 2297 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE", 2298 "Deprecated": "1", 2299 "MSRValue": "0x1004000100", 2300 "Counter": "0,1,2,3", 2301 "EventName": "OFFCORE_RESPONSE:request=PF_L3_RFO:response=L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE", 2302 "MSRIndex": "0x1a6,0x1a7", 2303 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2304 "SampleAfterValue": "100003", 2305 "CounterHTOff": "0,1,2,3" 2306 }, 2307 { 2308 "Offcore": "1", 2309 "EventCode": "0xB7, 0xBB", 2310 "UMask": "0x1", 2311 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS_LOCAL_DRAM.ANY_SNOOP", 2312 "Deprecated": "1", 2313 "MSRValue": "0x3F84000100", 2314 "Counter": "0,1,2,3", 2315 "EventName": "OFFCORE_RESPONSE:request=PF_L3_RFO:response=L3_MISS_LOCAL_DRAM.ANY_SNOOP", 2316 "MSRIndex": "0x1a6,0x1a7", 2317 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2318 "SampleAfterValue": "100003", 2319 "CounterHTOff": "0,1,2,3" 2320 }, 2321 { 2322 "Offcore": "1", 2323 "EventCode": "0xB7, 0xBB", 2324 "UMask": "0x1", 2325 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE", 2326 "Deprecated": "1", 2327 "MSRValue": "0x0090000100", 2328 "Counter": "0,1,2,3", 2329 "EventName": "OFFCORE_RESPONSE:request=PF_L3_RFO:response=L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE", 2330 "MSRIndex": "0x1a6,0x1a7", 2331 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2332 "SampleAfterValue": "100003", 2333 "CounterHTOff": "0,1,2,3" 2334 }, 2335 { 2336 "Offcore": "1", 2337 "EventCode": "0xB7, 0xBB", 2338 "UMask": "0x1", 2339 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED", 2340 "Deprecated": "1", 2341 "MSRValue": "0x0110000100", 2342 "Counter": "0,1,2,3", 2343 "EventName": "OFFCORE_RESPONSE:request=PF_L3_RFO:response=L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED", 2344 "MSRIndex": "0x1a6,0x1a7", 2345 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2346 "SampleAfterValue": "100003", 2347 "CounterHTOff": "0,1,2,3" 2348 }, 2349 { 2350 "Offcore": "1", 2351 "EventCode": "0xB7, 0xBB", 2352 "UMask": "0x1", 2353 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS", 2354 "Deprecated": "1", 2355 "MSRValue": "0x0210000100", 2356 "Counter": "0,1,2,3", 2357 "EventName": "OFFCORE_RESPONSE:request=PF_L3_RFO:response=L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS", 2358 "MSRIndex": "0x1a6,0x1a7", 2359 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2360 "SampleAfterValue": "100003", 2361 "CounterHTOff": "0,1,2,3" 2362 }, 2363 { 2364 "Offcore": "1", 2365 "EventCode": "0xB7, 0xBB", 2366 "UMask": "0x1", 2367 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD", 2368 "Deprecated": "1", 2369 "MSRValue": "0x0410000100", 2370 "Counter": "0,1,2,3", 2371 "EventName": "OFFCORE_RESPONSE:request=PF_L3_RFO:response=L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD", 2372 "MSRIndex": "0x1a6,0x1a7", 2373 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2374 "SampleAfterValue": "100003", 2375 "CounterHTOff": "0,1,2,3" 2376 }, 2377 { 2378 "Offcore": "1", 2379 "EventCode": "0xB7, 0xBB", 2380 "UMask": "0x1", 2381 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD", 2382 "Deprecated": "1", 2383 "MSRValue": "0x0810000100", 2384 "Counter": "0,1,2,3", 2385 "EventName": "OFFCORE_RESPONSE:request=PF_L3_RFO:response=L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD", 2386 "MSRIndex": "0x1a6,0x1a7", 2387 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2388 "SampleAfterValue": "100003", 2389 "CounterHTOff": "0,1,2,3" 2390 }, 2391 { 2392 "Offcore": "1", 2393 "EventCode": "0xB7, 0xBB", 2394 "UMask": "0x1", 2395 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE", 2396 "Deprecated": "1", 2397 "MSRValue": "0x1010000100", 2398 "Counter": "0,1,2,3", 2399 "EventName": "OFFCORE_RESPONSE:request=PF_L3_RFO:response=L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE", 2400 "MSRIndex": "0x1a6,0x1a7", 2401 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2402 "SampleAfterValue": "100003", 2403 "CounterHTOff": "0,1,2,3" 2404 }, 2405 { 2406 "Offcore": "1", 2407 "EventCode": "0xB7, 0xBB", 2408 "UMask": "0x1", 2409 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP", 2410 "Deprecated": "1", 2411 "MSRValue": "0x3F90000100", 2412 "Counter": "0,1,2,3", 2413 "EventName": "OFFCORE_RESPONSE:request=PF_L3_RFO:response=L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP", 2414 "MSRIndex": "0x1a6,0x1a7", 2415 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2416 "SampleAfterValue": "100003", 2417 "CounterHTOff": "0,1,2,3" 2418 }, 2419 { 2420 "Offcore": "1", 2421 "EventCode": "0xB7, 0xBB", 2422 "UMask": "0x1", 2423 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS.SNOOP_NONE", 2424 "Deprecated": "1", 2425 "MSRValue": "0x00BC000100", 2426 "Counter": "0,1,2,3", 2427 "EventName": "OFFCORE_RESPONSE:request=PF_L3_RFO:response=L3_MISS.SNOOP_NONE", 2428 "MSRIndex": "0x1a6,0x1a7", 2429 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2430 "SampleAfterValue": "100003", 2431 "CounterHTOff": "0,1,2,3" 2432 }, 2433 { 2434 "Offcore": "1", 2435 "EventCode": "0xB7, 0xBB", 2436 "UMask": "0x1", 2437 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS.NO_SNOOP_NEEDED", 2438 "Deprecated": "1", 2439 "MSRValue": "0x013C000100", 2440 "Counter": "0,1,2,3", 2441 "EventName": "OFFCORE_RESPONSE:request=PF_L3_RFO:response=L3_MISS.NO_SNOOP_NEEDED", 2442 "MSRIndex": "0x1a6,0x1a7", 2443 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2444 "SampleAfterValue": "100003", 2445 "CounterHTOff": "0,1,2,3" 2446 }, 2447 { 2448 "Offcore": "1", 2449 "EventCode": "0xB7, 0xBB", 2450 "UMask": "0x1", 2451 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS.SNOOP_MISS", 2452 "Deprecated": "1", 2453 "MSRValue": "0x023C000100", 2454 "Counter": "0,1,2,3", 2455 "EventName": "OFFCORE_RESPONSE:request=PF_L3_RFO:response=L3_MISS.SNOOP_MISS", 2456 "MSRIndex": "0x1a6,0x1a7", 2457 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2458 "SampleAfterValue": "100003", 2459 "CounterHTOff": "0,1,2,3" 2460 }, 2461 { 2462 "Offcore": "1", 2463 "EventCode": "0xB7, 0xBB", 2464 "UMask": "0x1", 2465 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS.HIT_OTHER_CORE_NO_FWD", 2466 "Deprecated": "1", 2467 "MSRValue": "0x043C000100", 2468 "Counter": "0,1,2,3", 2469 "EventName": "OFFCORE_RESPONSE:request=PF_L3_RFO:response=L3_MISS.HIT_OTHER_CORE_NO_FWD", 2470 "MSRIndex": "0x1a6,0x1a7", 2471 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2472 "SampleAfterValue": "100003", 2473 "CounterHTOff": "0,1,2,3" 2474 }, 2475 { 2476 "Offcore": "1", 2477 "EventCode": "0xB7, 0xBB", 2478 "UMask": "0x1", 2479 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS.HIT_OTHER_CORE_FWD", 2480 "Deprecated": "1", 2481 "MSRValue": "0x083C000100", 2482 "Counter": "0,1,2,3", 2483 "EventName": "OFFCORE_RESPONSE:request=PF_L3_RFO:response=L3_MISS.HIT_OTHER_CORE_FWD", 2484 "MSRIndex": "0x1a6,0x1a7", 2485 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2486 "SampleAfterValue": "100003", 2487 "CounterHTOff": "0,1,2,3" 2488 }, 2489 { 2490 "Offcore": "1", 2491 "EventCode": "0xB7, 0xBB", 2492 "UMask": "0x1", 2493 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS.HITM_OTHER_CORE", 2494 "Deprecated": "1", 2495 "MSRValue": "0x103C000100", 2496 "Counter": "0,1,2,3", 2497 "EventName": "OFFCORE_RESPONSE:request=PF_L3_RFO:response=L3_MISS.HITM_OTHER_CORE", 2498 "MSRIndex": "0x1a6,0x1a7", 2499 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2500 "SampleAfterValue": "100003", 2501 "CounterHTOff": "0,1,2,3" 2502 }, 2503 { 2504 "Offcore": "1", 2505 "EventCode": "0xB7, 0xBB", 2506 "UMask": "0x1", 2507 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS.ANY_SNOOP", 2508 "Deprecated": "1", 2509 "MSRValue": "0x3FBC000100", 2510 "Counter": "0,1,2,3", 2511 "EventName": "OFFCORE_RESPONSE:request=PF_L3_RFO:response=L3_MISS.ANY_SNOOP", 2512 "MSRIndex": "0x1a6,0x1a7", 2513 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2514 "SampleAfterValue": "100003", 2515 "CounterHTOff": "0,1,2,3" 2516 }, 2517 { 2518 "Offcore": "1", 2519 "EventCode": "0xB7, 0xBB", 2520 "UMask": "0x1", 2521 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.SNOOP_NONE", 2522 "Deprecated": "1", 2523 "MSRValue": "0x0084000400", 2524 "Counter": "0,1,2,3", 2525 "EventName": "OFFCORE_RESPONSE:request=PF_L1D_AND_SW:response=L3_MISS_LOCAL_DRAM.SNOOP_NONE", 2526 "MSRIndex": "0x1a6,0x1a7", 2527 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2528 "SampleAfterValue": "100003", 2529 "CounterHTOff": "0,1,2,3" 2530 }, 2531 { 2532 "Offcore": "1", 2533 "EventCode": "0xB7, 0xBB", 2534 "UMask": "0x1", 2535 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED", 2536 "Deprecated": "1", 2537 "MSRValue": "0x0104000400", 2538 "Counter": "0,1,2,3", 2539 "EventName": "OFFCORE_RESPONSE:request=PF_L1D_AND_SW:response=L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED", 2540 "MSRIndex": "0x1a6,0x1a7", 2541 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2542 "SampleAfterValue": "100003", 2543 "CounterHTOff": "0,1,2,3" 2544 }, 2545 { 2546 "Offcore": "1", 2547 "EventCode": "0xB7, 0xBB", 2548 "UMask": "0x1", 2549 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.SNOOP_MISS", 2550 "Deprecated": "1", 2551 "MSRValue": "0x0204000400", 2552 "Counter": "0,1,2,3", 2553 "EventName": "OFFCORE_RESPONSE:request=PF_L1D_AND_SW:response=L3_MISS_LOCAL_DRAM.SNOOP_MISS", 2554 "MSRIndex": "0x1a6,0x1a7", 2555 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2556 "SampleAfterValue": "100003", 2557 "CounterHTOff": "0,1,2,3" 2558 }, 2559 { 2560 "Offcore": "1", 2561 "EventCode": "0xB7, 0xBB", 2562 "UMask": "0x1", 2563 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD", 2564 "Deprecated": "1", 2565 "MSRValue": "0x0404000400", 2566 "Counter": "0,1,2,3", 2567 "EventName": "OFFCORE_RESPONSE:request=PF_L1D_AND_SW:response=L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD", 2568 "MSRIndex": "0x1a6,0x1a7", 2569 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2570 "SampleAfterValue": "100003", 2571 "CounterHTOff": "0,1,2,3" 2572 }, 2573 { 2574 "Offcore": "1", 2575 "EventCode": "0xB7, 0xBB", 2576 "UMask": "0x1", 2577 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD", 2578 "Deprecated": "1", 2579 "MSRValue": "0x0804000400", 2580 "Counter": "0,1,2,3", 2581 "EventName": "OFFCORE_RESPONSE:request=PF_L1D_AND_SW:response=L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD", 2582 "MSRIndex": "0x1a6,0x1a7", 2583 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2584 "SampleAfterValue": "100003", 2585 "CounterHTOff": "0,1,2,3" 2586 }, 2587 { 2588 "Offcore": "1", 2589 "EventCode": "0xB7, 0xBB", 2590 "UMask": "0x1", 2591 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE", 2592 "Deprecated": "1", 2593 "MSRValue": "0x1004000400", 2594 "Counter": "0,1,2,3", 2595 "EventName": "OFFCORE_RESPONSE:request=PF_L1D_AND_SW:response=L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE", 2596 "MSRIndex": "0x1a6,0x1a7", 2597 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2598 "SampleAfterValue": "100003", 2599 "CounterHTOff": "0,1,2,3" 2600 }, 2601 { 2602 "Offcore": "1", 2603 "EventCode": "0xB7, 0xBB", 2604 "UMask": "0x1", 2605 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.ANY_SNOOP", 2606 "Deprecated": "1", 2607 "MSRValue": "0x3F84000400", 2608 "Counter": "0,1,2,3", 2609 "EventName": "OFFCORE_RESPONSE:request=PF_L1D_AND_SW:response=L3_MISS_LOCAL_DRAM.ANY_SNOOP", 2610 "MSRIndex": "0x1a6,0x1a7", 2611 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2612 "SampleAfterValue": "100003", 2613 "CounterHTOff": "0,1,2,3" 2614 }, 2615 { 2616 "Offcore": "1", 2617 "EventCode": "0xB7, 0xBB", 2618 "UMask": "0x1", 2619 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE", 2620 "Deprecated": "1", 2621 "MSRValue": "0x0090000400", 2622 "Counter": "0,1,2,3", 2623 "EventName": "OFFCORE_RESPONSE:request=PF_L1D_AND_SW:response=L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE", 2624 "MSRIndex": "0x1a6,0x1a7", 2625 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2626 "SampleAfterValue": "100003", 2627 "CounterHTOff": "0,1,2,3" 2628 }, 2629 { 2630 "Offcore": "1", 2631 "EventCode": "0xB7, 0xBB", 2632 "UMask": "0x1", 2633 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED", 2634 "Deprecated": "1", 2635 "MSRValue": "0x0110000400", 2636 "Counter": "0,1,2,3", 2637 "EventName": "OFFCORE_RESPONSE:request=PF_L1D_AND_SW:response=L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED", 2638 "MSRIndex": "0x1a6,0x1a7", 2639 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2640 "SampleAfterValue": "100003", 2641 "CounterHTOff": "0,1,2,3" 2642 }, 2643 { 2644 "Offcore": "1", 2645 "EventCode": "0xB7, 0xBB", 2646 "UMask": "0x1", 2647 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS", 2648 "Deprecated": "1", 2649 "MSRValue": "0x0210000400", 2650 "Counter": "0,1,2,3", 2651 "EventName": "OFFCORE_RESPONSE:request=PF_L1D_AND_SW:response=L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS", 2652 "MSRIndex": "0x1a6,0x1a7", 2653 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2654 "SampleAfterValue": "100003", 2655 "CounterHTOff": "0,1,2,3" 2656 }, 2657 { 2658 "Offcore": "1", 2659 "EventCode": "0xB7, 0xBB", 2660 "UMask": "0x1", 2661 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD", 2662 "Deprecated": "1", 2663 "MSRValue": "0x0410000400", 2664 "Counter": "0,1,2,3", 2665 "EventName": "OFFCORE_RESPONSE:request=PF_L1D_AND_SW:response=L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD", 2666 "MSRIndex": "0x1a6,0x1a7", 2667 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2668 "SampleAfterValue": "100003", 2669 "CounterHTOff": "0,1,2,3" 2670 }, 2671 { 2672 "Offcore": "1", 2673 "EventCode": "0xB7, 0xBB", 2674 "UMask": "0x1", 2675 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD", 2676 "Deprecated": "1", 2677 "MSRValue": "0x0810000400", 2678 "Counter": "0,1,2,3", 2679 "EventName": "OFFCORE_RESPONSE:request=PF_L1D_AND_SW:response=L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD", 2680 "MSRIndex": "0x1a6,0x1a7", 2681 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2682 "SampleAfterValue": "100003", 2683 "CounterHTOff": "0,1,2,3" 2684 }, 2685 { 2686 "Offcore": "1", 2687 "EventCode": "0xB7, 0xBB", 2688 "UMask": "0x1", 2689 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE", 2690 "Deprecated": "1", 2691 "MSRValue": "0x1010000400", 2692 "Counter": "0,1,2,3", 2693 "EventName": "OFFCORE_RESPONSE:request=PF_L1D_AND_SW:response=L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE", 2694 "MSRIndex": "0x1a6,0x1a7", 2695 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2696 "SampleAfterValue": "100003", 2697 "CounterHTOff": "0,1,2,3" 2698 }, 2699 { 2700 "Offcore": "1", 2701 "EventCode": "0xB7, 0xBB", 2702 "UMask": "0x1", 2703 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP", 2704 "Deprecated": "1", 2705 "MSRValue": "0x3F90000400", 2706 "Counter": "0,1,2,3", 2707 "EventName": "OFFCORE_RESPONSE:request=PF_L1D_AND_SW:response=L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP", 2708 "MSRIndex": "0x1a6,0x1a7", 2709 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2710 "SampleAfterValue": "100003", 2711 "CounterHTOff": "0,1,2,3" 2712 }, 2713 { 2714 "Offcore": "1", 2715 "EventCode": "0xB7, 0xBB", 2716 "UMask": "0x1", 2717 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS.SNOOP_NONE", 2718 "Deprecated": "1", 2719 "MSRValue": "0x00BC000400", 2720 "Counter": "0,1,2,3", 2721 "EventName": "OFFCORE_RESPONSE:request=PF_L1D_AND_SW:response=L3_MISS.SNOOP_NONE", 2722 "MSRIndex": "0x1a6,0x1a7", 2723 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2724 "SampleAfterValue": "100003", 2725 "CounterHTOff": "0,1,2,3" 2726 }, 2727 { 2728 "Offcore": "1", 2729 "EventCode": "0xB7, 0xBB", 2730 "UMask": "0x1", 2731 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS.NO_SNOOP_NEEDED", 2732 "Deprecated": "1", 2733 "MSRValue": "0x013C000400", 2734 "Counter": "0,1,2,3", 2735 "EventName": "OFFCORE_RESPONSE:request=PF_L1D_AND_SW:response=L3_MISS.NO_SNOOP_NEEDED", 2736 "MSRIndex": "0x1a6,0x1a7", 2737 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2738 "SampleAfterValue": "100003", 2739 "CounterHTOff": "0,1,2,3" 2740 }, 2741 { 2742 "Offcore": "1", 2743 "EventCode": "0xB7, 0xBB", 2744 "UMask": "0x1", 2745 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS.SNOOP_MISS", 2746 "Deprecated": "1", 2747 "MSRValue": "0x023C000400", 2748 "Counter": "0,1,2,3", 2749 "EventName": "OFFCORE_RESPONSE:request=PF_L1D_AND_SW:response=L3_MISS.SNOOP_MISS", 2750 "MSRIndex": "0x1a6,0x1a7", 2751 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2752 "SampleAfterValue": "100003", 2753 "CounterHTOff": "0,1,2,3" 2754 }, 2755 { 2756 "Offcore": "1", 2757 "EventCode": "0xB7, 0xBB", 2758 "UMask": "0x1", 2759 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS.HIT_OTHER_CORE_NO_FWD", 2760 "Deprecated": "1", 2761 "MSRValue": "0x043C000400", 2762 "Counter": "0,1,2,3", 2763 "EventName": "OFFCORE_RESPONSE:request=PF_L1D_AND_SW:response=L3_MISS.HIT_OTHER_CORE_NO_FWD", 2764 "MSRIndex": "0x1a6,0x1a7", 2765 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2766 "SampleAfterValue": "100003", 2767 "CounterHTOff": "0,1,2,3" 2768 }, 2769 { 2770 "Offcore": "1", 2771 "EventCode": "0xB7, 0xBB", 2772 "UMask": "0x1", 2773 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS.HIT_OTHER_CORE_FWD", 2774 "Deprecated": "1", 2775 "MSRValue": "0x083C000400", 2776 "Counter": "0,1,2,3", 2777 "EventName": "OFFCORE_RESPONSE:request=PF_L1D_AND_SW:response=L3_MISS.HIT_OTHER_CORE_FWD", 2778 "MSRIndex": "0x1a6,0x1a7", 2779 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2780 "SampleAfterValue": "100003", 2781 "CounterHTOff": "0,1,2,3" 2782 }, 2783 { 2784 "Offcore": "1", 2785 "EventCode": "0xB7, 0xBB", 2786 "UMask": "0x1", 2787 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS.HITM_OTHER_CORE", 2788 "Deprecated": "1", 2789 "MSRValue": "0x103C000400", 2790 "Counter": "0,1,2,3", 2791 "EventName": "OFFCORE_RESPONSE:request=PF_L1D_AND_SW:response=L3_MISS.HITM_OTHER_CORE", 2792 "MSRIndex": "0x1a6,0x1a7", 2793 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2794 "SampleAfterValue": "100003", 2795 "CounterHTOff": "0,1,2,3" 2796 }, 2797 { 2798 "Offcore": "1", 2799 "EventCode": "0xB7, 0xBB", 2800 "UMask": "0x1", 2801 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS.ANY_SNOOP", 2802 "Deprecated": "1", 2803 "MSRValue": "0x3FBC000400", 2804 "Counter": "0,1,2,3", 2805 "EventName": "OFFCORE_RESPONSE:request=PF_L1D_AND_SW:response=L3_MISS.ANY_SNOOP", 2806 "MSRIndex": "0x1a6,0x1a7", 2807 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2808 "SampleAfterValue": "100003", 2809 "CounterHTOff": "0,1,2,3" 2810 }, 2811 { 2812 "Offcore": "1", 2813 "EventCode": "0xB7, 0xBB", 2814 "UMask": "0x1", 2815 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.OTHER.L3_MISS_LOCAL_DRAM.SNOOP_NONE", 2816 "Deprecated": "1", 2817 "MSRValue": "0x0084008000", 2818 "Counter": "0,1,2,3", 2819 "EventName": "OFFCORE_RESPONSE:request=OTHER:response=L3_MISS_LOCAL_DRAM.SNOOP_NONE", 2820 "MSRIndex": "0x1a6,0x1a7", 2821 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2822 "SampleAfterValue": "100003", 2823 "CounterHTOff": "0,1,2,3" 2824 }, 2825 { 2826 "Offcore": "1", 2827 "EventCode": "0xB7, 0xBB", 2828 "UMask": "0x1", 2829 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.OTHER.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED", 2830 "Deprecated": "1", 2831 "MSRValue": "0x0104008000", 2832 "Counter": "0,1,2,3", 2833 "EventName": "OFFCORE_RESPONSE:request=OTHER:response=L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED", 2834 "MSRIndex": "0x1a6,0x1a7", 2835 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2836 "SampleAfterValue": "100003", 2837 "CounterHTOff": "0,1,2,3" 2838 }, 2839 { 2840 "Offcore": "1", 2841 "EventCode": "0xB7, 0xBB", 2842 "UMask": "0x1", 2843 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.OTHER.L3_MISS_LOCAL_DRAM.SNOOP_MISS", 2844 "Deprecated": "1", 2845 "MSRValue": "0x0204008000", 2846 "Counter": "0,1,2,3", 2847 "EventName": "OFFCORE_RESPONSE:request=OTHER:response=L3_MISS_LOCAL_DRAM.SNOOP_MISS", 2848 "MSRIndex": "0x1a6,0x1a7", 2849 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2850 "SampleAfterValue": "100003", 2851 "CounterHTOff": "0,1,2,3" 2852 }, 2853 { 2854 "Offcore": "1", 2855 "EventCode": "0xB7, 0xBB", 2856 "UMask": "0x1", 2857 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.OTHER.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD", 2858 "Deprecated": "1", 2859 "MSRValue": "0x0404008000", 2860 "Counter": "0,1,2,3", 2861 "EventName": "OFFCORE_RESPONSE:request=OTHER:response=L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD", 2862 "MSRIndex": "0x1a6,0x1a7", 2863 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2864 "SampleAfterValue": "100003", 2865 "CounterHTOff": "0,1,2,3" 2866 }, 2867 { 2868 "Offcore": "1", 2869 "EventCode": "0xB7, 0xBB", 2870 "UMask": "0x1", 2871 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.OTHER.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD", 2872 "Deprecated": "1", 2873 "MSRValue": "0x0804008000", 2874 "Counter": "0,1,2,3", 2875 "EventName": "OFFCORE_RESPONSE:request=OTHER:response=L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD", 2876 "MSRIndex": "0x1a6,0x1a7", 2877 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2878 "SampleAfterValue": "100003", 2879 "CounterHTOff": "0,1,2,3" 2880 }, 2881 { 2882 "Offcore": "1", 2883 "EventCode": "0xB7, 0xBB", 2884 "UMask": "0x1", 2885 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.OTHER.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE", 2886 "Deprecated": "1", 2887 "MSRValue": "0x1004008000", 2888 "Counter": "0,1,2,3", 2889 "EventName": "OFFCORE_RESPONSE:request=OTHER:response=L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE", 2890 "MSRIndex": "0x1a6,0x1a7", 2891 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2892 "SampleAfterValue": "100003", 2893 "CounterHTOff": "0,1,2,3" 2894 }, 2895 { 2896 "Offcore": "1", 2897 "EventCode": "0xB7, 0xBB", 2898 "UMask": "0x1", 2899 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.OTHER.L3_MISS_LOCAL_DRAM.ANY_SNOOP", 2900 "Deprecated": "1", 2901 "MSRValue": "0x3F84008000", 2902 "Counter": "0,1,2,3", 2903 "EventName": "OFFCORE_RESPONSE:request=OTHER:response=L3_MISS_LOCAL_DRAM.ANY_SNOOP", 2904 "MSRIndex": "0x1a6,0x1a7", 2905 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2906 "SampleAfterValue": "100003", 2907 "CounterHTOff": "0,1,2,3" 2908 }, 2909 { 2910 "Offcore": "1", 2911 "EventCode": "0xB7, 0xBB", 2912 "UMask": "0x1", 2913 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.OTHER.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE", 2914 "Deprecated": "1", 2915 "MSRValue": "0x0090008000", 2916 "Counter": "0,1,2,3", 2917 "EventName": "OFFCORE_RESPONSE:request=OTHER:response=L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE", 2918 "MSRIndex": "0x1a6,0x1a7", 2919 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2920 "SampleAfterValue": "100003", 2921 "CounterHTOff": "0,1,2,3" 2922 }, 2923 { 2924 "Offcore": "1", 2925 "EventCode": "0xB7, 0xBB", 2926 "UMask": "0x1", 2927 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.OTHER.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED", 2928 "Deprecated": "1", 2929 "MSRValue": "0x0110008000", 2930 "Counter": "0,1,2,3", 2931 "EventName": "OFFCORE_RESPONSE:request=OTHER:response=L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED", 2932 "MSRIndex": "0x1a6,0x1a7", 2933 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2934 "SampleAfterValue": "100003", 2935 "CounterHTOff": "0,1,2,3" 2936 }, 2937 { 2938 "Offcore": "1", 2939 "EventCode": "0xB7, 0xBB", 2940 "UMask": "0x1", 2941 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.OTHER.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS", 2942 "Deprecated": "1", 2943 "MSRValue": "0x0210008000", 2944 "Counter": "0,1,2,3", 2945 "EventName": "OFFCORE_RESPONSE:request=OTHER:response=L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS", 2946 "MSRIndex": "0x1a6,0x1a7", 2947 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2948 "SampleAfterValue": "100003", 2949 "CounterHTOff": "0,1,2,3" 2950 }, 2951 { 2952 "Offcore": "1", 2953 "EventCode": "0xB7, 0xBB", 2954 "UMask": "0x1", 2955 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.OTHER.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD", 2956 "Deprecated": "1", 2957 "MSRValue": "0x0410008000", 2958 "Counter": "0,1,2,3", 2959 "EventName": "OFFCORE_RESPONSE:request=OTHER:response=L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD", 2960 "MSRIndex": "0x1a6,0x1a7", 2961 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2962 "SampleAfterValue": "100003", 2963 "CounterHTOff": "0,1,2,3" 2964 }, 2965 { 2966 "Offcore": "1", 2967 "EventCode": "0xB7, 0xBB", 2968 "UMask": "0x1", 2969 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.OTHER.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD", 2970 "Deprecated": "1", 2971 "MSRValue": "0x0810008000", 2972 "Counter": "0,1,2,3", 2973 "EventName": "OFFCORE_RESPONSE:request=OTHER:response=L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD", 2974 "MSRIndex": "0x1a6,0x1a7", 2975 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2976 "SampleAfterValue": "100003", 2977 "CounterHTOff": "0,1,2,3" 2978 }, 2979 { 2980 "Offcore": "1", 2981 "EventCode": "0xB7, 0xBB", 2982 "UMask": "0x1", 2983 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.OTHER.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE", 2984 "Deprecated": "1", 2985 "MSRValue": "0x1010008000", 2986 "Counter": "0,1,2,3", 2987 "EventName": "OFFCORE_RESPONSE:request=OTHER:response=L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE", 2988 "MSRIndex": "0x1a6,0x1a7", 2989 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2990 "SampleAfterValue": "100003", 2991 "CounterHTOff": "0,1,2,3" 2992 }, 2993 { 2994 "Offcore": "1", 2995 "EventCode": "0xB7, 0xBB", 2996 "UMask": "0x1", 2997 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.OTHER.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP", 2998 "Deprecated": "1", 2999 "MSRValue": "0x3F90008000", 3000 "Counter": "0,1,2,3", 3001 "EventName": "OFFCORE_RESPONSE:request=OTHER:response=L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP", 3002 "MSRIndex": "0x1a6,0x1a7", 3003 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3004 "SampleAfterValue": "100003", 3005 "CounterHTOff": "0,1,2,3" 3006 }, 3007 { 3008 "Offcore": "1", 3009 "EventCode": "0xB7, 0xBB", 3010 "UMask": "0x1", 3011 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.OTHER.L3_MISS.SNOOP_NONE", 3012 "Deprecated": "1", 3013 "MSRValue": "0x00BC008000", 3014 "Counter": "0,1,2,3", 3015 "EventName": "OFFCORE_RESPONSE:request=OTHER:response=L3_MISS.SNOOP_NONE", 3016 "MSRIndex": "0x1a6,0x1a7", 3017 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3018 "SampleAfterValue": "100003", 3019 "CounterHTOff": "0,1,2,3" 3020 }, 3021 { 3022 "Offcore": "1", 3023 "EventCode": "0xB7, 0xBB", 3024 "UMask": "0x1", 3025 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.OTHER.L3_MISS.NO_SNOOP_NEEDED", 3026 "Deprecated": "1", 3027 "MSRValue": "0x013C008000", 3028 "Counter": "0,1,2,3", 3029 "EventName": "OFFCORE_RESPONSE:request=OTHER:response=L3_MISS.NO_SNOOP_NEEDED", 3030 "MSRIndex": "0x1a6,0x1a7", 3031 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3032 "SampleAfterValue": "100003", 3033 "CounterHTOff": "0,1,2,3" 3034 }, 3035 { 3036 "Offcore": "1", 3037 "EventCode": "0xB7, 0xBB", 3038 "UMask": "0x1", 3039 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.OTHER.L3_MISS.SNOOP_MISS", 3040 "Deprecated": "1", 3041 "MSRValue": "0x023C008000", 3042 "Counter": "0,1,2,3", 3043 "EventName": "OFFCORE_RESPONSE:request=OTHER:response=L3_MISS.SNOOP_MISS", 3044 "MSRIndex": "0x1a6,0x1a7", 3045 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3046 "SampleAfterValue": "100003", 3047 "CounterHTOff": "0,1,2,3" 3048 }, 3049 { 3050 "Offcore": "1", 3051 "EventCode": "0xB7, 0xBB", 3052 "UMask": "0x1", 3053 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.OTHER.L3_MISS.HIT_OTHER_CORE_NO_FWD", 3054 "Deprecated": "1", 3055 "MSRValue": "0x043C008000", 3056 "Counter": "0,1,2,3", 3057 "EventName": "OFFCORE_RESPONSE:request=OTHER:response=L3_MISS.HIT_OTHER_CORE_NO_FWD", 3058 "MSRIndex": "0x1a6,0x1a7", 3059 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3060 "SampleAfterValue": "100003", 3061 "CounterHTOff": "0,1,2,3" 3062 }, 3063 { 3064 "Offcore": "1", 3065 "EventCode": "0xB7, 0xBB", 3066 "UMask": "0x1", 3067 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.OTHER.L3_MISS.HIT_OTHER_CORE_FWD", 3068 "Deprecated": "1", 3069 "MSRValue": "0x083C008000", 3070 "Counter": "0,1,2,3", 3071 "EventName": "OFFCORE_RESPONSE:request=OTHER:response=L3_MISS.HIT_OTHER_CORE_FWD", 3072 "MSRIndex": "0x1a6,0x1a7", 3073 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3074 "SampleAfterValue": "100003", 3075 "CounterHTOff": "0,1,2,3" 3076 }, 3077 { 3078 "Offcore": "1", 3079 "EventCode": "0xB7, 0xBB", 3080 "UMask": "0x1", 3081 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.OTHER.L3_MISS.HITM_OTHER_CORE", 3082 "Deprecated": "1", 3083 "MSRValue": "0x103C008000", 3084 "Counter": "0,1,2,3", 3085 "EventName": "OFFCORE_RESPONSE:request=OTHER:response=L3_MISS.HITM_OTHER_CORE", 3086 "MSRIndex": "0x1a6,0x1a7", 3087 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3088 "SampleAfterValue": "100003", 3089 "CounterHTOff": "0,1,2,3" 3090 }, 3091 { 3092 "Offcore": "1", 3093 "EventCode": "0xB7, 0xBB", 3094 "UMask": "0x1", 3095 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.OTHER.L3_MISS.ANY_SNOOP", 3096 "Deprecated": "1", 3097 "MSRValue": "0x3FBC008000", 3098 "Counter": "0,1,2,3", 3099 "EventName": "OFFCORE_RESPONSE:request=OTHER:response=L3_MISS.ANY_SNOOP", 3100 "MSRIndex": "0x1a6,0x1a7", 3101 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3102 "SampleAfterValue": "100003", 3103 "CounterHTOff": "0,1,2,3" 3104 }, 3105 { 3106 "Offcore": "1", 3107 "EventCode": "0xB7, 0xBB", 3108 "UMask": "0x1", 3109 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NONE", 3110 "Deprecated": "1", 3111 "MSRValue": "0x0084000490", 3112 "Counter": "0,1,2,3", 3113 "EventName": "OFFCORE_RESPONSE:request=ALL_PF_DATA_RD:response=L3_MISS_LOCAL_DRAM.SNOOP_NONE", 3114 "MSRIndex": "0x1a6,0x1a7", 3115 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3116 "SampleAfterValue": "100003", 3117 "CounterHTOff": "0,1,2,3" 3118 }, 3119 { 3120 "Offcore": "1", 3121 "EventCode": "0xB7, 0xBB", 3122 "UMask": "0x1", 3123 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED", 3124 "Deprecated": "1", 3125 "MSRValue": "0x0104000490", 3126 "Counter": "0,1,2,3", 3127 "EventName": "OFFCORE_RESPONSE:request=ALL_PF_DATA_RD:response=L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED", 3128 "MSRIndex": "0x1a6,0x1a7", 3129 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3130 "SampleAfterValue": "100003", 3131 "CounterHTOff": "0,1,2,3" 3132 }, 3133 { 3134 "Offcore": "1", 3135 "EventCode": "0xB7, 0xBB", 3136 "UMask": "0x1", 3137 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS", 3138 "Deprecated": "1", 3139 "MSRValue": "0x0204000490", 3140 "Counter": "0,1,2,3", 3141 "EventName": "OFFCORE_RESPONSE:request=ALL_PF_DATA_RD:response=L3_MISS_LOCAL_DRAM.SNOOP_MISS", 3142 "MSRIndex": "0x1a6,0x1a7", 3143 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3144 "SampleAfterValue": "100003", 3145 "CounterHTOff": "0,1,2,3" 3146 }, 3147 { 3148 "Offcore": "1", 3149 "EventCode": "0xB7, 0xBB", 3150 "UMask": "0x1", 3151 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD", 3152 "Deprecated": "1", 3153 "MSRValue": "0x0404000490", 3154 "Counter": "0,1,2,3", 3155 "EventName": "OFFCORE_RESPONSE:request=ALL_PF_DATA_RD:response=L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD", 3156 "MSRIndex": "0x1a6,0x1a7", 3157 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3158 "SampleAfterValue": "100003", 3159 "CounterHTOff": "0,1,2,3" 3160 }, 3161 { 3162 "Offcore": "1", 3163 "EventCode": "0xB7, 0xBB", 3164 "UMask": "0x1", 3165 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD", 3166 "Deprecated": "1", 3167 "MSRValue": "0x0804000490", 3168 "Counter": "0,1,2,3", 3169 "EventName": "OFFCORE_RESPONSE:request=ALL_PF_DATA_RD:response=L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD", 3170 "MSRIndex": "0x1a6,0x1a7", 3171 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3172 "SampleAfterValue": "100003", 3173 "CounterHTOff": "0,1,2,3" 3174 }, 3175 { 3176 "Offcore": "1", 3177 "EventCode": "0xB7, 0xBB", 3178 "UMask": "0x1", 3179 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE", 3180 "Deprecated": "1", 3181 "MSRValue": "0x1004000490", 3182 "Counter": "0,1,2,3", 3183 "EventName": "OFFCORE_RESPONSE:request=ALL_PF_DATA_RD:response=L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE", 3184 "MSRIndex": "0x1a6,0x1a7", 3185 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3186 "SampleAfterValue": "100003", 3187 "CounterHTOff": "0,1,2,3" 3188 }, 3189 { 3190 "Offcore": "1", 3191 "EventCode": "0xB7, 0xBB", 3192 "UMask": "0x1", 3193 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP", 3194 "Deprecated": "1", 3195 "MSRValue": "0x3F84000490", 3196 "Counter": "0,1,2,3", 3197 "EventName": "OFFCORE_RESPONSE:request=ALL_PF_DATA_RD:response=L3_MISS_LOCAL_DRAM.ANY_SNOOP", 3198 "MSRIndex": "0x1a6,0x1a7", 3199 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3200 "SampleAfterValue": "100003", 3201 "CounterHTOff": "0,1,2,3" 3202 }, 3203 { 3204 "Offcore": "1", 3205 "EventCode": "0xB7, 0xBB", 3206 "UMask": "0x1", 3207 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE", 3208 "Deprecated": "1", 3209 "MSRValue": "0x0090000490", 3210 "Counter": "0,1,2,3", 3211 "EventName": "OFFCORE_RESPONSE:request=ALL_PF_DATA_RD:response=L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE", 3212 "MSRIndex": "0x1a6,0x1a7", 3213 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3214 "SampleAfterValue": "100003", 3215 "CounterHTOff": "0,1,2,3" 3216 }, 3217 { 3218 "Offcore": "1", 3219 "EventCode": "0xB7, 0xBB", 3220 "UMask": "0x1", 3221 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED", 3222 "Deprecated": "1", 3223 "MSRValue": "0x0110000490", 3224 "Counter": "0,1,2,3", 3225 "EventName": "OFFCORE_RESPONSE:request=ALL_PF_DATA_RD:response=L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED", 3226 "MSRIndex": "0x1a6,0x1a7", 3227 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3228 "SampleAfterValue": "100003", 3229 "CounterHTOff": "0,1,2,3" 3230 }, 3231 { 3232 "Offcore": "1", 3233 "EventCode": "0xB7, 0xBB", 3234 "UMask": "0x1", 3235 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS", 3236 "Deprecated": "1", 3237 "MSRValue": "0x0210000490", 3238 "Counter": "0,1,2,3", 3239 "EventName": "OFFCORE_RESPONSE:request=ALL_PF_DATA_RD:response=L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS", 3240 "MSRIndex": "0x1a6,0x1a7", 3241 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3242 "SampleAfterValue": "100003", 3243 "CounterHTOff": "0,1,2,3" 3244 }, 3245 { 3246 "Offcore": "1", 3247 "EventCode": "0xB7, 0xBB", 3248 "UMask": "0x1", 3249 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD", 3250 "Deprecated": "1", 3251 "MSRValue": "0x0410000490", 3252 "Counter": "0,1,2,3", 3253 "EventName": "OFFCORE_RESPONSE:request=ALL_PF_DATA_RD:response=L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD", 3254 "MSRIndex": "0x1a6,0x1a7", 3255 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3256 "SampleAfterValue": "100003", 3257 "CounterHTOff": "0,1,2,3" 3258 }, 3259 { 3260 "Offcore": "1", 3261 "EventCode": "0xB7, 0xBB", 3262 "UMask": "0x1", 3263 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD", 3264 "Deprecated": "1", 3265 "MSRValue": "0x0810000490", 3266 "Counter": "0,1,2,3", 3267 "EventName": "OFFCORE_RESPONSE:request=ALL_PF_DATA_RD:response=L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD", 3268 "MSRIndex": "0x1a6,0x1a7", 3269 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3270 "SampleAfterValue": "100003", 3271 "CounterHTOff": "0,1,2,3" 3272 }, 3273 { 3274 "Offcore": "1", 3275 "EventCode": "0xB7, 0xBB", 3276 "UMask": "0x1", 3277 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE", 3278 "Deprecated": "1", 3279 "MSRValue": "0x1010000490", 3280 "Counter": "0,1,2,3", 3281 "EventName": "OFFCORE_RESPONSE:request=ALL_PF_DATA_RD:response=L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE", 3282 "MSRIndex": "0x1a6,0x1a7", 3283 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3284 "SampleAfterValue": "100003", 3285 "CounterHTOff": "0,1,2,3" 3286 }, 3287 { 3288 "Offcore": "1", 3289 "EventCode": "0xB7, 0xBB", 3290 "UMask": "0x1", 3291 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP", 3292 "Deprecated": "1", 3293 "MSRValue": "0x3F90000490", 3294 "Counter": "0,1,2,3", 3295 "EventName": "OFFCORE_RESPONSE:request=ALL_PF_DATA_RD:response=L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP", 3296 "MSRIndex": "0x1a6,0x1a7", 3297 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3298 "SampleAfterValue": "100003", 3299 "CounterHTOff": "0,1,2,3" 3300 }, 3301 { 3302 "Offcore": "1", 3303 "EventCode": "0xB7, 0xBB", 3304 "UMask": "0x1", 3305 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS.SNOOP_NONE", 3306 "Deprecated": "1", 3307 "MSRValue": "0x00BC000490", 3308 "Counter": "0,1,2,3", 3309 "EventName": "OFFCORE_RESPONSE:request=ALL_PF_DATA_RD:response=L3_MISS.SNOOP_NONE", 3310 "MSRIndex": "0x1a6,0x1a7", 3311 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3312 "SampleAfterValue": "100003", 3313 "CounterHTOff": "0,1,2,3" 3314 }, 3315 { 3316 "Offcore": "1", 3317 "EventCode": "0xB7, 0xBB", 3318 "UMask": "0x1", 3319 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS.NO_SNOOP_NEEDED", 3320 "Deprecated": "1", 3321 "MSRValue": "0x013C000490", 3322 "Counter": "0,1,2,3", 3323 "EventName": "OFFCORE_RESPONSE:request=ALL_PF_DATA_RD:response=L3_MISS.NO_SNOOP_NEEDED", 3324 "MSRIndex": "0x1a6,0x1a7", 3325 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3326 "SampleAfterValue": "100003", 3327 "CounterHTOff": "0,1,2,3" 3328 }, 3329 { 3330 "Offcore": "1", 3331 "EventCode": "0xB7, 0xBB", 3332 "UMask": "0x1", 3333 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS.SNOOP_MISS", 3334 "Deprecated": "1", 3335 "MSRValue": "0x023C000490", 3336 "Counter": "0,1,2,3", 3337 "EventName": "OFFCORE_RESPONSE:request=ALL_PF_DATA_RD:response=L3_MISS.SNOOP_MISS", 3338 "MSRIndex": "0x1a6,0x1a7", 3339 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3340 "SampleAfterValue": "100003", 3341 "CounterHTOff": "0,1,2,3" 3342 }, 3343 { 3344 "Offcore": "1", 3345 "EventCode": "0xB7, 0xBB", 3346 "UMask": "0x1", 3347 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS.HIT_OTHER_CORE_NO_FWD", 3348 "Deprecated": "1", 3349 "MSRValue": "0x043C000490", 3350 "Counter": "0,1,2,3", 3351 "EventName": "OFFCORE_RESPONSE:request=ALL_PF_DATA_RD:response=L3_MISS.HIT_OTHER_CORE_NO_FWD", 3352 "MSRIndex": "0x1a6,0x1a7", 3353 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3354 "SampleAfterValue": "100003", 3355 "CounterHTOff": "0,1,2,3" 3356 }, 3357 { 3358 "Offcore": "1", 3359 "EventCode": "0xB7, 0xBB", 3360 "UMask": "0x1", 3361 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS.HIT_OTHER_CORE_FWD", 3362 "Deprecated": "1", 3363 "MSRValue": "0x083C000490", 3364 "Counter": "0,1,2,3", 3365 "EventName": "OFFCORE_RESPONSE:request=ALL_PF_DATA_RD:response=L3_MISS.HIT_OTHER_CORE_FWD", 3366 "MSRIndex": "0x1a6,0x1a7", 3367 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3368 "SampleAfterValue": "100003", 3369 "CounterHTOff": "0,1,2,3" 3370 }, 3371 { 3372 "Offcore": "1", 3373 "EventCode": "0xB7, 0xBB", 3374 "UMask": "0x1", 3375 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS.HITM_OTHER_CORE", 3376 "Deprecated": "1", 3377 "MSRValue": "0x103C000490", 3378 "Counter": "0,1,2,3", 3379 "EventName": "OFFCORE_RESPONSE:request=ALL_PF_DATA_RD:response=L3_MISS.HITM_OTHER_CORE", 3380 "MSRIndex": "0x1a6,0x1a7", 3381 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3382 "SampleAfterValue": "100003", 3383 "CounterHTOff": "0,1,2,3" 3384 }, 3385 { 3386 "Offcore": "1", 3387 "EventCode": "0xB7, 0xBB", 3388 "UMask": "0x1", 3389 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS.ANY_SNOOP", 3390 "Deprecated": "1", 3391 "MSRValue": "0x3FBC000490", 3392 "Counter": "0,1,2,3", 3393 "EventName": "OFFCORE_RESPONSE:request=ALL_PF_DATA_RD:response=L3_MISS.ANY_SNOOP", 3394 "MSRIndex": "0x1a6,0x1a7", 3395 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3396 "SampleAfterValue": "100003", 3397 "CounterHTOff": "0,1,2,3" 3398 }, 3399 { 3400 "Offcore": "1", 3401 "EventCode": "0xB7, 0xBB", 3402 "UMask": "0x1", 3403 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NONE", 3404 "Deprecated": "1", 3405 "MSRValue": "0x0084000120", 3406 "Counter": "0,1,2,3", 3407 "EventName": "OFFCORE_RESPONSE:request=ALL_PF_RFO:response=L3_MISS_LOCAL_DRAM.SNOOP_NONE", 3408 "MSRIndex": "0x1a6,0x1a7", 3409 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3410 "SampleAfterValue": "100003", 3411 "CounterHTOff": "0,1,2,3" 3412 }, 3413 { 3414 "Offcore": "1", 3415 "EventCode": "0xB7, 0xBB", 3416 "UMask": "0x1", 3417 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED", 3418 "Deprecated": "1", 3419 "MSRValue": "0x0104000120", 3420 "Counter": "0,1,2,3", 3421 "EventName": "OFFCORE_RESPONSE:request=ALL_PF_RFO:response=L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED", 3422 "MSRIndex": "0x1a6,0x1a7", 3423 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3424 "SampleAfterValue": "100003", 3425 "CounterHTOff": "0,1,2,3" 3426 }, 3427 { 3428 "Offcore": "1", 3429 "EventCode": "0xB7, 0xBB", 3430 "UMask": "0x1", 3431 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS", 3432 "Deprecated": "1", 3433 "MSRValue": "0x0204000120", 3434 "Counter": "0,1,2,3", 3435 "EventName": "OFFCORE_RESPONSE:request=ALL_PF_RFO:response=L3_MISS_LOCAL_DRAM.SNOOP_MISS", 3436 "MSRIndex": "0x1a6,0x1a7", 3437 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3438 "SampleAfterValue": "100003", 3439 "CounterHTOff": "0,1,2,3" 3440 }, 3441 { 3442 "Offcore": "1", 3443 "EventCode": "0xB7, 0xBB", 3444 "UMask": "0x1", 3445 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD", 3446 "Deprecated": "1", 3447 "MSRValue": "0x0404000120", 3448 "Counter": "0,1,2,3", 3449 "EventName": "OFFCORE_RESPONSE:request=ALL_PF_RFO:response=L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD", 3450 "MSRIndex": "0x1a6,0x1a7", 3451 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3452 "SampleAfterValue": "100003", 3453 "CounterHTOff": "0,1,2,3" 3454 }, 3455 { 3456 "Offcore": "1", 3457 "EventCode": "0xB7, 0xBB", 3458 "UMask": "0x1", 3459 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD", 3460 "Deprecated": "1", 3461 "MSRValue": "0x0804000120", 3462 "Counter": "0,1,2,3", 3463 "EventName": "OFFCORE_RESPONSE:request=ALL_PF_RFO:response=L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD", 3464 "MSRIndex": "0x1a6,0x1a7", 3465 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3466 "SampleAfterValue": "100003", 3467 "CounterHTOff": "0,1,2,3" 3468 }, 3469 { 3470 "Offcore": "1", 3471 "EventCode": "0xB7, 0xBB", 3472 "UMask": "0x1", 3473 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE", 3474 "Deprecated": "1", 3475 "MSRValue": "0x1004000120", 3476 "Counter": "0,1,2,3", 3477 "EventName": "OFFCORE_RESPONSE:request=ALL_PF_RFO:response=L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE", 3478 "MSRIndex": "0x1a6,0x1a7", 3479 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3480 "SampleAfterValue": "100003", 3481 "CounterHTOff": "0,1,2,3" 3482 }, 3483 { 3484 "Offcore": "1", 3485 "EventCode": "0xB7, 0xBB", 3486 "UMask": "0x1", 3487 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.ANY_SNOOP", 3488 "Deprecated": "1", 3489 "MSRValue": "0x3F84000120", 3490 "Counter": "0,1,2,3", 3491 "EventName": "OFFCORE_RESPONSE:request=ALL_PF_RFO:response=L3_MISS_LOCAL_DRAM.ANY_SNOOP", 3492 "MSRIndex": "0x1a6,0x1a7", 3493 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3494 "SampleAfterValue": "100003", 3495 "CounterHTOff": "0,1,2,3" 3496 }, 3497 { 3498 "Offcore": "1", 3499 "EventCode": "0xB7, 0xBB", 3500 "UMask": "0x1", 3501 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE", 3502 "Deprecated": "1", 3503 "MSRValue": "0x0090000120", 3504 "Counter": "0,1,2,3", 3505 "EventName": "OFFCORE_RESPONSE:request=ALL_PF_RFO:response=L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE", 3506 "MSRIndex": "0x1a6,0x1a7", 3507 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3508 "SampleAfterValue": "100003", 3509 "CounterHTOff": "0,1,2,3" 3510 }, 3511 { 3512 "Offcore": "1", 3513 "EventCode": "0xB7, 0xBB", 3514 "UMask": "0x1", 3515 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED", 3516 "Deprecated": "1", 3517 "MSRValue": "0x0110000120", 3518 "Counter": "0,1,2,3", 3519 "EventName": "OFFCORE_RESPONSE:request=ALL_PF_RFO:response=L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED", 3520 "MSRIndex": "0x1a6,0x1a7", 3521 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3522 "SampleAfterValue": "100003", 3523 "CounterHTOff": "0,1,2,3" 3524 }, 3525 { 3526 "Offcore": "1", 3527 "EventCode": "0xB7, 0xBB", 3528 "UMask": "0x1", 3529 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS", 3530 "Deprecated": "1", 3531 "MSRValue": "0x0210000120", 3532 "Counter": "0,1,2,3", 3533 "EventName": "OFFCORE_RESPONSE:request=ALL_PF_RFO:response=L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS", 3534 "MSRIndex": "0x1a6,0x1a7", 3535 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3536 "SampleAfterValue": "100003", 3537 "CounterHTOff": "0,1,2,3" 3538 }, 3539 { 3540 "Offcore": "1", 3541 "EventCode": "0xB7, 0xBB", 3542 "UMask": "0x1", 3543 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD", 3544 "Deprecated": "1", 3545 "MSRValue": "0x0410000120", 3546 "Counter": "0,1,2,3", 3547 "EventName": "OFFCORE_RESPONSE:request=ALL_PF_RFO:response=L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD", 3548 "MSRIndex": "0x1a6,0x1a7", 3549 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3550 "SampleAfterValue": "100003", 3551 "CounterHTOff": "0,1,2,3" 3552 }, 3553 { 3554 "Offcore": "1", 3555 "EventCode": "0xB7, 0xBB", 3556 "UMask": "0x1", 3557 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD", 3558 "Deprecated": "1", 3559 "MSRValue": "0x0810000120", 3560 "Counter": "0,1,2,3", 3561 "EventName": "OFFCORE_RESPONSE:request=ALL_PF_RFO:response=L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD", 3562 "MSRIndex": "0x1a6,0x1a7", 3563 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3564 "SampleAfterValue": "100003", 3565 "CounterHTOff": "0,1,2,3" 3566 }, 3567 { 3568 "Offcore": "1", 3569 "EventCode": "0xB7, 0xBB", 3570 "UMask": "0x1", 3571 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE", 3572 "Deprecated": "1", 3573 "MSRValue": "0x1010000120", 3574 "Counter": "0,1,2,3", 3575 "EventName": "OFFCORE_RESPONSE:request=ALL_PF_RFO:response=L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE", 3576 "MSRIndex": "0x1a6,0x1a7", 3577 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3578 "SampleAfterValue": "100003", 3579 "CounterHTOff": "0,1,2,3" 3580 }, 3581 { 3582 "Offcore": "1", 3583 "EventCode": "0xB7, 0xBB", 3584 "UMask": "0x1", 3585 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP", 3586 "Deprecated": "1", 3587 "MSRValue": "0x3F90000120", 3588 "Counter": "0,1,2,3", 3589 "EventName": "OFFCORE_RESPONSE:request=ALL_PF_RFO:response=L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP", 3590 "MSRIndex": "0x1a6,0x1a7", 3591 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3592 "SampleAfterValue": "100003", 3593 "CounterHTOff": "0,1,2,3" 3594 }, 3595 { 3596 "Offcore": "1", 3597 "EventCode": "0xB7, 0xBB", 3598 "UMask": "0x1", 3599 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS.SNOOP_NONE", 3600 "Deprecated": "1", 3601 "MSRValue": "0x00BC000120", 3602 "Counter": "0,1,2,3", 3603 "EventName": "OFFCORE_RESPONSE:request=ALL_PF_RFO:response=L3_MISS.SNOOP_NONE", 3604 "MSRIndex": "0x1a6,0x1a7", 3605 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3606 "SampleAfterValue": "100003", 3607 "CounterHTOff": "0,1,2,3" 3608 }, 3609 { 3610 "Offcore": "1", 3611 "EventCode": "0xB7, 0xBB", 3612 "UMask": "0x1", 3613 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS.NO_SNOOP_NEEDED", 3614 "Deprecated": "1", 3615 "MSRValue": "0x013C000120", 3616 "Counter": "0,1,2,3", 3617 "EventName": "OFFCORE_RESPONSE:request=ALL_PF_RFO:response=L3_MISS.NO_SNOOP_NEEDED", 3618 "MSRIndex": "0x1a6,0x1a7", 3619 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3620 "SampleAfterValue": "100003", 3621 "CounterHTOff": "0,1,2,3" 3622 }, 3623 { 3624 "Offcore": "1", 3625 "EventCode": "0xB7, 0xBB", 3626 "UMask": "0x1", 3627 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS.SNOOP_MISS", 3628 "Deprecated": "1", 3629 "MSRValue": "0x023C000120", 3630 "Counter": "0,1,2,3", 3631 "EventName": "OFFCORE_RESPONSE:request=ALL_PF_RFO:response=L3_MISS.SNOOP_MISS", 3632 "MSRIndex": "0x1a6,0x1a7", 3633 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3634 "SampleAfterValue": "100003", 3635 "CounterHTOff": "0,1,2,3" 3636 }, 3637 { 3638 "Offcore": "1", 3639 "EventCode": "0xB7, 0xBB", 3640 "UMask": "0x1", 3641 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS.HIT_OTHER_CORE_NO_FWD", 3642 "Deprecated": "1", 3643 "MSRValue": "0x043C000120", 3644 "Counter": "0,1,2,3", 3645 "EventName": "OFFCORE_RESPONSE:request=ALL_PF_RFO:response=L3_MISS.HIT_OTHER_CORE_NO_FWD", 3646 "MSRIndex": "0x1a6,0x1a7", 3647 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3648 "SampleAfterValue": "100003", 3649 "CounterHTOff": "0,1,2,3" 3650 }, 3651 { 3652 "Offcore": "1", 3653 "EventCode": "0xB7, 0xBB", 3654 "UMask": "0x1", 3655 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS.HIT_OTHER_CORE_FWD", 3656 "Deprecated": "1", 3657 "MSRValue": "0x083C000120", 3658 "Counter": "0,1,2,3", 3659 "EventName": "OFFCORE_RESPONSE:request=ALL_PF_RFO:response=L3_MISS.HIT_OTHER_CORE_FWD", 3660 "MSRIndex": "0x1a6,0x1a7", 3661 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3662 "SampleAfterValue": "100003", 3663 "CounterHTOff": "0,1,2,3" 3664 }, 3665 { 3666 "Offcore": "1", 3667 "EventCode": "0xB7, 0xBB", 3668 "UMask": "0x1", 3669 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS.HITM_OTHER_CORE", 3670 "Deprecated": "1", 3671 "MSRValue": "0x103C000120", 3672 "Counter": "0,1,2,3", 3673 "EventName": "OFFCORE_RESPONSE:request=ALL_PF_RFO:response=L3_MISS.HITM_OTHER_CORE", 3674 "MSRIndex": "0x1a6,0x1a7", 3675 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3676 "SampleAfterValue": "100003", 3677 "CounterHTOff": "0,1,2,3" 3678 }, 3679 { 3680 "Offcore": "1", 3681 "EventCode": "0xB7, 0xBB", 3682 "UMask": "0x1", 3683 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS.ANY_SNOOP", 3684 "Deprecated": "1", 3685 "MSRValue": "0x3FBC000120", 3686 "Counter": "0,1,2,3", 3687 "EventName": "OFFCORE_RESPONSE:request=ALL_PF_RFO:response=L3_MISS.ANY_SNOOP", 3688 "MSRIndex": "0x1a6,0x1a7", 3689 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3690 "SampleAfterValue": "100003", 3691 "CounterHTOff": "0,1,2,3" 3692 }, 3693 { 3694 "Offcore": "1", 3695 "EventCode": "0xB7, 0xBB", 3696 "UMask": "0x1", 3697 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NONE", 3698 "Deprecated": "1", 3699 "MSRValue": "0x0084000491", 3700 "Counter": "0,1,2,3", 3701 "EventName": "OFFCORE_RESPONSE:request=ALL_DATA_RD:response=L3_MISS_LOCAL_DRAM.SNOOP_NONE", 3702 "MSRIndex": "0x1a6,0x1a7", 3703 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3704 "SampleAfterValue": "100003", 3705 "CounterHTOff": "0,1,2,3" 3706 }, 3707 { 3708 "Offcore": "1", 3709 "EventCode": "0xB7, 0xBB", 3710 "UMask": "0x1", 3711 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED", 3712 "Deprecated": "1", 3713 "MSRValue": "0x0104000491", 3714 "Counter": "0,1,2,3", 3715 "EventName": "OFFCORE_RESPONSE:request=ALL_DATA_RD:response=L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED", 3716 "MSRIndex": "0x1a6,0x1a7", 3717 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3718 "SampleAfterValue": "100003", 3719 "CounterHTOff": "0,1,2,3" 3720 }, 3721 { 3722 "Offcore": "1", 3723 "EventCode": "0xB7, 0xBB", 3724 "UMask": "0x1", 3725 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS", 3726 "Deprecated": "1", 3727 "MSRValue": "0x0204000491", 3728 "Counter": "0,1,2,3", 3729 "EventName": "OFFCORE_RESPONSE:request=ALL_DATA_RD:response=L3_MISS_LOCAL_DRAM.SNOOP_MISS", 3730 "MSRIndex": "0x1a6,0x1a7", 3731 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3732 "SampleAfterValue": "100003", 3733 "CounterHTOff": "0,1,2,3" 3734 }, 3735 { 3736 "Offcore": "1", 3737 "EventCode": "0xB7, 0xBB", 3738 "UMask": "0x1", 3739 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD", 3740 "Deprecated": "1", 3741 "MSRValue": "0x0404000491", 3742 "Counter": "0,1,2,3", 3743 "EventName": "OFFCORE_RESPONSE:request=ALL_DATA_RD:response=L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD", 3744 "MSRIndex": "0x1a6,0x1a7", 3745 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3746 "SampleAfterValue": "100003", 3747 "CounterHTOff": "0,1,2,3" 3748 }, 3749 { 3750 "Offcore": "1", 3751 "EventCode": "0xB7, 0xBB", 3752 "UMask": "0x1", 3753 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD", 3754 "Deprecated": "1", 3755 "MSRValue": "0x0804000491", 3756 "Counter": "0,1,2,3", 3757 "EventName": "OFFCORE_RESPONSE:request=ALL_DATA_RD:response=L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD", 3758 "MSRIndex": "0x1a6,0x1a7", 3759 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3760 "SampleAfterValue": "100003", 3761 "CounterHTOff": "0,1,2,3" 3762 }, 3763 { 3764 "Offcore": "1", 3765 "EventCode": "0xB7, 0xBB", 3766 "UMask": "0x1", 3767 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE", 3768 "Deprecated": "1", 3769 "MSRValue": "0x1004000491", 3770 "Counter": "0,1,2,3", 3771 "EventName": "OFFCORE_RESPONSE:request=ALL_DATA_RD:response=L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE", 3772 "MSRIndex": "0x1a6,0x1a7", 3773 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3774 "SampleAfterValue": "100003", 3775 "CounterHTOff": "0,1,2,3" 3776 }, 3777 { 3778 "Offcore": "1", 3779 "EventCode": "0xB7, 0xBB", 3780 "UMask": "0x1", 3781 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP", 3782 "Deprecated": "1", 3783 "MSRValue": "0x3F84000491", 3784 "Counter": "0,1,2,3", 3785 "EventName": "OFFCORE_RESPONSE:request=ALL_DATA_RD:response=L3_MISS_LOCAL_DRAM.ANY_SNOOP", 3786 "MSRIndex": "0x1a6,0x1a7", 3787 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3788 "SampleAfterValue": "100003", 3789 "CounterHTOff": "0,1,2,3" 3790 }, 3791 { 3792 "Offcore": "1", 3793 "EventCode": "0xB7, 0xBB", 3794 "UMask": "0x1", 3795 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE", 3796 "Deprecated": "1", 3797 "MSRValue": "0x0090000491", 3798 "Counter": "0,1,2,3", 3799 "EventName": "OFFCORE_RESPONSE:request=ALL_DATA_RD:response=L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE", 3800 "MSRIndex": "0x1a6,0x1a7", 3801 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3802 "SampleAfterValue": "100003", 3803 "CounterHTOff": "0,1,2,3" 3804 }, 3805 { 3806 "Offcore": "1", 3807 "EventCode": "0xB7, 0xBB", 3808 "UMask": "0x1", 3809 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED", 3810 "Deprecated": "1", 3811 "MSRValue": "0x0110000491", 3812 "Counter": "0,1,2,3", 3813 "EventName": "OFFCORE_RESPONSE:request=ALL_DATA_RD:response=L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED", 3814 "MSRIndex": "0x1a6,0x1a7", 3815 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3816 "SampleAfterValue": "100003", 3817 "CounterHTOff": "0,1,2,3" 3818 }, 3819 { 3820 "Offcore": "1", 3821 "EventCode": "0xB7, 0xBB", 3822 "UMask": "0x1", 3823 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS", 3824 "Deprecated": "1", 3825 "MSRValue": "0x0210000491", 3826 "Counter": "0,1,2,3", 3827 "EventName": "OFFCORE_RESPONSE:request=ALL_DATA_RD:response=L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS", 3828 "MSRIndex": "0x1a6,0x1a7", 3829 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3830 "SampleAfterValue": "100003", 3831 "CounterHTOff": "0,1,2,3" 3832 }, 3833 { 3834 "Offcore": "1", 3835 "EventCode": "0xB7, 0xBB", 3836 "UMask": "0x1", 3837 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD", 3838 "Deprecated": "1", 3839 "MSRValue": "0x0410000491", 3840 "Counter": "0,1,2,3", 3841 "EventName": "OFFCORE_RESPONSE:request=ALL_DATA_RD:response=L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD", 3842 "MSRIndex": "0x1a6,0x1a7", 3843 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3844 "SampleAfterValue": "100003", 3845 "CounterHTOff": "0,1,2,3" 3846 }, 3847 { 3848 "Offcore": "1", 3849 "EventCode": "0xB7, 0xBB", 3850 "UMask": "0x1", 3851 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD", 3852 "Deprecated": "1", 3853 "MSRValue": "0x0810000491", 3854 "Counter": "0,1,2,3", 3855 "EventName": "OFFCORE_RESPONSE:request=ALL_DATA_RD:response=L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD", 3856 "MSRIndex": "0x1a6,0x1a7", 3857 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3858 "SampleAfterValue": "100003", 3859 "CounterHTOff": "0,1,2,3" 3860 }, 3861 { 3862 "Offcore": "1", 3863 "EventCode": "0xB7, 0xBB", 3864 "UMask": "0x1", 3865 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE", 3866 "Deprecated": "1", 3867 "MSRValue": "0x1010000491", 3868 "Counter": "0,1,2,3", 3869 "EventName": "OFFCORE_RESPONSE:request=ALL_DATA_RD:response=L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE", 3870 "MSRIndex": "0x1a6,0x1a7", 3871 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3872 "SampleAfterValue": "100003", 3873 "CounterHTOff": "0,1,2,3" 3874 }, 3875 { 3876 "Offcore": "1", 3877 "EventCode": "0xB7, 0xBB", 3878 "UMask": "0x1", 3879 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP", 3880 "Deprecated": "1", 3881 "MSRValue": "0x3F90000491", 3882 "Counter": "0,1,2,3", 3883 "EventName": "OFFCORE_RESPONSE:request=ALL_DATA_RD:response=L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP", 3884 "MSRIndex": "0x1a6,0x1a7", 3885 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3886 "SampleAfterValue": "100003", 3887 "CounterHTOff": "0,1,2,3" 3888 }, 3889 { 3890 "Offcore": "1", 3891 "EventCode": "0xB7, 0xBB", 3892 "UMask": "0x1", 3893 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS.SNOOP_NONE", 3894 "Deprecated": "1", 3895 "MSRValue": "0x00BC000491", 3896 "Counter": "0,1,2,3", 3897 "EventName": "OFFCORE_RESPONSE:request=ALL_DATA_RD:response=L3_MISS.SNOOP_NONE", 3898 "MSRIndex": "0x1a6,0x1a7", 3899 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3900 "SampleAfterValue": "100003", 3901 "CounterHTOff": "0,1,2,3" 3902 }, 3903 { 3904 "Offcore": "1", 3905 "EventCode": "0xB7, 0xBB", 3906 "UMask": "0x1", 3907 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS.NO_SNOOP_NEEDED", 3908 "Deprecated": "1", 3909 "MSRValue": "0x013C000491", 3910 "Counter": "0,1,2,3", 3911 "EventName": "OFFCORE_RESPONSE:request=ALL_DATA_RD:response=L3_MISS.NO_SNOOP_NEEDED", 3912 "MSRIndex": "0x1a6,0x1a7", 3913 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3914 "SampleAfterValue": "100003", 3915 "CounterHTOff": "0,1,2,3" 3916 }, 3917 { 3918 "Offcore": "1", 3919 "EventCode": "0xB7, 0xBB", 3920 "UMask": "0x1", 3921 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS.SNOOP_MISS", 3922 "Deprecated": "1", 3923 "MSRValue": "0x023C000491", 3924 "Counter": "0,1,2,3", 3925 "EventName": "OFFCORE_RESPONSE:request=ALL_DATA_RD:response=L3_MISS.SNOOP_MISS", 3926 "MSRIndex": "0x1a6,0x1a7", 3927 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3928 "SampleAfterValue": "100003", 3929 "CounterHTOff": "0,1,2,3" 3930 }, 3931 { 3932 "Offcore": "1", 3933 "EventCode": "0xB7, 0xBB", 3934 "UMask": "0x1", 3935 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS.HIT_OTHER_CORE_NO_FWD", 3936 "Deprecated": "1", 3937 "MSRValue": "0x043C000491", 3938 "Counter": "0,1,2,3", 3939 "EventName": "OFFCORE_RESPONSE:request=ALL_DATA_RD:response=L3_MISS.HIT_OTHER_CORE_NO_FWD", 3940 "MSRIndex": "0x1a6,0x1a7", 3941 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3942 "SampleAfterValue": "100003", 3943 "CounterHTOff": "0,1,2,3" 3944 }, 3945 { 3946 "Offcore": "1", 3947 "EventCode": "0xB7, 0xBB", 3948 "UMask": "0x1", 3949 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS.HIT_OTHER_CORE_FWD", 3950 "Deprecated": "1", 3951 "MSRValue": "0x083C000491", 3952 "Counter": "0,1,2,3", 3953 "EventName": "OFFCORE_RESPONSE:request=ALL_DATA_RD:response=L3_MISS.HIT_OTHER_CORE_FWD", 3954 "MSRIndex": "0x1a6,0x1a7", 3955 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3956 "SampleAfterValue": "100003", 3957 "CounterHTOff": "0,1,2,3" 3958 }, 3959 { 3960 "Offcore": "1", 3961 "EventCode": "0xB7, 0xBB", 3962 "UMask": "0x1", 3963 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS.HITM_OTHER_CORE", 3964 "Deprecated": "1", 3965 "MSRValue": "0x103C000491", 3966 "Counter": "0,1,2,3", 3967 "EventName": "OFFCORE_RESPONSE:request=ALL_DATA_RD:response=L3_MISS.HITM_OTHER_CORE", 3968 "MSRIndex": "0x1a6,0x1a7", 3969 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3970 "SampleAfterValue": "100003", 3971 "CounterHTOff": "0,1,2,3" 3972 }, 3973 { 3974 "Offcore": "1", 3975 "EventCode": "0xB7, 0xBB", 3976 "UMask": "0x1", 3977 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS.ANY_SNOOP", 3978 "Deprecated": "1", 3979 "MSRValue": "0x3FBC000491", 3980 "Counter": "0,1,2,3", 3981 "EventName": "OFFCORE_RESPONSE:request=ALL_DATA_RD:response=L3_MISS.ANY_SNOOP", 3982 "MSRIndex": "0x1a6,0x1a7", 3983 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3984 "SampleAfterValue": "100003", 3985 "CounterHTOff": "0,1,2,3" 3986 }, 3987 { 3988 "Offcore": "1", 3989 "EventCode": "0xB7, 0xBB", 3990 "UMask": "0x1", 3991 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NONE", 3992 "Deprecated": "1", 3993 "MSRValue": "0x0084000122", 3994 "Counter": "0,1,2,3", 3995 "EventName": "OFFCORE_RESPONSE:request=ALL_RFO:response=L3_MISS_LOCAL_DRAM.SNOOP_NONE", 3996 "MSRIndex": "0x1a6,0x1a7", 3997 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3998 "SampleAfterValue": "100003", 3999 "CounterHTOff": "0,1,2,3" 4000 }, 4001 { 4002 "Offcore": "1", 4003 "EventCode": "0xB7, 0xBB", 4004 "UMask": "0x1", 4005 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED", 4006 "Deprecated": "1", 4007 "MSRValue": "0x0104000122", 4008 "Counter": "0,1,2,3", 4009 "EventName": "OFFCORE_RESPONSE:request=ALL_RFO:response=L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED", 4010 "MSRIndex": "0x1a6,0x1a7", 4011 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4012 "SampleAfterValue": "100003", 4013 "CounterHTOff": "0,1,2,3" 4014 }, 4015 { 4016 "Offcore": "1", 4017 "EventCode": "0xB7, 0xBB", 4018 "UMask": "0x1", 4019 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS", 4020 "Deprecated": "1", 4021 "MSRValue": "0x0204000122", 4022 "Counter": "0,1,2,3", 4023 "EventName": "OFFCORE_RESPONSE:request=ALL_RFO:response=L3_MISS_LOCAL_DRAM.SNOOP_MISS", 4024 "MSRIndex": "0x1a6,0x1a7", 4025 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4026 "SampleAfterValue": "100003", 4027 "CounterHTOff": "0,1,2,3" 4028 }, 4029 { 4030 "Offcore": "1", 4031 "EventCode": "0xB7, 0xBB", 4032 "UMask": "0x1", 4033 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD", 4034 "Deprecated": "1", 4035 "MSRValue": "0x0404000122", 4036 "Counter": "0,1,2,3", 4037 "EventName": "OFFCORE_RESPONSE:request=ALL_RFO:response=L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD", 4038 "MSRIndex": "0x1a6,0x1a7", 4039 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4040 "SampleAfterValue": "100003", 4041 "CounterHTOff": "0,1,2,3" 4042 }, 4043 { 4044 "Offcore": "1", 4045 "EventCode": "0xB7, 0xBB", 4046 "UMask": "0x1", 4047 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD", 4048 "Deprecated": "1", 4049 "MSRValue": "0x0804000122", 4050 "Counter": "0,1,2,3", 4051 "EventName": "OFFCORE_RESPONSE:request=ALL_RFO:response=L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD", 4052 "MSRIndex": "0x1a6,0x1a7", 4053 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4054 "SampleAfterValue": "100003", 4055 "CounterHTOff": "0,1,2,3" 4056 }, 4057 { 4058 "Offcore": "1", 4059 "EventCode": "0xB7, 0xBB", 4060 "UMask": "0x1", 4061 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE", 4062 "Deprecated": "1", 4063 "MSRValue": "0x1004000122", 4064 "Counter": "0,1,2,3", 4065 "EventName": "OFFCORE_RESPONSE:request=ALL_RFO:response=L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE", 4066 "MSRIndex": "0x1a6,0x1a7", 4067 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4068 "SampleAfterValue": "100003", 4069 "CounterHTOff": "0,1,2,3" 4070 }, 4071 { 4072 "Offcore": "1", 4073 "EventCode": "0xB7, 0xBB", 4074 "UMask": "0x1", 4075 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.ANY_SNOOP", 4076 "Deprecated": "1", 4077 "MSRValue": "0x3F84000122", 4078 "Counter": "0,1,2,3", 4079 "EventName": "OFFCORE_RESPONSE:request=ALL_RFO:response=L3_MISS_LOCAL_DRAM.ANY_SNOOP", 4080 "MSRIndex": "0x1a6,0x1a7", 4081 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4082 "SampleAfterValue": "100003", 4083 "CounterHTOff": "0,1,2,3" 4084 }, 4085 { 4086 "Offcore": "1", 4087 "EventCode": "0xB7, 0xBB", 4088 "UMask": "0x1", 4089 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE", 4090 "Deprecated": "1", 4091 "MSRValue": "0x0090000122", 4092 "Counter": "0,1,2,3", 4093 "EventName": "OFFCORE_RESPONSE:request=ALL_RFO:response=L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE", 4094 "MSRIndex": "0x1a6,0x1a7", 4095 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4096 "SampleAfterValue": "100003", 4097 "CounterHTOff": "0,1,2,3" 4098 }, 4099 { 4100 "Offcore": "1", 4101 "EventCode": "0xB7, 0xBB", 4102 "UMask": "0x1", 4103 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED", 4104 "Deprecated": "1", 4105 "MSRValue": "0x0110000122", 4106 "Counter": "0,1,2,3", 4107 "EventName": "OFFCORE_RESPONSE:request=ALL_RFO:response=L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED", 4108 "MSRIndex": "0x1a6,0x1a7", 4109 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4110 "SampleAfterValue": "100003", 4111 "CounterHTOff": "0,1,2,3" 4112 }, 4113 { 4114 "Offcore": "1", 4115 "EventCode": "0xB7, 0xBB", 4116 "UMask": "0x1", 4117 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS", 4118 "Deprecated": "1", 4119 "MSRValue": "0x0210000122", 4120 "Counter": "0,1,2,3", 4121 "EventName": "OFFCORE_RESPONSE:request=ALL_RFO:response=L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS", 4122 "MSRIndex": "0x1a6,0x1a7", 4123 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4124 "SampleAfterValue": "100003", 4125 "CounterHTOff": "0,1,2,3" 4126 }, 4127 { 4128 "Offcore": "1", 4129 "EventCode": "0xB7, 0xBB", 4130 "UMask": "0x1", 4131 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD", 4132 "Deprecated": "1", 4133 "MSRValue": "0x0410000122", 4134 "Counter": "0,1,2,3", 4135 "EventName": "OFFCORE_RESPONSE:request=ALL_RFO:response=L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD", 4136 "MSRIndex": "0x1a6,0x1a7", 4137 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4138 "SampleAfterValue": "100003", 4139 "CounterHTOff": "0,1,2,3" 4140 }, 4141 { 4142 "Offcore": "1", 4143 "EventCode": "0xB7, 0xBB", 4144 "UMask": "0x1", 4145 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD", 4146 "Deprecated": "1", 4147 "MSRValue": "0x0810000122", 4148 "Counter": "0,1,2,3", 4149 "EventName": "OFFCORE_RESPONSE:request=ALL_RFO:response=L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD", 4150 "MSRIndex": "0x1a6,0x1a7", 4151 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4152 "SampleAfterValue": "100003", 4153 "CounterHTOff": "0,1,2,3" 4154 }, 4155 { 4156 "Offcore": "1", 4157 "EventCode": "0xB7, 0xBB", 4158 "UMask": "0x1", 4159 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE", 4160 "Deprecated": "1", 4161 "MSRValue": "0x1010000122", 4162 "Counter": "0,1,2,3", 4163 "EventName": "OFFCORE_RESPONSE:request=ALL_RFO:response=L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE", 4164 "MSRIndex": "0x1a6,0x1a7", 4165 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4166 "SampleAfterValue": "100003", 4167 "CounterHTOff": "0,1,2,3" 4168 }, 4169 { 4170 "Offcore": "1", 4171 "EventCode": "0xB7, 0xBB", 4172 "UMask": "0x1", 4173 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP", 4174 "Deprecated": "1", 4175 "MSRValue": "0x3F90000122", 4176 "Counter": "0,1,2,3", 4177 "EventName": "OFFCORE_RESPONSE:request=ALL_RFO:response=L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP", 4178 "MSRIndex": "0x1a6,0x1a7", 4179 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4180 "SampleAfterValue": "100003", 4181 "CounterHTOff": "0,1,2,3" 4182 }, 4183 { 4184 "Offcore": "1", 4185 "EventCode": "0xB7, 0xBB", 4186 "UMask": "0x1", 4187 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS.SNOOP_NONE", 4188 "Deprecated": "1", 4189 "MSRValue": "0x00BC000122", 4190 "Counter": "0,1,2,3", 4191 "EventName": "OFFCORE_RESPONSE:request=ALL_RFO:response=L3_MISS.SNOOP_NONE", 4192 "MSRIndex": "0x1a6,0x1a7", 4193 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4194 "SampleAfterValue": "100003", 4195 "CounterHTOff": "0,1,2,3" 4196 }, 4197 { 4198 "Offcore": "1", 4199 "EventCode": "0xB7, 0xBB", 4200 "UMask": "0x1", 4201 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS.NO_SNOOP_NEEDED", 4202 "Deprecated": "1", 4203 "MSRValue": "0x013C000122", 4204 "Counter": "0,1,2,3", 4205 "EventName": "OFFCORE_RESPONSE:request=ALL_RFO:response=L3_MISS.NO_SNOOP_NEEDED", 4206 "MSRIndex": "0x1a6,0x1a7", 4207 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4208 "SampleAfterValue": "100003", 4209 "CounterHTOff": "0,1,2,3" 4210 }, 4211 { 4212 "Offcore": "1", 4213 "EventCode": "0xB7, 0xBB", 4214 "UMask": "0x1", 4215 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS.SNOOP_MISS", 4216 "Deprecated": "1", 4217 "MSRValue": "0x023C000122", 4218 "Counter": "0,1,2,3", 4219 "EventName": "OFFCORE_RESPONSE:request=ALL_RFO:response=L3_MISS.SNOOP_MISS", 4220 "MSRIndex": "0x1a6,0x1a7", 4221 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4222 "SampleAfterValue": "100003", 4223 "CounterHTOff": "0,1,2,3" 4224 }, 4225 { 4226 "Offcore": "1", 4227 "EventCode": "0xB7, 0xBB", 4228 "UMask": "0x1", 4229 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS.HIT_OTHER_CORE_NO_FWD", 4230 "Deprecated": "1", 4231 "MSRValue": "0x043C000122", 4232 "Counter": "0,1,2,3", 4233 "EventName": "OFFCORE_RESPONSE:request=ALL_RFO:response=L3_MISS.HIT_OTHER_CORE_NO_FWD", 4234 "MSRIndex": "0x1a6,0x1a7", 4235 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4236 "SampleAfterValue": "100003", 4237 "CounterHTOff": "0,1,2,3" 4238 }, 4239 { 4240 "Offcore": "1", 4241 "EventCode": "0xB7, 0xBB", 4242 "UMask": "0x1", 4243 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS.HIT_OTHER_CORE_FWD", 4244 "Deprecated": "1", 4245 "MSRValue": "0x083C000122", 4246 "Counter": "0,1,2,3", 4247 "EventName": "OFFCORE_RESPONSE:request=ALL_RFO:response=L3_MISS.HIT_OTHER_CORE_FWD", 4248 "MSRIndex": "0x1a6,0x1a7", 4249 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4250 "SampleAfterValue": "100003", 4251 "CounterHTOff": "0,1,2,3" 4252 }, 4253 { 4254 "Offcore": "1", 4255 "EventCode": "0xB7, 0xBB", 4256 "UMask": "0x1", 4257 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS.HITM_OTHER_CORE", 4258 "Deprecated": "1", 4259 "MSRValue": "0x103C000122", 4260 "Counter": "0,1,2,3", 4261 "EventName": "OFFCORE_RESPONSE:request=ALL_RFO:response=L3_MISS.HITM_OTHER_CORE", 4262 "MSRIndex": "0x1a6,0x1a7", 4263 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4264 "SampleAfterValue": "100003", 4265 "CounterHTOff": "0,1,2,3" 4266 }, 4267 { 4268 "Offcore": "1", 4269 "EventCode": "0xB7, 0xBB", 4270 "UMask": "0x1", 4271 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS.ANY_SNOOP", 4272 "Deprecated": "1", 4273 "MSRValue": "0x3FBC000122", 4274 "Counter": "0,1,2,3", 4275 "EventName": "OFFCORE_RESPONSE:request=ALL_RFO:response=L3_MISS.ANY_SNOOP", 4276 "MSRIndex": "0x1a6,0x1a7", 4277 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4278 "SampleAfterValue": "100003", 4279 "CounterHTOff": "0,1,2,3" 4280 }, 4281 { 4282 "Offcore": "1", 4283 "EventCode": "0xB7, 0xBB", 4284 "UMask": "0x1", 4285 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS_LOCAL_DRAM.SNOOP_NONE", 4286 "Deprecated": "1", 4287 "MSRValue": "0x00840007F7", 4288 "Counter": "0,1,2,3", 4289 "EventName": "OFFCORE_RESPONSE:request=ALL_READS:response=L3_MISS_LOCAL_DRAM.SNOOP_NONE", 4290 "MSRIndex": "0x1a6,0x1a7", 4291 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4292 "SampleAfterValue": "100003", 4293 "CounterHTOff": "0,1,2,3" 4294 }, 4295 { 4296 "Offcore": "1", 4297 "EventCode": "0xB7, 0xBB", 4298 "UMask": "0x1", 4299 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED", 4300 "Deprecated": "1", 4301 "MSRValue": "0x01040007F7", 4302 "Counter": "0,1,2,3", 4303 "EventName": "OFFCORE_RESPONSE:request=ALL_READS:response=L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED", 4304 "MSRIndex": "0x1a6,0x1a7", 4305 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4306 "SampleAfterValue": "100003", 4307 "CounterHTOff": "0,1,2,3" 4308 }, 4309 { 4310 "Offcore": "1", 4311 "EventCode": "0xB7, 0xBB", 4312 "UMask": "0x1", 4313 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS_LOCAL_DRAM.SNOOP_MISS", 4314 "Deprecated": "1", 4315 "MSRValue": "0x02040007F7", 4316 "Counter": "0,1,2,3", 4317 "EventName": "OFFCORE_RESPONSE:request=ALL_READS:response=L3_MISS_LOCAL_DRAM.SNOOP_MISS", 4318 "MSRIndex": "0x1a6,0x1a7", 4319 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4320 "SampleAfterValue": "100003", 4321 "CounterHTOff": "0,1,2,3" 4322 }, 4323 { 4324 "Offcore": "1", 4325 "EventCode": "0xB7, 0xBB", 4326 "UMask": "0x1", 4327 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD", 4328 "Deprecated": "1", 4329 "MSRValue": "0x04040007F7", 4330 "Counter": "0,1,2,3", 4331 "EventName": "OFFCORE_RESPONSE:request=ALL_READS:response=L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD", 4332 "MSRIndex": "0x1a6,0x1a7", 4333 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4334 "SampleAfterValue": "100003", 4335 "CounterHTOff": "0,1,2,3" 4336 }, 4337 { 4338 "Offcore": "1", 4339 "EventCode": "0xB7, 0xBB", 4340 "UMask": "0x1", 4341 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD", 4342 "Deprecated": "1", 4343 "MSRValue": "0x08040007F7", 4344 "Counter": "0,1,2,3", 4345 "EventName": "OFFCORE_RESPONSE:request=ALL_READS:response=L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD", 4346 "MSRIndex": "0x1a6,0x1a7", 4347 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4348 "SampleAfterValue": "100003", 4349 "CounterHTOff": "0,1,2,3" 4350 }, 4351 { 4352 "Offcore": "1", 4353 "EventCode": "0xB7, 0xBB", 4354 "UMask": "0x1", 4355 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE", 4356 "Deprecated": "1", 4357 "MSRValue": "0x10040007F7", 4358 "Counter": "0,1,2,3", 4359 "EventName": "OFFCORE_RESPONSE:request=ALL_READS:response=L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE", 4360 "MSRIndex": "0x1a6,0x1a7", 4361 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4362 "SampleAfterValue": "100003", 4363 "CounterHTOff": "0,1,2,3" 4364 }, 4365 { 4366 "Offcore": "1", 4367 "EventCode": "0xB7, 0xBB", 4368 "UMask": "0x1", 4369 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS_LOCAL_DRAM.ANY_SNOOP", 4370 "Deprecated": "1", 4371 "MSRValue": "0x3F840007F7", 4372 "Counter": "0,1,2,3", 4373 "EventName": "OFFCORE_RESPONSE:request=ALL_READS:response=L3_MISS_LOCAL_DRAM.ANY_SNOOP", 4374 "MSRIndex": "0x1a6,0x1a7", 4375 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4376 "SampleAfterValue": "100003", 4377 "CounterHTOff": "0,1,2,3" 4378 }, 4379 { 4380 "Offcore": "1", 4381 "EventCode": "0xB7, 0xBB", 4382 "UMask": "0x1", 4383 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE", 4384 "Deprecated": "1", 4385 "MSRValue": "0x00900007F7", 4386 "Counter": "0,1,2,3", 4387 "EventName": "OFFCORE_RESPONSE:request=ALL_READS:response=L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE", 4388 "MSRIndex": "0x1a6,0x1a7", 4389 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4390 "SampleAfterValue": "100003", 4391 "CounterHTOff": "0,1,2,3" 4392 }, 4393 { 4394 "Offcore": "1", 4395 "EventCode": "0xB7, 0xBB", 4396 "UMask": "0x1", 4397 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED", 4398 "Deprecated": "1", 4399 "MSRValue": "0x01100007F7", 4400 "Counter": "0,1,2,3", 4401 "EventName": "OFFCORE_RESPONSE:request=ALL_READS:response=L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED", 4402 "MSRIndex": "0x1a6,0x1a7", 4403 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4404 "SampleAfterValue": "100003", 4405 "CounterHTOff": "0,1,2,3" 4406 }, 4407 { 4408 "Offcore": "1", 4409 "EventCode": "0xB7, 0xBB", 4410 "UMask": "0x1", 4411 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS", 4412 "Deprecated": "1", 4413 "MSRValue": "0x02100007F7", 4414 "Counter": "0,1,2,3", 4415 "EventName": "OFFCORE_RESPONSE:request=ALL_READS:response=L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS", 4416 "MSRIndex": "0x1a6,0x1a7", 4417 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4418 "SampleAfterValue": "100003", 4419 "CounterHTOff": "0,1,2,3" 4420 }, 4421 { 4422 "Offcore": "1", 4423 "EventCode": "0xB7, 0xBB", 4424 "UMask": "0x1", 4425 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD", 4426 "Deprecated": "1", 4427 "MSRValue": "0x04100007F7", 4428 "Counter": "0,1,2,3", 4429 "EventName": "OFFCORE_RESPONSE:request=ALL_READS:response=L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD", 4430 "MSRIndex": "0x1a6,0x1a7", 4431 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4432 "SampleAfterValue": "100003", 4433 "CounterHTOff": "0,1,2,3" 4434 }, 4435 { 4436 "Offcore": "1", 4437 "EventCode": "0xB7, 0xBB", 4438 "UMask": "0x1", 4439 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD", 4440 "Deprecated": "1", 4441 "MSRValue": "0x08100007F7", 4442 "Counter": "0,1,2,3", 4443 "EventName": "OFFCORE_RESPONSE:request=ALL_READS:response=L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD", 4444 "MSRIndex": "0x1a6,0x1a7", 4445 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4446 "SampleAfterValue": "100003", 4447 "CounterHTOff": "0,1,2,3" 4448 }, 4449 { 4450 "Offcore": "1", 4451 "EventCode": "0xB7, 0xBB", 4452 "UMask": "0x1", 4453 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE", 4454 "Deprecated": "1", 4455 "MSRValue": "0x10100007F7", 4456 "Counter": "0,1,2,3", 4457 "EventName": "OFFCORE_RESPONSE:request=ALL_READS:response=L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE", 4458 "MSRIndex": "0x1a6,0x1a7", 4459 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4460 "SampleAfterValue": "100003", 4461 "CounterHTOff": "0,1,2,3" 4462 }, 4463 { 4464 "Offcore": "1", 4465 "EventCode": "0xB7, 0xBB", 4466 "UMask": "0x1", 4467 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP", 4468 "Deprecated": "1", 4469 "MSRValue": "0x3F900007F7", 4470 "Counter": "0,1,2,3", 4471 "EventName": "OFFCORE_RESPONSE:request=ALL_READS:response=L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP", 4472 "MSRIndex": "0x1a6,0x1a7", 4473 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4474 "SampleAfterValue": "100003", 4475 "CounterHTOff": "0,1,2,3" 4476 }, 4477 { 4478 "Offcore": "1", 4479 "EventCode": "0xB7, 0xBB", 4480 "UMask": "0x1", 4481 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS.SNOOP_NONE", 4482 "Deprecated": "1", 4483 "MSRValue": "0x00BC0007F7", 4484 "Counter": "0,1,2,3", 4485 "EventName": "OFFCORE_RESPONSE:request=ALL_READS:response=L3_MISS.SNOOP_NONE", 4486 "MSRIndex": "0x1a6,0x1a7", 4487 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4488 "SampleAfterValue": "100003", 4489 "CounterHTOff": "0,1,2,3" 4490 }, 4491 { 4492 "Offcore": "1", 4493 "EventCode": "0xB7, 0xBB", 4494 "UMask": "0x1", 4495 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS.NO_SNOOP_NEEDED", 4496 "Deprecated": "1", 4497 "MSRValue": "0x013C0007F7", 4498 "Counter": "0,1,2,3", 4499 "EventName": "OFFCORE_RESPONSE:request=ALL_READS:response=L3_MISS.NO_SNOOP_NEEDED", 4500 "MSRIndex": "0x1a6,0x1a7", 4501 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4502 "SampleAfterValue": "100003", 4503 "CounterHTOff": "0,1,2,3" 4504 }, 4505 { 4506 "Offcore": "1", 4507 "EventCode": "0xB7, 0xBB", 4508 "UMask": "0x1", 4509 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS.SNOOP_MISS", 4510 "Deprecated": "1", 4511 "MSRValue": "0x023C0007F7", 4512 "Counter": "0,1,2,3", 4513 "EventName": "OFFCORE_RESPONSE:request=ALL_READS:response=L3_MISS.SNOOP_MISS", 4514 "MSRIndex": "0x1a6,0x1a7", 4515 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4516 "SampleAfterValue": "100003", 4517 "CounterHTOff": "0,1,2,3" 4518 }, 4519 { 4520 "Offcore": "1", 4521 "EventCode": "0xB7, 0xBB", 4522 "UMask": "0x1", 4523 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS.HIT_OTHER_CORE_NO_FWD", 4524 "Deprecated": "1", 4525 "MSRValue": "0x043C0007F7", 4526 "Counter": "0,1,2,3", 4527 "EventName": "OFFCORE_RESPONSE:request=ALL_READS:response=L3_MISS.HIT_OTHER_CORE_NO_FWD", 4528 "MSRIndex": "0x1a6,0x1a7", 4529 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4530 "SampleAfterValue": "100003", 4531 "CounterHTOff": "0,1,2,3" 4532 }, 4533 { 4534 "Offcore": "1", 4535 "EventCode": "0xB7, 0xBB", 4536 "UMask": "0x1", 4537 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS.HIT_OTHER_CORE_FWD", 4538 "Deprecated": "1", 4539 "MSRValue": "0x083C0007F7", 4540 "Counter": "0,1,2,3", 4541 "EventName": "OFFCORE_RESPONSE:request=ALL_READS:response=L3_MISS.HIT_OTHER_CORE_FWD", 4542 "MSRIndex": "0x1a6,0x1a7", 4543 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4544 "SampleAfterValue": "100003", 4545 "CounterHTOff": "0,1,2,3" 4546 }, 4547 { 4548 "Offcore": "1", 4549 "EventCode": "0xB7, 0xBB", 4550 "UMask": "0x1", 4551 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS.HITM_OTHER_CORE", 4552 "Deprecated": "1", 4553 "MSRValue": "0x103C0007F7", 4554 "Counter": "0,1,2,3", 4555 "EventName": "OFFCORE_RESPONSE:request=ALL_READS:response=L3_MISS.HITM_OTHER_CORE", 4556 "MSRIndex": "0x1a6,0x1a7", 4557 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4558 "SampleAfterValue": "100003", 4559 "CounterHTOff": "0,1,2,3" 4560 }, 4561 { 4562 "Offcore": "1", 4563 "EventCode": "0xB7, 0xBB", 4564 "UMask": "0x1", 4565 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS.ANY_SNOOP", 4566 "Deprecated": "1", 4567 "MSRValue": "0x3FBC0007F7", 4568 "Counter": "0,1,2,3", 4569 "EventName": "OFFCORE_RESPONSE:request=ALL_READS:response=L3_MISS.ANY_SNOOP", 4570 "MSRIndex": "0x1a6,0x1a7", 4571 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4572 "SampleAfterValue": "100003", 4573 "CounterHTOff": "0,1,2,3" 4574 }, 4575 { 4576 "Offcore": "1", 4577 "EventCode": "0xB7, 0xBB", 4578 "UMask": "0x1", 4579 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", 4580 "Deprecated": "1", 4581 "MSRValue": "0x063B800001", 4582 "Counter": "0,1,2,3", 4583 "EventName": "OFFCORE_RESPONSE:request=DEMAND_DATA_RD:response=L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", 4584 "MSRIndex": "0x1a6,0x1a7", 4585 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4586 "SampleAfterValue": "100003", 4587 "CounterHTOff": "0,1,2,3" 4588 }, 4589 { 4590 "Offcore": "1", 4591 "EventCode": "0xB7, 0xBB", 4592 "UMask": "0x1", 4593 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", 4594 "Deprecated": "1", 4595 "MSRValue": "0x0604000001", 4596 "Counter": "0,1,2,3", 4597 "EventName": "OFFCORE_RESPONSE:request=DEMAND_DATA_RD:response=L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", 4598 "MSRIndex": "0x1a6,0x1a7", 4599 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4600 "SampleAfterValue": "100003", 4601 "CounterHTOff": "0,1,2,3" 4602 }, 4603 { 4604 "Offcore": "1", 4605 "EventCode": "0xB7, 0xBB", 4606 "UMask": "0x1", 4607 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", 4608 "Deprecated": "1", 4609 "MSRValue": "0x063B800002", 4610 "Counter": "0,1,2,3", 4611 "EventName": "OFFCORE_RESPONSE:request=DEMAND_RFO:response=L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", 4612 "MSRIndex": "0x1a6,0x1a7", 4613 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4614 "SampleAfterValue": "100003", 4615 "CounterHTOff": "0,1,2,3" 4616 }, 4617 { 4618 "Offcore": "1", 4619 "EventCode": "0xB7, 0xBB", 4620 "UMask": "0x1", 4621 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", 4622 "Deprecated": "1", 4623 "MSRValue": "0x0604000002", 4624 "Counter": "0,1,2,3", 4625 "EventName": "OFFCORE_RESPONSE:request=DEMAND_RFO:response=L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", 4626 "MSRIndex": "0x1a6,0x1a7", 4627 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4628 "SampleAfterValue": "100003", 4629 "CounterHTOff": "0,1,2,3" 4630 }, 4631 { 4632 "Offcore": "1", 4633 "EventCode": "0xB7, 0xBB", 4634 "UMask": "0x1", 4635 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", 4636 "Deprecated": "1", 4637 "MSRValue": "0x063B800004", 4638 "Counter": "0,1,2,3", 4639 "EventName": "OFFCORE_RESPONSE:request=DEMAND_CODE_RD:response=L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", 4640 "MSRIndex": "0x1a6,0x1a7", 4641 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4642 "SampleAfterValue": "100003", 4643 "CounterHTOff": "0,1,2,3" 4644 }, 4645 { 4646 "Offcore": "1", 4647 "EventCode": "0xB7, 0xBB", 4648 "UMask": "0x1", 4649 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", 4650 "Deprecated": "1", 4651 "MSRValue": "0x0604000004", 4652 "Counter": "0,1,2,3", 4653 "EventName": "OFFCORE_RESPONSE:request=DEMAND_CODE_RD:response=L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", 4654 "MSRIndex": "0x1a6,0x1a7", 4655 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4656 "SampleAfterValue": "100003", 4657 "CounterHTOff": "0,1,2,3" 4658 }, 4659 { 4660 "Offcore": "1", 4661 "EventCode": "0xB7, 0xBB", 4662 "UMask": "0x1", 4663 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", 4664 "Deprecated": "1", 4665 "MSRValue": "0x063B800010", 4666 "Counter": "0,1,2,3", 4667 "EventName": "OFFCORE_RESPONSE:request=PF_L2_DATA_RD:response=L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", 4668 "MSRIndex": "0x1a6,0x1a7", 4669 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4670 "SampleAfterValue": "100003", 4671 "CounterHTOff": "0,1,2,3" 4672 }, 4673 { 4674 "Offcore": "1", 4675 "EventCode": "0xB7, 0xBB", 4676 "UMask": "0x1", 4677 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", 4678 "Deprecated": "1", 4679 "MSRValue": "0x0604000010", 4680 "Counter": "0,1,2,3", 4681 "EventName": "OFFCORE_RESPONSE:request=PF_L2_DATA_RD:response=L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", 4682 "MSRIndex": "0x1a6,0x1a7", 4683 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4684 "SampleAfterValue": "100003", 4685 "CounterHTOff": "0,1,2,3" 4686 }, 4687 { 4688 "Offcore": "1", 4689 "EventCode": "0xB7, 0xBB", 4690 "UMask": "0x1", 4691 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", 4692 "Deprecated": "1", 4693 "MSRValue": "0x063B800020", 4694 "Counter": "0,1,2,3", 4695 "EventName": "OFFCORE_RESPONSE:request=PF_L2_RFO:response=L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", 4696 "MSRIndex": "0x1a6,0x1a7", 4697 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4698 "SampleAfterValue": "100003", 4699 "CounterHTOff": "0,1,2,3" 4700 }, 4701 { 4702 "Offcore": "1", 4703 "EventCode": "0xB7, 0xBB", 4704 "UMask": "0x1", 4705 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", 4706 "Deprecated": "1", 4707 "MSRValue": "0x0604000020", 4708 "Counter": "0,1,2,3", 4709 "EventName": "OFFCORE_RESPONSE:request=PF_L2_RFO:response=L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", 4710 "MSRIndex": "0x1a6,0x1a7", 4711 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4712 "SampleAfterValue": "100003", 4713 "CounterHTOff": "0,1,2,3" 4714 }, 4715 { 4716 "Offcore": "1", 4717 "EventCode": "0xB7, 0xBB", 4718 "UMask": "0x1", 4719 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", 4720 "Deprecated": "1", 4721 "MSRValue": "0x063B800080", 4722 "Counter": "0,1,2,3", 4723 "EventName": "OFFCORE_RESPONSE:request=PF_L3_DATA_RD:response=L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", 4724 "MSRIndex": "0x1a6,0x1a7", 4725 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4726 "SampleAfterValue": "100003", 4727 "CounterHTOff": "0,1,2,3" 4728 }, 4729 { 4730 "Offcore": "1", 4731 "EventCode": "0xB7, 0xBB", 4732 "UMask": "0x1", 4733 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", 4734 "Deprecated": "1", 4735 "MSRValue": "0x0604000080", 4736 "Counter": "0,1,2,3", 4737 "EventName": "OFFCORE_RESPONSE:request=PF_L3_DATA_RD:response=L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", 4738 "MSRIndex": "0x1a6,0x1a7", 4739 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4740 "SampleAfterValue": "100003", 4741 "CounterHTOff": "0,1,2,3" 4742 }, 4743 { 4744 "Offcore": "1", 4745 "EventCode": "0xB7, 0xBB", 4746 "UMask": "0x1", 4747 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", 4748 "Deprecated": "1", 4749 "MSRValue": "0x063B800100", 4750 "Counter": "0,1,2,3", 4751 "EventName": "OFFCORE_RESPONSE:request=PF_L3_RFO:response=L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", 4752 "MSRIndex": "0x1a6,0x1a7", 4753 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4754 "SampleAfterValue": "100003", 4755 "CounterHTOff": "0,1,2,3" 4756 }, 4757 { 4758 "Offcore": "1", 4759 "EventCode": "0xB7, 0xBB", 4760 "UMask": "0x1", 4761 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", 4762 "Deprecated": "1", 4763 "MSRValue": "0x0604000100", 4764 "Counter": "0,1,2,3", 4765 "EventName": "OFFCORE_RESPONSE:request=PF_L3_RFO:response=L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", 4766 "MSRIndex": "0x1a6,0x1a7", 4767 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4768 "SampleAfterValue": "100003", 4769 "CounterHTOff": "0,1,2,3" 4770 }, 4771 { 4772 "Offcore": "1", 4773 "EventCode": "0xB7, 0xBB", 4774 "UMask": "0x1", 4775 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", 4776 "Deprecated": "1", 4777 "MSRValue": "0x063B800400", 4778 "Counter": "0,1,2,3", 4779 "EventName": "OFFCORE_RESPONSE:request=PF_L1D_AND_SW:response=L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", 4780 "MSRIndex": "0x1a6,0x1a7", 4781 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4782 "SampleAfterValue": "100003", 4783 "CounterHTOff": "0,1,2,3" 4784 }, 4785 { 4786 "Offcore": "1", 4787 "EventCode": "0xB7, 0xBB", 4788 "UMask": "0x1", 4789 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", 4790 "Deprecated": "1", 4791 "MSRValue": "0x0604000400", 4792 "Counter": "0,1,2,3", 4793 "EventName": "OFFCORE_RESPONSE:request=PF_L1D_AND_SW:response=L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", 4794 "MSRIndex": "0x1a6,0x1a7", 4795 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4796 "SampleAfterValue": "100003", 4797 "CounterHTOff": "0,1,2,3" 4798 }, 4799 { 4800 "Offcore": "1", 4801 "EventCode": "0xB7, 0xBB", 4802 "UMask": "0x1", 4803 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.OTHER.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", 4804 "Deprecated": "1", 4805 "MSRValue": "0x063B808000", 4806 "Counter": "0,1,2,3", 4807 "EventName": "OFFCORE_RESPONSE:request=OTHER:response=L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", 4808 "MSRIndex": "0x1a6,0x1a7", 4809 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4810 "SampleAfterValue": "100003", 4811 "CounterHTOff": "0,1,2,3" 4812 }, 4813 { 4814 "Offcore": "1", 4815 "EventCode": "0xB7, 0xBB", 4816 "UMask": "0x1", 4817 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.OTHER.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", 4818 "Deprecated": "1", 4819 "MSRValue": "0x0604008000", 4820 "Counter": "0,1,2,3", 4821 "EventName": "OFFCORE_RESPONSE:request=OTHER:response=L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", 4822 "MSRIndex": "0x1a6,0x1a7", 4823 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4824 "SampleAfterValue": "100003", 4825 "CounterHTOff": "0,1,2,3" 4826 }, 4827 { 4828 "Offcore": "1", 4829 "EventCode": "0xB7, 0xBB", 4830 "UMask": "0x1", 4831 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", 4832 "Deprecated": "1", 4833 "MSRValue": "0x063B800490", 4834 "Counter": "0,1,2,3", 4835 "EventName": "OFFCORE_RESPONSE:request=ALL_PF_DATA_RD:response=L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", 4836 "MSRIndex": "0x1a6,0x1a7", 4837 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4838 "SampleAfterValue": "100003", 4839 "CounterHTOff": "0,1,2,3" 4840 }, 4841 { 4842 "Offcore": "1", 4843 "EventCode": "0xB7, 0xBB", 4844 "UMask": "0x1", 4845 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", 4846 "Deprecated": "1", 4847 "MSRValue": "0x0604000490", 4848 "Counter": "0,1,2,3", 4849 "EventName": "OFFCORE_RESPONSE:request=ALL_PF_DATA_RD:response=L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", 4850 "MSRIndex": "0x1a6,0x1a7", 4851 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4852 "SampleAfterValue": "100003", 4853 "CounterHTOff": "0,1,2,3" 4854 }, 4855 { 4856 "Offcore": "1", 4857 "EventCode": "0xB7, 0xBB", 4858 "UMask": "0x1", 4859 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", 4860 "Deprecated": "1", 4861 "MSRValue": "0x063B800120", 4862 "Counter": "0,1,2,3", 4863 "EventName": "OFFCORE_RESPONSE:request=ALL_PF_RFO:response=L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", 4864 "MSRIndex": "0x1a6,0x1a7", 4865 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4866 "SampleAfterValue": "100003", 4867 "CounterHTOff": "0,1,2,3" 4868 }, 4869 { 4870 "Offcore": "1", 4871 "EventCode": "0xB7, 0xBB", 4872 "UMask": "0x1", 4873 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", 4874 "Deprecated": "1", 4875 "MSRValue": "0x0604000120", 4876 "Counter": "0,1,2,3", 4877 "EventName": "OFFCORE_RESPONSE:request=ALL_PF_RFO:response=L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", 4878 "MSRIndex": "0x1a6,0x1a7", 4879 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4880 "SampleAfterValue": "100003", 4881 "CounterHTOff": "0,1,2,3" 4882 }, 4883 { 4884 "Offcore": "1", 4885 "EventCode": "0xB7, 0xBB", 4886 "UMask": "0x1", 4887 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", 4888 "Deprecated": "1", 4889 "MSRValue": "0x063B800491", 4890 "Counter": "0,1,2,3", 4891 "EventName": "OFFCORE_RESPONSE:request=ALL_DATA_RD:response=L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", 4892 "MSRIndex": "0x1a6,0x1a7", 4893 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4894 "SampleAfterValue": "100003", 4895 "CounterHTOff": "0,1,2,3" 4896 }, 4897 { 4898 "Offcore": "1", 4899 "EventCode": "0xB7, 0xBB", 4900 "UMask": "0x1", 4901 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", 4902 "Deprecated": "1", 4903 "MSRValue": "0x0604000491", 4904 "Counter": "0,1,2,3", 4905 "EventName": "OFFCORE_RESPONSE:request=ALL_DATA_RD:response=L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", 4906 "MSRIndex": "0x1a6,0x1a7", 4907 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4908 "SampleAfterValue": "100003", 4909 "CounterHTOff": "0,1,2,3" 4910 }, 4911 { 4912 "Offcore": "1", 4913 "EventCode": "0xB7, 0xBB", 4914 "UMask": "0x1", 4915 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", 4916 "Deprecated": "1", 4917 "MSRValue": "0x063B800122", 4918 "Counter": "0,1,2,3", 4919 "EventName": "OFFCORE_RESPONSE:request=ALL_RFO:response=L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", 4920 "MSRIndex": "0x1a6,0x1a7", 4921 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4922 "SampleAfterValue": "100003", 4923 "CounterHTOff": "0,1,2,3" 4924 }, 4925 { 4926 "Offcore": "1", 4927 "EventCode": "0xB7, 0xBB", 4928 "UMask": "0x1", 4929 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", 4930 "Deprecated": "1", 4931 "MSRValue": "0x0604000122", 4932 "Counter": "0,1,2,3", 4933 "EventName": "OFFCORE_RESPONSE:request=ALL_RFO:response=L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", 4934 "MSRIndex": "0x1a6,0x1a7", 4935 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4936 "SampleAfterValue": "100003", 4937 "CounterHTOff": "0,1,2,3" 4938 }, 4939 { 4940 "Offcore": "1", 4941 "EventCode": "0xB7, 0xBB", 4942 "UMask": "0x1", 4943 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", 4944 "Deprecated": "1", 4945 "MSRValue": "0x063B8007F7", 4946 "Counter": "0,1,2,3", 4947 "EventName": "OFFCORE_RESPONSE:request=ALL_READS:response=L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", 4948 "MSRIndex": "0x1a6,0x1a7", 4949 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4950 "SampleAfterValue": "100003", 4951 "CounterHTOff": "0,1,2,3" 4952 }, 4953 { 4954 "Offcore": "1", 4955 "EventCode": "0xB7, 0xBB", 4956 "UMask": "0x1", 4957 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", 4958 "Deprecated": "1", 4959 "MSRValue": "0x06040007F7", 4960 "Counter": "0,1,2,3", 4961 "EventName": "OFFCORE_RESPONSE:request=ALL_READS:response=L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", 4962 "MSRIndex": "0x1a6,0x1a7", 4963 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4964 "SampleAfterValue": "100003", 4965 "CounterHTOff": "0,1,2,3" 4966 }, 4967 { 4968 "Offcore": "1", 4969 "EventCode": "0xB7, 0xBB", 4970 "UMask": "0x1", 4971 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS.REMOTE_HITM", 4972 "Deprecated": "1", 4973 "MSRValue": "0x103FC00001", 4974 "Counter": "0,1,2,3", 4975 "EventName": "OFFCORE_RESPONSE:request=DEMAND_DATA_RD:response=L3_MISS.REMOTE_HITM", 4976 "MSRIndex": "0x1a6,0x1a7", 4977 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4978 "SampleAfterValue": "100003", 4979 "CounterHTOff": "0,1,2,3" 4980 }, 4981 { 4982 "Offcore": "1", 4983 "EventCode": "0xB7, 0xBB", 4984 "UMask": "0x1", 4985 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS.REMOTE_HITM", 4986 "Deprecated": "1", 4987 "MSRValue": "0x103FC00002", 4988 "Counter": "0,1,2,3", 4989 "EventName": "OFFCORE_RESPONSE:request=DEMAND_RFO:response=L3_MISS.REMOTE_HITM", 4990 "MSRIndex": "0x1a6,0x1a7", 4991 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4992 "SampleAfterValue": "100003", 4993 "CounterHTOff": "0,1,2,3" 4994 }, 4995 { 4996 "Offcore": "1", 4997 "EventCode": "0xB7, 0xBB", 4998 "UMask": "0x1", 4999 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS.REMOTE_HITM", 5000 "Deprecated": "1", 5001 "MSRValue": "0x103FC00004", 5002 "Counter": "0,1,2,3", 5003 "EventName": "OFFCORE_RESPONSE:request=DEMAND_CODE_RD:response=L3_MISS.REMOTE_HITM", 5004 "MSRIndex": "0x1a6,0x1a7", 5005 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5006 "SampleAfterValue": "100003", 5007 "CounterHTOff": "0,1,2,3" 5008 }, 5009 { 5010 "Offcore": "1", 5011 "EventCode": "0xB7, 0xBB", 5012 "UMask": "0x1", 5013 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS.REMOTE_HITM", 5014 "Deprecated": "1", 5015 "MSRValue": "0x103FC00010", 5016 "Counter": "0,1,2,3", 5017 "EventName": "OFFCORE_RESPONSE:request=PF_L2_DATA_RD:response=L3_MISS.REMOTE_HITM", 5018 "MSRIndex": "0x1a6,0x1a7", 5019 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5020 "SampleAfterValue": "100003", 5021 "CounterHTOff": "0,1,2,3" 5022 }, 5023 { 5024 "Offcore": "1", 5025 "EventCode": "0xB7, 0xBB", 5026 "UMask": "0x1", 5027 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS.REMOTE_HITM", 5028 "Deprecated": "1", 5029 "MSRValue": "0x103FC00020", 5030 "Counter": "0,1,2,3", 5031 "EventName": "OFFCORE_RESPONSE:request=PF_L2_RFO:response=L3_MISS.REMOTE_HITM", 5032 "MSRIndex": "0x1a6,0x1a7", 5033 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5034 "SampleAfterValue": "100003", 5035 "CounterHTOff": "0,1,2,3" 5036 }, 5037 { 5038 "Offcore": "1", 5039 "EventCode": "0xB7, 0xBB", 5040 "UMask": "0x1", 5041 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS.REMOTE_HITM", 5042 "Deprecated": "1", 5043 "MSRValue": "0x103FC00080", 5044 "Counter": "0,1,2,3", 5045 "EventName": "OFFCORE_RESPONSE:request=PF_L3_DATA_RD:response=L3_MISS.REMOTE_HITM", 5046 "MSRIndex": "0x1a6,0x1a7", 5047 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5048 "SampleAfterValue": "100003", 5049 "CounterHTOff": "0,1,2,3" 5050 }, 5051 { 5052 "Offcore": "1", 5053 "EventCode": "0xB7, 0xBB", 5054 "UMask": "0x1", 5055 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS.REMOTE_HITM", 5056 "Deprecated": "1", 5057 "MSRValue": "0x103FC00100", 5058 "Counter": "0,1,2,3", 5059 "EventName": "OFFCORE_RESPONSE:request=PF_L3_RFO:response=L3_MISS.REMOTE_HITM", 5060 "MSRIndex": "0x1a6,0x1a7", 5061 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5062 "SampleAfterValue": "100003", 5063 "CounterHTOff": "0,1,2,3" 5064 }, 5065 { 5066 "Offcore": "1", 5067 "EventCode": "0xB7, 0xBB", 5068 "UMask": "0x1", 5069 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS.REMOTE_HITM", 5070 "Deprecated": "1", 5071 "MSRValue": "0x103FC00400", 5072 "Counter": "0,1,2,3", 5073 "EventName": "OFFCORE_RESPONSE:request=PF_L1D_AND_SW:response=L3_MISS.REMOTE_HITM", 5074 "MSRIndex": "0x1a6,0x1a7", 5075 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5076 "SampleAfterValue": "100003", 5077 "CounterHTOff": "0,1,2,3" 5078 }, 5079 { 5080 "Offcore": "1", 5081 "EventCode": "0xB7, 0xBB", 5082 "UMask": "0x1", 5083 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.OTHER.L3_MISS.REMOTE_HITM", 5084 "Deprecated": "1", 5085 "MSRValue": "0x103FC08000", 5086 "Counter": "0,1,2,3", 5087 "EventName": "OFFCORE_RESPONSE:request=OTHER:response=L3_MISS.REMOTE_HITM", 5088 "MSRIndex": "0x1a6,0x1a7", 5089 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5090 "SampleAfterValue": "100003", 5091 "CounterHTOff": "0,1,2,3" 5092 }, 5093 { 5094 "Offcore": "1", 5095 "EventCode": "0xB7, 0xBB", 5096 "UMask": "0x1", 5097 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS.REMOTE_HITM", 5098 "Deprecated": "1", 5099 "MSRValue": "0x103FC00490", 5100 "Counter": "0,1,2,3", 5101 "EventName": "OFFCORE_RESPONSE:request=ALL_PF_DATA_RD:response=L3_MISS.REMOTE_HITM", 5102 "MSRIndex": "0x1a6,0x1a7", 5103 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5104 "SampleAfterValue": "100003", 5105 "CounterHTOff": "0,1,2,3" 5106 }, 5107 { 5108 "Offcore": "1", 5109 "EventCode": "0xB7, 0xBB", 5110 "UMask": "0x1", 5111 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS.REMOTE_HITM", 5112 "Deprecated": "1", 5113 "MSRValue": "0x103FC00120", 5114 "Counter": "0,1,2,3", 5115 "EventName": "OFFCORE_RESPONSE:request=ALL_PF_RFO:response=L3_MISS.REMOTE_HITM", 5116 "MSRIndex": "0x1a6,0x1a7", 5117 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5118 "SampleAfterValue": "100003", 5119 "CounterHTOff": "0,1,2,3" 5120 }, 5121 { 5122 "Offcore": "1", 5123 "EventCode": "0xB7, 0xBB", 5124 "UMask": "0x1", 5125 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS.REMOTE_HITM", 5126 "Deprecated": "1", 5127 "MSRValue": "0x103FC00491", 5128 "Counter": "0,1,2,3", 5129 "EventName": "OFFCORE_RESPONSE:request=ALL_DATA_RD:response=L3_MISS.REMOTE_HITM", 5130 "MSRIndex": "0x1a6,0x1a7", 5131 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5132 "SampleAfterValue": "100003", 5133 "CounterHTOff": "0,1,2,3" 5134 }, 5135 { 5136 "Offcore": "1", 5137 "EventCode": "0xB7, 0xBB", 5138 "UMask": "0x1", 5139 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS.REMOTE_HITM", 5140 "Deprecated": "1", 5141 "MSRValue": "0x103FC00122", 5142 "Counter": "0,1,2,3", 5143 "EventName": "OFFCORE_RESPONSE:request=ALL_RFO:response=L3_MISS.REMOTE_HITM", 5144 "MSRIndex": "0x1a6,0x1a7", 5145 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5146 "SampleAfterValue": "100003", 5147 "CounterHTOff": "0,1,2,3" 5148 }, 5149 { 5150 "Offcore": "1", 5151 "EventCode": "0xB7, 0xBB", 5152 "UMask": "0x1", 5153 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS.REMOTE_HITM", 5154 "Deprecated": "1", 5155 "MSRValue": "0x103FC007F7", 5156 "Counter": "0,1,2,3", 5157 "EventName": "OFFCORE_RESPONSE:request=ALL_READS:response=L3_MISS.REMOTE_HITM", 5158 "MSRIndex": "0x1a6,0x1a7", 5159 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5160 "SampleAfterValue": "100003", 5161 "CounterHTOff": "0,1,2,3" 5162 }, 5163 { 5164 "Offcore": "1", 5165 "EventCode": "0xB7, 0xBB", 5166 "UMask": "0x1", 5167 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS.REMOTE_HIT_FORWARD", 5168 "Deprecated": "1", 5169 "MSRValue": "0x083FC00001", 5170 "Counter": "0,1,2,3", 5171 "EventName": "OFFCORE_RESPONSE:request=DEMAND_DATA_RD:response=L3_MISS.REMOTE_HIT_FORWARD", 5172 "MSRIndex": "0x1a6,0x1a7", 5173 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5174 "SampleAfterValue": "100003", 5175 "CounterHTOff": "0,1,2,3" 5176 }, 5177 { 5178 "Offcore": "1", 5179 "EventCode": "0xB7, 0xBB", 5180 "UMask": "0x1", 5181 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS.REMOTE_HIT_FORWARD", 5182 "Deprecated": "1", 5183 "MSRValue": "0x083FC00002", 5184 "Counter": "0,1,2,3", 5185 "EventName": "OFFCORE_RESPONSE:request=DEMAND_RFO:response=L3_MISS.REMOTE_HIT_FORWARD", 5186 "MSRIndex": "0x1a6,0x1a7", 5187 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5188 "SampleAfterValue": "100003", 5189 "CounterHTOff": "0,1,2,3" 5190 }, 5191 { 5192 "Offcore": "1", 5193 "EventCode": "0xB7, 0xBB", 5194 "UMask": "0x1", 5195 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS.REMOTE_HIT_FORWARD", 5196 "Deprecated": "1", 5197 "MSRValue": "0x083FC00004", 5198 "Counter": "0,1,2,3", 5199 "EventName": "OFFCORE_RESPONSE:request=DEMAND_CODE_RD:response=L3_MISS.REMOTE_HIT_FORWARD", 5200 "MSRIndex": "0x1a6,0x1a7", 5201 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5202 "SampleAfterValue": "100003", 5203 "CounterHTOff": "0,1,2,3" 5204 }, 5205 { 5206 "Offcore": "1", 5207 "EventCode": "0xB7, 0xBB", 5208 "UMask": "0x1", 5209 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS.REMOTE_HIT_FORWARD", 5210 "Deprecated": "1", 5211 "MSRValue": "0x083FC00010", 5212 "Counter": "0,1,2,3", 5213 "EventName": "OFFCORE_RESPONSE:request=PF_L2_DATA_RD:response=L3_MISS.REMOTE_HIT_FORWARD", 5214 "MSRIndex": "0x1a6,0x1a7", 5215 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5216 "SampleAfterValue": "100003", 5217 "CounterHTOff": "0,1,2,3" 5218 }, 5219 { 5220 "Offcore": "1", 5221 "EventCode": "0xB7, 0xBB", 5222 "UMask": "0x1", 5223 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS.REMOTE_HIT_FORWARD", 5224 "Deprecated": "1", 5225 "MSRValue": "0x083FC00020", 5226 "Counter": "0,1,2,3", 5227 "EventName": "OFFCORE_RESPONSE:request=PF_L2_RFO:response=L3_MISS.REMOTE_HIT_FORWARD", 5228 "MSRIndex": "0x1a6,0x1a7", 5229 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5230 "SampleAfterValue": "100003", 5231 "CounterHTOff": "0,1,2,3" 5232 }, 5233 { 5234 "Offcore": "1", 5235 "EventCode": "0xB7, 0xBB", 5236 "UMask": "0x1", 5237 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS.REMOTE_HIT_FORWARD", 5238 "Deprecated": "1", 5239 "MSRValue": "0x083FC00080", 5240 "Counter": "0,1,2,3", 5241 "EventName": "OFFCORE_RESPONSE:request=PF_L3_DATA_RD:response=L3_MISS.REMOTE_HIT_FORWARD", 5242 "MSRIndex": "0x1a6,0x1a7", 5243 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5244 "SampleAfterValue": "100003", 5245 "CounterHTOff": "0,1,2,3" 5246 }, 5247 { 5248 "Offcore": "1", 5249 "EventCode": "0xB7, 0xBB", 5250 "UMask": "0x1", 5251 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS.REMOTE_HIT_FORWARD", 5252 "Deprecated": "1", 5253 "MSRValue": "0x083FC00100", 5254 "Counter": "0,1,2,3", 5255 "EventName": "OFFCORE_RESPONSE:request=PF_L3_RFO:response=L3_MISS.REMOTE_HIT_FORWARD", 5256 "MSRIndex": "0x1a6,0x1a7", 5257 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5258 "SampleAfterValue": "100003", 5259 "CounterHTOff": "0,1,2,3" 5260 }, 5261 { 5262 "Offcore": "1", 5263 "EventCode": "0xB7, 0xBB", 5264 "UMask": "0x1", 5265 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS.REMOTE_HIT_FORWARD", 5266 "Deprecated": "1", 5267 "MSRValue": "0x083FC00400", 5268 "Counter": "0,1,2,3", 5269 "EventName": "OFFCORE_RESPONSE:request=PF_L1D_AND_SW:response=L3_MISS.REMOTE_HIT_FORWARD", 5270 "MSRIndex": "0x1a6,0x1a7", 5271 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5272 "SampleAfterValue": "100003", 5273 "CounterHTOff": "0,1,2,3" 5274 }, 5275 { 5276 "Offcore": "1", 5277 "EventCode": "0xB7, 0xBB", 5278 "UMask": "0x1", 5279 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.OTHER.L3_MISS.REMOTE_HIT_FORWARD", 5280 "Deprecated": "1", 5281 "MSRValue": "0x083FC08000", 5282 "Counter": "0,1,2,3", 5283 "EventName": "OFFCORE_RESPONSE:request=OTHER:response=L3_MISS.REMOTE_HIT_FORWARD", 5284 "MSRIndex": "0x1a6,0x1a7", 5285 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5286 "SampleAfterValue": "100003", 5287 "CounterHTOff": "0,1,2,3" 5288 }, 5289 { 5290 "Offcore": "1", 5291 "EventCode": "0xB7, 0xBB", 5292 "UMask": "0x1", 5293 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS.REMOTE_HIT_FORWARD", 5294 "Deprecated": "1", 5295 "MSRValue": "0x083FC00490", 5296 "Counter": "0,1,2,3", 5297 "EventName": "OFFCORE_RESPONSE:request=ALL_PF_DATA_RD:response=L3_MISS.REMOTE_HIT_FORWARD", 5298 "MSRIndex": "0x1a6,0x1a7", 5299 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5300 "SampleAfterValue": "100003", 5301 "CounterHTOff": "0,1,2,3" 5302 }, 5303 { 5304 "Offcore": "1", 5305 "EventCode": "0xB7, 0xBB", 5306 "UMask": "0x1", 5307 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS.REMOTE_HIT_FORWARD", 5308 "Deprecated": "1", 5309 "MSRValue": "0x083FC00120", 5310 "Counter": "0,1,2,3", 5311 "EventName": "OFFCORE_RESPONSE:request=ALL_PF_RFO:response=L3_MISS.REMOTE_HIT_FORWARD", 5312 "MSRIndex": "0x1a6,0x1a7", 5313 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5314 "SampleAfterValue": "100003", 5315 "CounterHTOff": "0,1,2,3" 5316 }, 5317 { 5318 "Offcore": "1", 5319 "EventCode": "0xB7, 0xBB", 5320 "UMask": "0x1", 5321 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS.REMOTE_HIT_FORWARD", 5322 "Deprecated": "1", 5323 "MSRValue": "0x083FC00491", 5324 "Counter": "0,1,2,3", 5325 "EventName": "OFFCORE_RESPONSE:request=ALL_DATA_RD:response=L3_MISS.REMOTE_HIT_FORWARD", 5326 "MSRIndex": "0x1a6,0x1a7", 5327 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5328 "SampleAfterValue": "100003", 5329 "CounterHTOff": "0,1,2,3" 5330 }, 5331 { 5332 "Offcore": "1", 5333 "EventCode": "0xB7, 0xBB", 5334 "UMask": "0x1", 5335 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS.REMOTE_HIT_FORWARD", 5336 "Deprecated": "1", 5337 "MSRValue": "0x083FC00122", 5338 "Counter": "0,1,2,3", 5339 "EventName": "OFFCORE_RESPONSE:request=ALL_RFO:response=L3_MISS.REMOTE_HIT_FORWARD", 5340 "MSRIndex": "0x1a6,0x1a7", 5341 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5342 "SampleAfterValue": "100003", 5343 "CounterHTOff": "0,1,2,3" 5344 }, 5345 { 5346 "Offcore": "1", 5347 "EventCode": "0xB7, 0xBB", 5348 "UMask": "0x1", 5349 "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS.REMOTE_HIT_FORWARD", 5350 "Deprecated": "1", 5351 "MSRValue": "0x083FC007F7", 5352 "Counter": "0,1,2,3", 5353 "EventName": "OFFCORE_RESPONSE:request=ALL_READS:response=L3_MISS.REMOTE_HIT_FORWARD", 5354 "MSRIndex": "0x1a6,0x1a7", 5355 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5356 "SampleAfterValue": "100003", 5357 "CounterHTOff": "0,1,2,3" 5358 }, 5359 { 5360 "Offcore": "1", 5361 "EventCode": "0xB7, 0xBB", 5362 "UMask": "0x1", 5363 "BriefDescription": "Counts demand data reads", 5364 "MSRValue": "0x0084000001", 5365 "Counter": "0,1,2,3", 5366 "EventName": "OCR.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NONE", 5367 "MSRIndex": "0x1a6,0x1a7", 5368 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5369 "SampleAfterValue": "100003", 5370 "CounterHTOff": "0,1,2,3" 5371 }, 5372 { 5373 "Offcore": "1", 5374 "EventCode": "0xB7, 0xBB", 5375 "UMask": "0x1", 5376 "BriefDescription": "Counts demand data reads TBD", 5377 "MSRValue": "0x0104000001", 5378 "Counter": "0,1,2,3", 5379 "EventName": "OCR.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED", 5380 "MSRIndex": "0x1a6,0x1a7", 5381 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5382 "SampleAfterValue": "100003", 5383 "CounterHTOff": "0,1,2,3" 5384 }, 5385 { 5386 "Offcore": "1", 5387 "EventCode": "0xB7, 0xBB", 5388 "UMask": "0x1", 5389 "BriefDescription": "Counts demand data reads", 5390 "MSRValue": "0x0204000001", 5391 "Counter": "0,1,2,3", 5392 "EventName": "OCR.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS", 5393 "MSRIndex": "0x1a6,0x1a7", 5394 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5395 "SampleAfterValue": "100003", 5396 "CounterHTOff": "0,1,2,3" 5397 }, 5398 { 5399 "Offcore": "1", 5400 "EventCode": "0xB7, 0xBB", 5401 "UMask": "0x1", 5402 "BriefDescription": "Counts demand data reads TBD", 5403 "MSRValue": "0x0404000001", 5404 "Counter": "0,1,2,3", 5405 "EventName": "OCR.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD", 5406 "MSRIndex": "0x1a6,0x1a7", 5407 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5408 "SampleAfterValue": "100003", 5409 "CounterHTOff": "0,1,2,3" 5410 }, 5411 { 5412 "Offcore": "1", 5413 "EventCode": "0xB7, 0xBB", 5414 "UMask": "0x1", 5415 "BriefDescription": "Counts demand data reads TBD", 5416 "MSRValue": "0x0804000001", 5417 "Counter": "0,1,2,3", 5418 "EventName": "OCR.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD", 5419 "MSRIndex": "0x1a6,0x1a7", 5420 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5421 "SampleAfterValue": "100003", 5422 "CounterHTOff": "0,1,2,3" 5423 }, 5424 { 5425 "Offcore": "1", 5426 "EventCode": "0xB7, 0xBB", 5427 "UMask": "0x1", 5428 "BriefDescription": "Counts demand data reads TBD", 5429 "MSRValue": "0x1004000001", 5430 "Counter": "0,1,2,3", 5431 "EventName": "OCR.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE", 5432 "MSRIndex": "0x1a6,0x1a7", 5433 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5434 "SampleAfterValue": "100003", 5435 "CounterHTOff": "0,1,2,3" 5436 }, 5437 { 5438 "Offcore": "1", 5439 "EventCode": "0xB7, 0xBB", 5440 "UMask": "0x1", 5441 "BriefDescription": "Counts demand data reads TBD", 5442 "MSRValue": "0x3F84000001", 5443 "Counter": "0,1,2,3", 5444 "EventName": "OCR.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP", 5445 "MSRIndex": "0x1a6,0x1a7", 5446 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5447 "SampleAfterValue": "100003", 5448 "CounterHTOff": "0,1,2,3" 5449 }, 5450 { 5451 "Offcore": "1", 5452 "EventCode": "0xB7, 0xBB", 5453 "UMask": "0x1", 5454 "BriefDescription": "Counts demand data reads", 5455 "MSRValue": "0x0090000001", 5456 "Counter": "0,1,2,3", 5457 "EventName": "OCR.DEMAND_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE", 5458 "MSRIndex": "0x1a6,0x1a7", 5459 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5460 "SampleAfterValue": "100003", 5461 "CounterHTOff": "0,1,2,3" 5462 }, 5463 { 5464 "Offcore": "1", 5465 "EventCode": "0xB7, 0xBB", 5466 "UMask": "0x1", 5467 "BriefDescription": "Counts demand data reads TBD", 5468 "MSRValue": "0x0110000001", 5469 "Counter": "0,1,2,3", 5470 "EventName": "OCR.DEMAND_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED", 5471 "MSRIndex": "0x1a6,0x1a7", 5472 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5473 "SampleAfterValue": "100003", 5474 "CounterHTOff": "0,1,2,3" 5475 }, 5476 { 5477 "Offcore": "1", 5478 "EventCode": "0xB7, 0xBB", 5479 "UMask": "0x1", 5480 "BriefDescription": "Counts demand data reads", 5481 "MSRValue": "0x0210000001", 5482 "Counter": "0,1,2,3", 5483 "EventName": "OCR.DEMAND_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS", 5484 "MSRIndex": "0x1a6,0x1a7", 5485 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5486 "SampleAfterValue": "100003", 5487 "CounterHTOff": "0,1,2,3" 5488 }, 5489 { 5490 "Offcore": "1", 5491 "EventCode": "0xB7, 0xBB", 5492 "UMask": "0x1", 5493 "BriefDescription": "Counts demand data reads TBD", 5494 "MSRValue": "0x0410000001", 5495 "Counter": "0,1,2,3", 5496 "EventName": "OCR.DEMAND_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD", 5497 "MSRIndex": "0x1a6,0x1a7", 5498 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5499 "SampleAfterValue": "100003", 5500 "CounterHTOff": "0,1,2,3" 5501 }, 5502 { 5503 "Offcore": "1", 5504 "EventCode": "0xB7, 0xBB", 5505 "UMask": "0x1", 5506 "BriefDescription": "Counts demand data reads TBD", 5507 "MSRValue": "0x0810000001", 5508 "Counter": "0,1,2,3", 5509 "EventName": "OCR.DEMAND_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD", 5510 "MSRIndex": "0x1a6,0x1a7", 5511 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5512 "SampleAfterValue": "100003", 5513 "CounterHTOff": "0,1,2,3" 5514 }, 5515 { 5516 "Offcore": "1", 5517 "EventCode": "0xB7, 0xBB", 5518 "UMask": "0x1", 5519 "BriefDescription": "Counts demand data reads TBD", 5520 "MSRValue": "0x1010000001", 5521 "Counter": "0,1,2,3", 5522 "EventName": "OCR.DEMAND_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE", 5523 "MSRIndex": "0x1a6,0x1a7", 5524 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5525 "SampleAfterValue": "100003", 5526 "CounterHTOff": "0,1,2,3" 5527 }, 5528 { 5529 "Offcore": "1", 5530 "EventCode": "0xB7, 0xBB", 5531 "UMask": "0x1", 5532 "BriefDescription": "Counts demand data reads TBD", 5533 "MSRValue": "0x3F90000001", 5534 "Counter": "0,1,2,3", 5535 "EventName": "OCR.DEMAND_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP", 5536 "MSRIndex": "0x1a6,0x1a7", 5537 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5538 "SampleAfterValue": "100003", 5539 "CounterHTOff": "0,1,2,3" 5540 }, 5541 { 5542 "Offcore": "1", 5543 "EventCode": "0xB7, 0xBB", 5544 "UMask": "0x1", 5545 "BriefDescription": "Counts demand data reads TBD", 5546 "MSRValue": "0x00BC000001", 5547 "Counter": "0,1,2,3", 5548 "EventName": "OCR.DEMAND_DATA_RD.L3_MISS.SNOOP_NONE", 5549 "MSRIndex": "0x1a6,0x1a7", 5550 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5551 "SampleAfterValue": "100003", 5552 "CounterHTOff": "0,1,2,3" 5553 }, 5554 { 5555 "Offcore": "1", 5556 "EventCode": "0xB7, 0xBB", 5557 "UMask": "0x1", 5558 "BriefDescription": "Counts demand data reads TBD TBD", 5559 "MSRValue": "0x013C000001", 5560 "Counter": "0,1,2,3", 5561 "EventName": "OCR.DEMAND_DATA_RD.L3_MISS.NO_SNOOP_NEEDED", 5562 "MSRIndex": "0x1a6,0x1a7", 5563 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5564 "SampleAfterValue": "100003", 5565 "CounterHTOff": "0,1,2,3" 5566 }, 5567 { 5568 "Offcore": "1", 5569 "EventCode": "0xB7, 0xBB", 5570 "UMask": "0x1", 5571 "BriefDescription": "Counts demand data reads TBD", 5572 "MSRValue": "0x023C000001", 5573 "Counter": "0,1,2,3", 5574 "EventName": "OCR.DEMAND_DATA_RD.L3_MISS.SNOOP_MISS", 5575 "MSRIndex": "0x1a6,0x1a7", 5576 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5577 "SampleAfterValue": "100003", 5578 "CounterHTOff": "0,1,2,3" 5579 }, 5580 { 5581 "Offcore": "1", 5582 "EventCode": "0xB7, 0xBB", 5583 "UMask": "0x1", 5584 "BriefDescription": "Counts demand data reads TBD TBD", 5585 "MSRValue": "0x043C000001", 5586 "Counter": "0,1,2,3", 5587 "EventName": "OCR.DEMAND_DATA_RD.L3_MISS.HIT_OTHER_CORE_NO_FWD", 5588 "MSRIndex": "0x1a6,0x1a7", 5589 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5590 "SampleAfterValue": "100003", 5591 "CounterHTOff": "0,1,2,3" 5592 }, 5593 { 5594 "Offcore": "1", 5595 "EventCode": "0xB7, 0xBB", 5596 "UMask": "0x1", 5597 "BriefDescription": "Counts demand data reads TBD TBD", 5598 "MSRValue": "0x083C000001", 5599 "Counter": "0,1,2,3", 5600 "EventName": "OCR.DEMAND_DATA_RD.L3_MISS.HIT_OTHER_CORE_FWD", 5601 "MSRIndex": "0x1a6,0x1a7", 5602 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5603 "SampleAfterValue": "100003", 5604 "CounterHTOff": "0,1,2,3" 5605 }, 5606 { 5607 "Offcore": "1", 5608 "EventCode": "0xB7, 0xBB", 5609 "UMask": "0x1", 5610 "BriefDescription": "Counts demand data reads TBD TBD", 5611 "MSRValue": "0x103C000001", 5612 "Counter": "0,1,2,3", 5613 "EventName": "OCR.DEMAND_DATA_RD.L3_MISS.HITM_OTHER_CORE", 5614 "MSRIndex": "0x1a6,0x1a7", 5615 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5616 "SampleAfterValue": "100003", 5617 "CounterHTOff": "0,1,2,3" 5618 }, 5619 { 5620 "Offcore": "1", 5621 "EventCode": "0xB7, 0xBB", 5622 "UMask": "0x1", 5623 "BriefDescription": "Counts demand data reads TBD TBD", 5624 "MSRValue": "0x3FBC000001", 5625 "Counter": "0,1,2,3", 5626 "EventName": "OCR.DEMAND_DATA_RD.L3_MISS.ANY_SNOOP", 5627 "MSRIndex": "0x1a6,0x1a7", 5628 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5629 "SampleAfterValue": "100003", 5630 "CounterHTOff": "0,1,2,3" 5631 }, 5632 { 5633 "Offcore": "1", 5634 "EventCode": "0xB7, 0xBB", 5635 "UMask": "0x1", 5636 "BriefDescription": "Counts all demand data writes (RFOs)", 5637 "MSRValue": "0x0084000002", 5638 "Counter": "0,1,2,3", 5639 "EventName": "OCR.DEMAND_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NONE", 5640 "MSRIndex": "0x1a6,0x1a7", 5641 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5642 "SampleAfterValue": "100003", 5643 "CounterHTOff": "0,1,2,3" 5644 }, 5645 { 5646 "Offcore": "1", 5647 "EventCode": "0xB7, 0xBB", 5648 "UMask": "0x1", 5649 "BriefDescription": "Counts all demand data writes (RFOs) TBD", 5650 "MSRValue": "0x0104000002", 5651 "Counter": "0,1,2,3", 5652 "EventName": "OCR.DEMAND_RFO.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED", 5653 "MSRIndex": "0x1a6,0x1a7", 5654 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5655 "SampleAfterValue": "100003", 5656 "CounterHTOff": "0,1,2,3" 5657 }, 5658 { 5659 "Offcore": "1", 5660 "EventCode": "0xB7, 0xBB", 5661 "UMask": "0x1", 5662 "BriefDescription": "Counts all demand data writes (RFOs)", 5663 "MSRValue": "0x0204000002", 5664 "Counter": "0,1,2,3", 5665 "EventName": "OCR.DEMAND_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS", 5666 "MSRIndex": "0x1a6,0x1a7", 5667 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5668 "SampleAfterValue": "100003", 5669 "CounterHTOff": "0,1,2,3" 5670 }, 5671 { 5672 "Offcore": "1", 5673 "EventCode": "0xB7, 0xBB", 5674 "UMask": "0x1", 5675 "BriefDescription": "Counts all demand data writes (RFOs) TBD", 5676 "MSRValue": "0x0404000002", 5677 "Counter": "0,1,2,3", 5678 "EventName": "OCR.DEMAND_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD", 5679 "MSRIndex": "0x1a6,0x1a7", 5680 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5681 "SampleAfterValue": "100003", 5682 "CounterHTOff": "0,1,2,3" 5683 }, 5684 { 5685 "Offcore": "1", 5686 "EventCode": "0xB7, 0xBB", 5687 "UMask": "0x1", 5688 "BriefDescription": "Counts all demand data writes (RFOs) TBD", 5689 "MSRValue": "0x0804000002", 5690 "Counter": "0,1,2,3", 5691 "EventName": "OCR.DEMAND_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD", 5692 "MSRIndex": "0x1a6,0x1a7", 5693 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5694 "SampleAfterValue": "100003", 5695 "CounterHTOff": "0,1,2,3" 5696 }, 5697 { 5698 "Offcore": "1", 5699 "EventCode": "0xB7, 0xBB", 5700 "UMask": "0x1", 5701 "BriefDescription": "Counts all demand data writes (RFOs) TBD", 5702 "MSRValue": "0x1004000002", 5703 "Counter": "0,1,2,3", 5704 "EventName": "OCR.DEMAND_RFO.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE", 5705 "MSRIndex": "0x1a6,0x1a7", 5706 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5707 "SampleAfterValue": "100003", 5708 "CounterHTOff": "0,1,2,3" 5709 }, 5710 { 5711 "Offcore": "1", 5712 "EventCode": "0xB7, 0xBB", 5713 "UMask": "0x1", 5714 "BriefDescription": "Counts all demand data writes (RFOs) TBD", 5715 "MSRValue": "0x3F84000002", 5716 "Counter": "0,1,2,3", 5717 "EventName": "OCR.DEMAND_RFO.L3_MISS_LOCAL_DRAM.ANY_SNOOP", 5718 "MSRIndex": "0x1a6,0x1a7", 5719 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5720 "SampleAfterValue": "100003", 5721 "CounterHTOff": "0,1,2,3" 5722 }, 5723 { 5724 "Offcore": "1", 5725 "EventCode": "0xB7, 0xBB", 5726 "UMask": "0x1", 5727 "BriefDescription": "Counts all demand data writes (RFOs)", 5728 "MSRValue": "0x0090000002", 5729 "Counter": "0,1,2,3", 5730 "EventName": "OCR.DEMAND_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE", 5731 "MSRIndex": "0x1a6,0x1a7", 5732 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5733 "SampleAfterValue": "100003", 5734 "CounterHTOff": "0,1,2,3" 5735 }, 5736 { 5737 "Offcore": "1", 5738 "EventCode": "0xB7, 0xBB", 5739 "UMask": "0x1", 5740 "BriefDescription": "Counts all demand data writes (RFOs) TBD", 5741 "MSRValue": "0x0110000002", 5742 "Counter": "0,1,2,3", 5743 "EventName": "OCR.DEMAND_RFO.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED", 5744 "MSRIndex": "0x1a6,0x1a7", 5745 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5746 "SampleAfterValue": "100003", 5747 "CounterHTOff": "0,1,2,3" 5748 }, 5749 { 5750 "Offcore": "1", 5751 "EventCode": "0xB7, 0xBB", 5752 "UMask": "0x1", 5753 "BriefDescription": "Counts all demand data writes (RFOs)", 5754 "MSRValue": "0x0210000002", 5755 "Counter": "0,1,2,3", 5756 "EventName": "OCR.DEMAND_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS", 5757 "MSRIndex": "0x1a6,0x1a7", 5758 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5759 "SampleAfterValue": "100003", 5760 "CounterHTOff": "0,1,2,3" 5761 }, 5762 { 5763 "Offcore": "1", 5764 "EventCode": "0xB7, 0xBB", 5765 "UMask": "0x1", 5766 "BriefDescription": "Counts all demand data writes (RFOs) TBD", 5767 "MSRValue": "0x0410000002", 5768 "Counter": "0,1,2,3", 5769 "EventName": "OCR.DEMAND_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD", 5770 "MSRIndex": "0x1a6,0x1a7", 5771 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5772 "SampleAfterValue": "100003", 5773 "CounterHTOff": "0,1,2,3" 5774 }, 5775 { 5776 "Offcore": "1", 5777 "EventCode": "0xB7, 0xBB", 5778 "UMask": "0x1", 5779 "BriefDescription": "Counts all demand data writes (RFOs) TBD", 5780 "MSRValue": "0x0810000002", 5781 "Counter": "0,1,2,3", 5782 "EventName": "OCR.DEMAND_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD", 5783 "MSRIndex": "0x1a6,0x1a7", 5784 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5785 "SampleAfterValue": "100003", 5786 "CounterHTOff": "0,1,2,3" 5787 }, 5788 { 5789 "Offcore": "1", 5790 "EventCode": "0xB7, 0xBB", 5791 "UMask": "0x1", 5792 "BriefDescription": "Counts all demand data writes (RFOs) TBD", 5793 "MSRValue": "0x1010000002", 5794 "Counter": "0,1,2,3", 5795 "EventName": "OCR.DEMAND_RFO.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE", 5796 "MSRIndex": "0x1a6,0x1a7", 5797 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5798 "SampleAfterValue": "100003", 5799 "CounterHTOff": "0,1,2,3" 5800 }, 5801 { 5802 "Offcore": "1", 5803 "EventCode": "0xB7, 0xBB", 5804 "UMask": "0x1", 5805 "BriefDescription": "Counts all demand data writes (RFOs) TBD", 5806 "MSRValue": "0x3F90000002", 5807 "Counter": "0,1,2,3", 5808 "EventName": "OCR.DEMAND_RFO.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP", 5809 "MSRIndex": "0x1a6,0x1a7", 5810 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5811 "SampleAfterValue": "100003", 5812 "CounterHTOff": "0,1,2,3" 5813 }, 5814 { 5815 "Offcore": "1", 5816 "EventCode": "0xB7, 0xBB", 5817 "UMask": "0x1", 5818 "BriefDescription": "Counts all demand data writes (RFOs) TBD", 5819 "MSRValue": "0x00BC000002", 5820 "Counter": "0,1,2,3", 5821 "EventName": "OCR.DEMAND_RFO.L3_MISS.SNOOP_NONE", 5822 "MSRIndex": "0x1a6,0x1a7", 5823 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5824 "SampleAfterValue": "100003", 5825 "CounterHTOff": "0,1,2,3" 5826 }, 5827 { 5828 "Offcore": "1", 5829 "EventCode": "0xB7, 0xBB", 5830 "UMask": "0x1", 5831 "BriefDescription": "Counts all demand data writes (RFOs) TBD TBD", 5832 "MSRValue": "0x013C000002", 5833 "Counter": "0,1,2,3", 5834 "EventName": "OCR.DEMAND_RFO.L3_MISS.NO_SNOOP_NEEDED", 5835 "MSRIndex": "0x1a6,0x1a7", 5836 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5837 "SampleAfterValue": "100003", 5838 "CounterHTOff": "0,1,2,3" 5839 }, 5840 { 5841 "Offcore": "1", 5842 "EventCode": "0xB7, 0xBB", 5843 "UMask": "0x1", 5844 "BriefDescription": "Counts all demand data writes (RFOs) TBD", 5845 "MSRValue": "0x023C000002", 5846 "Counter": "0,1,2,3", 5847 "EventName": "OCR.DEMAND_RFO.L3_MISS.SNOOP_MISS", 5848 "MSRIndex": "0x1a6,0x1a7", 5849 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5850 "SampleAfterValue": "100003", 5851 "CounterHTOff": "0,1,2,3" 5852 }, 5853 { 5854 "Offcore": "1", 5855 "EventCode": "0xB7, 0xBB", 5856 "UMask": "0x1", 5857 "BriefDescription": "Counts all demand data writes (RFOs) TBD TBD", 5858 "MSRValue": "0x043C000002", 5859 "Counter": "0,1,2,3", 5860 "EventName": "OCR.DEMAND_RFO.L3_MISS.HIT_OTHER_CORE_NO_FWD", 5861 "MSRIndex": "0x1a6,0x1a7", 5862 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5863 "SampleAfterValue": "100003", 5864 "CounterHTOff": "0,1,2,3" 5865 }, 5866 { 5867 "Offcore": "1", 5868 "EventCode": "0xB7, 0xBB", 5869 "UMask": "0x1", 5870 "BriefDescription": "Counts all demand data writes (RFOs) TBD TBD", 5871 "MSRValue": "0x083C000002", 5872 "Counter": "0,1,2,3", 5873 "EventName": "OCR.DEMAND_RFO.L3_MISS.HIT_OTHER_CORE_FWD", 5874 "MSRIndex": "0x1a6,0x1a7", 5875 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5876 "SampleAfterValue": "100003", 5877 "CounterHTOff": "0,1,2,3" 5878 }, 5879 { 5880 "Offcore": "1", 5881 "EventCode": "0xB7, 0xBB", 5882 "UMask": "0x1", 5883 "BriefDescription": "Counts all demand data writes (RFOs) TBD TBD", 5884 "MSRValue": "0x103C000002", 5885 "Counter": "0,1,2,3", 5886 "EventName": "OCR.DEMAND_RFO.L3_MISS.HITM_OTHER_CORE", 5887 "MSRIndex": "0x1a6,0x1a7", 5888 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5889 "SampleAfterValue": "100003", 5890 "CounterHTOff": "0,1,2,3" 5891 }, 5892 { 5893 "Offcore": "1", 5894 "EventCode": "0xB7, 0xBB", 5895 "UMask": "0x1", 5896 "BriefDescription": "Counts all demand data writes (RFOs) TBD TBD", 5897 "MSRValue": "0x3FBC000002", 5898 "Counter": "0,1,2,3", 5899 "EventName": "OCR.DEMAND_RFO.L3_MISS.ANY_SNOOP", 5900 "MSRIndex": "0x1a6,0x1a7", 5901 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5902 "SampleAfterValue": "100003", 5903 "CounterHTOff": "0,1,2,3" 5904 }, 5905 { 5906 "Offcore": "1", 5907 "EventCode": "0xB7, 0xBB", 5908 "UMask": "0x1", 5909 "BriefDescription": "Counts all demand code reads", 5910 "MSRValue": "0x0084000004", 5911 "Counter": "0,1,2,3", 5912 "EventName": "OCR.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_NONE", 5913 "MSRIndex": "0x1a6,0x1a7", 5914 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5915 "SampleAfterValue": "100003", 5916 "CounterHTOff": "0,1,2,3" 5917 }, 5918 { 5919 "Offcore": "1", 5920 "EventCode": "0xB7, 0xBB", 5921 "UMask": "0x1", 5922 "BriefDescription": "Counts all demand code reads TBD", 5923 "MSRValue": "0x0104000004", 5924 "Counter": "0,1,2,3", 5925 "EventName": "OCR.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED", 5926 "MSRIndex": "0x1a6,0x1a7", 5927 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5928 "SampleAfterValue": "100003", 5929 "CounterHTOff": "0,1,2,3" 5930 }, 5931 { 5932 "Offcore": "1", 5933 "EventCode": "0xB7, 0xBB", 5934 "UMask": "0x1", 5935 "BriefDescription": "Counts all demand code reads", 5936 "MSRValue": "0x0204000004", 5937 "Counter": "0,1,2,3", 5938 "EventName": "OCR.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS", 5939 "MSRIndex": "0x1a6,0x1a7", 5940 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5941 "SampleAfterValue": "100003", 5942 "CounterHTOff": "0,1,2,3" 5943 }, 5944 { 5945 "Offcore": "1", 5946 "EventCode": "0xB7, 0xBB", 5947 "UMask": "0x1", 5948 "BriefDescription": "Counts all demand code reads TBD", 5949 "MSRValue": "0x0404000004", 5950 "Counter": "0,1,2,3", 5951 "EventName": "OCR.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD", 5952 "MSRIndex": "0x1a6,0x1a7", 5953 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5954 "SampleAfterValue": "100003", 5955 "CounterHTOff": "0,1,2,3" 5956 }, 5957 { 5958 "Offcore": "1", 5959 "EventCode": "0xB7, 0xBB", 5960 "UMask": "0x1", 5961 "BriefDescription": "Counts all demand code reads TBD", 5962 "MSRValue": "0x0804000004", 5963 "Counter": "0,1,2,3", 5964 "EventName": "OCR.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD", 5965 "MSRIndex": "0x1a6,0x1a7", 5966 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5967 "SampleAfterValue": "100003", 5968 "CounterHTOff": "0,1,2,3" 5969 }, 5970 { 5971 "Offcore": "1", 5972 "EventCode": "0xB7, 0xBB", 5973 "UMask": "0x1", 5974 "BriefDescription": "Counts all demand code reads TBD", 5975 "MSRValue": "0x1004000004", 5976 "Counter": "0,1,2,3", 5977 "EventName": "OCR.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE", 5978 "MSRIndex": "0x1a6,0x1a7", 5979 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5980 "SampleAfterValue": "100003", 5981 "CounterHTOff": "0,1,2,3" 5982 }, 5983 { 5984 "Offcore": "1", 5985 "EventCode": "0xB7, 0xBB", 5986 "UMask": "0x1", 5987 "BriefDescription": "Counts all demand code reads TBD", 5988 "MSRValue": "0x3F84000004", 5989 "Counter": "0,1,2,3", 5990 "EventName": "OCR.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP", 5991 "MSRIndex": "0x1a6,0x1a7", 5992 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5993 "SampleAfterValue": "100003", 5994 "CounterHTOff": "0,1,2,3" 5995 }, 5996 { 5997 "Offcore": "1", 5998 "EventCode": "0xB7, 0xBB", 5999 "UMask": "0x1", 6000 "BriefDescription": "Counts all demand code reads", 6001 "MSRValue": "0x0090000004", 6002 "Counter": "0,1,2,3", 6003 "EventName": "OCR.DEMAND_CODE_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE", 6004 "MSRIndex": "0x1a6,0x1a7", 6005 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6006 "SampleAfterValue": "100003", 6007 "CounterHTOff": "0,1,2,3" 6008 }, 6009 { 6010 "Offcore": "1", 6011 "EventCode": "0xB7, 0xBB", 6012 "UMask": "0x1", 6013 "BriefDescription": "Counts all demand code reads TBD", 6014 "MSRValue": "0x0110000004", 6015 "Counter": "0,1,2,3", 6016 "EventName": "OCR.DEMAND_CODE_RD.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED", 6017 "MSRIndex": "0x1a6,0x1a7", 6018 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6019 "SampleAfterValue": "100003", 6020 "CounterHTOff": "0,1,2,3" 6021 }, 6022 { 6023 "Offcore": "1", 6024 "EventCode": "0xB7, 0xBB", 6025 "UMask": "0x1", 6026 "BriefDescription": "Counts all demand code reads", 6027 "MSRValue": "0x0210000004", 6028 "Counter": "0,1,2,3", 6029 "EventName": "OCR.DEMAND_CODE_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS", 6030 "MSRIndex": "0x1a6,0x1a7", 6031 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6032 "SampleAfterValue": "100003", 6033 "CounterHTOff": "0,1,2,3" 6034 }, 6035 { 6036 "Offcore": "1", 6037 "EventCode": "0xB7, 0xBB", 6038 "UMask": "0x1", 6039 "BriefDescription": "Counts all demand code reads TBD", 6040 "MSRValue": "0x0410000004", 6041 "Counter": "0,1,2,3", 6042 "EventName": "OCR.DEMAND_CODE_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD", 6043 "MSRIndex": "0x1a6,0x1a7", 6044 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6045 "SampleAfterValue": "100003", 6046 "CounterHTOff": "0,1,2,3" 6047 }, 6048 { 6049 "Offcore": "1", 6050 "EventCode": "0xB7, 0xBB", 6051 "UMask": "0x1", 6052 "BriefDescription": "Counts all demand code reads TBD", 6053 "MSRValue": "0x0810000004", 6054 "Counter": "0,1,2,3", 6055 "EventName": "OCR.DEMAND_CODE_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD", 6056 "MSRIndex": "0x1a6,0x1a7", 6057 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6058 "SampleAfterValue": "100003", 6059 "CounterHTOff": "0,1,2,3" 6060 }, 6061 { 6062 "Offcore": "1", 6063 "EventCode": "0xB7, 0xBB", 6064 "UMask": "0x1", 6065 "BriefDescription": "Counts all demand code reads TBD", 6066 "MSRValue": "0x1010000004", 6067 "Counter": "0,1,2,3", 6068 "EventName": "OCR.DEMAND_CODE_RD.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE", 6069 "MSRIndex": "0x1a6,0x1a7", 6070 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6071 "SampleAfterValue": "100003", 6072 "CounterHTOff": "0,1,2,3" 6073 }, 6074 { 6075 "Offcore": "1", 6076 "EventCode": "0xB7, 0xBB", 6077 "UMask": "0x1", 6078 "BriefDescription": "Counts all demand code reads TBD", 6079 "MSRValue": "0x3F90000004", 6080 "Counter": "0,1,2,3", 6081 "EventName": "OCR.DEMAND_CODE_RD.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP", 6082 "MSRIndex": "0x1a6,0x1a7", 6083 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6084 "SampleAfterValue": "100003", 6085 "CounterHTOff": "0,1,2,3" 6086 }, 6087 { 6088 "Offcore": "1", 6089 "EventCode": "0xB7, 0xBB", 6090 "UMask": "0x1", 6091 "BriefDescription": "Counts all demand code reads TBD", 6092 "MSRValue": "0x00BC000004", 6093 "Counter": "0,1,2,3", 6094 "EventName": "OCR.DEMAND_CODE_RD.L3_MISS.SNOOP_NONE", 6095 "MSRIndex": "0x1a6,0x1a7", 6096 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6097 "SampleAfterValue": "100003", 6098 "CounterHTOff": "0,1,2,3" 6099 }, 6100 { 6101 "Offcore": "1", 6102 "EventCode": "0xB7, 0xBB", 6103 "UMask": "0x1", 6104 "BriefDescription": "Counts all demand code reads TBD TBD", 6105 "MSRValue": "0x013C000004", 6106 "Counter": "0,1,2,3", 6107 "EventName": "OCR.DEMAND_CODE_RD.L3_MISS.NO_SNOOP_NEEDED", 6108 "MSRIndex": "0x1a6,0x1a7", 6109 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6110 "SampleAfterValue": "100003", 6111 "CounterHTOff": "0,1,2,3" 6112 }, 6113 { 6114 "Offcore": "1", 6115 "EventCode": "0xB7, 0xBB", 6116 "UMask": "0x1", 6117 "BriefDescription": "Counts all demand code reads TBD", 6118 "MSRValue": "0x023C000004", 6119 "Counter": "0,1,2,3", 6120 "EventName": "OCR.DEMAND_CODE_RD.L3_MISS.SNOOP_MISS", 6121 "MSRIndex": "0x1a6,0x1a7", 6122 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6123 "SampleAfterValue": "100003", 6124 "CounterHTOff": "0,1,2,3" 6125 }, 6126 { 6127 "Offcore": "1", 6128 "EventCode": "0xB7, 0xBB", 6129 "UMask": "0x1", 6130 "BriefDescription": "Counts all demand code reads TBD TBD", 6131 "MSRValue": "0x043C000004", 6132 "Counter": "0,1,2,3", 6133 "EventName": "OCR.DEMAND_CODE_RD.L3_MISS.HIT_OTHER_CORE_NO_FWD", 6134 "MSRIndex": "0x1a6,0x1a7", 6135 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6136 "SampleAfterValue": "100003", 6137 "CounterHTOff": "0,1,2,3" 6138 }, 6139 { 6140 "Offcore": "1", 6141 "EventCode": "0xB7, 0xBB", 6142 "UMask": "0x1", 6143 "BriefDescription": "Counts all demand code reads TBD TBD", 6144 "MSRValue": "0x083C000004", 6145 "Counter": "0,1,2,3", 6146 "EventName": "OCR.DEMAND_CODE_RD.L3_MISS.HIT_OTHER_CORE_FWD", 6147 "MSRIndex": "0x1a6,0x1a7", 6148 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6149 "SampleAfterValue": "100003", 6150 "CounterHTOff": "0,1,2,3" 6151 }, 6152 { 6153 "Offcore": "1", 6154 "EventCode": "0xB7, 0xBB", 6155 "UMask": "0x1", 6156 "BriefDescription": "Counts all demand code reads TBD TBD", 6157 "MSRValue": "0x103C000004", 6158 "Counter": "0,1,2,3", 6159 "EventName": "OCR.DEMAND_CODE_RD.L3_MISS.HITM_OTHER_CORE", 6160 "MSRIndex": "0x1a6,0x1a7", 6161 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6162 "SampleAfterValue": "100003", 6163 "CounterHTOff": "0,1,2,3" 6164 }, 6165 { 6166 "Offcore": "1", 6167 "EventCode": "0xB7, 0xBB", 6168 "UMask": "0x1", 6169 "BriefDescription": "Counts all demand code reads TBD TBD", 6170 "MSRValue": "0x3FBC000004", 6171 "Counter": "0,1,2,3", 6172 "EventName": "OCR.DEMAND_CODE_RD.L3_MISS.ANY_SNOOP", 6173 "MSRIndex": "0x1a6,0x1a7", 6174 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6175 "SampleAfterValue": "100003", 6176 "CounterHTOff": "0,1,2,3" 6177 }, 6178 { 6179 "Offcore": "1", 6180 "EventCode": "0xB7, 0xBB", 6181 "UMask": "0x1", 6182 "BriefDescription": "Counts prefetch (that bring data to L2) data reads", 6183 "MSRValue": "0x0084000010", 6184 "Counter": "0,1,2,3", 6185 "EventName": "OCR.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NONE", 6186 "MSRIndex": "0x1a6,0x1a7", 6187 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6188 "SampleAfterValue": "100003", 6189 "CounterHTOff": "0,1,2,3" 6190 }, 6191 { 6192 "Offcore": "1", 6193 "EventCode": "0xB7, 0xBB", 6194 "UMask": "0x1", 6195 "BriefDescription": "Counts prefetch (that bring data to L2) data reads TBD", 6196 "MSRValue": "0x0104000010", 6197 "Counter": "0,1,2,3", 6198 "EventName": "OCR.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED", 6199 "MSRIndex": "0x1a6,0x1a7", 6200 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6201 "SampleAfterValue": "100003", 6202 "CounterHTOff": "0,1,2,3" 6203 }, 6204 { 6205 "Offcore": "1", 6206 "EventCode": "0xB7, 0xBB", 6207 "UMask": "0x1", 6208 "BriefDescription": "Counts prefetch (that bring data to L2) data reads", 6209 "MSRValue": "0x0204000010", 6210 "Counter": "0,1,2,3", 6211 "EventName": "OCR.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS", 6212 "MSRIndex": "0x1a6,0x1a7", 6213 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6214 "SampleAfterValue": "100003", 6215 "CounterHTOff": "0,1,2,3" 6216 }, 6217 { 6218 "Offcore": "1", 6219 "EventCode": "0xB7, 0xBB", 6220 "UMask": "0x1", 6221 "BriefDescription": "Counts prefetch (that bring data to L2) data reads TBD", 6222 "MSRValue": "0x0404000010", 6223 "Counter": "0,1,2,3", 6224 "EventName": "OCR.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD", 6225 "MSRIndex": "0x1a6,0x1a7", 6226 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6227 "SampleAfterValue": "100003", 6228 "CounterHTOff": "0,1,2,3" 6229 }, 6230 { 6231 "Offcore": "1", 6232 "EventCode": "0xB7, 0xBB", 6233 "UMask": "0x1", 6234 "BriefDescription": "Counts prefetch (that bring data to L2) data reads TBD", 6235 "MSRValue": "0x0804000010", 6236 "Counter": "0,1,2,3", 6237 "EventName": "OCR.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD", 6238 "MSRIndex": "0x1a6,0x1a7", 6239 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6240 "SampleAfterValue": "100003", 6241 "CounterHTOff": "0,1,2,3" 6242 }, 6243 { 6244 "Offcore": "1", 6245 "EventCode": "0xB7, 0xBB", 6246 "UMask": "0x1", 6247 "BriefDescription": "Counts prefetch (that bring data to L2) data reads TBD", 6248 "MSRValue": "0x1004000010", 6249 "Counter": "0,1,2,3", 6250 "EventName": "OCR.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE", 6251 "MSRIndex": "0x1a6,0x1a7", 6252 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6253 "SampleAfterValue": "100003", 6254 "CounterHTOff": "0,1,2,3" 6255 }, 6256 { 6257 "Offcore": "1", 6258 "EventCode": "0xB7, 0xBB", 6259 "UMask": "0x1", 6260 "BriefDescription": "Counts prefetch (that bring data to L2) data reads TBD", 6261 "MSRValue": "0x3F84000010", 6262 "Counter": "0,1,2,3", 6263 "EventName": "OCR.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP", 6264 "MSRIndex": "0x1a6,0x1a7", 6265 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6266 "SampleAfterValue": "100003", 6267 "CounterHTOff": "0,1,2,3" 6268 }, 6269 { 6270 "Offcore": "1", 6271 "EventCode": "0xB7, 0xBB", 6272 "UMask": "0x1", 6273 "BriefDescription": "Counts prefetch (that bring data to L2) data reads", 6274 "MSRValue": "0x0090000010", 6275 "Counter": "0,1,2,3", 6276 "EventName": "OCR.PF_L2_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE", 6277 "MSRIndex": "0x1a6,0x1a7", 6278 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6279 "SampleAfterValue": "100003", 6280 "CounterHTOff": "0,1,2,3" 6281 }, 6282 { 6283 "Offcore": "1", 6284 "EventCode": "0xB7, 0xBB", 6285 "UMask": "0x1", 6286 "BriefDescription": "Counts prefetch (that bring data to L2) data reads TBD", 6287 "MSRValue": "0x0110000010", 6288 "Counter": "0,1,2,3", 6289 "EventName": "OCR.PF_L2_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED", 6290 "MSRIndex": "0x1a6,0x1a7", 6291 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6292 "SampleAfterValue": "100003", 6293 "CounterHTOff": "0,1,2,3" 6294 }, 6295 { 6296 "Offcore": "1", 6297 "EventCode": "0xB7, 0xBB", 6298 "UMask": "0x1", 6299 "BriefDescription": "Counts prefetch (that bring data to L2) data reads", 6300 "MSRValue": "0x0210000010", 6301 "Counter": "0,1,2,3", 6302 "EventName": "OCR.PF_L2_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS", 6303 "MSRIndex": "0x1a6,0x1a7", 6304 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6305 "SampleAfterValue": "100003", 6306 "CounterHTOff": "0,1,2,3" 6307 }, 6308 { 6309 "Offcore": "1", 6310 "EventCode": "0xB7, 0xBB", 6311 "UMask": "0x1", 6312 "BriefDescription": "Counts prefetch (that bring data to L2) data reads TBD", 6313 "MSRValue": "0x0410000010", 6314 "Counter": "0,1,2,3", 6315 "EventName": "OCR.PF_L2_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD", 6316 "MSRIndex": "0x1a6,0x1a7", 6317 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6318 "SampleAfterValue": "100003", 6319 "CounterHTOff": "0,1,2,3" 6320 }, 6321 { 6322 "Offcore": "1", 6323 "EventCode": "0xB7, 0xBB", 6324 "UMask": "0x1", 6325 "BriefDescription": "Counts prefetch (that bring data to L2) data reads TBD", 6326 "MSRValue": "0x0810000010", 6327 "Counter": "0,1,2,3", 6328 "EventName": "OCR.PF_L2_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD", 6329 "MSRIndex": "0x1a6,0x1a7", 6330 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6331 "SampleAfterValue": "100003", 6332 "CounterHTOff": "0,1,2,3" 6333 }, 6334 { 6335 "Offcore": "1", 6336 "EventCode": "0xB7, 0xBB", 6337 "UMask": "0x1", 6338 "BriefDescription": "Counts prefetch (that bring data to L2) data reads TBD", 6339 "MSRValue": "0x1010000010", 6340 "Counter": "0,1,2,3", 6341 "EventName": "OCR.PF_L2_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE", 6342 "MSRIndex": "0x1a6,0x1a7", 6343 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6344 "SampleAfterValue": "100003", 6345 "CounterHTOff": "0,1,2,3" 6346 }, 6347 { 6348 "Offcore": "1", 6349 "EventCode": "0xB7, 0xBB", 6350 "UMask": "0x1", 6351 "BriefDescription": "Counts prefetch (that bring data to L2) data reads TBD", 6352 "MSRValue": "0x3F90000010", 6353 "Counter": "0,1,2,3", 6354 "EventName": "OCR.PF_L2_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP", 6355 "MSRIndex": "0x1a6,0x1a7", 6356 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6357 "SampleAfterValue": "100003", 6358 "CounterHTOff": "0,1,2,3" 6359 }, 6360 { 6361 "Offcore": "1", 6362 "EventCode": "0xB7, 0xBB", 6363 "UMask": "0x1", 6364 "BriefDescription": "Counts prefetch (that bring data to L2) data reads TBD", 6365 "MSRValue": "0x00BC000010", 6366 "Counter": "0,1,2,3", 6367 "EventName": "OCR.PF_L2_DATA_RD.L3_MISS.SNOOP_NONE", 6368 "MSRIndex": "0x1a6,0x1a7", 6369 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6370 "SampleAfterValue": "100003", 6371 "CounterHTOff": "0,1,2,3" 6372 }, 6373 { 6374 "Offcore": "1", 6375 "EventCode": "0xB7, 0xBB", 6376 "UMask": "0x1", 6377 "BriefDescription": "Counts prefetch (that bring data to L2) data reads TBD TBD", 6378 "MSRValue": "0x013C000010", 6379 "Counter": "0,1,2,3", 6380 "EventName": "OCR.PF_L2_DATA_RD.L3_MISS.NO_SNOOP_NEEDED", 6381 "MSRIndex": "0x1a6,0x1a7", 6382 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6383 "SampleAfterValue": "100003", 6384 "CounterHTOff": "0,1,2,3" 6385 }, 6386 { 6387 "Offcore": "1", 6388 "EventCode": "0xB7, 0xBB", 6389 "UMask": "0x1", 6390 "BriefDescription": "Counts prefetch (that bring data to L2) data reads TBD", 6391 "MSRValue": "0x023C000010", 6392 "Counter": "0,1,2,3", 6393 "EventName": "OCR.PF_L2_DATA_RD.L3_MISS.SNOOP_MISS", 6394 "MSRIndex": "0x1a6,0x1a7", 6395 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6396 "SampleAfterValue": "100003", 6397 "CounterHTOff": "0,1,2,3" 6398 }, 6399 { 6400 "Offcore": "1", 6401 "EventCode": "0xB7, 0xBB", 6402 "UMask": "0x1", 6403 "BriefDescription": "Counts prefetch (that bring data to L2) data reads TBD TBD", 6404 "MSRValue": "0x043C000010", 6405 "Counter": "0,1,2,3", 6406 "EventName": "OCR.PF_L2_DATA_RD.L3_MISS.HIT_OTHER_CORE_NO_FWD", 6407 "MSRIndex": "0x1a6,0x1a7", 6408 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6409 "SampleAfterValue": "100003", 6410 "CounterHTOff": "0,1,2,3" 6411 }, 6412 { 6413 "Offcore": "1", 6414 "EventCode": "0xB7, 0xBB", 6415 "UMask": "0x1", 6416 "BriefDescription": "Counts prefetch (that bring data to L2) data reads TBD TBD", 6417 "MSRValue": "0x083C000010", 6418 "Counter": "0,1,2,3", 6419 "EventName": "OCR.PF_L2_DATA_RD.L3_MISS.HIT_OTHER_CORE_FWD", 6420 "MSRIndex": "0x1a6,0x1a7", 6421 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6422 "SampleAfterValue": "100003", 6423 "CounterHTOff": "0,1,2,3" 6424 }, 6425 { 6426 "Offcore": "1", 6427 "EventCode": "0xB7, 0xBB", 6428 "UMask": "0x1", 6429 "BriefDescription": "Counts prefetch (that bring data to L2) data reads TBD TBD", 6430 "MSRValue": "0x103C000010", 6431 "Counter": "0,1,2,3", 6432 "EventName": "OCR.PF_L2_DATA_RD.L3_MISS.HITM_OTHER_CORE", 6433 "MSRIndex": "0x1a6,0x1a7", 6434 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6435 "SampleAfterValue": "100003", 6436 "CounterHTOff": "0,1,2,3" 6437 }, 6438 { 6439 "Offcore": "1", 6440 "EventCode": "0xB7, 0xBB", 6441 "UMask": "0x1", 6442 "BriefDescription": "Counts prefetch (that bring data to L2) data reads TBD TBD", 6443 "MSRValue": "0x3FBC000010", 6444 "Counter": "0,1,2,3", 6445 "EventName": "OCR.PF_L2_DATA_RD.L3_MISS.ANY_SNOOP", 6446 "MSRIndex": "0x1a6,0x1a7", 6447 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6448 "SampleAfterValue": "100003", 6449 "CounterHTOff": "0,1,2,3" 6450 }, 6451 { 6452 "Offcore": "1", 6453 "EventCode": "0xB7, 0xBB", 6454 "UMask": "0x1", 6455 "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs", 6456 "MSRValue": "0x0084000020", 6457 "Counter": "0,1,2,3", 6458 "EventName": "OCR.PF_L2_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NONE", 6459 "MSRIndex": "0x1a6,0x1a7", 6460 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6461 "SampleAfterValue": "100003", 6462 "CounterHTOff": "0,1,2,3" 6463 }, 6464 { 6465 "Offcore": "1", 6466 "EventCode": "0xB7, 0xBB", 6467 "UMask": "0x1", 6468 "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs TBD", 6469 "MSRValue": "0x0104000020", 6470 "Counter": "0,1,2,3", 6471 "EventName": "OCR.PF_L2_RFO.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED", 6472 "MSRIndex": "0x1a6,0x1a7", 6473 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6474 "SampleAfterValue": "100003", 6475 "CounterHTOff": "0,1,2,3" 6476 }, 6477 { 6478 "Offcore": "1", 6479 "EventCode": "0xB7, 0xBB", 6480 "UMask": "0x1", 6481 "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs", 6482 "MSRValue": "0x0204000020", 6483 "Counter": "0,1,2,3", 6484 "EventName": "OCR.PF_L2_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS", 6485 "MSRIndex": "0x1a6,0x1a7", 6486 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6487 "SampleAfterValue": "100003", 6488 "CounterHTOff": "0,1,2,3" 6489 }, 6490 { 6491 "Offcore": "1", 6492 "EventCode": "0xB7, 0xBB", 6493 "UMask": "0x1", 6494 "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs TBD", 6495 "MSRValue": "0x0404000020", 6496 "Counter": "0,1,2,3", 6497 "EventName": "OCR.PF_L2_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD", 6498 "MSRIndex": "0x1a6,0x1a7", 6499 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6500 "SampleAfterValue": "100003", 6501 "CounterHTOff": "0,1,2,3" 6502 }, 6503 { 6504 "Offcore": "1", 6505 "EventCode": "0xB7, 0xBB", 6506 "UMask": "0x1", 6507 "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs TBD", 6508 "MSRValue": "0x0804000020", 6509 "Counter": "0,1,2,3", 6510 "EventName": "OCR.PF_L2_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD", 6511 "MSRIndex": "0x1a6,0x1a7", 6512 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6513 "SampleAfterValue": "100003", 6514 "CounterHTOff": "0,1,2,3" 6515 }, 6516 { 6517 "Offcore": "1", 6518 "EventCode": "0xB7, 0xBB", 6519 "UMask": "0x1", 6520 "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs TBD", 6521 "MSRValue": "0x1004000020", 6522 "Counter": "0,1,2,3", 6523 "EventName": "OCR.PF_L2_RFO.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE", 6524 "MSRIndex": "0x1a6,0x1a7", 6525 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6526 "SampleAfterValue": "100003", 6527 "CounterHTOff": "0,1,2,3" 6528 }, 6529 { 6530 "Offcore": "1", 6531 "EventCode": "0xB7, 0xBB", 6532 "UMask": "0x1", 6533 "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs TBD", 6534 "MSRValue": "0x3F84000020", 6535 "Counter": "0,1,2,3", 6536 "EventName": "OCR.PF_L2_RFO.L3_MISS_LOCAL_DRAM.ANY_SNOOP", 6537 "MSRIndex": "0x1a6,0x1a7", 6538 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6539 "SampleAfterValue": "100003", 6540 "CounterHTOff": "0,1,2,3" 6541 }, 6542 { 6543 "Offcore": "1", 6544 "EventCode": "0xB7, 0xBB", 6545 "UMask": "0x1", 6546 "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs", 6547 "MSRValue": "0x0090000020", 6548 "Counter": "0,1,2,3", 6549 "EventName": "OCR.PF_L2_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE", 6550 "MSRIndex": "0x1a6,0x1a7", 6551 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6552 "SampleAfterValue": "100003", 6553 "CounterHTOff": "0,1,2,3" 6554 }, 6555 { 6556 "Offcore": "1", 6557 "EventCode": "0xB7, 0xBB", 6558 "UMask": "0x1", 6559 "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs TBD", 6560 "MSRValue": "0x0110000020", 6561 "Counter": "0,1,2,3", 6562 "EventName": "OCR.PF_L2_RFO.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED", 6563 "MSRIndex": "0x1a6,0x1a7", 6564 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6565 "SampleAfterValue": "100003", 6566 "CounterHTOff": "0,1,2,3" 6567 }, 6568 { 6569 "Offcore": "1", 6570 "EventCode": "0xB7, 0xBB", 6571 "UMask": "0x1", 6572 "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs", 6573 "MSRValue": "0x0210000020", 6574 "Counter": "0,1,2,3", 6575 "EventName": "OCR.PF_L2_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS", 6576 "MSRIndex": "0x1a6,0x1a7", 6577 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6578 "SampleAfterValue": "100003", 6579 "CounterHTOff": "0,1,2,3" 6580 }, 6581 { 6582 "Offcore": "1", 6583 "EventCode": "0xB7, 0xBB", 6584 "UMask": "0x1", 6585 "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs TBD", 6586 "MSRValue": "0x0410000020", 6587 "Counter": "0,1,2,3", 6588 "EventName": "OCR.PF_L2_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD", 6589 "MSRIndex": "0x1a6,0x1a7", 6590 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6591 "SampleAfterValue": "100003", 6592 "CounterHTOff": "0,1,2,3" 6593 }, 6594 { 6595 "Offcore": "1", 6596 "EventCode": "0xB7, 0xBB", 6597 "UMask": "0x1", 6598 "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs TBD", 6599 "MSRValue": "0x0810000020", 6600 "Counter": "0,1,2,3", 6601 "EventName": "OCR.PF_L2_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD", 6602 "MSRIndex": "0x1a6,0x1a7", 6603 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6604 "SampleAfterValue": "100003", 6605 "CounterHTOff": "0,1,2,3" 6606 }, 6607 { 6608 "Offcore": "1", 6609 "EventCode": "0xB7, 0xBB", 6610 "UMask": "0x1", 6611 "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs TBD", 6612 "MSRValue": "0x1010000020", 6613 "Counter": "0,1,2,3", 6614 "EventName": "OCR.PF_L2_RFO.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE", 6615 "MSRIndex": "0x1a6,0x1a7", 6616 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6617 "SampleAfterValue": "100003", 6618 "CounterHTOff": "0,1,2,3" 6619 }, 6620 { 6621 "Offcore": "1", 6622 "EventCode": "0xB7, 0xBB", 6623 "UMask": "0x1", 6624 "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs TBD", 6625 "MSRValue": "0x3F90000020", 6626 "Counter": "0,1,2,3", 6627 "EventName": "OCR.PF_L2_RFO.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP", 6628 "MSRIndex": "0x1a6,0x1a7", 6629 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6630 "SampleAfterValue": "100003", 6631 "CounterHTOff": "0,1,2,3" 6632 }, 6633 { 6634 "Offcore": "1", 6635 "EventCode": "0xB7, 0xBB", 6636 "UMask": "0x1", 6637 "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs TBD", 6638 "MSRValue": "0x00BC000020", 6639 "Counter": "0,1,2,3", 6640 "EventName": "OCR.PF_L2_RFO.L3_MISS.SNOOP_NONE", 6641 "MSRIndex": "0x1a6,0x1a7", 6642 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6643 "SampleAfterValue": "100003", 6644 "CounterHTOff": "0,1,2,3" 6645 }, 6646 { 6647 "Offcore": "1", 6648 "EventCode": "0xB7, 0xBB", 6649 "UMask": "0x1", 6650 "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs TBD TBD", 6651 "MSRValue": "0x013C000020", 6652 "Counter": "0,1,2,3", 6653 "EventName": "OCR.PF_L2_RFO.L3_MISS.NO_SNOOP_NEEDED", 6654 "MSRIndex": "0x1a6,0x1a7", 6655 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6656 "SampleAfterValue": "100003", 6657 "CounterHTOff": "0,1,2,3" 6658 }, 6659 { 6660 "Offcore": "1", 6661 "EventCode": "0xB7, 0xBB", 6662 "UMask": "0x1", 6663 "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs TBD", 6664 "MSRValue": "0x023C000020", 6665 "Counter": "0,1,2,3", 6666 "EventName": "OCR.PF_L2_RFO.L3_MISS.SNOOP_MISS", 6667 "MSRIndex": "0x1a6,0x1a7", 6668 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6669 "SampleAfterValue": "100003", 6670 "CounterHTOff": "0,1,2,3" 6671 }, 6672 { 6673 "Offcore": "1", 6674 "EventCode": "0xB7, 0xBB", 6675 "UMask": "0x1", 6676 "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs TBD TBD", 6677 "MSRValue": "0x043C000020", 6678 "Counter": "0,1,2,3", 6679 "EventName": "OCR.PF_L2_RFO.L3_MISS.HIT_OTHER_CORE_NO_FWD", 6680 "MSRIndex": "0x1a6,0x1a7", 6681 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6682 "SampleAfterValue": "100003", 6683 "CounterHTOff": "0,1,2,3" 6684 }, 6685 { 6686 "Offcore": "1", 6687 "EventCode": "0xB7, 0xBB", 6688 "UMask": "0x1", 6689 "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs TBD TBD", 6690 "MSRValue": "0x083C000020", 6691 "Counter": "0,1,2,3", 6692 "EventName": "OCR.PF_L2_RFO.L3_MISS.HIT_OTHER_CORE_FWD", 6693 "MSRIndex": "0x1a6,0x1a7", 6694 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6695 "SampleAfterValue": "100003", 6696 "CounterHTOff": "0,1,2,3" 6697 }, 6698 { 6699 "Offcore": "1", 6700 "EventCode": "0xB7, 0xBB", 6701 "UMask": "0x1", 6702 "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs TBD TBD", 6703 "MSRValue": "0x103C000020", 6704 "Counter": "0,1,2,3", 6705 "EventName": "OCR.PF_L2_RFO.L3_MISS.HITM_OTHER_CORE", 6706 "MSRIndex": "0x1a6,0x1a7", 6707 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6708 "SampleAfterValue": "100003", 6709 "CounterHTOff": "0,1,2,3" 6710 }, 6711 { 6712 "Offcore": "1", 6713 "EventCode": "0xB7, 0xBB", 6714 "UMask": "0x1", 6715 "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs TBD TBD", 6716 "MSRValue": "0x3FBC000020", 6717 "Counter": "0,1,2,3", 6718 "EventName": "OCR.PF_L2_RFO.L3_MISS.ANY_SNOOP", 6719 "MSRIndex": "0x1a6,0x1a7", 6720 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6721 "SampleAfterValue": "100003", 6722 "CounterHTOff": "0,1,2,3" 6723 }, 6724 { 6725 "Offcore": "1", 6726 "EventCode": "0xB7, 0xBB", 6727 "UMask": "0x1", 6728 "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads", 6729 "MSRValue": "0x0084000080", 6730 "Counter": "0,1,2,3", 6731 "EventName": "OCR.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NONE", 6732 "MSRIndex": "0x1a6,0x1a7", 6733 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6734 "SampleAfterValue": "100003", 6735 "CounterHTOff": "0,1,2,3" 6736 }, 6737 { 6738 "Offcore": "1", 6739 "EventCode": "0xB7, 0xBB", 6740 "UMask": "0x1", 6741 "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads TBD", 6742 "MSRValue": "0x0104000080", 6743 "Counter": "0,1,2,3", 6744 "EventName": "OCR.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED", 6745 "MSRIndex": "0x1a6,0x1a7", 6746 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6747 "SampleAfterValue": "100003", 6748 "CounterHTOff": "0,1,2,3" 6749 }, 6750 { 6751 "Offcore": "1", 6752 "EventCode": "0xB7, 0xBB", 6753 "UMask": "0x1", 6754 "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads", 6755 "MSRValue": "0x0204000080", 6756 "Counter": "0,1,2,3", 6757 "EventName": "OCR.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS", 6758 "MSRIndex": "0x1a6,0x1a7", 6759 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6760 "SampleAfterValue": "100003", 6761 "CounterHTOff": "0,1,2,3" 6762 }, 6763 { 6764 "Offcore": "1", 6765 "EventCode": "0xB7, 0xBB", 6766 "UMask": "0x1", 6767 "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads TBD", 6768 "MSRValue": "0x0404000080", 6769 "Counter": "0,1,2,3", 6770 "EventName": "OCR.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD", 6771 "MSRIndex": "0x1a6,0x1a7", 6772 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6773 "SampleAfterValue": "100003", 6774 "CounterHTOff": "0,1,2,3" 6775 }, 6776 { 6777 "Offcore": "1", 6778 "EventCode": "0xB7, 0xBB", 6779 "UMask": "0x1", 6780 "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads TBD", 6781 "MSRValue": "0x0804000080", 6782 "Counter": "0,1,2,3", 6783 "EventName": "OCR.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD", 6784 "MSRIndex": "0x1a6,0x1a7", 6785 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6786 "SampleAfterValue": "100003", 6787 "CounterHTOff": "0,1,2,3" 6788 }, 6789 { 6790 "Offcore": "1", 6791 "EventCode": "0xB7, 0xBB", 6792 "UMask": "0x1", 6793 "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads TBD", 6794 "MSRValue": "0x1004000080", 6795 "Counter": "0,1,2,3", 6796 "EventName": "OCR.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE", 6797 "MSRIndex": "0x1a6,0x1a7", 6798 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6799 "SampleAfterValue": "100003", 6800 "CounterHTOff": "0,1,2,3" 6801 }, 6802 { 6803 "Offcore": "1", 6804 "EventCode": "0xB7, 0xBB", 6805 "UMask": "0x1", 6806 "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads TBD", 6807 "MSRValue": "0x3F84000080", 6808 "Counter": "0,1,2,3", 6809 "EventName": "OCR.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP", 6810 "MSRIndex": "0x1a6,0x1a7", 6811 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6812 "SampleAfterValue": "100003", 6813 "CounterHTOff": "0,1,2,3" 6814 }, 6815 { 6816 "Offcore": "1", 6817 "EventCode": "0xB7, 0xBB", 6818 "UMask": "0x1", 6819 "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads", 6820 "MSRValue": "0x0090000080", 6821 "Counter": "0,1,2,3", 6822 "EventName": "OCR.PF_L3_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE", 6823 "MSRIndex": "0x1a6,0x1a7", 6824 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6825 "SampleAfterValue": "100003", 6826 "CounterHTOff": "0,1,2,3" 6827 }, 6828 { 6829 "Offcore": "1", 6830 "EventCode": "0xB7, 0xBB", 6831 "UMask": "0x1", 6832 "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads TBD", 6833 "MSRValue": "0x0110000080", 6834 "Counter": "0,1,2,3", 6835 "EventName": "OCR.PF_L3_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED", 6836 "MSRIndex": "0x1a6,0x1a7", 6837 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6838 "SampleAfterValue": "100003", 6839 "CounterHTOff": "0,1,2,3" 6840 }, 6841 { 6842 "Offcore": "1", 6843 "EventCode": "0xB7, 0xBB", 6844 "UMask": "0x1", 6845 "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads", 6846 "MSRValue": "0x0210000080", 6847 "Counter": "0,1,2,3", 6848 "EventName": "OCR.PF_L3_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS", 6849 "MSRIndex": "0x1a6,0x1a7", 6850 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6851 "SampleAfterValue": "100003", 6852 "CounterHTOff": "0,1,2,3" 6853 }, 6854 { 6855 "Offcore": "1", 6856 "EventCode": "0xB7, 0xBB", 6857 "UMask": "0x1", 6858 "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads TBD", 6859 "MSRValue": "0x0410000080", 6860 "Counter": "0,1,2,3", 6861 "EventName": "OCR.PF_L3_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD", 6862 "MSRIndex": "0x1a6,0x1a7", 6863 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6864 "SampleAfterValue": "100003", 6865 "CounterHTOff": "0,1,2,3" 6866 }, 6867 { 6868 "Offcore": "1", 6869 "EventCode": "0xB7, 0xBB", 6870 "UMask": "0x1", 6871 "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads TBD", 6872 "MSRValue": "0x0810000080", 6873 "Counter": "0,1,2,3", 6874 "EventName": "OCR.PF_L3_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD", 6875 "MSRIndex": "0x1a6,0x1a7", 6876 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6877 "SampleAfterValue": "100003", 6878 "CounterHTOff": "0,1,2,3" 6879 }, 6880 { 6881 "Offcore": "1", 6882 "EventCode": "0xB7, 0xBB", 6883 "UMask": "0x1", 6884 "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads TBD", 6885 "MSRValue": "0x1010000080", 6886 "Counter": "0,1,2,3", 6887 "EventName": "OCR.PF_L3_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE", 6888 "MSRIndex": "0x1a6,0x1a7", 6889 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6890 "SampleAfterValue": "100003", 6891 "CounterHTOff": "0,1,2,3" 6892 }, 6893 { 6894 "Offcore": "1", 6895 "EventCode": "0xB7, 0xBB", 6896 "UMask": "0x1", 6897 "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads TBD", 6898 "MSRValue": "0x3F90000080", 6899 "Counter": "0,1,2,3", 6900 "EventName": "OCR.PF_L3_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP", 6901 "MSRIndex": "0x1a6,0x1a7", 6902 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6903 "SampleAfterValue": "100003", 6904 "CounterHTOff": "0,1,2,3" 6905 }, 6906 { 6907 "Offcore": "1", 6908 "EventCode": "0xB7, 0xBB", 6909 "UMask": "0x1", 6910 "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads TBD", 6911 "MSRValue": "0x00BC000080", 6912 "Counter": "0,1,2,3", 6913 "EventName": "OCR.PF_L3_DATA_RD.L3_MISS.SNOOP_NONE", 6914 "MSRIndex": "0x1a6,0x1a7", 6915 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6916 "SampleAfterValue": "100003", 6917 "CounterHTOff": "0,1,2,3" 6918 }, 6919 { 6920 "Offcore": "1", 6921 "EventCode": "0xB7, 0xBB", 6922 "UMask": "0x1", 6923 "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads TBD TBD", 6924 "MSRValue": "0x013C000080", 6925 "Counter": "0,1,2,3", 6926 "EventName": "OCR.PF_L3_DATA_RD.L3_MISS.NO_SNOOP_NEEDED", 6927 "MSRIndex": "0x1a6,0x1a7", 6928 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6929 "SampleAfterValue": "100003", 6930 "CounterHTOff": "0,1,2,3" 6931 }, 6932 { 6933 "Offcore": "1", 6934 "EventCode": "0xB7, 0xBB", 6935 "UMask": "0x1", 6936 "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads TBD", 6937 "MSRValue": "0x023C000080", 6938 "Counter": "0,1,2,3", 6939 "EventName": "OCR.PF_L3_DATA_RD.L3_MISS.SNOOP_MISS", 6940 "MSRIndex": "0x1a6,0x1a7", 6941 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6942 "SampleAfterValue": "100003", 6943 "CounterHTOff": "0,1,2,3" 6944 }, 6945 { 6946 "Offcore": "1", 6947 "EventCode": "0xB7, 0xBB", 6948 "UMask": "0x1", 6949 "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads TBD TBD", 6950 "MSRValue": "0x043C000080", 6951 "Counter": "0,1,2,3", 6952 "EventName": "OCR.PF_L3_DATA_RD.L3_MISS.HIT_OTHER_CORE_NO_FWD", 6953 "MSRIndex": "0x1a6,0x1a7", 6954 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6955 "SampleAfterValue": "100003", 6956 "CounterHTOff": "0,1,2,3" 6957 }, 6958 { 6959 "Offcore": "1", 6960 "EventCode": "0xB7, 0xBB", 6961 "UMask": "0x1", 6962 "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads TBD TBD", 6963 "MSRValue": "0x083C000080", 6964 "Counter": "0,1,2,3", 6965 "EventName": "OCR.PF_L3_DATA_RD.L3_MISS.HIT_OTHER_CORE_FWD", 6966 "MSRIndex": "0x1a6,0x1a7", 6967 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6968 "SampleAfterValue": "100003", 6969 "CounterHTOff": "0,1,2,3" 6970 }, 6971 { 6972 "Offcore": "1", 6973 "EventCode": "0xB7, 0xBB", 6974 "UMask": "0x1", 6975 "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads TBD TBD", 6976 "MSRValue": "0x103C000080", 6977 "Counter": "0,1,2,3", 6978 "EventName": "OCR.PF_L3_DATA_RD.L3_MISS.HITM_OTHER_CORE", 6979 "MSRIndex": "0x1a6,0x1a7", 6980 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6981 "SampleAfterValue": "100003", 6982 "CounterHTOff": "0,1,2,3" 6983 }, 6984 { 6985 "Offcore": "1", 6986 "EventCode": "0xB7, 0xBB", 6987 "UMask": "0x1", 6988 "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads TBD TBD", 6989 "MSRValue": "0x3FBC000080", 6990 "Counter": "0,1,2,3", 6991 "EventName": "OCR.PF_L3_DATA_RD.L3_MISS.ANY_SNOOP", 6992 "MSRIndex": "0x1a6,0x1a7", 6993 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6994 "SampleAfterValue": "100003", 6995 "CounterHTOff": "0,1,2,3" 6996 }, 6997 { 6998 "Offcore": "1", 6999 "EventCode": "0xB7, 0xBB", 7000 "UMask": "0x1", 7001 "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs", 7002 "MSRValue": "0x0084000100", 7003 "Counter": "0,1,2,3", 7004 "EventName": "OCR.PF_L3_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NONE", 7005 "MSRIndex": "0x1a6,0x1a7", 7006 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7007 "SampleAfterValue": "100003", 7008 "CounterHTOff": "0,1,2,3" 7009 }, 7010 { 7011 "Offcore": "1", 7012 "EventCode": "0xB7, 0xBB", 7013 "UMask": "0x1", 7014 "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs TBD", 7015 "MSRValue": "0x0104000100", 7016 "Counter": "0,1,2,3", 7017 "EventName": "OCR.PF_L3_RFO.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED", 7018 "MSRIndex": "0x1a6,0x1a7", 7019 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7020 "SampleAfterValue": "100003", 7021 "CounterHTOff": "0,1,2,3" 7022 }, 7023 { 7024 "Offcore": "1", 7025 "EventCode": "0xB7, 0xBB", 7026 "UMask": "0x1", 7027 "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs", 7028 "MSRValue": "0x0204000100", 7029 "Counter": "0,1,2,3", 7030 "EventName": "OCR.PF_L3_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS", 7031 "MSRIndex": "0x1a6,0x1a7", 7032 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7033 "SampleAfterValue": "100003", 7034 "CounterHTOff": "0,1,2,3" 7035 }, 7036 { 7037 "Offcore": "1", 7038 "EventCode": "0xB7, 0xBB", 7039 "UMask": "0x1", 7040 "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs TBD", 7041 "MSRValue": "0x0404000100", 7042 "Counter": "0,1,2,3", 7043 "EventName": "OCR.PF_L3_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD", 7044 "MSRIndex": "0x1a6,0x1a7", 7045 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7046 "SampleAfterValue": "100003", 7047 "CounterHTOff": "0,1,2,3" 7048 }, 7049 { 7050 "Offcore": "1", 7051 "EventCode": "0xB7, 0xBB", 7052 "UMask": "0x1", 7053 "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs TBD", 7054 "MSRValue": "0x0804000100", 7055 "Counter": "0,1,2,3", 7056 "EventName": "OCR.PF_L3_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD", 7057 "MSRIndex": "0x1a6,0x1a7", 7058 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7059 "SampleAfterValue": "100003", 7060 "CounterHTOff": "0,1,2,3" 7061 }, 7062 { 7063 "Offcore": "1", 7064 "EventCode": "0xB7, 0xBB", 7065 "UMask": "0x1", 7066 "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs TBD", 7067 "MSRValue": "0x1004000100", 7068 "Counter": "0,1,2,3", 7069 "EventName": "OCR.PF_L3_RFO.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE", 7070 "MSRIndex": "0x1a6,0x1a7", 7071 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7072 "SampleAfterValue": "100003", 7073 "CounterHTOff": "0,1,2,3" 7074 }, 7075 { 7076 "Offcore": "1", 7077 "EventCode": "0xB7, 0xBB", 7078 "UMask": "0x1", 7079 "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs TBD", 7080 "MSRValue": "0x3F84000100", 7081 "Counter": "0,1,2,3", 7082 "EventName": "OCR.PF_L3_RFO.L3_MISS_LOCAL_DRAM.ANY_SNOOP", 7083 "MSRIndex": "0x1a6,0x1a7", 7084 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7085 "SampleAfterValue": "100003", 7086 "CounterHTOff": "0,1,2,3" 7087 }, 7088 { 7089 "Offcore": "1", 7090 "EventCode": "0xB7, 0xBB", 7091 "UMask": "0x1", 7092 "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs", 7093 "MSRValue": "0x0090000100", 7094 "Counter": "0,1,2,3", 7095 "EventName": "OCR.PF_L3_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE", 7096 "MSRIndex": "0x1a6,0x1a7", 7097 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7098 "SampleAfterValue": "100003", 7099 "CounterHTOff": "0,1,2,3" 7100 }, 7101 { 7102 "Offcore": "1", 7103 "EventCode": "0xB7, 0xBB", 7104 "UMask": "0x1", 7105 "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs TBD", 7106 "MSRValue": "0x0110000100", 7107 "Counter": "0,1,2,3", 7108 "EventName": "OCR.PF_L3_RFO.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED", 7109 "MSRIndex": "0x1a6,0x1a7", 7110 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7111 "SampleAfterValue": "100003", 7112 "CounterHTOff": "0,1,2,3" 7113 }, 7114 { 7115 "Offcore": "1", 7116 "EventCode": "0xB7, 0xBB", 7117 "UMask": "0x1", 7118 "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs", 7119 "MSRValue": "0x0210000100", 7120 "Counter": "0,1,2,3", 7121 "EventName": "OCR.PF_L3_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS", 7122 "MSRIndex": "0x1a6,0x1a7", 7123 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7124 "SampleAfterValue": "100003", 7125 "CounterHTOff": "0,1,2,3" 7126 }, 7127 { 7128 "Offcore": "1", 7129 "EventCode": "0xB7, 0xBB", 7130 "UMask": "0x1", 7131 "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs TBD", 7132 "MSRValue": "0x0410000100", 7133 "Counter": "0,1,2,3", 7134 "EventName": "OCR.PF_L3_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD", 7135 "MSRIndex": "0x1a6,0x1a7", 7136 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7137 "SampleAfterValue": "100003", 7138 "CounterHTOff": "0,1,2,3" 7139 }, 7140 { 7141 "Offcore": "1", 7142 "EventCode": "0xB7, 0xBB", 7143 "UMask": "0x1", 7144 "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs TBD", 7145 "MSRValue": "0x0810000100", 7146 "Counter": "0,1,2,3", 7147 "EventName": "OCR.PF_L3_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD", 7148 "MSRIndex": "0x1a6,0x1a7", 7149 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7150 "SampleAfterValue": "100003", 7151 "CounterHTOff": "0,1,2,3" 7152 }, 7153 { 7154 "Offcore": "1", 7155 "EventCode": "0xB7, 0xBB", 7156 "UMask": "0x1", 7157 "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs TBD", 7158 "MSRValue": "0x1010000100", 7159 "Counter": "0,1,2,3", 7160 "EventName": "OCR.PF_L3_RFO.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE", 7161 "MSRIndex": "0x1a6,0x1a7", 7162 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7163 "SampleAfterValue": "100003", 7164 "CounterHTOff": "0,1,2,3" 7165 }, 7166 { 7167 "Offcore": "1", 7168 "EventCode": "0xB7, 0xBB", 7169 "UMask": "0x1", 7170 "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs TBD", 7171 "MSRValue": "0x3F90000100", 7172 "Counter": "0,1,2,3", 7173 "EventName": "OCR.PF_L3_RFO.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP", 7174 "MSRIndex": "0x1a6,0x1a7", 7175 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7176 "SampleAfterValue": "100003", 7177 "CounterHTOff": "0,1,2,3" 7178 }, 7179 { 7180 "Offcore": "1", 7181 "EventCode": "0xB7, 0xBB", 7182 "UMask": "0x1", 7183 "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs TBD", 7184 "MSRValue": "0x00BC000100", 7185 "Counter": "0,1,2,3", 7186 "EventName": "OCR.PF_L3_RFO.L3_MISS.SNOOP_NONE", 7187 "MSRIndex": "0x1a6,0x1a7", 7188 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7189 "SampleAfterValue": "100003", 7190 "CounterHTOff": "0,1,2,3" 7191 }, 7192 { 7193 "Offcore": "1", 7194 "EventCode": "0xB7, 0xBB", 7195 "UMask": "0x1", 7196 "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs TBD TBD", 7197 "MSRValue": "0x013C000100", 7198 "Counter": "0,1,2,3", 7199 "EventName": "OCR.PF_L3_RFO.L3_MISS.NO_SNOOP_NEEDED", 7200 "MSRIndex": "0x1a6,0x1a7", 7201 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7202 "SampleAfterValue": "100003", 7203 "CounterHTOff": "0,1,2,3" 7204 }, 7205 { 7206 "Offcore": "1", 7207 "EventCode": "0xB7, 0xBB", 7208 "UMask": "0x1", 7209 "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs TBD", 7210 "MSRValue": "0x023C000100", 7211 "Counter": "0,1,2,3", 7212 "EventName": "OCR.PF_L3_RFO.L3_MISS.SNOOP_MISS", 7213 "MSRIndex": "0x1a6,0x1a7", 7214 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7215 "SampleAfterValue": "100003", 7216 "CounterHTOff": "0,1,2,3" 7217 }, 7218 { 7219 "Offcore": "1", 7220 "EventCode": "0xB7, 0xBB", 7221 "UMask": "0x1", 7222 "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs TBD TBD", 7223 "MSRValue": "0x043C000100", 7224 "Counter": "0,1,2,3", 7225 "EventName": "OCR.PF_L3_RFO.L3_MISS.HIT_OTHER_CORE_NO_FWD", 7226 "MSRIndex": "0x1a6,0x1a7", 7227 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7228 "SampleAfterValue": "100003", 7229 "CounterHTOff": "0,1,2,3" 7230 }, 7231 { 7232 "Offcore": "1", 7233 "EventCode": "0xB7, 0xBB", 7234 "UMask": "0x1", 7235 "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs TBD TBD", 7236 "MSRValue": "0x083C000100", 7237 "Counter": "0,1,2,3", 7238 "EventName": "OCR.PF_L3_RFO.L3_MISS.HIT_OTHER_CORE_FWD", 7239 "MSRIndex": "0x1a6,0x1a7", 7240 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7241 "SampleAfterValue": "100003", 7242 "CounterHTOff": "0,1,2,3" 7243 }, 7244 { 7245 "Offcore": "1", 7246 "EventCode": "0xB7, 0xBB", 7247 "UMask": "0x1", 7248 "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs TBD TBD", 7249 "MSRValue": "0x103C000100", 7250 "Counter": "0,1,2,3", 7251 "EventName": "OCR.PF_L3_RFO.L3_MISS.HITM_OTHER_CORE", 7252 "MSRIndex": "0x1a6,0x1a7", 7253 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7254 "SampleAfterValue": "100003", 7255 "CounterHTOff": "0,1,2,3" 7256 }, 7257 { 7258 "Offcore": "1", 7259 "EventCode": "0xB7, 0xBB", 7260 "UMask": "0x1", 7261 "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs TBD TBD", 7262 "MSRValue": "0x3FBC000100", 7263 "Counter": "0,1,2,3", 7264 "EventName": "OCR.PF_L3_RFO.L3_MISS.ANY_SNOOP", 7265 "MSRIndex": "0x1a6,0x1a7", 7266 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7267 "SampleAfterValue": "100003", 7268 "CounterHTOff": "0,1,2,3" 7269 }, 7270 { 7271 "Offcore": "1", 7272 "EventCode": "0xB7, 0xBB", 7273 "UMask": "0x1", 7274 "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests", 7275 "MSRValue": "0x0084000400", 7276 "Counter": "0,1,2,3", 7277 "EventName": "OCR.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.SNOOP_NONE", 7278 "MSRIndex": "0x1a6,0x1a7", 7279 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7280 "SampleAfterValue": "100003", 7281 "CounterHTOff": "0,1,2,3" 7282 }, 7283 { 7284 "Offcore": "1", 7285 "EventCode": "0xB7, 0xBB", 7286 "UMask": "0x1", 7287 "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests TBD", 7288 "MSRValue": "0x0104000400", 7289 "Counter": "0,1,2,3", 7290 "EventName": "OCR.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED", 7291 "MSRIndex": "0x1a6,0x1a7", 7292 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7293 "SampleAfterValue": "100003", 7294 "CounterHTOff": "0,1,2,3" 7295 }, 7296 { 7297 "Offcore": "1", 7298 "EventCode": "0xB7, 0xBB", 7299 "UMask": "0x1", 7300 "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests", 7301 "MSRValue": "0x0204000400", 7302 "Counter": "0,1,2,3", 7303 "EventName": "OCR.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.SNOOP_MISS", 7304 "MSRIndex": "0x1a6,0x1a7", 7305 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7306 "SampleAfterValue": "100003", 7307 "CounterHTOff": "0,1,2,3" 7308 }, 7309 { 7310 "Offcore": "1", 7311 "EventCode": "0xB7, 0xBB", 7312 "UMask": "0x1", 7313 "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests TBD", 7314 "MSRValue": "0x0404000400", 7315 "Counter": "0,1,2,3", 7316 "EventName": "OCR.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD", 7317 "MSRIndex": "0x1a6,0x1a7", 7318 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7319 "SampleAfterValue": "100003", 7320 "CounterHTOff": "0,1,2,3" 7321 }, 7322 { 7323 "Offcore": "1", 7324 "EventCode": "0xB7, 0xBB", 7325 "UMask": "0x1", 7326 "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests TBD", 7327 "MSRValue": "0x0804000400", 7328 "Counter": "0,1,2,3", 7329 "EventName": "OCR.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD", 7330 "MSRIndex": "0x1a6,0x1a7", 7331 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7332 "SampleAfterValue": "100003", 7333 "CounterHTOff": "0,1,2,3" 7334 }, 7335 { 7336 "Offcore": "1", 7337 "EventCode": "0xB7, 0xBB", 7338 "UMask": "0x1", 7339 "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests TBD", 7340 "MSRValue": "0x1004000400", 7341 "Counter": "0,1,2,3", 7342 "EventName": "OCR.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE", 7343 "MSRIndex": "0x1a6,0x1a7", 7344 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7345 "SampleAfterValue": "100003", 7346 "CounterHTOff": "0,1,2,3" 7347 }, 7348 { 7349 "Offcore": "1", 7350 "EventCode": "0xB7, 0xBB", 7351 "UMask": "0x1", 7352 "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests TBD", 7353 "MSRValue": "0x3F84000400", 7354 "Counter": "0,1,2,3", 7355 "EventName": "OCR.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.ANY_SNOOP", 7356 "MSRIndex": "0x1a6,0x1a7", 7357 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7358 "SampleAfterValue": "100003", 7359 "CounterHTOff": "0,1,2,3" 7360 }, 7361 { 7362 "Offcore": "1", 7363 "EventCode": "0xB7, 0xBB", 7364 "UMask": "0x1", 7365 "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests", 7366 "MSRValue": "0x0090000400", 7367 "Counter": "0,1,2,3", 7368 "EventName": "OCR.PF_L1D_AND_SW.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE", 7369 "MSRIndex": "0x1a6,0x1a7", 7370 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7371 "SampleAfterValue": "100003", 7372 "CounterHTOff": "0,1,2,3" 7373 }, 7374 { 7375 "Offcore": "1", 7376 "EventCode": "0xB7, 0xBB", 7377 "UMask": "0x1", 7378 "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests TBD", 7379 "MSRValue": "0x0110000400", 7380 "Counter": "0,1,2,3", 7381 "EventName": "OCR.PF_L1D_AND_SW.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED", 7382 "MSRIndex": "0x1a6,0x1a7", 7383 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7384 "SampleAfterValue": "100003", 7385 "CounterHTOff": "0,1,2,3" 7386 }, 7387 { 7388 "Offcore": "1", 7389 "EventCode": "0xB7, 0xBB", 7390 "UMask": "0x1", 7391 "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests", 7392 "MSRValue": "0x0210000400", 7393 "Counter": "0,1,2,3", 7394 "EventName": "OCR.PF_L1D_AND_SW.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS", 7395 "MSRIndex": "0x1a6,0x1a7", 7396 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7397 "SampleAfterValue": "100003", 7398 "CounterHTOff": "0,1,2,3" 7399 }, 7400 { 7401 "Offcore": "1", 7402 "EventCode": "0xB7, 0xBB", 7403 "UMask": "0x1", 7404 "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests TBD", 7405 "MSRValue": "0x0410000400", 7406 "Counter": "0,1,2,3", 7407 "EventName": "OCR.PF_L1D_AND_SW.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD", 7408 "MSRIndex": "0x1a6,0x1a7", 7409 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7410 "SampleAfterValue": "100003", 7411 "CounterHTOff": "0,1,2,3" 7412 }, 7413 { 7414 "Offcore": "1", 7415 "EventCode": "0xB7, 0xBB", 7416 "UMask": "0x1", 7417 "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests TBD", 7418 "MSRValue": "0x0810000400", 7419 "Counter": "0,1,2,3", 7420 "EventName": "OCR.PF_L1D_AND_SW.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD", 7421 "MSRIndex": "0x1a6,0x1a7", 7422 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7423 "SampleAfterValue": "100003", 7424 "CounterHTOff": "0,1,2,3" 7425 }, 7426 { 7427 "Offcore": "1", 7428 "EventCode": "0xB7, 0xBB", 7429 "UMask": "0x1", 7430 "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests TBD", 7431 "MSRValue": "0x1010000400", 7432 "Counter": "0,1,2,3", 7433 "EventName": "OCR.PF_L1D_AND_SW.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE", 7434 "MSRIndex": "0x1a6,0x1a7", 7435 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7436 "SampleAfterValue": "100003", 7437 "CounterHTOff": "0,1,2,3" 7438 }, 7439 { 7440 "Offcore": "1", 7441 "EventCode": "0xB7, 0xBB", 7442 "UMask": "0x1", 7443 "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests TBD", 7444 "MSRValue": "0x3F90000400", 7445 "Counter": "0,1,2,3", 7446 "EventName": "OCR.PF_L1D_AND_SW.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP", 7447 "MSRIndex": "0x1a6,0x1a7", 7448 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7449 "SampleAfterValue": "100003", 7450 "CounterHTOff": "0,1,2,3" 7451 }, 7452 { 7453 "Offcore": "1", 7454 "EventCode": "0xB7, 0xBB", 7455 "UMask": "0x1", 7456 "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests TBD", 7457 "MSRValue": "0x00BC000400", 7458 "Counter": "0,1,2,3", 7459 "EventName": "OCR.PF_L1D_AND_SW.L3_MISS.SNOOP_NONE", 7460 "MSRIndex": "0x1a6,0x1a7", 7461 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7462 "SampleAfterValue": "100003", 7463 "CounterHTOff": "0,1,2,3" 7464 }, 7465 { 7466 "Offcore": "1", 7467 "EventCode": "0xB7, 0xBB", 7468 "UMask": "0x1", 7469 "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests TBD TBD", 7470 "MSRValue": "0x013C000400", 7471 "Counter": "0,1,2,3", 7472 "EventName": "OCR.PF_L1D_AND_SW.L3_MISS.NO_SNOOP_NEEDED", 7473 "MSRIndex": "0x1a6,0x1a7", 7474 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7475 "SampleAfterValue": "100003", 7476 "CounterHTOff": "0,1,2,3" 7477 }, 7478 { 7479 "Offcore": "1", 7480 "EventCode": "0xB7, 0xBB", 7481 "UMask": "0x1", 7482 "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests TBD", 7483 "MSRValue": "0x023C000400", 7484 "Counter": "0,1,2,3", 7485 "EventName": "OCR.PF_L1D_AND_SW.L3_MISS.SNOOP_MISS", 7486 "MSRIndex": "0x1a6,0x1a7", 7487 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7488 "SampleAfterValue": "100003", 7489 "CounterHTOff": "0,1,2,3" 7490 }, 7491 { 7492 "Offcore": "1", 7493 "EventCode": "0xB7, 0xBB", 7494 "UMask": "0x1", 7495 "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests TBD TBD", 7496 "MSRValue": "0x043C000400", 7497 "Counter": "0,1,2,3", 7498 "EventName": "OCR.PF_L1D_AND_SW.L3_MISS.HIT_OTHER_CORE_NO_FWD", 7499 "MSRIndex": "0x1a6,0x1a7", 7500 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7501 "SampleAfterValue": "100003", 7502 "CounterHTOff": "0,1,2,3" 7503 }, 7504 { 7505 "Offcore": "1", 7506 "EventCode": "0xB7, 0xBB", 7507 "UMask": "0x1", 7508 "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests TBD TBD", 7509 "MSRValue": "0x083C000400", 7510 "Counter": "0,1,2,3", 7511 "EventName": "OCR.PF_L1D_AND_SW.L3_MISS.HIT_OTHER_CORE_FWD", 7512 "MSRIndex": "0x1a6,0x1a7", 7513 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7514 "SampleAfterValue": "100003", 7515 "CounterHTOff": "0,1,2,3" 7516 }, 7517 { 7518 "Offcore": "1", 7519 "EventCode": "0xB7, 0xBB", 7520 "UMask": "0x1", 7521 "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests TBD TBD", 7522 "MSRValue": "0x103C000400", 7523 "Counter": "0,1,2,3", 7524 "EventName": "OCR.PF_L1D_AND_SW.L3_MISS.HITM_OTHER_CORE", 7525 "MSRIndex": "0x1a6,0x1a7", 7526 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7527 "SampleAfterValue": "100003", 7528 "CounterHTOff": "0,1,2,3" 7529 }, 7530 { 7531 "Offcore": "1", 7532 "EventCode": "0xB7, 0xBB", 7533 "UMask": "0x1", 7534 "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests TBD TBD", 7535 "MSRValue": "0x3FBC000400", 7536 "Counter": "0,1,2,3", 7537 "EventName": "OCR.PF_L1D_AND_SW.L3_MISS.ANY_SNOOP", 7538 "MSRIndex": "0x1a6,0x1a7", 7539 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7540 "SampleAfterValue": "100003", 7541 "CounterHTOff": "0,1,2,3" 7542 }, 7543 { 7544 "Offcore": "1", 7545 "EventCode": "0xB7, 0xBB", 7546 "UMask": "0x1", 7547 "BriefDescription": "Counts any other requests", 7548 "MSRValue": "0x0084008000", 7549 "Counter": "0,1,2,3", 7550 "EventName": "OCR.OTHER.L3_MISS_LOCAL_DRAM.SNOOP_NONE", 7551 "MSRIndex": "0x1a6,0x1a7", 7552 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7553 "SampleAfterValue": "100003", 7554 "CounterHTOff": "0,1,2,3" 7555 }, 7556 { 7557 "Offcore": "1", 7558 "EventCode": "0xB7, 0xBB", 7559 "UMask": "0x1", 7560 "BriefDescription": "Counts any other requests TBD", 7561 "MSRValue": "0x0104008000", 7562 "Counter": "0,1,2,3", 7563 "EventName": "OCR.OTHER.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED", 7564 "MSRIndex": "0x1a6,0x1a7", 7565 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7566 "SampleAfterValue": "100003", 7567 "CounterHTOff": "0,1,2,3" 7568 }, 7569 { 7570 "Offcore": "1", 7571 "EventCode": "0xB7, 0xBB", 7572 "UMask": "0x1", 7573 "BriefDescription": "Counts any other requests", 7574 "MSRValue": "0x0204008000", 7575 "Counter": "0,1,2,3", 7576 "EventName": "OCR.OTHER.L3_MISS_LOCAL_DRAM.SNOOP_MISS", 7577 "MSRIndex": "0x1a6,0x1a7", 7578 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7579 "SampleAfterValue": "100003", 7580 "CounterHTOff": "0,1,2,3" 7581 }, 7582 { 7583 "Offcore": "1", 7584 "EventCode": "0xB7, 0xBB", 7585 "UMask": "0x1", 7586 "BriefDescription": "Counts any other requests TBD", 7587 "MSRValue": "0x0404008000", 7588 "Counter": "0,1,2,3", 7589 "EventName": "OCR.OTHER.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD", 7590 "MSRIndex": "0x1a6,0x1a7", 7591 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7592 "SampleAfterValue": "100003", 7593 "CounterHTOff": "0,1,2,3" 7594 }, 7595 { 7596 "Offcore": "1", 7597 "EventCode": "0xB7, 0xBB", 7598 "UMask": "0x1", 7599 "BriefDescription": "Counts any other requests TBD", 7600 "MSRValue": "0x0804008000", 7601 "Counter": "0,1,2,3", 7602 "EventName": "OCR.OTHER.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD", 7603 "MSRIndex": "0x1a6,0x1a7", 7604 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7605 "SampleAfterValue": "100003", 7606 "CounterHTOff": "0,1,2,3" 7607 }, 7608 { 7609 "Offcore": "1", 7610 "EventCode": "0xB7, 0xBB", 7611 "UMask": "0x1", 7612 "BriefDescription": "Counts any other requests TBD", 7613 "MSRValue": "0x1004008000", 7614 "Counter": "0,1,2,3", 7615 "EventName": "OCR.OTHER.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE", 7616 "MSRIndex": "0x1a6,0x1a7", 7617 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7618 "SampleAfterValue": "100003", 7619 "CounterHTOff": "0,1,2,3" 7620 }, 7621 { 7622 "Offcore": "1", 7623 "EventCode": "0xB7, 0xBB", 7624 "UMask": "0x1", 7625 "BriefDescription": "Counts any other requests TBD", 7626 "MSRValue": "0x3F84008000", 7627 "Counter": "0,1,2,3", 7628 "EventName": "OCR.OTHER.L3_MISS_LOCAL_DRAM.ANY_SNOOP", 7629 "MSRIndex": "0x1a6,0x1a7", 7630 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7631 "SampleAfterValue": "100003", 7632 "CounterHTOff": "0,1,2,3" 7633 }, 7634 { 7635 "Offcore": "1", 7636 "EventCode": "0xB7, 0xBB", 7637 "UMask": "0x1", 7638 "BriefDescription": "Counts any other requests", 7639 "MSRValue": "0x0090008000", 7640 "Counter": "0,1,2,3", 7641 "EventName": "OCR.OTHER.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE", 7642 "MSRIndex": "0x1a6,0x1a7", 7643 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7644 "SampleAfterValue": "100003", 7645 "CounterHTOff": "0,1,2,3" 7646 }, 7647 { 7648 "Offcore": "1", 7649 "EventCode": "0xB7, 0xBB", 7650 "UMask": "0x1", 7651 "BriefDescription": "Counts any other requests TBD", 7652 "MSRValue": "0x0110008000", 7653 "Counter": "0,1,2,3", 7654 "EventName": "OCR.OTHER.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED", 7655 "MSRIndex": "0x1a6,0x1a7", 7656 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7657 "SampleAfterValue": "100003", 7658 "CounterHTOff": "0,1,2,3" 7659 }, 7660 { 7661 "Offcore": "1", 7662 "EventCode": "0xB7, 0xBB", 7663 "UMask": "0x1", 7664 "BriefDescription": "Counts any other requests", 7665 "MSRValue": "0x0210008000", 7666 "Counter": "0,1,2,3", 7667 "EventName": "OCR.OTHER.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS", 7668 "MSRIndex": "0x1a6,0x1a7", 7669 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7670 "SampleAfterValue": "100003", 7671 "CounterHTOff": "0,1,2,3" 7672 }, 7673 { 7674 "Offcore": "1", 7675 "EventCode": "0xB7, 0xBB", 7676 "UMask": "0x1", 7677 "BriefDescription": "Counts any other requests TBD", 7678 "MSRValue": "0x0410008000", 7679 "Counter": "0,1,2,3", 7680 "EventName": "OCR.OTHER.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD", 7681 "MSRIndex": "0x1a6,0x1a7", 7682 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7683 "SampleAfterValue": "100003", 7684 "CounterHTOff": "0,1,2,3" 7685 }, 7686 { 7687 "Offcore": "1", 7688 "EventCode": "0xB7, 0xBB", 7689 "UMask": "0x1", 7690 "BriefDescription": "Counts any other requests TBD", 7691 "MSRValue": "0x0810008000", 7692 "Counter": "0,1,2,3", 7693 "EventName": "OCR.OTHER.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD", 7694 "MSRIndex": "0x1a6,0x1a7", 7695 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7696 "SampleAfterValue": "100003", 7697 "CounterHTOff": "0,1,2,3" 7698 }, 7699 { 7700 "Offcore": "1", 7701 "EventCode": "0xB7, 0xBB", 7702 "UMask": "0x1", 7703 "BriefDescription": "Counts any other requests TBD", 7704 "MSRValue": "0x1010008000", 7705 "Counter": "0,1,2,3", 7706 "EventName": "OCR.OTHER.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE", 7707 "MSRIndex": "0x1a6,0x1a7", 7708 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7709 "SampleAfterValue": "100003", 7710 "CounterHTOff": "0,1,2,3" 7711 }, 7712 { 7713 "Offcore": "1", 7714 "EventCode": "0xB7, 0xBB", 7715 "UMask": "0x1", 7716 "BriefDescription": "Counts any other requests TBD", 7717 "MSRValue": "0x3F90008000", 7718 "Counter": "0,1,2,3", 7719 "EventName": "OCR.OTHER.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP", 7720 "MSRIndex": "0x1a6,0x1a7", 7721 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7722 "SampleAfterValue": "100003", 7723 "CounterHTOff": "0,1,2,3" 7724 }, 7725 { 7726 "Offcore": "1", 7727 "EventCode": "0xB7, 0xBB", 7728 "UMask": "0x1", 7729 "BriefDescription": "Counts any other requests TBD", 7730 "MSRValue": "0x00BC008000", 7731 "Counter": "0,1,2,3", 7732 "EventName": "OCR.OTHER.L3_MISS.SNOOP_NONE", 7733 "MSRIndex": "0x1a6,0x1a7", 7734 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7735 "SampleAfterValue": "100003", 7736 "CounterHTOff": "0,1,2,3" 7737 }, 7738 { 7739 "Offcore": "1", 7740 "EventCode": "0xB7, 0xBB", 7741 "UMask": "0x1", 7742 "BriefDescription": "Counts any other requests TBD TBD", 7743 "MSRValue": "0x013C008000", 7744 "Counter": "0,1,2,3", 7745 "EventName": "OCR.OTHER.L3_MISS.NO_SNOOP_NEEDED", 7746 "MSRIndex": "0x1a6,0x1a7", 7747 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7748 "SampleAfterValue": "100003", 7749 "CounterHTOff": "0,1,2,3" 7750 }, 7751 { 7752 "Offcore": "1", 7753 "EventCode": "0xB7, 0xBB", 7754 "UMask": "0x1", 7755 "BriefDescription": "Counts any other requests TBD", 7756 "MSRValue": "0x023C008000", 7757 "Counter": "0,1,2,3", 7758 "EventName": "OCR.OTHER.L3_MISS.SNOOP_MISS", 7759 "MSRIndex": "0x1a6,0x1a7", 7760 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7761 "SampleAfterValue": "100003", 7762 "CounterHTOff": "0,1,2,3" 7763 }, 7764 { 7765 "Offcore": "1", 7766 "EventCode": "0xB7, 0xBB", 7767 "UMask": "0x1", 7768 "BriefDescription": "Counts any other requests TBD TBD", 7769 "MSRValue": "0x043C008000", 7770 "Counter": "0,1,2,3", 7771 "EventName": "OCR.OTHER.L3_MISS.HIT_OTHER_CORE_NO_FWD", 7772 "MSRIndex": "0x1a6,0x1a7", 7773 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7774 "SampleAfterValue": "100003", 7775 "CounterHTOff": "0,1,2,3" 7776 }, 7777 { 7778 "Offcore": "1", 7779 "EventCode": "0xB7, 0xBB", 7780 "UMask": "0x1", 7781 "BriefDescription": "Counts any other requests TBD TBD", 7782 "MSRValue": "0x083C008000", 7783 "Counter": "0,1,2,3", 7784 "EventName": "OCR.OTHER.L3_MISS.HIT_OTHER_CORE_FWD", 7785 "MSRIndex": "0x1a6,0x1a7", 7786 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7787 "SampleAfterValue": "100003", 7788 "CounterHTOff": "0,1,2,3" 7789 }, 7790 { 7791 "Offcore": "1", 7792 "EventCode": "0xB7, 0xBB", 7793 "UMask": "0x1", 7794 "BriefDescription": "Counts any other requests TBD TBD", 7795 "MSRValue": "0x103C008000", 7796 "Counter": "0,1,2,3", 7797 "EventName": "OCR.OTHER.L3_MISS.HITM_OTHER_CORE", 7798 "MSRIndex": "0x1a6,0x1a7", 7799 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7800 "SampleAfterValue": "100003", 7801 "CounterHTOff": "0,1,2,3" 7802 }, 7803 { 7804 "Offcore": "1", 7805 "EventCode": "0xB7, 0xBB", 7806 "UMask": "0x1", 7807 "BriefDescription": "Counts any other requests TBD TBD", 7808 "MSRValue": "0x3FBC008000", 7809 "Counter": "0,1,2,3", 7810 "EventName": "OCR.OTHER.L3_MISS.ANY_SNOOP", 7811 "MSRIndex": "0x1a6,0x1a7", 7812 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7813 "SampleAfterValue": "100003", 7814 "CounterHTOff": "0,1,2,3" 7815 }, 7816 { 7817 "Offcore": "1", 7818 "EventCode": "0xB7, 0xBB", 7819 "UMask": "0x1", 7820 "BriefDescription": "TBD", 7821 "MSRValue": "0x0084000490", 7822 "Counter": "0,1,2,3", 7823 "EventName": "OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NONE", 7824 "MSRIndex": "0x1a6,0x1a7", 7825 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7826 "SampleAfterValue": "100003", 7827 "CounterHTOff": "0,1,2,3" 7828 }, 7829 { 7830 "Offcore": "1", 7831 "EventCode": "0xB7, 0xBB", 7832 "UMask": "0x1", 7833 "BriefDescription": "TBD TBD", 7834 "MSRValue": "0x0104000490", 7835 "Counter": "0,1,2,3", 7836 "EventName": "OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED", 7837 "MSRIndex": "0x1a6,0x1a7", 7838 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7839 "SampleAfterValue": "100003", 7840 "CounterHTOff": "0,1,2,3" 7841 }, 7842 { 7843 "Offcore": "1", 7844 "EventCode": "0xB7, 0xBB", 7845 "UMask": "0x1", 7846 "BriefDescription": "TBD", 7847 "MSRValue": "0x0204000490", 7848 "Counter": "0,1,2,3", 7849 "EventName": "OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS", 7850 "MSRIndex": "0x1a6,0x1a7", 7851 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7852 "SampleAfterValue": "100003", 7853 "CounterHTOff": "0,1,2,3" 7854 }, 7855 { 7856 "Offcore": "1", 7857 "EventCode": "0xB7, 0xBB", 7858 "UMask": "0x1", 7859 "BriefDescription": "TBD TBD", 7860 "MSRValue": "0x0404000490", 7861 "Counter": "0,1,2,3", 7862 "EventName": "OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD", 7863 "MSRIndex": "0x1a6,0x1a7", 7864 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7865 "SampleAfterValue": "100003", 7866 "CounterHTOff": "0,1,2,3" 7867 }, 7868 { 7869 "Offcore": "1", 7870 "EventCode": "0xB7, 0xBB", 7871 "UMask": "0x1", 7872 "BriefDescription": "TBD TBD", 7873 "MSRValue": "0x0804000490", 7874 "Counter": "0,1,2,3", 7875 "EventName": "OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD", 7876 "MSRIndex": "0x1a6,0x1a7", 7877 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7878 "SampleAfterValue": "100003", 7879 "CounterHTOff": "0,1,2,3" 7880 }, 7881 { 7882 "Offcore": "1", 7883 "EventCode": "0xB7, 0xBB", 7884 "UMask": "0x1", 7885 "BriefDescription": "TBD TBD", 7886 "MSRValue": "0x1004000490", 7887 "Counter": "0,1,2,3", 7888 "EventName": "OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE", 7889 "MSRIndex": "0x1a6,0x1a7", 7890 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7891 "SampleAfterValue": "100003", 7892 "CounterHTOff": "0,1,2,3" 7893 }, 7894 { 7895 "Offcore": "1", 7896 "EventCode": "0xB7, 0xBB", 7897 "UMask": "0x1", 7898 "BriefDescription": "TBD TBD", 7899 "MSRValue": "0x3F84000490", 7900 "Counter": "0,1,2,3", 7901 "EventName": "OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP", 7902 "MSRIndex": "0x1a6,0x1a7", 7903 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7904 "SampleAfterValue": "100003", 7905 "CounterHTOff": "0,1,2,3" 7906 }, 7907 { 7908 "Offcore": "1", 7909 "EventCode": "0xB7, 0xBB", 7910 "UMask": "0x1", 7911 "BriefDescription": "TBD", 7912 "MSRValue": "0x0090000490", 7913 "Counter": "0,1,2,3", 7914 "EventName": "OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE", 7915 "MSRIndex": "0x1a6,0x1a7", 7916 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7917 "SampleAfterValue": "100003", 7918 "CounterHTOff": "0,1,2,3" 7919 }, 7920 { 7921 "Offcore": "1", 7922 "EventCode": "0xB7, 0xBB", 7923 "UMask": "0x1", 7924 "BriefDescription": "TBD TBD", 7925 "MSRValue": "0x0110000490", 7926 "Counter": "0,1,2,3", 7927 "EventName": "OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED", 7928 "MSRIndex": "0x1a6,0x1a7", 7929 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7930 "SampleAfterValue": "100003", 7931 "CounterHTOff": "0,1,2,3" 7932 }, 7933 { 7934 "Offcore": "1", 7935 "EventCode": "0xB7, 0xBB", 7936 "UMask": "0x1", 7937 "BriefDescription": "TBD", 7938 "MSRValue": "0x0210000490", 7939 "Counter": "0,1,2,3", 7940 "EventName": "OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS", 7941 "MSRIndex": "0x1a6,0x1a7", 7942 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7943 "SampleAfterValue": "100003", 7944 "CounterHTOff": "0,1,2,3" 7945 }, 7946 { 7947 "Offcore": "1", 7948 "EventCode": "0xB7, 0xBB", 7949 "UMask": "0x1", 7950 "BriefDescription": "TBD TBD", 7951 "MSRValue": "0x0410000490", 7952 "Counter": "0,1,2,3", 7953 "EventName": "OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD", 7954 "MSRIndex": "0x1a6,0x1a7", 7955 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7956 "SampleAfterValue": "100003", 7957 "CounterHTOff": "0,1,2,3" 7958 }, 7959 { 7960 "Offcore": "1", 7961 "EventCode": "0xB7, 0xBB", 7962 "UMask": "0x1", 7963 "BriefDescription": "TBD TBD", 7964 "MSRValue": "0x0810000490", 7965 "Counter": "0,1,2,3", 7966 "EventName": "OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD", 7967 "MSRIndex": "0x1a6,0x1a7", 7968 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7969 "SampleAfterValue": "100003", 7970 "CounterHTOff": "0,1,2,3" 7971 }, 7972 { 7973 "Offcore": "1", 7974 "EventCode": "0xB7, 0xBB", 7975 "UMask": "0x1", 7976 "BriefDescription": "TBD TBD", 7977 "MSRValue": "0x1010000490", 7978 "Counter": "0,1,2,3", 7979 "EventName": "OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE", 7980 "MSRIndex": "0x1a6,0x1a7", 7981 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7982 "SampleAfterValue": "100003", 7983 "CounterHTOff": "0,1,2,3" 7984 }, 7985 { 7986 "Offcore": "1", 7987 "EventCode": "0xB7, 0xBB", 7988 "UMask": "0x1", 7989 "BriefDescription": "TBD TBD", 7990 "MSRValue": "0x3F90000490", 7991 "Counter": "0,1,2,3", 7992 "EventName": "OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP", 7993 "MSRIndex": "0x1a6,0x1a7", 7994 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7995 "SampleAfterValue": "100003", 7996 "CounterHTOff": "0,1,2,3" 7997 }, 7998 { 7999 "Offcore": "1", 8000 "EventCode": "0xB7, 0xBB", 8001 "UMask": "0x1", 8002 "BriefDescription": "TBD TBD", 8003 "MSRValue": "0x00BC000490", 8004 "Counter": "0,1,2,3", 8005 "EventName": "OCR.ALL_PF_DATA_RD.L3_MISS.SNOOP_NONE", 8006 "MSRIndex": "0x1a6,0x1a7", 8007 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8008 "SampleAfterValue": "100003", 8009 "CounterHTOff": "0,1,2,3" 8010 }, 8011 { 8012 "Offcore": "1", 8013 "EventCode": "0xB7, 0xBB", 8014 "UMask": "0x1", 8015 "BriefDescription": "TBD TBD TBD", 8016 "MSRValue": "0x013C000490", 8017 "Counter": "0,1,2,3", 8018 "EventName": "OCR.ALL_PF_DATA_RD.L3_MISS.NO_SNOOP_NEEDED", 8019 "MSRIndex": "0x1a6,0x1a7", 8020 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8021 "SampleAfterValue": "100003", 8022 "CounterHTOff": "0,1,2,3" 8023 }, 8024 { 8025 "Offcore": "1", 8026 "EventCode": "0xB7, 0xBB", 8027 "UMask": "0x1", 8028 "BriefDescription": "TBD TBD", 8029 "MSRValue": "0x023C000490", 8030 "Counter": "0,1,2,3", 8031 "EventName": "OCR.ALL_PF_DATA_RD.L3_MISS.SNOOP_MISS", 8032 "MSRIndex": "0x1a6,0x1a7", 8033 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8034 "SampleAfterValue": "100003", 8035 "CounterHTOff": "0,1,2,3" 8036 }, 8037 { 8038 "Offcore": "1", 8039 "EventCode": "0xB7, 0xBB", 8040 "UMask": "0x1", 8041 "BriefDescription": "TBD TBD TBD", 8042 "MSRValue": "0x043C000490", 8043 "Counter": "0,1,2,3", 8044 "EventName": "OCR.ALL_PF_DATA_RD.L3_MISS.HIT_OTHER_CORE_NO_FWD", 8045 "MSRIndex": "0x1a6,0x1a7", 8046 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8047 "SampleAfterValue": "100003", 8048 "CounterHTOff": "0,1,2,3" 8049 }, 8050 { 8051 "Offcore": "1", 8052 "EventCode": "0xB7, 0xBB", 8053 "UMask": "0x1", 8054 "BriefDescription": "TBD TBD TBD", 8055 "MSRValue": "0x083C000490", 8056 "Counter": "0,1,2,3", 8057 "EventName": "OCR.ALL_PF_DATA_RD.L3_MISS.HIT_OTHER_CORE_FWD", 8058 "MSRIndex": "0x1a6,0x1a7", 8059 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8060 "SampleAfterValue": "100003", 8061 "CounterHTOff": "0,1,2,3" 8062 }, 8063 { 8064 "Offcore": "1", 8065 "EventCode": "0xB7, 0xBB", 8066 "UMask": "0x1", 8067 "BriefDescription": "TBD TBD TBD", 8068 "MSRValue": "0x103C000490", 8069 "Counter": "0,1,2,3", 8070 "EventName": "OCR.ALL_PF_DATA_RD.L3_MISS.HITM_OTHER_CORE", 8071 "MSRIndex": "0x1a6,0x1a7", 8072 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8073 "SampleAfterValue": "100003", 8074 "CounterHTOff": "0,1,2,3" 8075 }, 8076 { 8077 "Offcore": "1", 8078 "EventCode": "0xB7, 0xBB", 8079 "UMask": "0x1", 8080 "BriefDescription": "TBD TBD TBD", 8081 "MSRValue": "0x3FBC000490", 8082 "Counter": "0,1,2,3", 8083 "EventName": "OCR.ALL_PF_DATA_RD.L3_MISS.ANY_SNOOP", 8084 "MSRIndex": "0x1a6,0x1a7", 8085 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8086 "SampleAfterValue": "100003", 8087 "CounterHTOff": "0,1,2,3" 8088 }, 8089 { 8090 "Offcore": "1", 8091 "EventCode": "0xB7, 0xBB", 8092 "UMask": "0x1", 8093 "BriefDescription": "TBD", 8094 "MSRValue": "0x0084000120", 8095 "Counter": "0,1,2,3", 8096 "EventName": "OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NONE", 8097 "MSRIndex": "0x1a6,0x1a7", 8098 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8099 "SampleAfterValue": "100003", 8100 "CounterHTOff": "0,1,2,3" 8101 }, 8102 { 8103 "Offcore": "1", 8104 "EventCode": "0xB7, 0xBB", 8105 "UMask": "0x1", 8106 "BriefDescription": "TBD TBD", 8107 "MSRValue": "0x0104000120", 8108 "Counter": "0,1,2,3", 8109 "EventName": "OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED", 8110 "MSRIndex": "0x1a6,0x1a7", 8111 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8112 "SampleAfterValue": "100003", 8113 "CounterHTOff": "0,1,2,3" 8114 }, 8115 { 8116 "Offcore": "1", 8117 "EventCode": "0xB7, 0xBB", 8118 "UMask": "0x1", 8119 "BriefDescription": "TBD", 8120 "MSRValue": "0x0204000120", 8121 "Counter": "0,1,2,3", 8122 "EventName": "OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS", 8123 "MSRIndex": "0x1a6,0x1a7", 8124 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8125 "SampleAfterValue": "100003", 8126 "CounterHTOff": "0,1,2,3" 8127 }, 8128 { 8129 "Offcore": "1", 8130 "EventCode": "0xB7, 0xBB", 8131 "UMask": "0x1", 8132 "BriefDescription": "TBD TBD", 8133 "MSRValue": "0x0404000120", 8134 "Counter": "0,1,2,3", 8135 "EventName": "OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD", 8136 "MSRIndex": "0x1a6,0x1a7", 8137 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8138 "SampleAfterValue": "100003", 8139 "CounterHTOff": "0,1,2,3" 8140 }, 8141 { 8142 "Offcore": "1", 8143 "EventCode": "0xB7, 0xBB", 8144 "UMask": "0x1", 8145 "BriefDescription": "TBD TBD", 8146 "MSRValue": "0x0804000120", 8147 "Counter": "0,1,2,3", 8148 "EventName": "OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD", 8149 "MSRIndex": "0x1a6,0x1a7", 8150 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8151 "SampleAfterValue": "100003", 8152 "CounterHTOff": "0,1,2,3" 8153 }, 8154 { 8155 "Offcore": "1", 8156 "EventCode": "0xB7, 0xBB", 8157 "UMask": "0x1", 8158 "BriefDescription": "TBD TBD", 8159 "MSRValue": "0x1004000120", 8160 "Counter": "0,1,2,3", 8161 "EventName": "OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE", 8162 "MSRIndex": "0x1a6,0x1a7", 8163 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8164 "SampleAfterValue": "100003", 8165 "CounterHTOff": "0,1,2,3" 8166 }, 8167 { 8168 "Offcore": "1", 8169 "EventCode": "0xB7, 0xBB", 8170 "UMask": "0x1", 8171 "BriefDescription": "TBD TBD", 8172 "MSRValue": "0x3F84000120", 8173 "Counter": "0,1,2,3", 8174 "EventName": "OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.ANY_SNOOP", 8175 "MSRIndex": "0x1a6,0x1a7", 8176 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8177 "SampleAfterValue": "100003", 8178 "CounterHTOff": "0,1,2,3" 8179 }, 8180 { 8181 "Offcore": "1", 8182 "EventCode": "0xB7, 0xBB", 8183 "UMask": "0x1", 8184 "BriefDescription": "TBD", 8185 "MSRValue": "0x0090000120", 8186 "Counter": "0,1,2,3", 8187 "EventName": "OCR.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE", 8188 "MSRIndex": "0x1a6,0x1a7", 8189 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8190 "SampleAfterValue": "100003", 8191 "CounterHTOff": "0,1,2,3" 8192 }, 8193 { 8194 "Offcore": "1", 8195 "EventCode": "0xB7, 0xBB", 8196 "UMask": "0x1", 8197 "BriefDescription": "TBD TBD", 8198 "MSRValue": "0x0110000120", 8199 "Counter": "0,1,2,3", 8200 "EventName": "OCR.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED", 8201 "MSRIndex": "0x1a6,0x1a7", 8202 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8203 "SampleAfterValue": "100003", 8204 "CounterHTOff": "0,1,2,3" 8205 }, 8206 { 8207 "Offcore": "1", 8208 "EventCode": "0xB7, 0xBB", 8209 "UMask": "0x1", 8210 "BriefDescription": "TBD", 8211 "MSRValue": "0x0210000120", 8212 "Counter": "0,1,2,3", 8213 "EventName": "OCR.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS", 8214 "MSRIndex": "0x1a6,0x1a7", 8215 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8216 "SampleAfterValue": "100003", 8217 "CounterHTOff": "0,1,2,3" 8218 }, 8219 { 8220 "Offcore": "1", 8221 "EventCode": "0xB7, 0xBB", 8222 "UMask": "0x1", 8223 "BriefDescription": "TBD TBD", 8224 "MSRValue": "0x0410000120", 8225 "Counter": "0,1,2,3", 8226 "EventName": "OCR.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD", 8227 "MSRIndex": "0x1a6,0x1a7", 8228 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8229 "SampleAfterValue": "100003", 8230 "CounterHTOff": "0,1,2,3" 8231 }, 8232 { 8233 "Offcore": "1", 8234 "EventCode": "0xB7, 0xBB", 8235 "UMask": "0x1", 8236 "BriefDescription": "TBD TBD", 8237 "MSRValue": "0x0810000120", 8238 "Counter": "0,1,2,3", 8239 "EventName": "OCR.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD", 8240 "MSRIndex": "0x1a6,0x1a7", 8241 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8242 "SampleAfterValue": "100003", 8243 "CounterHTOff": "0,1,2,3" 8244 }, 8245 { 8246 "Offcore": "1", 8247 "EventCode": "0xB7, 0xBB", 8248 "UMask": "0x1", 8249 "BriefDescription": "TBD TBD", 8250 "MSRValue": "0x1010000120", 8251 "Counter": "0,1,2,3", 8252 "EventName": "OCR.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE", 8253 "MSRIndex": "0x1a6,0x1a7", 8254 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8255 "SampleAfterValue": "100003", 8256 "CounterHTOff": "0,1,2,3" 8257 }, 8258 { 8259 "Offcore": "1", 8260 "EventCode": "0xB7, 0xBB", 8261 "UMask": "0x1", 8262 "BriefDescription": "TBD TBD", 8263 "MSRValue": "0x3F90000120", 8264 "Counter": "0,1,2,3", 8265 "EventName": "OCR.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP", 8266 "MSRIndex": "0x1a6,0x1a7", 8267 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8268 "SampleAfterValue": "100003", 8269 "CounterHTOff": "0,1,2,3" 8270 }, 8271 { 8272 "Offcore": "1", 8273 "EventCode": "0xB7, 0xBB", 8274 "UMask": "0x1", 8275 "BriefDescription": "TBD TBD", 8276 "MSRValue": "0x00BC000120", 8277 "Counter": "0,1,2,3", 8278 "EventName": "OCR.ALL_PF_RFO.L3_MISS.SNOOP_NONE", 8279 "MSRIndex": "0x1a6,0x1a7", 8280 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8281 "SampleAfterValue": "100003", 8282 "CounterHTOff": "0,1,2,3" 8283 }, 8284 { 8285 "Offcore": "1", 8286 "EventCode": "0xB7, 0xBB", 8287 "UMask": "0x1", 8288 "BriefDescription": "TBD TBD TBD", 8289 "MSRValue": "0x013C000120", 8290 "Counter": "0,1,2,3", 8291 "EventName": "OCR.ALL_PF_RFO.L3_MISS.NO_SNOOP_NEEDED", 8292 "MSRIndex": "0x1a6,0x1a7", 8293 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8294 "SampleAfterValue": "100003", 8295 "CounterHTOff": "0,1,2,3" 8296 }, 8297 { 8298 "Offcore": "1", 8299 "EventCode": "0xB7, 0xBB", 8300 "UMask": "0x1", 8301 "BriefDescription": "TBD TBD", 8302 "MSRValue": "0x023C000120", 8303 "Counter": "0,1,2,3", 8304 "EventName": "OCR.ALL_PF_RFO.L3_MISS.SNOOP_MISS", 8305 "MSRIndex": "0x1a6,0x1a7", 8306 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8307 "SampleAfterValue": "100003", 8308 "CounterHTOff": "0,1,2,3" 8309 }, 8310 { 8311 "Offcore": "1", 8312 "EventCode": "0xB7, 0xBB", 8313 "UMask": "0x1", 8314 "BriefDescription": "TBD TBD TBD", 8315 "MSRValue": "0x043C000120", 8316 "Counter": "0,1,2,3", 8317 "EventName": "OCR.ALL_PF_RFO.L3_MISS.HIT_OTHER_CORE_NO_FWD", 8318 "MSRIndex": "0x1a6,0x1a7", 8319 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8320 "SampleAfterValue": "100003", 8321 "CounterHTOff": "0,1,2,3" 8322 }, 8323 { 8324 "Offcore": "1", 8325 "EventCode": "0xB7, 0xBB", 8326 "UMask": "0x1", 8327 "BriefDescription": "TBD TBD TBD", 8328 "MSRValue": "0x083C000120", 8329 "Counter": "0,1,2,3", 8330 "EventName": "OCR.ALL_PF_RFO.L3_MISS.HIT_OTHER_CORE_FWD", 8331 "MSRIndex": "0x1a6,0x1a7", 8332 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8333 "SampleAfterValue": "100003", 8334 "CounterHTOff": "0,1,2,3" 8335 }, 8336 { 8337 "Offcore": "1", 8338 "EventCode": "0xB7, 0xBB", 8339 "UMask": "0x1", 8340 "BriefDescription": "TBD TBD TBD", 8341 "MSRValue": "0x103C000120", 8342 "Counter": "0,1,2,3", 8343 "EventName": "OCR.ALL_PF_RFO.L3_MISS.HITM_OTHER_CORE", 8344 "MSRIndex": "0x1a6,0x1a7", 8345 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8346 "SampleAfterValue": "100003", 8347 "CounterHTOff": "0,1,2,3" 8348 }, 8349 { 8350 "Offcore": "1", 8351 "EventCode": "0xB7, 0xBB", 8352 "UMask": "0x1", 8353 "BriefDescription": "TBD TBD TBD", 8354 "MSRValue": "0x3FBC000120", 8355 "Counter": "0,1,2,3", 8356 "EventName": "OCR.ALL_PF_RFO.L3_MISS.ANY_SNOOP", 8357 "MSRIndex": "0x1a6,0x1a7", 8358 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8359 "SampleAfterValue": "100003", 8360 "CounterHTOff": "0,1,2,3" 8361 }, 8362 { 8363 "Offcore": "1", 8364 "EventCode": "0xB7, 0xBB", 8365 "UMask": "0x1", 8366 "BriefDescription": "TBD", 8367 "MSRValue": "0x0084000491", 8368 "Counter": "0,1,2,3", 8369 "EventName": "OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NONE", 8370 "MSRIndex": "0x1a6,0x1a7", 8371 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8372 "SampleAfterValue": "100003", 8373 "CounterHTOff": "0,1,2,3" 8374 }, 8375 { 8376 "Offcore": "1", 8377 "EventCode": "0xB7, 0xBB", 8378 "UMask": "0x1", 8379 "BriefDescription": "TBD TBD", 8380 "MSRValue": "0x0104000491", 8381 "Counter": "0,1,2,3", 8382 "EventName": "OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED", 8383 "MSRIndex": "0x1a6,0x1a7", 8384 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8385 "SampleAfterValue": "100003", 8386 "CounterHTOff": "0,1,2,3" 8387 }, 8388 { 8389 "Offcore": "1", 8390 "EventCode": "0xB7, 0xBB", 8391 "UMask": "0x1", 8392 "BriefDescription": "TBD", 8393 "MSRValue": "0x0204000491", 8394 "Counter": "0,1,2,3", 8395 "EventName": "OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS", 8396 "MSRIndex": "0x1a6,0x1a7", 8397 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8398 "SampleAfterValue": "100003", 8399 "CounterHTOff": "0,1,2,3" 8400 }, 8401 { 8402 "Offcore": "1", 8403 "EventCode": "0xB7, 0xBB", 8404 "UMask": "0x1", 8405 "BriefDescription": "TBD TBD", 8406 "MSRValue": "0x0404000491", 8407 "Counter": "0,1,2,3", 8408 "EventName": "OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD", 8409 "MSRIndex": "0x1a6,0x1a7", 8410 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8411 "SampleAfterValue": "100003", 8412 "CounterHTOff": "0,1,2,3" 8413 }, 8414 { 8415 "Offcore": "1", 8416 "EventCode": "0xB7, 0xBB", 8417 "UMask": "0x1", 8418 "BriefDescription": "TBD TBD", 8419 "MSRValue": "0x0804000491", 8420 "Counter": "0,1,2,3", 8421 "EventName": "OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD", 8422 "MSRIndex": "0x1a6,0x1a7", 8423 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8424 "SampleAfterValue": "100003", 8425 "CounterHTOff": "0,1,2,3" 8426 }, 8427 { 8428 "Offcore": "1", 8429 "EventCode": "0xB7, 0xBB", 8430 "UMask": "0x1", 8431 "BriefDescription": "TBD TBD", 8432 "MSRValue": "0x1004000491", 8433 "Counter": "0,1,2,3", 8434 "EventName": "OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE", 8435 "MSRIndex": "0x1a6,0x1a7", 8436 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8437 "SampleAfterValue": "100003", 8438 "CounterHTOff": "0,1,2,3" 8439 }, 8440 { 8441 "Offcore": "1", 8442 "EventCode": "0xB7, 0xBB", 8443 "UMask": "0x1", 8444 "BriefDescription": "TBD TBD", 8445 "MSRValue": "0x3F84000491", 8446 "Counter": "0,1,2,3", 8447 "EventName": "OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP", 8448 "MSRIndex": "0x1a6,0x1a7", 8449 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8450 "SampleAfterValue": "100003", 8451 "CounterHTOff": "0,1,2,3" 8452 }, 8453 { 8454 "Offcore": "1", 8455 "EventCode": "0xB7, 0xBB", 8456 "UMask": "0x1", 8457 "BriefDescription": "TBD", 8458 "MSRValue": "0x0090000491", 8459 "Counter": "0,1,2,3", 8460 "EventName": "OCR.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE", 8461 "MSRIndex": "0x1a6,0x1a7", 8462 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8463 "SampleAfterValue": "100003", 8464 "CounterHTOff": "0,1,2,3" 8465 }, 8466 { 8467 "Offcore": "1", 8468 "EventCode": "0xB7, 0xBB", 8469 "UMask": "0x1", 8470 "BriefDescription": "TBD TBD", 8471 "MSRValue": "0x0110000491", 8472 "Counter": "0,1,2,3", 8473 "EventName": "OCR.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED", 8474 "MSRIndex": "0x1a6,0x1a7", 8475 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8476 "SampleAfterValue": "100003", 8477 "CounterHTOff": "0,1,2,3" 8478 }, 8479 { 8480 "Offcore": "1", 8481 "EventCode": "0xB7, 0xBB", 8482 "UMask": "0x1", 8483 "BriefDescription": "TBD", 8484 "MSRValue": "0x0210000491", 8485 "Counter": "0,1,2,3", 8486 "EventName": "OCR.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS", 8487 "MSRIndex": "0x1a6,0x1a7", 8488 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8489 "SampleAfterValue": "100003", 8490 "CounterHTOff": "0,1,2,3" 8491 }, 8492 { 8493 "Offcore": "1", 8494 "EventCode": "0xB7, 0xBB", 8495 "UMask": "0x1", 8496 "BriefDescription": "TBD TBD", 8497 "MSRValue": "0x0410000491", 8498 "Counter": "0,1,2,3", 8499 "EventName": "OCR.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD", 8500 "MSRIndex": "0x1a6,0x1a7", 8501 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8502 "SampleAfterValue": "100003", 8503 "CounterHTOff": "0,1,2,3" 8504 }, 8505 { 8506 "Offcore": "1", 8507 "EventCode": "0xB7, 0xBB", 8508 "UMask": "0x1", 8509 "BriefDescription": "TBD TBD", 8510 "MSRValue": "0x0810000491", 8511 "Counter": "0,1,2,3", 8512 "EventName": "OCR.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD", 8513 "MSRIndex": "0x1a6,0x1a7", 8514 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8515 "SampleAfterValue": "100003", 8516 "CounterHTOff": "0,1,2,3" 8517 }, 8518 { 8519 "Offcore": "1", 8520 "EventCode": "0xB7, 0xBB", 8521 "UMask": "0x1", 8522 "BriefDescription": "TBD TBD", 8523 "MSRValue": "0x1010000491", 8524 "Counter": "0,1,2,3", 8525 "EventName": "OCR.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE", 8526 "MSRIndex": "0x1a6,0x1a7", 8527 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8528 "SampleAfterValue": "100003", 8529 "CounterHTOff": "0,1,2,3" 8530 }, 8531 { 8532 "Offcore": "1", 8533 "EventCode": "0xB7, 0xBB", 8534 "UMask": "0x1", 8535 "BriefDescription": "TBD TBD", 8536 "MSRValue": "0x3F90000491", 8537 "Counter": "0,1,2,3", 8538 "EventName": "OCR.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP", 8539 "MSRIndex": "0x1a6,0x1a7", 8540 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8541 "SampleAfterValue": "100003", 8542 "CounterHTOff": "0,1,2,3" 8543 }, 8544 { 8545 "Offcore": "1", 8546 "EventCode": "0xB7, 0xBB", 8547 "UMask": "0x1", 8548 "BriefDescription": "TBD TBD", 8549 "MSRValue": "0x00BC000491", 8550 "Counter": "0,1,2,3", 8551 "EventName": "OCR.ALL_DATA_RD.L3_MISS.SNOOP_NONE", 8552 "MSRIndex": "0x1a6,0x1a7", 8553 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8554 "SampleAfterValue": "100003", 8555 "CounterHTOff": "0,1,2,3" 8556 }, 8557 { 8558 "Offcore": "1", 8559 "EventCode": "0xB7, 0xBB", 8560 "UMask": "0x1", 8561 "BriefDescription": "TBD TBD TBD", 8562 "MSRValue": "0x013C000491", 8563 "Counter": "0,1,2,3", 8564 "EventName": "OCR.ALL_DATA_RD.L3_MISS.NO_SNOOP_NEEDED", 8565 "MSRIndex": "0x1a6,0x1a7", 8566 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8567 "SampleAfterValue": "100003", 8568 "CounterHTOff": "0,1,2,3" 8569 }, 8570 { 8571 "Offcore": "1", 8572 "EventCode": "0xB7, 0xBB", 8573 "UMask": "0x1", 8574 "BriefDescription": "TBD TBD", 8575 "MSRValue": "0x023C000491", 8576 "Counter": "0,1,2,3", 8577 "EventName": "OCR.ALL_DATA_RD.L3_MISS.SNOOP_MISS", 8578 "MSRIndex": "0x1a6,0x1a7", 8579 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8580 "SampleAfterValue": "100003", 8581 "CounterHTOff": "0,1,2,3" 8582 }, 8583 { 8584 "Offcore": "1", 8585 "EventCode": "0xB7, 0xBB", 8586 "UMask": "0x1", 8587 "BriefDescription": "TBD TBD TBD", 8588 "MSRValue": "0x043C000491", 8589 "Counter": "0,1,2,3", 8590 "EventName": "OCR.ALL_DATA_RD.L3_MISS.HIT_OTHER_CORE_NO_FWD", 8591 "MSRIndex": "0x1a6,0x1a7", 8592 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8593 "SampleAfterValue": "100003", 8594 "CounterHTOff": "0,1,2,3" 8595 }, 8596 { 8597 "Offcore": "1", 8598 "EventCode": "0xB7, 0xBB", 8599 "UMask": "0x1", 8600 "BriefDescription": "TBD TBD TBD", 8601 "MSRValue": "0x083C000491", 8602 "Counter": "0,1,2,3", 8603 "EventName": "OCR.ALL_DATA_RD.L3_MISS.HIT_OTHER_CORE_FWD", 8604 "MSRIndex": "0x1a6,0x1a7", 8605 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8606 "SampleAfterValue": "100003", 8607 "CounterHTOff": "0,1,2,3" 8608 }, 8609 { 8610 "Offcore": "1", 8611 "EventCode": "0xB7, 0xBB", 8612 "UMask": "0x1", 8613 "BriefDescription": "TBD TBD TBD", 8614 "MSRValue": "0x103C000491", 8615 "Counter": "0,1,2,3", 8616 "EventName": "OCR.ALL_DATA_RD.L3_MISS.HITM_OTHER_CORE", 8617 "MSRIndex": "0x1a6,0x1a7", 8618 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8619 "SampleAfterValue": "100003", 8620 "CounterHTOff": "0,1,2,3" 8621 }, 8622 { 8623 "Offcore": "1", 8624 "EventCode": "0xB7, 0xBB", 8625 "UMask": "0x1", 8626 "BriefDescription": "TBD TBD TBD", 8627 "MSRValue": "0x3FBC000491", 8628 "Counter": "0,1,2,3", 8629 "EventName": "OCR.ALL_DATA_RD.L3_MISS.ANY_SNOOP", 8630 "MSRIndex": "0x1a6,0x1a7", 8631 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8632 "SampleAfterValue": "100003", 8633 "CounterHTOff": "0,1,2,3" 8634 }, 8635 { 8636 "Offcore": "1", 8637 "EventCode": "0xB7, 0xBB", 8638 "UMask": "0x1", 8639 "BriefDescription": "TBD", 8640 "MSRValue": "0x0084000122", 8641 "Counter": "0,1,2,3", 8642 "EventName": "OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NONE", 8643 "MSRIndex": "0x1a6,0x1a7", 8644 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8645 "SampleAfterValue": "100003", 8646 "CounterHTOff": "0,1,2,3" 8647 }, 8648 { 8649 "Offcore": "1", 8650 "EventCode": "0xB7, 0xBB", 8651 "UMask": "0x1", 8652 "BriefDescription": "TBD TBD", 8653 "MSRValue": "0x0104000122", 8654 "Counter": "0,1,2,3", 8655 "EventName": "OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED", 8656 "MSRIndex": "0x1a6,0x1a7", 8657 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8658 "SampleAfterValue": "100003", 8659 "CounterHTOff": "0,1,2,3" 8660 }, 8661 { 8662 "Offcore": "1", 8663 "EventCode": "0xB7, 0xBB", 8664 "UMask": "0x1", 8665 "BriefDescription": "TBD", 8666 "MSRValue": "0x0204000122", 8667 "Counter": "0,1,2,3", 8668 "EventName": "OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS", 8669 "MSRIndex": "0x1a6,0x1a7", 8670 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8671 "SampleAfterValue": "100003", 8672 "CounterHTOff": "0,1,2,3" 8673 }, 8674 { 8675 "Offcore": "1", 8676 "EventCode": "0xB7, 0xBB", 8677 "UMask": "0x1", 8678 "BriefDescription": "TBD TBD", 8679 "MSRValue": "0x0404000122", 8680 "Counter": "0,1,2,3", 8681 "EventName": "OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD", 8682 "MSRIndex": "0x1a6,0x1a7", 8683 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8684 "SampleAfterValue": "100003", 8685 "CounterHTOff": "0,1,2,3" 8686 }, 8687 { 8688 "Offcore": "1", 8689 "EventCode": "0xB7, 0xBB", 8690 "UMask": "0x1", 8691 "BriefDescription": "TBD TBD", 8692 "MSRValue": "0x0804000122", 8693 "Counter": "0,1,2,3", 8694 "EventName": "OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD", 8695 "MSRIndex": "0x1a6,0x1a7", 8696 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8697 "SampleAfterValue": "100003", 8698 "CounterHTOff": "0,1,2,3" 8699 }, 8700 { 8701 "Offcore": "1", 8702 "EventCode": "0xB7, 0xBB", 8703 "UMask": "0x1", 8704 "BriefDescription": "TBD TBD", 8705 "MSRValue": "0x1004000122", 8706 "Counter": "0,1,2,3", 8707 "EventName": "OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE", 8708 "MSRIndex": "0x1a6,0x1a7", 8709 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8710 "SampleAfterValue": "100003", 8711 "CounterHTOff": "0,1,2,3" 8712 }, 8713 { 8714 "Offcore": "1", 8715 "EventCode": "0xB7, 0xBB", 8716 "UMask": "0x1", 8717 "BriefDescription": "TBD TBD", 8718 "MSRValue": "0x3F84000122", 8719 "Counter": "0,1,2,3", 8720 "EventName": "OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.ANY_SNOOP", 8721 "MSRIndex": "0x1a6,0x1a7", 8722 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8723 "SampleAfterValue": "100003", 8724 "CounterHTOff": "0,1,2,3" 8725 }, 8726 { 8727 "Offcore": "1", 8728 "EventCode": "0xB7, 0xBB", 8729 "UMask": "0x1", 8730 "BriefDescription": "TBD", 8731 "MSRValue": "0x0090000122", 8732 "Counter": "0,1,2,3", 8733 "EventName": "OCR.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE", 8734 "MSRIndex": "0x1a6,0x1a7", 8735 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8736 "SampleAfterValue": "100003", 8737 "CounterHTOff": "0,1,2,3" 8738 }, 8739 { 8740 "Offcore": "1", 8741 "EventCode": "0xB7, 0xBB", 8742 "UMask": "0x1", 8743 "BriefDescription": "TBD TBD", 8744 "MSRValue": "0x0110000122", 8745 "Counter": "0,1,2,3", 8746 "EventName": "OCR.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED", 8747 "MSRIndex": "0x1a6,0x1a7", 8748 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8749 "SampleAfterValue": "100003", 8750 "CounterHTOff": "0,1,2,3" 8751 }, 8752 { 8753 "Offcore": "1", 8754 "EventCode": "0xB7, 0xBB", 8755 "UMask": "0x1", 8756 "BriefDescription": "TBD", 8757 "MSRValue": "0x0210000122", 8758 "Counter": "0,1,2,3", 8759 "EventName": "OCR.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS", 8760 "MSRIndex": "0x1a6,0x1a7", 8761 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8762 "SampleAfterValue": "100003", 8763 "CounterHTOff": "0,1,2,3" 8764 }, 8765 { 8766 "Offcore": "1", 8767 "EventCode": "0xB7, 0xBB", 8768 "UMask": "0x1", 8769 "BriefDescription": "TBD TBD", 8770 "MSRValue": "0x0410000122", 8771 "Counter": "0,1,2,3", 8772 "EventName": "OCR.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD", 8773 "MSRIndex": "0x1a6,0x1a7", 8774 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8775 "SampleAfterValue": "100003", 8776 "CounterHTOff": "0,1,2,3" 8777 }, 8778 { 8779 "Offcore": "1", 8780 "EventCode": "0xB7, 0xBB", 8781 "UMask": "0x1", 8782 "BriefDescription": "TBD TBD", 8783 "MSRValue": "0x0810000122", 8784 "Counter": "0,1,2,3", 8785 "EventName": "OCR.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD", 8786 "MSRIndex": "0x1a6,0x1a7", 8787 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8788 "SampleAfterValue": "100003", 8789 "CounterHTOff": "0,1,2,3" 8790 }, 8791 { 8792 "Offcore": "1", 8793 "EventCode": "0xB7, 0xBB", 8794 "UMask": "0x1", 8795 "BriefDescription": "TBD TBD", 8796 "MSRValue": "0x1010000122", 8797 "Counter": "0,1,2,3", 8798 "EventName": "OCR.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE", 8799 "MSRIndex": "0x1a6,0x1a7", 8800 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8801 "SampleAfterValue": "100003", 8802 "CounterHTOff": "0,1,2,3" 8803 }, 8804 { 8805 "Offcore": "1", 8806 "EventCode": "0xB7, 0xBB", 8807 "UMask": "0x1", 8808 "BriefDescription": "TBD TBD", 8809 "MSRValue": "0x3F90000122", 8810 "Counter": "0,1,2,3", 8811 "EventName": "OCR.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP", 8812 "MSRIndex": "0x1a6,0x1a7", 8813 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8814 "SampleAfterValue": "100003", 8815 "CounterHTOff": "0,1,2,3" 8816 }, 8817 { 8818 "Offcore": "1", 8819 "EventCode": "0xB7, 0xBB", 8820 "UMask": "0x1", 8821 "BriefDescription": "TBD TBD", 8822 "MSRValue": "0x00BC000122", 8823 "Counter": "0,1,2,3", 8824 "EventName": "OCR.ALL_RFO.L3_MISS.SNOOP_NONE", 8825 "MSRIndex": "0x1a6,0x1a7", 8826 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8827 "SampleAfterValue": "100003", 8828 "CounterHTOff": "0,1,2,3" 8829 }, 8830 { 8831 "Offcore": "1", 8832 "EventCode": "0xB7, 0xBB", 8833 "UMask": "0x1", 8834 "BriefDescription": "TBD TBD TBD", 8835 "MSRValue": "0x013C000122", 8836 "Counter": "0,1,2,3", 8837 "EventName": "OCR.ALL_RFO.L3_MISS.NO_SNOOP_NEEDED", 8838 "MSRIndex": "0x1a6,0x1a7", 8839 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8840 "SampleAfterValue": "100003", 8841 "CounterHTOff": "0,1,2,3" 8842 }, 8843 { 8844 "Offcore": "1", 8845 "EventCode": "0xB7, 0xBB", 8846 "UMask": "0x1", 8847 "BriefDescription": "TBD TBD", 8848 "MSRValue": "0x023C000122", 8849 "Counter": "0,1,2,3", 8850 "EventName": "OCR.ALL_RFO.L3_MISS.SNOOP_MISS", 8851 "MSRIndex": "0x1a6,0x1a7", 8852 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8853 "SampleAfterValue": "100003", 8854 "CounterHTOff": "0,1,2,3" 8855 }, 8856 { 8857 "Offcore": "1", 8858 "EventCode": "0xB7, 0xBB", 8859 "UMask": "0x1", 8860 "BriefDescription": "TBD TBD TBD", 8861 "MSRValue": "0x043C000122", 8862 "Counter": "0,1,2,3", 8863 "EventName": "OCR.ALL_RFO.L3_MISS.HIT_OTHER_CORE_NO_FWD", 8864 "MSRIndex": "0x1a6,0x1a7", 8865 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8866 "SampleAfterValue": "100003", 8867 "CounterHTOff": "0,1,2,3" 8868 }, 8869 { 8870 "Offcore": "1", 8871 "EventCode": "0xB7, 0xBB", 8872 "UMask": "0x1", 8873 "BriefDescription": "TBD TBD TBD", 8874 "MSRValue": "0x083C000122", 8875 "Counter": "0,1,2,3", 8876 "EventName": "OCR.ALL_RFO.L3_MISS.HIT_OTHER_CORE_FWD", 8877 "MSRIndex": "0x1a6,0x1a7", 8878 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8879 "SampleAfterValue": "100003", 8880 "CounterHTOff": "0,1,2,3" 8881 }, 8882 { 8883 "Offcore": "1", 8884 "EventCode": "0xB7, 0xBB", 8885 "UMask": "0x1", 8886 "BriefDescription": "TBD TBD TBD", 8887 "MSRValue": "0x103C000122", 8888 "Counter": "0,1,2,3", 8889 "EventName": "OCR.ALL_RFO.L3_MISS.HITM_OTHER_CORE", 8890 "MSRIndex": "0x1a6,0x1a7", 8891 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8892 "SampleAfterValue": "100003", 8893 "CounterHTOff": "0,1,2,3" 8894 }, 8895 { 8896 "Offcore": "1", 8897 "EventCode": "0xB7, 0xBB", 8898 "UMask": "0x1", 8899 "BriefDescription": "TBD TBD TBD", 8900 "MSRValue": "0x3FBC000122", 8901 "Counter": "0,1,2,3", 8902 "EventName": "OCR.ALL_RFO.L3_MISS.ANY_SNOOP", 8903 "MSRIndex": "0x1a6,0x1a7", 8904 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8905 "SampleAfterValue": "100003", 8906 "CounterHTOff": "0,1,2,3" 8907 }, 8908 { 8909 "Offcore": "1", 8910 "EventCode": "0xB7, 0xBB", 8911 "UMask": "0x1", 8912 "BriefDescription": "TBD", 8913 "MSRValue": "0x00840007F7", 8914 "Counter": "0,1,2,3", 8915 "EventName": "OCR.ALL_READS.L3_MISS_LOCAL_DRAM.SNOOP_NONE", 8916 "MSRIndex": "0x1a6,0x1a7", 8917 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8918 "SampleAfterValue": "100003", 8919 "CounterHTOff": "0,1,2,3" 8920 }, 8921 { 8922 "Offcore": "1", 8923 "EventCode": "0xB7, 0xBB", 8924 "UMask": "0x1", 8925 "BriefDescription": "TBD TBD", 8926 "MSRValue": "0x01040007F7", 8927 "Counter": "0,1,2,3", 8928 "EventName": "OCR.ALL_READS.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED", 8929 "MSRIndex": "0x1a6,0x1a7", 8930 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8931 "SampleAfterValue": "100003", 8932 "CounterHTOff": "0,1,2,3" 8933 }, 8934 { 8935 "Offcore": "1", 8936 "EventCode": "0xB7, 0xBB", 8937 "UMask": "0x1", 8938 "BriefDescription": "TBD", 8939 "MSRValue": "0x02040007F7", 8940 "Counter": "0,1,2,3", 8941 "EventName": "OCR.ALL_READS.L3_MISS_LOCAL_DRAM.SNOOP_MISS", 8942 "MSRIndex": "0x1a6,0x1a7", 8943 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8944 "SampleAfterValue": "100003", 8945 "CounterHTOff": "0,1,2,3" 8946 }, 8947 { 8948 "Offcore": "1", 8949 "EventCode": "0xB7, 0xBB", 8950 "UMask": "0x1", 8951 "BriefDescription": "TBD TBD", 8952 "MSRValue": "0x04040007F7", 8953 "Counter": "0,1,2,3", 8954 "EventName": "OCR.ALL_READS.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD", 8955 "MSRIndex": "0x1a6,0x1a7", 8956 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8957 "SampleAfterValue": "100003", 8958 "CounterHTOff": "0,1,2,3" 8959 }, 8960 { 8961 "Offcore": "1", 8962 "EventCode": "0xB7, 0xBB", 8963 "UMask": "0x1", 8964 "BriefDescription": "TBD TBD", 8965 "MSRValue": "0x08040007F7", 8966 "Counter": "0,1,2,3", 8967 "EventName": "OCR.ALL_READS.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD", 8968 "MSRIndex": "0x1a6,0x1a7", 8969 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8970 "SampleAfterValue": "100003", 8971 "CounterHTOff": "0,1,2,3" 8972 }, 8973 { 8974 "Offcore": "1", 8975 "EventCode": "0xB7, 0xBB", 8976 "UMask": "0x1", 8977 "BriefDescription": "TBD TBD", 8978 "MSRValue": "0x10040007F7", 8979 "Counter": "0,1,2,3", 8980 "EventName": "OCR.ALL_READS.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE", 8981 "MSRIndex": "0x1a6,0x1a7", 8982 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8983 "SampleAfterValue": "100003", 8984 "CounterHTOff": "0,1,2,3" 8985 }, 8986 { 8987 "Offcore": "1", 8988 "EventCode": "0xB7, 0xBB", 8989 "UMask": "0x1", 8990 "BriefDescription": "TBD TBD", 8991 "MSRValue": "0x3F840007F7", 8992 "Counter": "0,1,2,3", 8993 "EventName": "OCR.ALL_READS.L3_MISS_LOCAL_DRAM.ANY_SNOOP", 8994 "MSRIndex": "0x1a6,0x1a7", 8995 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8996 "SampleAfterValue": "100003", 8997 "CounterHTOff": "0,1,2,3" 8998 }, 8999 { 9000 "Offcore": "1", 9001 "EventCode": "0xB7, 0xBB", 9002 "UMask": "0x1", 9003 "BriefDescription": "TBD", 9004 "MSRValue": "0x00900007F7", 9005 "Counter": "0,1,2,3", 9006 "EventName": "OCR.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE", 9007 "MSRIndex": "0x1a6,0x1a7", 9008 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 9009 "SampleAfterValue": "100003", 9010 "CounterHTOff": "0,1,2,3" 9011 }, 9012 { 9013 "Offcore": "1", 9014 "EventCode": "0xB7, 0xBB", 9015 "UMask": "0x1", 9016 "BriefDescription": "TBD TBD", 9017 "MSRValue": "0x01100007F7", 9018 "Counter": "0,1,2,3", 9019 "EventName": "OCR.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED", 9020 "MSRIndex": "0x1a6,0x1a7", 9021 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 9022 "SampleAfterValue": "100003", 9023 "CounterHTOff": "0,1,2,3" 9024 }, 9025 { 9026 "Offcore": "1", 9027 "EventCode": "0xB7, 0xBB", 9028 "UMask": "0x1", 9029 "BriefDescription": "TBD", 9030 "MSRValue": "0x02100007F7", 9031 "Counter": "0,1,2,3", 9032 "EventName": "OCR.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS", 9033 "MSRIndex": "0x1a6,0x1a7", 9034 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 9035 "SampleAfterValue": "100003", 9036 "CounterHTOff": "0,1,2,3" 9037 }, 9038 { 9039 "Offcore": "1", 9040 "EventCode": "0xB7, 0xBB", 9041 "UMask": "0x1", 9042 "BriefDescription": "TBD TBD", 9043 "MSRValue": "0x04100007F7", 9044 "Counter": "0,1,2,3", 9045 "EventName": "OCR.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD", 9046 "MSRIndex": "0x1a6,0x1a7", 9047 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 9048 "SampleAfterValue": "100003", 9049 "CounterHTOff": "0,1,2,3" 9050 }, 9051 { 9052 "Offcore": "1", 9053 "EventCode": "0xB7, 0xBB", 9054 "UMask": "0x1", 9055 "BriefDescription": "TBD TBD", 9056 "MSRValue": "0x08100007F7", 9057 "Counter": "0,1,2,3", 9058 "EventName": "OCR.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD", 9059 "MSRIndex": "0x1a6,0x1a7", 9060 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 9061 "SampleAfterValue": "100003", 9062 "CounterHTOff": "0,1,2,3" 9063 }, 9064 { 9065 "Offcore": "1", 9066 "EventCode": "0xB7, 0xBB", 9067 "UMask": "0x1", 9068 "BriefDescription": "TBD TBD", 9069 "MSRValue": "0x10100007F7", 9070 "Counter": "0,1,2,3", 9071 "EventName": "OCR.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE", 9072 "MSRIndex": "0x1a6,0x1a7", 9073 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 9074 "SampleAfterValue": "100003", 9075 "CounterHTOff": "0,1,2,3" 9076 }, 9077 { 9078 "Offcore": "1", 9079 "EventCode": "0xB7, 0xBB", 9080 "UMask": "0x1", 9081 "BriefDescription": "TBD TBD", 9082 "MSRValue": "0x3F900007F7", 9083 "Counter": "0,1,2,3", 9084 "EventName": "OCR.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP", 9085 "MSRIndex": "0x1a6,0x1a7", 9086 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 9087 "SampleAfterValue": "100003", 9088 "CounterHTOff": "0,1,2,3" 9089 }, 9090 { 9091 "Offcore": "1", 9092 "EventCode": "0xB7, 0xBB", 9093 "UMask": "0x1", 9094 "BriefDescription": "TBD TBD", 9095 "MSRValue": "0x00BC0007F7", 9096 "Counter": "0,1,2,3", 9097 "EventName": "OCR.ALL_READS.L3_MISS.SNOOP_NONE", 9098 "MSRIndex": "0x1a6,0x1a7", 9099 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 9100 "SampleAfterValue": "100003", 9101 "CounterHTOff": "0,1,2,3" 9102 }, 9103 { 9104 "Offcore": "1", 9105 "EventCode": "0xB7, 0xBB", 9106 "UMask": "0x1", 9107 "BriefDescription": "TBD TBD TBD", 9108 "MSRValue": "0x013C0007F7", 9109 "Counter": "0,1,2,3", 9110 "EventName": "OCR.ALL_READS.L3_MISS.NO_SNOOP_NEEDED", 9111 "MSRIndex": "0x1a6,0x1a7", 9112 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 9113 "SampleAfterValue": "100003", 9114 "CounterHTOff": "0,1,2,3" 9115 }, 9116 { 9117 "Offcore": "1", 9118 "EventCode": "0xB7, 0xBB", 9119 "UMask": "0x1", 9120 "BriefDescription": "TBD TBD", 9121 "MSRValue": "0x023C0007F7", 9122 "Counter": "0,1,2,3", 9123 "EventName": "OCR.ALL_READS.L3_MISS.SNOOP_MISS", 9124 "MSRIndex": "0x1a6,0x1a7", 9125 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 9126 "SampleAfterValue": "100003", 9127 "CounterHTOff": "0,1,2,3" 9128 }, 9129 { 9130 "Offcore": "1", 9131 "EventCode": "0xB7, 0xBB", 9132 "UMask": "0x1", 9133 "BriefDescription": "TBD TBD TBD", 9134 "MSRValue": "0x043C0007F7", 9135 "Counter": "0,1,2,3", 9136 "EventName": "OCR.ALL_READS.L3_MISS.HIT_OTHER_CORE_NO_FWD", 9137 "MSRIndex": "0x1a6,0x1a7", 9138 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 9139 "SampleAfterValue": "100003", 9140 "CounterHTOff": "0,1,2,3" 9141 }, 9142 { 9143 "Offcore": "1", 9144 "EventCode": "0xB7, 0xBB", 9145 "UMask": "0x1", 9146 "BriefDescription": "TBD TBD TBD", 9147 "MSRValue": "0x083C0007F7", 9148 "Counter": "0,1,2,3", 9149 "EventName": "OCR.ALL_READS.L3_MISS.HIT_OTHER_CORE_FWD", 9150 "MSRIndex": "0x1a6,0x1a7", 9151 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 9152 "SampleAfterValue": "100003", 9153 "CounterHTOff": "0,1,2,3" 9154 }, 9155 { 9156 "Offcore": "1", 9157 "EventCode": "0xB7, 0xBB", 9158 "UMask": "0x1", 9159 "BriefDescription": "TBD TBD TBD", 9160 "MSRValue": "0x103C0007F7", 9161 "Counter": "0,1,2,3", 9162 "EventName": "OCR.ALL_READS.L3_MISS.HITM_OTHER_CORE", 9163 "MSRIndex": "0x1a6,0x1a7", 9164 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 9165 "SampleAfterValue": "100003", 9166 "CounterHTOff": "0,1,2,3" 9167 }, 9168 { 9169 "Offcore": "1", 9170 "EventCode": "0xB7, 0xBB", 9171 "UMask": "0x1", 9172 "BriefDescription": "TBD TBD TBD", 9173 "MSRValue": "0x3FBC0007F7", 9174 "Counter": "0,1,2,3", 9175 "EventName": "OCR.ALL_READS.L3_MISS.ANY_SNOOP", 9176 "MSRIndex": "0x1a6,0x1a7", 9177 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 9178 "SampleAfterValue": "100003", 9179 "CounterHTOff": "0,1,2,3" 9180 }, 9181 { 9182 "Offcore": "1", 9183 "EventCode": "0xB7, 0xBB", 9184 "UMask": "0x1", 9185 "BriefDescription": "Counts demand data reads TBD", 9186 "MSRValue": "0x063B800001", 9187 "Counter": "0,1,2,3", 9188 "EventName": "OCR.DEMAND_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", 9189 "MSRIndex": "0x1a6,0x1a7", 9190 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 9191 "SampleAfterValue": "100003", 9192 "CounterHTOff": "0,1,2,3" 9193 }, 9194 { 9195 "Offcore": "1", 9196 "EventCode": "0xB7, 0xBB", 9197 "UMask": "0x1", 9198 "BriefDescription": "Counts demand data reads TBD", 9199 "MSRValue": "0x0604000001", 9200 "Counter": "0,1,2,3", 9201 "EventName": "OCR.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", 9202 "MSRIndex": "0x1a6,0x1a7", 9203 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 9204 "SampleAfterValue": "100003", 9205 "CounterHTOff": "0,1,2,3" 9206 }, 9207 { 9208 "Offcore": "1", 9209 "EventCode": "0xB7, 0xBB", 9210 "UMask": "0x1", 9211 "BriefDescription": "Counts all demand data writes (RFOs) TBD", 9212 "MSRValue": "0x063B800002", 9213 "Counter": "0,1,2,3", 9214 "EventName": "OCR.DEMAND_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", 9215 "MSRIndex": "0x1a6,0x1a7", 9216 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 9217 "SampleAfterValue": "100003", 9218 "CounterHTOff": "0,1,2,3" 9219 }, 9220 { 9221 "Offcore": "1", 9222 "EventCode": "0xB7, 0xBB", 9223 "UMask": "0x1", 9224 "BriefDescription": "Counts all demand data writes (RFOs) TBD", 9225 "MSRValue": "0x0604000002", 9226 "Counter": "0,1,2,3", 9227 "EventName": "OCR.DEMAND_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", 9228 "MSRIndex": "0x1a6,0x1a7", 9229 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 9230 "SampleAfterValue": "100003", 9231 "CounterHTOff": "0,1,2,3" 9232 }, 9233 { 9234 "Offcore": "1", 9235 "EventCode": "0xB7, 0xBB", 9236 "UMask": "0x1", 9237 "BriefDescription": "Counts all demand code reads TBD", 9238 "MSRValue": "0x063B800004", 9239 "Counter": "0,1,2,3", 9240 "EventName": "OCR.DEMAND_CODE_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", 9241 "MSRIndex": "0x1a6,0x1a7", 9242 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 9243 "SampleAfterValue": "100003", 9244 "CounterHTOff": "0,1,2,3" 9245 }, 9246 { 9247 "Offcore": "1", 9248 "EventCode": "0xB7, 0xBB", 9249 "UMask": "0x1", 9250 "BriefDescription": "Counts all demand code reads TBD", 9251 "MSRValue": "0x0604000004", 9252 "Counter": "0,1,2,3", 9253 "EventName": "OCR.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", 9254 "MSRIndex": "0x1a6,0x1a7", 9255 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 9256 "SampleAfterValue": "100003", 9257 "CounterHTOff": "0,1,2,3" 9258 }, 9259 { 9260 "Offcore": "1", 9261 "EventCode": "0xB7, 0xBB", 9262 "UMask": "0x1", 9263 "BriefDescription": "Counts prefetch (that bring data to L2) data reads TBD", 9264 "MSRValue": "0x063B800010", 9265 "Counter": "0,1,2,3", 9266 "EventName": "OCR.PF_L2_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", 9267 "MSRIndex": "0x1a6,0x1a7", 9268 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 9269 "SampleAfterValue": "100003", 9270 "CounterHTOff": "0,1,2,3" 9271 }, 9272 { 9273 "Offcore": "1", 9274 "EventCode": "0xB7, 0xBB", 9275 "UMask": "0x1", 9276 "BriefDescription": "Counts prefetch (that bring data to L2) data reads TBD", 9277 "MSRValue": "0x0604000010", 9278 "Counter": "0,1,2,3", 9279 "EventName": "OCR.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", 9280 "MSRIndex": "0x1a6,0x1a7", 9281 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 9282 "SampleAfterValue": "100003", 9283 "CounterHTOff": "0,1,2,3" 9284 }, 9285 { 9286 "Offcore": "1", 9287 "EventCode": "0xB7, 0xBB", 9288 "UMask": "0x1", 9289 "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs TBD", 9290 "MSRValue": "0x063B800020", 9291 "Counter": "0,1,2,3", 9292 "EventName": "OCR.PF_L2_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", 9293 "MSRIndex": "0x1a6,0x1a7", 9294 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 9295 "SampleAfterValue": "100003", 9296 "CounterHTOff": "0,1,2,3" 9297 }, 9298 { 9299 "Offcore": "1", 9300 "EventCode": "0xB7, 0xBB", 9301 "UMask": "0x1", 9302 "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs TBD", 9303 "MSRValue": "0x0604000020", 9304 "Counter": "0,1,2,3", 9305 "EventName": "OCR.PF_L2_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", 9306 "MSRIndex": "0x1a6,0x1a7", 9307 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 9308 "SampleAfterValue": "100003", 9309 "CounterHTOff": "0,1,2,3" 9310 }, 9311 { 9312 "Offcore": "1", 9313 "EventCode": "0xB7, 0xBB", 9314 "UMask": "0x1", 9315 "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads TBD", 9316 "MSRValue": "0x063B800080", 9317 "Counter": "0,1,2,3", 9318 "EventName": "OCR.PF_L3_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", 9319 "MSRIndex": "0x1a6,0x1a7", 9320 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 9321 "SampleAfterValue": "100003", 9322 "CounterHTOff": "0,1,2,3" 9323 }, 9324 { 9325 "Offcore": "1", 9326 "EventCode": "0xB7, 0xBB", 9327 "UMask": "0x1", 9328 "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads TBD", 9329 "MSRValue": "0x0604000080", 9330 "Counter": "0,1,2,3", 9331 "EventName": "OCR.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", 9332 "MSRIndex": "0x1a6,0x1a7", 9333 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 9334 "SampleAfterValue": "100003", 9335 "CounterHTOff": "0,1,2,3" 9336 }, 9337 { 9338 "Offcore": "1", 9339 "EventCode": "0xB7, 0xBB", 9340 "UMask": "0x1", 9341 "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs TBD", 9342 "MSRValue": "0x063B800100", 9343 "Counter": "0,1,2,3", 9344 "EventName": "OCR.PF_L3_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", 9345 "MSRIndex": "0x1a6,0x1a7", 9346 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 9347 "SampleAfterValue": "100003", 9348 "CounterHTOff": "0,1,2,3" 9349 }, 9350 { 9351 "Offcore": "1", 9352 "EventCode": "0xB7, 0xBB", 9353 "UMask": "0x1", 9354 "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs TBD", 9355 "MSRValue": "0x0604000100", 9356 "Counter": "0,1,2,3", 9357 "EventName": "OCR.PF_L3_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", 9358 "MSRIndex": "0x1a6,0x1a7", 9359 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 9360 "SampleAfterValue": "100003", 9361 "CounterHTOff": "0,1,2,3" 9362 }, 9363 { 9364 "Offcore": "1", 9365 "EventCode": "0xB7, 0xBB", 9366 "UMask": "0x1", 9367 "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests TBD", 9368 "MSRValue": "0x063B800400", 9369 "Counter": "0,1,2,3", 9370 "EventName": "OCR.PF_L1D_AND_SW.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", 9371 "MSRIndex": "0x1a6,0x1a7", 9372 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 9373 "SampleAfterValue": "100003", 9374 "CounterHTOff": "0,1,2,3" 9375 }, 9376 { 9377 "Offcore": "1", 9378 "EventCode": "0xB7, 0xBB", 9379 "UMask": "0x1", 9380 "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests TBD", 9381 "MSRValue": "0x0604000400", 9382 "Counter": "0,1,2,3", 9383 "EventName": "OCR.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", 9384 "MSRIndex": "0x1a6,0x1a7", 9385 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 9386 "SampleAfterValue": "100003", 9387 "CounterHTOff": "0,1,2,3" 9388 }, 9389 { 9390 "Offcore": "1", 9391 "EventCode": "0xB7, 0xBB", 9392 "UMask": "0x1", 9393 "BriefDescription": "Counts any other requests TBD", 9394 "MSRValue": "0x063B808000", 9395 "Counter": "0,1,2,3", 9396 "EventName": "OCR.OTHER.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", 9397 "MSRIndex": "0x1a6,0x1a7", 9398 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 9399 "SampleAfterValue": "100003", 9400 "CounterHTOff": "0,1,2,3" 9401 }, 9402 { 9403 "Offcore": "1", 9404 "EventCode": "0xB7, 0xBB", 9405 "UMask": "0x1", 9406 "BriefDescription": "Counts any other requests TBD", 9407 "MSRValue": "0x0604008000", 9408 "Counter": "0,1,2,3", 9409 "EventName": "OCR.OTHER.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", 9410 "MSRIndex": "0x1a6,0x1a7", 9411 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 9412 "SampleAfterValue": "100003", 9413 "CounterHTOff": "0,1,2,3" 9414 }, 9415 { 9416 "Offcore": "1", 9417 "EventCode": "0xB7, 0xBB", 9418 "UMask": "0x1", 9419 "BriefDescription": "TBD TBD", 9420 "MSRValue": "0x063B800490", 9421 "Counter": "0,1,2,3", 9422 "EventName": "OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", 9423 "MSRIndex": "0x1a6,0x1a7", 9424 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 9425 "SampleAfterValue": "100003", 9426 "CounterHTOff": "0,1,2,3" 9427 }, 9428 { 9429 "Offcore": "1", 9430 "EventCode": "0xB7, 0xBB", 9431 "UMask": "0x1", 9432 "BriefDescription": "TBD TBD", 9433 "MSRValue": "0x0604000490", 9434 "Counter": "0,1,2,3", 9435 "EventName": "OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", 9436 "MSRIndex": "0x1a6,0x1a7", 9437 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 9438 "SampleAfterValue": "100003", 9439 "CounterHTOff": "0,1,2,3" 9440 }, 9441 { 9442 "Offcore": "1", 9443 "EventCode": "0xB7, 0xBB", 9444 "UMask": "0x1", 9445 "BriefDescription": "TBD TBD", 9446 "MSRValue": "0x063B800120", 9447 "Counter": "0,1,2,3", 9448 "EventName": "OCR.ALL_PF_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", 9449 "MSRIndex": "0x1a6,0x1a7", 9450 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 9451 "SampleAfterValue": "100003", 9452 "CounterHTOff": "0,1,2,3" 9453 }, 9454 { 9455 "Offcore": "1", 9456 "EventCode": "0xB7, 0xBB", 9457 "UMask": "0x1", 9458 "BriefDescription": "TBD TBD", 9459 "MSRValue": "0x0604000120", 9460 "Counter": "0,1,2,3", 9461 "EventName": "OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", 9462 "MSRIndex": "0x1a6,0x1a7", 9463 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 9464 "SampleAfterValue": "100003", 9465 "CounterHTOff": "0,1,2,3" 9466 }, 9467 { 9468 "Offcore": "1", 9469 "EventCode": "0xB7, 0xBB", 9470 "UMask": "0x1", 9471 "BriefDescription": "TBD TBD", 9472 "MSRValue": "0x063B800491", 9473 "Counter": "0,1,2,3", 9474 "EventName": "OCR.ALL_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", 9475 "MSRIndex": "0x1a6,0x1a7", 9476 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 9477 "SampleAfterValue": "100003", 9478 "CounterHTOff": "0,1,2,3" 9479 }, 9480 { 9481 "Offcore": "1", 9482 "EventCode": "0xB7, 0xBB", 9483 "UMask": "0x1", 9484 "BriefDescription": "TBD TBD", 9485 "MSRValue": "0x0604000491", 9486 "Counter": "0,1,2,3", 9487 "EventName": "OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", 9488 "MSRIndex": "0x1a6,0x1a7", 9489 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 9490 "SampleAfterValue": "100003", 9491 "CounterHTOff": "0,1,2,3" 9492 }, 9493 { 9494 "Offcore": "1", 9495 "EventCode": "0xB7, 0xBB", 9496 "UMask": "0x1", 9497 "BriefDescription": "TBD TBD", 9498 "MSRValue": "0x063B800122", 9499 "Counter": "0,1,2,3", 9500 "EventName": "OCR.ALL_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", 9501 "MSRIndex": "0x1a6,0x1a7", 9502 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 9503 "SampleAfterValue": "100003", 9504 "CounterHTOff": "0,1,2,3" 9505 }, 9506 { 9507 "Offcore": "1", 9508 "EventCode": "0xB7, 0xBB", 9509 "UMask": "0x1", 9510 "BriefDescription": "TBD TBD", 9511 "MSRValue": "0x0604000122", 9512 "Counter": "0,1,2,3", 9513 "EventName": "OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", 9514 "MSRIndex": "0x1a6,0x1a7", 9515 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 9516 "SampleAfterValue": "100003", 9517 "CounterHTOff": "0,1,2,3" 9518 }, 9519 { 9520 "Offcore": "1", 9521 "EventCode": "0xB7, 0xBB", 9522 "UMask": "0x1", 9523 "BriefDescription": "TBD TBD", 9524 "MSRValue": "0x063B8007F7", 9525 "Counter": "0,1,2,3", 9526 "EventName": "OCR.ALL_READS.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", 9527 "MSRIndex": "0x1a6,0x1a7", 9528 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 9529 "SampleAfterValue": "100003", 9530 "CounterHTOff": "0,1,2,3" 9531 }, 9532 { 9533 "Offcore": "1", 9534 "EventCode": "0xB7, 0xBB", 9535 "UMask": "0x1", 9536 "BriefDescription": "TBD TBD", 9537 "MSRValue": "0x06040007F7", 9538 "Counter": "0,1,2,3", 9539 "EventName": "OCR.ALL_READS.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", 9540 "MSRIndex": "0x1a6,0x1a7", 9541 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 9542 "SampleAfterValue": "100003", 9543 "CounterHTOff": "0,1,2,3" 9544 }, 9545 { 9546 "Offcore": "1", 9547 "EventCode": "0xB7, 0xBB", 9548 "UMask": "0x1", 9549 "BriefDescription": "Counts demand data reads TBD", 9550 "MSRValue": "0x103FC00001", 9551 "Counter": "0,1,2,3", 9552 "EventName": "OCR.DEMAND_DATA_RD.L3_MISS.REMOTE_HITM", 9553 "MSRIndex": "0x1a6,0x1a7", 9554 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 9555 "SampleAfterValue": "100003", 9556 "CounterHTOff": "0,1,2,3" 9557 }, 9558 { 9559 "Offcore": "1", 9560 "EventCode": "0xB7, 0xBB", 9561 "UMask": "0x1", 9562 "BriefDescription": "Counts all demand data writes (RFOs) TBD", 9563 "MSRValue": "0x103FC00002", 9564 "Counter": "0,1,2,3", 9565 "EventName": "OCR.DEMAND_RFO.L3_MISS.REMOTE_HITM", 9566 "MSRIndex": "0x1a6,0x1a7", 9567 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 9568 "SampleAfterValue": "100003", 9569 "CounterHTOff": "0,1,2,3" 9570 }, 9571 { 9572 "Offcore": "1", 9573 "EventCode": "0xB7, 0xBB", 9574 "UMask": "0x1", 9575 "BriefDescription": "Counts all demand code reads TBD", 9576 "MSRValue": "0x103FC00004", 9577 "Counter": "0,1,2,3", 9578 "EventName": "OCR.DEMAND_CODE_RD.L3_MISS.REMOTE_HITM", 9579 "MSRIndex": "0x1a6,0x1a7", 9580 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 9581 "SampleAfterValue": "100003", 9582 "CounterHTOff": "0,1,2,3" 9583 }, 9584 { 9585 "Offcore": "1", 9586 "EventCode": "0xB7, 0xBB", 9587 "UMask": "0x1", 9588 "BriefDescription": "Counts prefetch (that bring data to L2) data reads TBD", 9589 "MSRValue": "0x103FC00010", 9590 "Counter": "0,1,2,3", 9591 "EventName": "OCR.PF_L2_DATA_RD.L3_MISS.REMOTE_HITM", 9592 "MSRIndex": "0x1a6,0x1a7", 9593 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 9594 "SampleAfterValue": "100003", 9595 "CounterHTOff": "0,1,2,3" 9596 }, 9597 { 9598 "Offcore": "1", 9599 "EventCode": "0xB7, 0xBB", 9600 "UMask": "0x1", 9601 "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs TBD", 9602 "MSRValue": "0x103FC00020", 9603 "Counter": "0,1,2,3", 9604 "EventName": "OCR.PF_L2_RFO.L3_MISS.REMOTE_HITM", 9605 "MSRIndex": "0x1a6,0x1a7", 9606 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 9607 "SampleAfterValue": "100003", 9608 "CounterHTOff": "0,1,2,3" 9609 }, 9610 { 9611 "Offcore": "1", 9612 "EventCode": "0xB7, 0xBB", 9613 "UMask": "0x1", 9614 "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads TBD", 9615 "MSRValue": "0x103FC00080", 9616 "Counter": "0,1,2,3", 9617 "EventName": "OCR.PF_L3_DATA_RD.L3_MISS.REMOTE_HITM", 9618 "MSRIndex": "0x1a6,0x1a7", 9619 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 9620 "SampleAfterValue": "100003", 9621 "CounterHTOff": "0,1,2,3" 9622 }, 9623 { 9624 "Offcore": "1", 9625 "EventCode": "0xB7, 0xBB", 9626 "UMask": "0x1", 9627 "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs TBD", 9628 "MSRValue": "0x103FC00100", 9629 "Counter": "0,1,2,3", 9630 "EventName": "OCR.PF_L3_RFO.L3_MISS.REMOTE_HITM", 9631 "MSRIndex": "0x1a6,0x1a7", 9632 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 9633 "SampleAfterValue": "100003", 9634 "CounterHTOff": "0,1,2,3" 9635 }, 9636 { 9637 "Offcore": "1", 9638 "EventCode": "0xB7, 0xBB", 9639 "UMask": "0x1", 9640 "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests TBD", 9641 "MSRValue": "0x103FC00400", 9642 "Counter": "0,1,2,3", 9643 "EventName": "OCR.PF_L1D_AND_SW.L3_MISS.REMOTE_HITM", 9644 "MSRIndex": "0x1a6,0x1a7", 9645 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 9646 "SampleAfterValue": "100003", 9647 "CounterHTOff": "0,1,2,3" 9648 }, 9649 { 9650 "Offcore": "1", 9651 "EventCode": "0xB7, 0xBB", 9652 "UMask": "0x1", 9653 "BriefDescription": "Counts any other requests TBD", 9654 "MSRValue": "0x103FC08000", 9655 "Counter": "0,1,2,3", 9656 "EventName": "OCR.OTHER.L3_MISS.REMOTE_HITM", 9657 "MSRIndex": "0x1a6,0x1a7", 9658 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 9659 "SampleAfterValue": "100003", 9660 "CounterHTOff": "0,1,2,3" 9661 }, 9662 { 9663 "Offcore": "1", 9664 "EventCode": "0xB7, 0xBB", 9665 "UMask": "0x1", 9666 "BriefDescription": "TBD TBD", 9667 "MSRValue": "0x103FC00490", 9668 "Counter": "0,1,2,3", 9669 "EventName": "OCR.ALL_PF_DATA_RD.L3_MISS.REMOTE_HITM", 9670 "MSRIndex": "0x1a6,0x1a7", 9671 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 9672 "SampleAfterValue": "100003", 9673 "CounterHTOff": "0,1,2,3" 9674 }, 9675 { 9676 "Offcore": "1", 9677 "EventCode": "0xB7, 0xBB", 9678 "UMask": "0x1", 9679 "BriefDescription": "TBD TBD", 9680 "MSRValue": "0x103FC00120", 9681 "Counter": "0,1,2,3", 9682 "EventName": "OCR.ALL_PF_RFO.L3_MISS.REMOTE_HITM", 9683 "MSRIndex": "0x1a6,0x1a7", 9684 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 9685 "SampleAfterValue": "100003", 9686 "CounterHTOff": "0,1,2,3" 9687 }, 9688 { 9689 "Offcore": "1", 9690 "EventCode": "0xB7, 0xBB", 9691 "UMask": "0x1", 9692 "BriefDescription": "TBD TBD", 9693 "MSRValue": "0x103FC00491", 9694 "Counter": "0,1,2,3", 9695 "EventName": "OCR.ALL_DATA_RD.L3_MISS.REMOTE_HITM", 9696 "MSRIndex": "0x1a6,0x1a7", 9697 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 9698 "SampleAfterValue": "100003", 9699 "CounterHTOff": "0,1,2,3" 9700 }, 9701 { 9702 "Offcore": "1", 9703 "EventCode": "0xB7, 0xBB", 9704 "UMask": "0x1", 9705 "BriefDescription": "TBD TBD", 9706 "MSRValue": "0x103FC00122", 9707 "Counter": "0,1,2,3", 9708 "EventName": "OCR.ALL_RFO.L3_MISS.REMOTE_HITM", 9709 "MSRIndex": "0x1a6,0x1a7", 9710 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 9711 "SampleAfterValue": "100003", 9712 "CounterHTOff": "0,1,2,3" 9713 }, 9714 { 9715 "Offcore": "1", 9716 "EventCode": "0xB7, 0xBB", 9717 "UMask": "0x1", 9718 "BriefDescription": "TBD TBD", 9719 "MSRValue": "0x103FC007F7", 9720 "Counter": "0,1,2,3", 9721 "EventName": "OCR.ALL_READS.L3_MISS.REMOTE_HITM", 9722 "MSRIndex": "0x1a6,0x1a7", 9723 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 9724 "SampleAfterValue": "100003", 9725 "CounterHTOff": "0,1,2,3" 9726 }, 9727 { 9728 "Offcore": "1", 9729 "EventCode": "0xB7, 0xBB", 9730 "UMask": "0x1", 9731 "BriefDescription": "Counts demand data reads TBD", 9732 "MSRValue": "0x083FC00001", 9733 "Counter": "0,1,2,3", 9734 "EventName": "OCR.DEMAND_DATA_RD.L3_MISS.REMOTE_HIT_FORWARD", 9735 "MSRIndex": "0x1a6,0x1a7", 9736 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 9737 "SampleAfterValue": "100003", 9738 "CounterHTOff": "0,1,2,3" 9739 }, 9740 { 9741 "Offcore": "1", 9742 "EventCode": "0xB7, 0xBB", 9743 "UMask": "0x1", 9744 "BriefDescription": "Counts all demand data writes (RFOs) TBD", 9745 "MSRValue": "0x083FC00002", 9746 "Counter": "0,1,2,3", 9747 "EventName": "OCR.DEMAND_RFO.L3_MISS.REMOTE_HIT_FORWARD", 9748 "MSRIndex": "0x1a6,0x1a7", 9749 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 9750 "SampleAfterValue": "100003", 9751 "CounterHTOff": "0,1,2,3" 9752 }, 9753 { 9754 "Offcore": "1", 9755 "EventCode": "0xB7, 0xBB", 9756 "UMask": "0x1", 9757 "BriefDescription": "Counts all demand code reads TBD", 9758 "MSRValue": "0x083FC00004", 9759 "Counter": "0,1,2,3", 9760 "EventName": "OCR.DEMAND_CODE_RD.L3_MISS.REMOTE_HIT_FORWARD", 9761 "MSRIndex": "0x1a6,0x1a7", 9762 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 9763 "SampleAfterValue": "100003", 9764 "CounterHTOff": "0,1,2,3" 9765 }, 9766 { 9767 "Offcore": "1", 9768 "EventCode": "0xB7, 0xBB", 9769 "UMask": "0x1", 9770 "BriefDescription": "Counts prefetch (that bring data to L2) data reads TBD", 9771 "MSRValue": "0x083FC00010", 9772 "Counter": "0,1,2,3", 9773 "EventName": "OCR.PF_L2_DATA_RD.L3_MISS.REMOTE_HIT_FORWARD", 9774 "MSRIndex": "0x1a6,0x1a7", 9775 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 9776 "SampleAfterValue": "100003", 9777 "CounterHTOff": "0,1,2,3" 9778 }, 9779 { 9780 "Offcore": "1", 9781 "EventCode": "0xB7, 0xBB", 9782 "UMask": "0x1", 9783 "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs TBD", 9784 "MSRValue": "0x083FC00020", 9785 "Counter": "0,1,2,3", 9786 "EventName": "OCR.PF_L2_RFO.L3_MISS.REMOTE_HIT_FORWARD", 9787 "MSRIndex": "0x1a6,0x1a7", 9788 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 9789 "SampleAfterValue": "100003", 9790 "CounterHTOff": "0,1,2,3" 9791 }, 9792 { 9793 "Offcore": "1", 9794 "EventCode": "0xB7, 0xBB", 9795 "UMask": "0x1", 9796 "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads TBD", 9797 "MSRValue": "0x083FC00080", 9798 "Counter": "0,1,2,3", 9799 "EventName": "OCR.PF_L3_DATA_RD.L3_MISS.REMOTE_HIT_FORWARD", 9800 "MSRIndex": "0x1a6,0x1a7", 9801 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 9802 "SampleAfterValue": "100003", 9803 "CounterHTOff": "0,1,2,3" 9804 }, 9805 { 9806 "Offcore": "1", 9807 "EventCode": "0xB7, 0xBB", 9808 "UMask": "0x1", 9809 "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs TBD", 9810 "MSRValue": "0x083FC00100", 9811 "Counter": "0,1,2,3", 9812 "EventName": "OCR.PF_L3_RFO.L3_MISS.REMOTE_HIT_FORWARD", 9813 "MSRIndex": "0x1a6,0x1a7", 9814 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 9815 "SampleAfterValue": "100003", 9816 "CounterHTOff": "0,1,2,3" 9817 }, 9818 { 9819 "Offcore": "1", 9820 "EventCode": "0xB7, 0xBB", 9821 "UMask": "0x1", 9822 "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests TBD", 9823 "MSRValue": "0x083FC00400", 9824 "Counter": "0,1,2,3", 9825 "EventName": "OCR.PF_L1D_AND_SW.L3_MISS.REMOTE_HIT_FORWARD", 9826 "MSRIndex": "0x1a6,0x1a7", 9827 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 9828 "SampleAfterValue": "100003", 9829 "CounterHTOff": "0,1,2,3" 9830 }, 9831 { 9832 "Offcore": "1", 9833 "EventCode": "0xB7, 0xBB", 9834 "UMask": "0x1", 9835 "BriefDescription": "Counts any other requests TBD", 9836 "MSRValue": "0x083FC08000", 9837 "Counter": "0,1,2,3", 9838 "EventName": "OCR.OTHER.L3_MISS.REMOTE_HIT_FORWARD", 9839 "MSRIndex": "0x1a6,0x1a7", 9840 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 9841 "SampleAfterValue": "100003", 9842 "CounterHTOff": "0,1,2,3" 9843 }, 9844 { 9845 "Offcore": "1", 9846 "EventCode": "0xB7, 0xBB", 9847 "UMask": "0x1", 9848 "BriefDescription": "TBD TBD", 9849 "MSRValue": "0x083FC00490", 9850 "Counter": "0,1,2,3", 9851 "EventName": "OCR.ALL_PF_DATA_RD.L3_MISS.REMOTE_HIT_FORWARD", 9852 "MSRIndex": "0x1a6,0x1a7", 9853 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 9854 "SampleAfterValue": "100003", 9855 "CounterHTOff": "0,1,2,3" 9856 }, 9857 { 9858 "Offcore": "1", 9859 "EventCode": "0xB7, 0xBB", 9860 "UMask": "0x1", 9861 "BriefDescription": "TBD TBD", 9862 "MSRValue": "0x083FC00120", 9863 "Counter": "0,1,2,3", 9864 "EventName": "OCR.ALL_PF_RFO.L3_MISS.REMOTE_HIT_FORWARD", 9865 "MSRIndex": "0x1a6,0x1a7", 9866 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 9867 "SampleAfterValue": "100003", 9868 "CounterHTOff": "0,1,2,3" 9869 }, 9870 { 9871 "Offcore": "1", 9872 "EventCode": "0xB7, 0xBB", 9873 "UMask": "0x1", 9874 "BriefDescription": "TBD TBD", 9875 "MSRValue": "0x083FC00491", 9876 "Counter": "0,1,2,3", 9877 "EventName": "OCR.ALL_DATA_RD.L3_MISS.REMOTE_HIT_FORWARD", 9878 "MSRIndex": "0x1a6,0x1a7", 9879 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 9880 "SampleAfterValue": "100003", 9881 "CounterHTOff": "0,1,2,3" 9882 }, 9883 { 9884 "Offcore": "1", 9885 "EventCode": "0xB7, 0xBB", 9886 "UMask": "0x1", 9887 "BriefDescription": "TBD TBD", 9888 "MSRValue": "0x083FC00122", 9889 "Counter": "0,1,2,3", 9890 "EventName": "OCR.ALL_RFO.L3_MISS.REMOTE_HIT_FORWARD", 9891 "MSRIndex": "0x1a6,0x1a7", 9892 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 9893 "SampleAfterValue": "100003", 9894 "CounterHTOff": "0,1,2,3" 9895 }, 9896 { 9897 "Offcore": "1", 9898 "EventCode": "0xB7, 0xBB", 9899 "UMask": "0x1", 9900 "BriefDescription": "TBD TBD", 9901 "MSRValue": "0x083FC007F7", 9902 "Counter": "0,1,2,3", 9903 "EventName": "OCR.ALL_READS.L3_MISS.REMOTE_HIT_FORWARD", 9904 "MSRIndex": "0x1a6,0x1a7", 9905 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 9906 "SampleAfterValue": "100003", 9907 "CounterHTOff": "0,1,2,3" 9908 } 9909]