1ecd94f1bSKan Liang[ 2ecd94f1bSKan Liang { 3ecd94f1bSKan Liang "EventCode": "0x54", 4ecd94f1bSKan Liang "UMask": "0x1", 5ecd94f1bSKan Liang "BriefDescription": "Number of times a transactional abort was signaled due to a data conflict on a transactionally accessed address", 6ecd94f1bSKan Liang "Counter": "0,1,2,3", 7ecd94f1bSKan Liang "EventName": "TX_MEM.ABORT_CONFLICT", 8ecd94f1bSKan Liang "PublicDescription": "Number of times a TSX line had a cache conflict.", 9ecd94f1bSKan Liang "SampleAfterValue": "2000003", 10ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3,4,5,6,7" 11ecd94f1bSKan Liang }, 12ecd94f1bSKan Liang { 13ecd94f1bSKan Liang "EventCode": "0x54", 14ecd94f1bSKan Liang "UMask": "0x2", 15ecd94f1bSKan Liang "BriefDescription": "Number of times a transactional abort was signaled due to a data capacity limitation for transactional reads or writes.", 16ecd94f1bSKan Liang "Counter": "0,1,2,3", 17ecd94f1bSKan Liang "EventName": "TX_MEM.ABORT_CAPACITY", 18ecd94f1bSKan Liang "SampleAfterValue": "2000003", 19ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3,4,5,6,7" 20ecd94f1bSKan Liang }, 21ecd94f1bSKan Liang { 22ecd94f1bSKan Liang "EventCode": "0x54", 23ecd94f1bSKan Liang "UMask": "0x4", 24ecd94f1bSKan Liang "BriefDescription": "Number of times a HLE transactional region aborted due to a non XRELEASE prefixed instruction writing to an elided lock in the elision buffer", 25ecd94f1bSKan Liang "Counter": "0,1,2,3", 26ecd94f1bSKan Liang "EventName": "TX_MEM.ABORT_HLE_STORE_TO_ELIDED_LOCK", 27ecd94f1bSKan Liang "PublicDescription": "Number of times a TSX Abort was triggered due to a non-release/commit store to lock.", 28ecd94f1bSKan Liang "SampleAfterValue": "2000003", 29ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3,4,5,6,7" 30ecd94f1bSKan Liang }, 31ecd94f1bSKan Liang { 32ecd94f1bSKan Liang "EventCode": "0x54", 33ecd94f1bSKan Liang "UMask": "0x8", 34ecd94f1bSKan Liang "BriefDescription": "Number of times an HLE transactional execution aborted due to NoAllocatedElisionBuffer being non-zero.", 35ecd94f1bSKan Liang "Counter": "0,1,2,3", 36ecd94f1bSKan Liang "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_NOT_EMPTY", 37ecd94f1bSKan Liang "PublicDescription": "Number of times a TSX Abort was triggered due to commit but Lock Buffer not empty.", 38ecd94f1bSKan Liang "SampleAfterValue": "2000003", 39ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3,4,5,6,7" 40ecd94f1bSKan Liang }, 41ecd94f1bSKan Liang { 42ecd94f1bSKan Liang "EventCode": "0x54", 43ecd94f1bSKan Liang "UMask": "0x10", 44ecd94f1bSKan Liang "BriefDescription": "Number of times an HLE transactional execution aborted due to XRELEASE lock not satisfying the address and value requirements in the elision buffer", 45ecd94f1bSKan Liang "Counter": "0,1,2,3", 46ecd94f1bSKan Liang "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_MISMATCH", 47ecd94f1bSKan Liang "PublicDescription": "Number of times a TSX Abort was triggered due to release/commit but data and address mismatch.", 48ecd94f1bSKan Liang "SampleAfterValue": "2000003", 49ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3,4,5,6,7" 50ecd94f1bSKan Liang }, 51ecd94f1bSKan Liang { 52ecd94f1bSKan Liang "EventCode": "0x54", 53ecd94f1bSKan Liang "UMask": "0x20", 54ecd94f1bSKan Liang "BriefDescription": "Number of times an HLE transactional execution aborted due to an unsupported read alignment from the elision buffer.", 55ecd94f1bSKan Liang "Counter": "0,1,2,3", 56ecd94f1bSKan Liang "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_UNSUPPORTED_ALIGNMENT", 57ecd94f1bSKan Liang "PublicDescription": "Number of times a TSX Abort was triggered due to attempting an unsupported alignment from Lock Buffer.", 58ecd94f1bSKan Liang "SampleAfterValue": "2000003", 59ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3,4,5,6,7" 60ecd94f1bSKan Liang }, 61ecd94f1bSKan Liang { 62ecd94f1bSKan Liang "EventCode": "0x54", 63ecd94f1bSKan Liang "UMask": "0x40", 64ecd94f1bSKan Liang "BriefDescription": "Number of times HLE lock could not be elided due to ElisionBufferAvailable being zero.", 65ecd94f1bSKan Liang "Counter": "0,1,2,3", 66ecd94f1bSKan Liang "EventName": "TX_MEM.HLE_ELISION_BUFFER_FULL", 67ecd94f1bSKan Liang "PublicDescription": "Number of times we could not allocate Lock Buffer.", 68ecd94f1bSKan Liang "SampleAfterValue": "2000003", 69ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3,4,5,6,7" 70ecd94f1bSKan Liang }, 71ecd94f1bSKan Liang { 72ecd94f1bSKan Liang "EventCode": "0x5d", 73ecd94f1bSKan Liang "UMask": "0x1", 74ecd94f1bSKan Liang "BriefDescription": "Counts the number of times a class of instructions that may cause a transactional abort was executed. Since this is the count of execution, it may not always cause a transactional abort.", 75ecd94f1bSKan Liang "Counter": "0,1,2,3", 76ecd94f1bSKan Liang "EventName": "TX_EXEC.MISC1", 77ecd94f1bSKan Liang "SampleAfterValue": "2000003", 78ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3,4,5,6,7" 79ecd94f1bSKan Liang }, 80ecd94f1bSKan Liang { 81ecd94f1bSKan Liang "EventCode": "0x5d", 82ecd94f1bSKan Liang "UMask": "0x2", 83ecd94f1bSKan Liang "BriefDescription": "Counts the number of times a class of instructions (e.g., vzeroupper) that may cause a transactional abort was executed inside a transactional region", 84ecd94f1bSKan Liang "Counter": "0,1,2,3", 85ecd94f1bSKan Liang "EventName": "TX_EXEC.MISC2", 86ecd94f1bSKan Liang "PublicDescription": "Unfriendly TSX abort triggered by a vzeroupper instruction.", 87ecd94f1bSKan Liang "SampleAfterValue": "2000003", 88ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3,4,5,6,7" 89ecd94f1bSKan Liang }, 90ecd94f1bSKan Liang { 91ecd94f1bSKan Liang "EventCode": "0x5d", 92ecd94f1bSKan Liang "UMask": "0x4", 93ecd94f1bSKan Liang "BriefDescription": "Counts the number of times an instruction execution caused the transactional nest count supported to be exceeded", 94ecd94f1bSKan Liang "Counter": "0,1,2,3", 95ecd94f1bSKan Liang "EventName": "TX_EXEC.MISC3", 96ecd94f1bSKan Liang "PublicDescription": "Unfriendly TSX abort triggered by a nest count that is too deep.", 97ecd94f1bSKan Liang "SampleAfterValue": "2000003", 98ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3,4,5,6,7" 99ecd94f1bSKan Liang }, 100ecd94f1bSKan Liang { 101ecd94f1bSKan Liang "EventCode": "0x5d", 102ecd94f1bSKan Liang "UMask": "0x8", 103ecd94f1bSKan Liang "BriefDescription": "Counts the number of times a XBEGIN instruction was executed inside an HLE transactional region.", 104ecd94f1bSKan Liang "Counter": "0,1,2,3", 105ecd94f1bSKan Liang "EventName": "TX_EXEC.MISC4", 106ecd94f1bSKan Liang "PublicDescription": "RTM region detected inside HLE.", 107ecd94f1bSKan Liang "SampleAfterValue": "2000003", 108ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3,4,5,6,7" 109ecd94f1bSKan Liang }, 110ecd94f1bSKan Liang { 111ecd94f1bSKan Liang "EventCode": "0x5d", 112ecd94f1bSKan Liang "UMask": "0x10", 113ecd94f1bSKan Liang "BriefDescription": "Counts the number of times an HLE XACQUIRE instruction was executed inside an RTM transactional region", 114ecd94f1bSKan Liang "Counter": "0,1,2,3", 115ecd94f1bSKan Liang "EventName": "TX_EXEC.MISC5", 116ecd94f1bSKan Liang "PublicDescription": "Counts the number of times an HLE XACQUIRE instruction was executed inside an RTM transactional region.", 117ecd94f1bSKan Liang "SampleAfterValue": "2000003", 118ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3,4,5,6,7" 119ecd94f1bSKan Liang }, 120ecd94f1bSKan Liang { 121ecd94f1bSKan Liang "EventCode": "0x60", 122ecd94f1bSKan Liang "UMask": "0x10", 123ecd94f1bSKan Liang "BriefDescription": "Counts number of Offcore outstanding Demand Data Read requests that miss L3 cache in the superQ every cycle.", 124ecd94f1bSKan Liang "Counter": "0,1,2,3", 125ecd94f1bSKan Liang "EventName": "OFFCORE_REQUESTS_OUTSTANDING.L3_MISS_DEMAND_DATA_RD", 126ecd94f1bSKan Liang "SampleAfterValue": "2000003", 127ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3,4,5,6,7" 128ecd94f1bSKan Liang }, 129ecd94f1bSKan Liang { 130ecd94f1bSKan Liang "EventCode": "0x60", 131ecd94f1bSKan Liang "UMask": "0x10", 132ecd94f1bSKan Liang "BriefDescription": "Cycles with at least 6 Demand Data Read requests that miss L3 cache in the superQ.", 133ecd94f1bSKan Liang "Counter": "0,1,2,3", 134ecd94f1bSKan Liang "EventName": "OFFCORE_REQUESTS_OUTSTANDING.L3_MISS_DEMAND_DATA_RD_GE_6", 135ecd94f1bSKan Liang "CounterMask": "6", 136ecd94f1bSKan Liang "SampleAfterValue": "2000003", 137ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3,4,5,6,7" 138ecd94f1bSKan Liang }, 139ecd94f1bSKan Liang { 140ecd94f1bSKan Liang "EventCode": "0x60", 141ecd94f1bSKan Liang "UMask": "0x10", 142ecd94f1bSKan Liang "BriefDescription": "Cycles with at least 1 Demand Data Read requests who miss L3 cache in the superQ.", 143ecd94f1bSKan Liang "Counter": "0,1,2,3", 144ecd94f1bSKan Liang "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_L3_MISS_DEMAND_DATA_RD", 145ecd94f1bSKan Liang "CounterMask": "1", 146ecd94f1bSKan Liang "SampleAfterValue": "2000003", 147ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3,4,5,6,7" 148ecd94f1bSKan Liang }, 149ecd94f1bSKan Liang { 150ecd94f1bSKan Liang "EventCode": "0xA3", 151ecd94f1bSKan Liang "UMask": "0x2", 152ecd94f1bSKan Liang "BriefDescription": "Cycles while L3 cache miss demand load is outstanding.", 153ecd94f1bSKan Liang "Counter": "0,1,2,3", 154ecd94f1bSKan Liang "EventName": "CYCLE_ACTIVITY.CYCLES_L3_MISS", 155ecd94f1bSKan Liang "CounterMask": "2", 156ecd94f1bSKan Liang "SampleAfterValue": "2000003", 157ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3,4,5,6,7" 158ecd94f1bSKan Liang }, 159ecd94f1bSKan Liang { 160ecd94f1bSKan Liang "EventCode": "0xA3", 161ecd94f1bSKan Liang "UMask": "0x6", 162ecd94f1bSKan Liang "BriefDescription": "Execution stalls while L3 cache miss demand load is outstanding.", 163ecd94f1bSKan Liang "Counter": "0,1,2,3", 164ecd94f1bSKan Liang "EventName": "CYCLE_ACTIVITY.STALLS_L3_MISS", 165ecd94f1bSKan Liang "CounterMask": "6", 166ecd94f1bSKan Liang "SampleAfterValue": "2000003", 167ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3,4,5,6,7" 168ecd94f1bSKan Liang }, 169ecd94f1bSKan Liang { 170ecd94f1bSKan Liang "EventCode": "0xB0", 171ecd94f1bSKan Liang "UMask": "0x10", 172ecd94f1bSKan Liang "BriefDescription": "Demand Data Read requests who miss L3 cache", 173ecd94f1bSKan Liang "Counter": "0,1,2,3", 174ecd94f1bSKan Liang "EventName": "OFFCORE_REQUESTS.L3_MISS_DEMAND_DATA_RD", 175ecd94f1bSKan Liang "PublicDescription": "Demand Data Read requests who miss L3 cache.", 176ecd94f1bSKan Liang "SampleAfterValue": "100003", 177ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3,4,5,6,7" 178ecd94f1bSKan Liang }, 179ecd94f1bSKan Liang { 180ecd94f1bSKan Liang "EventCode": "0xC3", 181ecd94f1bSKan Liang "UMask": "0x2", 182ecd94f1bSKan Liang "BriefDescription": "Counts the number of machine clears due to memory order conflicts.", 183ecd94f1bSKan Liang "Counter": "0,1,2,3", 184ecd94f1bSKan Liang "EventName": "MACHINE_CLEARS.MEMORY_ORDERING", 185ecd94f1bSKan Liang "Errata": "SKL089", 186ecd94f1bSKan Liang "PublicDescription": "Counts the number of memory ordering Machine Clears detected. Memory Ordering Machine Clears can result from one of the following:a. memory disambiguation,b. external snoop, orc. cross SMT-HW-thread snoop (stores) hitting load buffer.", 187ecd94f1bSKan Liang "SampleAfterValue": "100003", 188ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3,4,5,6,7" 189ecd94f1bSKan Liang }, 190ecd94f1bSKan Liang { 191ecd94f1bSKan Liang "EventCode": "0xC8", 192ecd94f1bSKan Liang "UMask": "0x1", 193ecd94f1bSKan Liang "BriefDescription": "Number of times an HLE execution started.", 194ecd94f1bSKan Liang "Counter": "0,1,2,3", 195ecd94f1bSKan Liang "EventName": "HLE_RETIRED.START", 196ecd94f1bSKan Liang "PublicDescription": "Number of times we entered an HLE region. Does not count nested transactions.", 197ecd94f1bSKan Liang "SampleAfterValue": "2000003", 198ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3,4,5,6,7" 199ecd94f1bSKan Liang }, 200ecd94f1bSKan Liang { 201ecd94f1bSKan Liang "EventCode": "0xC8", 202ecd94f1bSKan Liang "UMask": "0x2", 203ecd94f1bSKan Liang "BriefDescription": "Number of times an HLE execution successfully committed", 204ecd94f1bSKan Liang "Counter": "0,1,2,3", 205ecd94f1bSKan Liang "EventName": "HLE_RETIRED.COMMIT", 206ecd94f1bSKan Liang "PublicDescription": "Number of times HLE commit succeeded.", 207ecd94f1bSKan Liang "SampleAfterValue": "2000003", 208ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3,4,5,6,7" 209ecd94f1bSKan Liang }, 210ecd94f1bSKan Liang { 211ecd94f1bSKan Liang "EventCode": "0xC8", 212ecd94f1bSKan Liang "UMask": "0x4", 213ecd94f1bSKan Liang "BriefDescription": "Number of times an HLE execution aborted due to any reasons (multiple categories may count as one). ", 214ecd94f1bSKan Liang "PEBS": "1", 215ecd94f1bSKan Liang "Counter": "0,1,2,3", 216ecd94f1bSKan Liang "EventName": "HLE_RETIRED.ABORTED", 217ecd94f1bSKan Liang "PublicDescription": "Number of times HLE abort was triggered.", 218ecd94f1bSKan Liang "SampleAfterValue": "2000003", 219ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3,4,5,6,7" 220ecd94f1bSKan Liang }, 221ecd94f1bSKan Liang { 222ecd94f1bSKan Liang "EventCode": "0xC8", 223ecd94f1bSKan Liang "UMask": "0x8", 224ecd94f1bSKan Liang "BriefDescription": "Number of times an HLE execution aborted due to various memory events (e.g., read/write capacity and conflicts).", 225ecd94f1bSKan Liang "Counter": "0,1,2,3", 226ecd94f1bSKan Liang "EventName": "HLE_RETIRED.ABORTED_MEM", 227ecd94f1bSKan Liang "SampleAfterValue": "2000003", 228ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3,4,5,6,7" 229ecd94f1bSKan Liang }, 230ecd94f1bSKan Liang { 231ecd94f1bSKan Liang "EventCode": "0xC8", 232ecd94f1bSKan Liang "UMask": "0x10", 233ecd94f1bSKan Liang "BriefDescription": "Number of times an HLE execution aborted due to hardware timer expiration.", 234ecd94f1bSKan Liang "Counter": "0,1,2,3", 235ecd94f1bSKan Liang "EventName": "HLE_RETIRED.ABORTED_TIMER", 236ecd94f1bSKan Liang "SampleAfterValue": "2000003", 237ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3,4,5,6,7" 238ecd94f1bSKan Liang }, 239ecd94f1bSKan Liang { 240ecd94f1bSKan Liang "EventCode": "0xC8", 241ecd94f1bSKan Liang "UMask": "0x20", 242ecd94f1bSKan Liang "BriefDescription": "Number of times an HLE execution aborted due to HLE-unfriendly instructions and certain unfriendly events (such as AD assists etc.).", 243ecd94f1bSKan Liang "Counter": "0,1,2,3", 244ecd94f1bSKan Liang "EventName": "HLE_RETIRED.ABORTED_UNFRIENDLY", 245ecd94f1bSKan Liang "SampleAfterValue": "2000003", 246ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3,4,5,6,7" 247ecd94f1bSKan Liang }, 248ecd94f1bSKan Liang { 249ecd94f1bSKan Liang "EventCode": "0xC8", 250ecd94f1bSKan Liang "UMask": "0x40", 251ecd94f1bSKan Liang "BriefDescription": "Number of times an HLE execution aborted due to incompatible memory type", 252ecd94f1bSKan Liang "Counter": "0,1,2,3", 253ecd94f1bSKan Liang "EventName": "HLE_RETIRED.ABORTED_MEMTYPE", 254ecd94f1bSKan Liang "PublicDescription": "Number of times an HLE execution aborted due to incompatible memory type.", 255ecd94f1bSKan Liang "SampleAfterValue": "2000003", 256ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3,4,5,6,7" 257ecd94f1bSKan Liang }, 258ecd94f1bSKan Liang { 259ecd94f1bSKan Liang "EventCode": "0xC8", 260ecd94f1bSKan Liang "UMask": "0x80", 261ecd94f1bSKan Liang "BriefDescription": "Number of times an HLE execution aborted due to unfriendly events (such as interrupts).", 262ecd94f1bSKan Liang "Counter": "0,1,2,3", 263ecd94f1bSKan Liang "EventName": "HLE_RETIRED.ABORTED_EVENTS", 264ecd94f1bSKan Liang "SampleAfterValue": "2000003", 265ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3,4,5,6,7" 266ecd94f1bSKan Liang }, 267ecd94f1bSKan Liang { 268ecd94f1bSKan Liang "EventCode": "0xC9", 269ecd94f1bSKan Liang "UMask": "0x1", 270ecd94f1bSKan Liang "BriefDescription": "Number of times an RTM execution started.", 271ecd94f1bSKan Liang "Counter": "0,1,2,3", 272ecd94f1bSKan Liang "EventName": "RTM_RETIRED.START", 273ecd94f1bSKan Liang "PublicDescription": "Number of times we entered an RTM region. Does not count nested transactions.", 274ecd94f1bSKan Liang "SampleAfterValue": "2000003", 275ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3,4,5,6,7" 276ecd94f1bSKan Liang }, 277ecd94f1bSKan Liang { 278ecd94f1bSKan Liang "EventCode": "0xC9", 279ecd94f1bSKan Liang "UMask": "0x2", 280ecd94f1bSKan Liang "BriefDescription": "Number of times an RTM execution successfully committed", 281ecd94f1bSKan Liang "Counter": "0,1,2,3", 282ecd94f1bSKan Liang "EventName": "RTM_RETIRED.COMMIT", 283ecd94f1bSKan Liang "PublicDescription": "Number of times RTM commit succeeded.", 284ecd94f1bSKan Liang "SampleAfterValue": "2000003", 285ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3,4,5,6,7" 286ecd94f1bSKan Liang }, 287ecd94f1bSKan Liang { 288ecd94f1bSKan Liang "EventCode": "0xC9", 289ecd94f1bSKan Liang "UMask": "0x4", 290ecd94f1bSKan Liang "BriefDescription": "Number of times an RTM execution aborted due to any reasons (multiple categories may count as one). ", 291ecd94f1bSKan Liang "PEBS": "1", 292ecd94f1bSKan Liang "Counter": "0,1,2,3", 293ecd94f1bSKan Liang "EventName": "RTM_RETIRED.ABORTED", 294ecd94f1bSKan Liang "PublicDescription": "Number of times RTM abort was triggered.", 295ecd94f1bSKan Liang "SampleAfterValue": "2000003", 296ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3,4,5,6,7" 297ecd94f1bSKan Liang }, 298ecd94f1bSKan Liang { 299ecd94f1bSKan Liang "EventCode": "0xC9", 300ecd94f1bSKan Liang "UMask": "0x8", 301ecd94f1bSKan Liang "BriefDescription": "Number of times an RTM execution aborted due to various memory events (e.g. read/write capacity and conflicts)", 302ecd94f1bSKan Liang "Counter": "0,1,2,3", 303ecd94f1bSKan Liang "EventName": "RTM_RETIRED.ABORTED_MEM", 304ecd94f1bSKan Liang "PublicDescription": "Number of times an RTM execution aborted due to various memory events (e.g. read/write capacity and conflicts).", 305ecd94f1bSKan Liang "SampleAfterValue": "2000003", 306ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3,4,5,6,7" 307ecd94f1bSKan Liang }, 308ecd94f1bSKan Liang { 309ecd94f1bSKan Liang "EventCode": "0xC9", 310ecd94f1bSKan Liang "UMask": "0x10", 311ecd94f1bSKan Liang "BriefDescription": "Number of times an RTM execution aborted due to uncommon conditions.", 312ecd94f1bSKan Liang "Counter": "0,1,2,3", 313ecd94f1bSKan Liang "EventName": "RTM_RETIRED.ABORTED_TIMER", 314ecd94f1bSKan Liang "SampleAfterValue": "2000003", 315ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3,4,5,6,7" 316ecd94f1bSKan Liang }, 317ecd94f1bSKan Liang { 318ecd94f1bSKan Liang "EventCode": "0xC9", 319ecd94f1bSKan Liang "UMask": "0x20", 320ecd94f1bSKan Liang "BriefDescription": "Number of times an RTM execution aborted due to HLE-unfriendly instructions", 321ecd94f1bSKan Liang "Counter": "0,1,2,3", 322ecd94f1bSKan Liang "EventName": "RTM_RETIRED.ABORTED_UNFRIENDLY", 323ecd94f1bSKan Liang "PublicDescription": "Number of times an RTM execution aborted due to HLE-unfriendly instructions.", 324ecd94f1bSKan Liang "SampleAfterValue": "2000003", 325ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3,4,5,6,7" 326ecd94f1bSKan Liang }, 327ecd94f1bSKan Liang { 328ecd94f1bSKan Liang "EventCode": "0xC9", 329ecd94f1bSKan Liang "UMask": "0x40", 330ecd94f1bSKan Liang "BriefDescription": "Number of times an RTM execution aborted due to incompatible memory type", 331ecd94f1bSKan Liang "Counter": "0,1,2,3", 332ecd94f1bSKan Liang "EventName": "RTM_RETIRED.ABORTED_MEMTYPE", 333ecd94f1bSKan Liang "PublicDescription": "Number of times an RTM execution aborted due to incompatible memory type.", 334ecd94f1bSKan Liang "SampleAfterValue": "2000003", 335ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3,4,5,6,7" 336ecd94f1bSKan Liang }, 337ecd94f1bSKan Liang { 338ecd94f1bSKan Liang "EventCode": "0xC9", 339ecd94f1bSKan Liang "UMask": "0x80", 340ecd94f1bSKan Liang "BriefDescription": "Number of times an RTM execution aborted due to none of the previous 4 categories (e.g. interrupt)", 341ecd94f1bSKan Liang "Counter": "0,1,2,3", 342ecd94f1bSKan Liang "EventName": "RTM_RETIRED.ABORTED_EVENTS", 343ecd94f1bSKan Liang "PublicDescription": "Number of times an RTM execution aborted due to none of the previous 4 categories (e.g. interrupt).", 344ecd94f1bSKan Liang "SampleAfterValue": "2000003", 345ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3,4,5,6,7" 346ecd94f1bSKan Liang }, 347ecd94f1bSKan Liang { 348ecd94f1bSKan Liang "EventCode": "0xCD", 349ecd94f1bSKan Liang "UMask": "0x1", 350ecd94f1bSKan Liang "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 512 cycles.", 351ecd94f1bSKan Liang "PEBS": "2", 352ecd94f1bSKan Liang "MSRValue": "0x200", 353ecd94f1bSKan Liang "Counter": "0,1,2,3", 354ecd94f1bSKan Liang "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_512", 355ecd94f1bSKan Liang "MSRIndex": "0x3F6", 356ecd94f1bSKan Liang "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 512 cycles. Reported latency may be longer than just the memory latency.", 357ecd94f1bSKan Liang "TakenAlone": "1", 358ecd94f1bSKan Liang "SampleAfterValue": "101", 359ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 360ecd94f1bSKan Liang }, 361ecd94f1bSKan Liang { 362ecd94f1bSKan Liang "EventCode": "0xCD", 363ecd94f1bSKan Liang "UMask": "0x1", 364ecd94f1bSKan Liang "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 256 cycles.", 365ecd94f1bSKan Liang "PEBS": "2", 366ecd94f1bSKan Liang "MSRValue": "0x100", 367ecd94f1bSKan Liang "Counter": "0,1,2,3", 368ecd94f1bSKan Liang "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_256", 369ecd94f1bSKan Liang "MSRIndex": "0x3F6", 370ecd94f1bSKan Liang "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 256 cycles. Reported latency may be longer than just the memory latency.", 371ecd94f1bSKan Liang "TakenAlone": "1", 372ecd94f1bSKan Liang "SampleAfterValue": "503", 373ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 374ecd94f1bSKan Liang }, 375ecd94f1bSKan Liang { 376ecd94f1bSKan Liang "EventCode": "0xCD", 377ecd94f1bSKan Liang "UMask": "0x1", 378ecd94f1bSKan Liang "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 128 cycles.", 379ecd94f1bSKan Liang "PEBS": "2", 380ecd94f1bSKan Liang "MSRValue": "0x80", 381ecd94f1bSKan Liang "Counter": "0,1,2,3", 382ecd94f1bSKan Liang "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_128", 383ecd94f1bSKan Liang "MSRIndex": "0x3F6", 384ecd94f1bSKan Liang "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 128 cycles. Reported latency may be longer than just the memory latency.", 385ecd94f1bSKan Liang "TakenAlone": "1", 386ecd94f1bSKan Liang "SampleAfterValue": "1009", 387ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 388ecd94f1bSKan Liang }, 389ecd94f1bSKan Liang { 390ecd94f1bSKan Liang "EventCode": "0xCD", 391ecd94f1bSKan Liang "UMask": "0x1", 392ecd94f1bSKan Liang "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 64 cycles.", 393ecd94f1bSKan Liang "PEBS": "2", 394ecd94f1bSKan Liang "MSRValue": "0x40", 395ecd94f1bSKan Liang "Counter": "0,1,2,3", 396ecd94f1bSKan Liang "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_64", 397ecd94f1bSKan Liang "MSRIndex": "0x3F6", 398ecd94f1bSKan Liang "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 64 cycles. Reported latency may be longer than just the memory latency.", 399ecd94f1bSKan Liang "TakenAlone": "1", 400ecd94f1bSKan Liang "SampleAfterValue": "2003", 401ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 402ecd94f1bSKan Liang }, 403ecd94f1bSKan Liang { 404ecd94f1bSKan Liang "EventCode": "0xCD", 405ecd94f1bSKan Liang "UMask": "0x1", 406ecd94f1bSKan Liang "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 32 cycles.", 407ecd94f1bSKan Liang "PEBS": "2", 408ecd94f1bSKan Liang "MSRValue": "0x20", 409ecd94f1bSKan Liang "Counter": "0,1,2,3", 410ecd94f1bSKan Liang "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_32", 411ecd94f1bSKan Liang "MSRIndex": "0x3F6", 412ecd94f1bSKan Liang "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 32 cycles. Reported latency may be longer than just the memory latency.", 413ecd94f1bSKan Liang "TakenAlone": "1", 414ecd94f1bSKan Liang "SampleAfterValue": "100007", 415ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 416ecd94f1bSKan Liang }, 417ecd94f1bSKan Liang { 418ecd94f1bSKan Liang "EventCode": "0xCD", 419ecd94f1bSKan Liang "UMask": "0x1", 420ecd94f1bSKan Liang "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 16 cycles.", 421ecd94f1bSKan Liang "PEBS": "2", 422ecd94f1bSKan Liang "MSRValue": "0x10", 423ecd94f1bSKan Liang "Counter": "0,1,2,3", 424ecd94f1bSKan Liang "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_16", 425ecd94f1bSKan Liang "MSRIndex": "0x3F6", 426ecd94f1bSKan Liang "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 16 cycles. Reported latency may be longer than just the memory latency.", 427ecd94f1bSKan Liang "TakenAlone": "1", 428ecd94f1bSKan Liang "SampleAfterValue": "20011", 429ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 430ecd94f1bSKan Liang }, 431ecd94f1bSKan Liang { 432ecd94f1bSKan Liang "EventCode": "0xCD", 433ecd94f1bSKan Liang "UMask": "0x1", 434ecd94f1bSKan Liang "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 8 cycles.", 435ecd94f1bSKan Liang "PEBS": "2", 436ecd94f1bSKan Liang "MSRValue": "0x8", 437ecd94f1bSKan Liang "Counter": "0,1,2,3", 438ecd94f1bSKan Liang "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_8", 439ecd94f1bSKan Liang "MSRIndex": "0x3F6", 440ecd94f1bSKan Liang "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 8 cycles. Reported latency may be longer than just the memory latency.", 441ecd94f1bSKan Liang "TakenAlone": "1", 442ecd94f1bSKan Liang "SampleAfterValue": "50021", 443ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 444ecd94f1bSKan Liang }, 445ecd94f1bSKan Liang { 446ecd94f1bSKan Liang "EventCode": "0xCD", 447ecd94f1bSKan Liang "UMask": "0x1", 448ecd94f1bSKan Liang "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 4 cycles.", 449ecd94f1bSKan Liang "PEBS": "2", 450ecd94f1bSKan Liang "MSRValue": "0x4", 451ecd94f1bSKan Liang "Counter": "0,1,2,3", 452ecd94f1bSKan Liang "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_4", 453ecd94f1bSKan Liang "MSRIndex": "0x3F6", 454ecd94f1bSKan Liang "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 4 cycles. Reported latency may be longer than just the memory latency.", 455ecd94f1bSKan Liang "TakenAlone": "1", 456ecd94f1bSKan Liang "SampleAfterValue": "100003", 457ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 458ecd94f1bSKan Liang }, 459ecd94f1bSKan Liang { 460ecd94f1bSKan Liang "Offcore": "1", 461ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 462ecd94f1bSKan Liang "UMask": "0x1", 463ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NONE", 464ecd94f1bSKan Liang "Deprecated": "1", 465ecd94f1bSKan Liang "MSRValue": "0x0084000001", 466ecd94f1bSKan Liang "Counter": "0,1,2,3", 467ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=DEMAND_DATA_RD:response=L3_MISS_LOCAL_DRAM.SNOOP_NONE", 468ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 469ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 470ecd94f1bSKan Liang "SampleAfterValue": "100003", 471ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 472ecd94f1bSKan Liang }, 473ecd94f1bSKan Liang { 474ecd94f1bSKan Liang "Offcore": "1", 475ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 476ecd94f1bSKan Liang "UMask": "0x1", 477ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED", 478ecd94f1bSKan Liang "Deprecated": "1", 479ecd94f1bSKan Liang "MSRValue": "0x0104000001", 480ecd94f1bSKan Liang "Counter": "0,1,2,3", 481ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=DEMAND_DATA_RD:response=L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED", 482ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 483ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 484ecd94f1bSKan Liang "SampleAfterValue": "100003", 485ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 486ecd94f1bSKan Liang }, 487ecd94f1bSKan Liang { 488ecd94f1bSKan Liang "Offcore": "1", 489ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 490ecd94f1bSKan Liang "UMask": "0x1", 491ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS", 492ecd94f1bSKan Liang "Deprecated": "1", 493ecd94f1bSKan Liang "MSRValue": "0x0204000001", 494ecd94f1bSKan Liang "Counter": "0,1,2,3", 495ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=DEMAND_DATA_RD:response=L3_MISS_LOCAL_DRAM.SNOOP_MISS", 496ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 497ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 498ecd94f1bSKan Liang "SampleAfterValue": "100003", 499ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 500ecd94f1bSKan Liang }, 501ecd94f1bSKan Liang { 502ecd94f1bSKan Liang "Offcore": "1", 503ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 504ecd94f1bSKan Liang "UMask": "0x1", 505ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD", 506ecd94f1bSKan Liang "Deprecated": "1", 507ecd94f1bSKan Liang "MSRValue": "0x0404000001", 508ecd94f1bSKan Liang "Counter": "0,1,2,3", 509ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=DEMAND_DATA_RD:response=L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD", 510ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 511ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 512ecd94f1bSKan Liang "SampleAfterValue": "100003", 513ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 514ecd94f1bSKan Liang }, 515ecd94f1bSKan Liang { 516ecd94f1bSKan Liang "Offcore": "1", 517ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 518ecd94f1bSKan Liang "UMask": "0x1", 519ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD", 520ecd94f1bSKan Liang "Deprecated": "1", 521ecd94f1bSKan Liang "MSRValue": "0x0804000001", 522ecd94f1bSKan Liang "Counter": "0,1,2,3", 523ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=DEMAND_DATA_RD:response=L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD", 524ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 525ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 526ecd94f1bSKan Liang "SampleAfterValue": "100003", 527ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 528ecd94f1bSKan Liang }, 529ecd94f1bSKan Liang { 530ecd94f1bSKan Liang "Offcore": "1", 531ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 532ecd94f1bSKan Liang "UMask": "0x1", 533ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE", 534ecd94f1bSKan Liang "Deprecated": "1", 535ecd94f1bSKan Liang "MSRValue": "0x1004000001", 536ecd94f1bSKan Liang "Counter": "0,1,2,3", 537ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=DEMAND_DATA_RD:response=L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE", 538ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 539ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 540ecd94f1bSKan Liang "SampleAfterValue": "100003", 541ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 542ecd94f1bSKan Liang }, 543ecd94f1bSKan Liang { 544ecd94f1bSKan Liang "Offcore": "1", 545ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 546ecd94f1bSKan Liang "UMask": "0x1", 547ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP", 548ecd94f1bSKan Liang "Deprecated": "1", 549ecd94f1bSKan Liang "MSRValue": "0x3F84000001", 550ecd94f1bSKan Liang "Counter": "0,1,2,3", 551ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=DEMAND_DATA_RD:response=L3_MISS_LOCAL_DRAM.ANY_SNOOP", 552ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 553ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 554ecd94f1bSKan Liang "SampleAfterValue": "100003", 555ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 556ecd94f1bSKan Liang }, 557ecd94f1bSKan Liang { 558ecd94f1bSKan Liang "Offcore": "1", 559ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 560ecd94f1bSKan Liang "UMask": "0x1", 561ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE", 562ecd94f1bSKan Liang "Deprecated": "1", 563ecd94f1bSKan Liang "MSRValue": "0x0090000001", 564ecd94f1bSKan Liang "Counter": "0,1,2,3", 565ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=DEMAND_DATA_RD:response=L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE", 566ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 567ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 568ecd94f1bSKan Liang "SampleAfterValue": "100003", 569ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 570ecd94f1bSKan Liang }, 571ecd94f1bSKan Liang { 572ecd94f1bSKan Liang "Offcore": "1", 573ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 574ecd94f1bSKan Liang "UMask": "0x1", 575ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED", 576ecd94f1bSKan Liang "Deprecated": "1", 577ecd94f1bSKan Liang "MSRValue": "0x0110000001", 578ecd94f1bSKan Liang "Counter": "0,1,2,3", 579ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=DEMAND_DATA_RD:response=L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED", 580ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 581ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 582ecd94f1bSKan Liang "SampleAfterValue": "100003", 583ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 584ecd94f1bSKan Liang }, 585ecd94f1bSKan Liang { 586ecd94f1bSKan Liang "Offcore": "1", 587ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 588ecd94f1bSKan Liang "UMask": "0x1", 589ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS", 590ecd94f1bSKan Liang "Deprecated": "1", 591ecd94f1bSKan Liang "MSRValue": "0x0210000001", 592ecd94f1bSKan Liang "Counter": "0,1,2,3", 593ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=DEMAND_DATA_RD:response=L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS", 594ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 595ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 596ecd94f1bSKan Liang "SampleAfterValue": "100003", 597ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 598ecd94f1bSKan Liang }, 599ecd94f1bSKan Liang { 600ecd94f1bSKan Liang "Offcore": "1", 601ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 602ecd94f1bSKan Liang "UMask": "0x1", 603ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD", 604ecd94f1bSKan Liang "Deprecated": "1", 605ecd94f1bSKan Liang "MSRValue": "0x0410000001", 606ecd94f1bSKan Liang "Counter": "0,1,2,3", 607ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=DEMAND_DATA_RD:response=L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD", 608ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 609ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 610ecd94f1bSKan Liang "SampleAfterValue": "100003", 611ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 612ecd94f1bSKan Liang }, 613ecd94f1bSKan Liang { 614ecd94f1bSKan Liang "Offcore": "1", 615ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 616ecd94f1bSKan Liang "UMask": "0x1", 617ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD", 618ecd94f1bSKan Liang "Deprecated": "1", 619ecd94f1bSKan Liang "MSRValue": "0x0810000001", 620ecd94f1bSKan Liang "Counter": "0,1,2,3", 621ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=DEMAND_DATA_RD:response=L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD", 622ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 623ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 624ecd94f1bSKan Liang "SampleAfterValue": "100003", 625ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 626ecd94f1bSKan Liang }, 627ecd94f1bSKan Liang { 628ecd94f1bSKan Liang "Offcore": "1", 629ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 630ecd94f1bSKan Liang "UMask": "0x1", 631ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE", 632ecd94f1bSKan Liang "Deprecated": "1", 633ecd94f1bSKan Liang "MSRValue": "0x1010000001", 634ecd94f1bSKan Liang "Counter": "0,1,2,3", 635ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=DEMAND_DATA_RD:response=L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE", 636ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 637ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 638ecd94f1bSKan Liang "SampleAfterValue": "100003", 639ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 640ecd94f1bSKan Liang }, 641ecd94f1bSKan Liang { 642ecd94f1bSKan Liang "Offcore": "1", 643ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 644ecd94f1bSKan Liang "UMask": "0x1", 645ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP", 646ecd94f1bSKan Liang "Deprecated": "1", 647ecd94f1bSKan Liang "MSRValue": "0x3F90000001", 648ecd94f1bSKan Liang "Counter": "0,1,2,3", 649ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=DEMAND_DATA_RD:response=L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP", 650ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 651ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 652ecd94f1bSKan Liang "SampleAfterValue": "100003", 653ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 654ecd94f1bSKan Liang }, 655ecd94f1bSKan Liang { 656ecd94f1bSKan Liang "Offcore": "1", 657ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 658ecd94f1bSKan Liang "UMask": "0x1", 659ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS.SNOOP_NONE", 660ecd94f1bSKan Liang "Deprecated": "1", 661ecd94f1bSKan Liang "MSRValue": "0x00BC000001", 662ecd94f1bSKan Liang "Counter": "0,1,2,3", 663ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=DEMAND_DATA_RD:response=L3_MISS.SNOOP_NONE", 664ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 665ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 666ecd94f1bSKan Liang "SampleAfterValue": "100003", 667ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 668ecd94f1bSKan Liang }, 669ecd94f1bSKan Liang { 670ecd94f1bSKan Liang "Offcore": "1", 671ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 672ecd94f1bSKan Liang "UMask": "0x1", 673ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS.NO_SNOOP_NEEDED", 674ecd94f1bSKan Liang "Deprecated": "1", 675ecd94f1bSKan Liang "MSRValue": "0x013C000001", 676ecd94f1bSKan Liang "Counter": "0,1,2,3", 677ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=DEMAND_DATA_RD:response=L3_MISS.NO_SNOOP_NEEDED", 678ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 679ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 680ecd94f1bSKan Liang "SampleAfterValue": "100003", 681ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 682ecd94f1bSKan Liang }, 683ecd94f1bSKan Liang { 684ecd94f1bSKan Liang "Offcore": "1", 685ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 686ecd94f1bSKan Liang "UMask": "0x1", 687ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS.SNOOP_MISS", 688ecd94f1bSKan Liang "Deprecated": "1", 689ecd94f1bSKan Liang "MSRValue": "0x023C000001", 690ecd94f1bSKan Liang "Counter": "0,1,2,3", 691ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=DEMAND_DATA_RD:response=L3_MISS.SNOOP_MISS", 692ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 693ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 694ecd94f1bSKan Liang "SampleAfterValue": "100003", 695ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 696ecd94f1bSKan Liang }, 697ecd94f1bSKan Liang { 698ecd94f1bSKan Liang "Offcore": "1", 699ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 700ecd94f1bSKan Liang "UMask": "0x1", 701ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS.HIT_OTHER_CORE_NO_FWD", 702ecd94f1bSKan Liang "Deprecated": "1", 703ecd94f1bSKan Liang "MSRValue": "0x043C000001", 704ecd94f1bSKan Liang "Counter": "0,1,2,3", 705ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=DEMAND_DATA_RD:response=L3_MISS.HIT_OTHER_CORE_NO_FWD", 706ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 707ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 708ecd94f1bSKan Liang "SampleAfterValue": "100003", 709ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 710ecd94f1bSKan Liang }, 711ecd94f1bSKan Liang { 712ecd94f1bSKan Liang "Offcore": "1", 713ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 714ecd94f1bSKan Liang "UMask": "0x1", 715ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS.HIT_OTHER_CORE_FWD", 716ecd94f1bSKan Liang "Deprecated": "1", 717ecd94f1bSKan Liang "MSRValue": "0x083C000001", 718ecd94f1bSKan Liang "Counter": "0,1,2,3", 719ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=DEMAND_DATA_RD:response=L3_MISS.HIT_OTHER_CORE_FWD", 720ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 721ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 722ecd94f1bSKan Liang "SampleAfterValue": "100003", 723ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 724ecd94f1bSKan Liang }, 725ecd94f1bSKan Liang { 726ecd94f1bSKan Liang "Offcore": "1", 727ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 728ecd94f1bSKan Liang "UMask": "0x1", 729ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS.HITM_OTHER_CORE", 730ecd94f1bSKan Liang "Deprecated": "1", 731ecd94f1bSKan Liang "MSRValue": "0x103C000001", 732ecd94f1bSKan Liang "Counter": "0,1,2,3", 733ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=DEMAND_DATA_RD:response=L3_MISS.HITM_OTHER_CORE", 734ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 735ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 736ecd94f1bSKan Liang "SampleAfterValue": "100003", 737ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 738ecd94f1bSKan Liang }, 739ecd94f1bSKan Liang { 740ecd94f1bSKan Liang "Offcore": "1", 741ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 742ecd94f1bSKan Liang "UMask": "0x1", 743ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS.ANY_SNOOP", 744ecd94f1bSKan Liang "Deprecated": "1", 745ecd94f1bSKan Liang "MSRValue": "0x3FBC000001", 746ecd94f1bSKan Liang "Counter": "0,1,2,3", 747ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=DEMAND_DATA_RD:response=L3_MISS.ANY_SNOOP", 748ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 749ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 750ecd94f1bSKan Liang "SampleAfterValue": "100003", 751ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 752ecd94f1bSKan Liang }, 753ecd94f1bSKan Liang { 754ecd94f1bSKan Liang "Offcore": "1", 755ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 756ecd94f1bSKan Liang "UMask": "0x1", 757ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NONE", 758ecd94f1bSKan Liang "Deprecated": "1", 759ecd94f1bSKan Liang "MSRValue": "0x0084000002", 760ecd94f1bSKan Liang "Counter": "0,1,2,3", 761ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=DEMAND_RFO:response=L3_MISS_LOCAL_DRAM.SNOOP_NONE", 762ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 763ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 764ecd94f1bSKan Liang "SampleAfterValue": "100003", 765ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 766ecd94f1bSKan Liang }, 767ecd94f1bSKan Liang { 768ecd94f1bSKan Liang "Offcore": "1", 769ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 770ecd94f1bSKan Liang "UMask": "0x1", 771ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED", 772ecd94f1bSKan Liang "Deprecated": "1", 773ecd94f1bSKan Liang "MSRValue": "0x0104000002", 774ecd94f1bSKan Liang "Counter": "0,1,2,3", 775ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=DEMAND_RFO:response=L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED", 776ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 777ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 778ecd94f1bSKan Liang "SampleAfterValue": "100003", 779ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 780ecd94f1bSKan Liang }, 781ecd94f1bSKan Liang { 782ecd94f1bSKan Liang "Offcore": "1", 783ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 784ecd94f1bSKan Liang "UMask": "0x1", 785ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS", 786ecd94f1bSKan Liang "Deprecated": "1", 787ecd94f1bSKan Liang "MSRValue": "0x0204000002", 788ecd94f1bSKan Liang "Counter": "0,1,2,3", 789ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=DEMAND_RFO:response=L3_MISS_LOCAL_DRAM.SNOOP_MISS", 790ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 791ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 792ecd94f1bSKan Liang "SampleAfterValue": "100003", 793ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 794ecd94f1bSKan Liang }, 795ecd94f1bSKan Liang { 796ecd94f1bSKan Liang "Offcore": "1", 797ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 798ecd94f1bSKan Liang "UMask": "0x1", 799ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD", 800ecd94f1bSKan Liang "Deprecated": "1", 801ecd94f1bSKan Liang "MSRValue": "0x0404000002", 802ecd94f1bSKan Liang "Counter": "0,1,2,3", 803ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=DEMAND_RFO:response=L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD", 804ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 805ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 806ecd94f1bSKan Liang "SampleAfterValue": "100003", 807ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 808ecd94f1bSKan Liang }, 809ecd94f1bSKan Liang { 810ecd94f1bSKan Liang "Offcore": "1", 811ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 812ecd94f1bSKan Liang "UMask": "0x1", 813ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD", 814ecd94f1bSKan Liang "Deprecated": "1", 815ecd94f1bSKan Liang "MSRValue": "0x0804000002", 816ecd94f1bSKan Liang "Counter": "0,1,2,3", 817ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=DEMAND_RFO:response=L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD", 818ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 819ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 820ecd94f1bSKan Liang "SampleAfterValue": "100003", 821ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 822ecd94f1bSKan Liang }, 823ecd94f1bSKan Liang { 824ecd94f1bSKan Liang "Offcore": "1", 825ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 826ecd94f1bSKan Liang "UMask": "0x1", 827ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE", 828ecd94f1bSKan Liang "Deprecated": "1", 829ecd94f1bSKan Liang "MSRValue": "0x1004000002", 830ecd94f1bSKan Liang "Counter": "0,1,2,3", 831ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=DEMAND_RFO:response=L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE", 832ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 833ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 834ecd94f1bSKan Liang "SampleAfterValue": "100003", 835ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 836ecd94f1bSKan Liang }, 837ecd94f1bSKan Liang { 838ecd94f1bSKan Liang "Offcore": "1", 839ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 840ecd94f1bSKan Liang "UMask": "0x1", 841ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS_LOCAL_DRAM.ANY_SNOOP", 842ecd94f1bSKan Liang "Deprecated": "1", 843ecd94f1bSKan Liang "MSRValue": "0x3F84000002", 844ecd94f1bSKan Liang "Counter": "0,1,2,3", 845ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=DEMAND_RFO:response=L3_MISS_LOCAL_DRAM.ANY_SNOOP", 846ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 847ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 848ecd94f1bSKan Liang "SampleAfterValue": "100003", 849ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 850ecd94f1bSKan Liang }, 851ecd94f1bSKan Liang { 852ecd94f1bSKan Liang "Offcore": "1", 853ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 854ecd94f1bSKan Liang "UMask": "0x1", 855ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE", 856ecd94f1bSKan Liang "Deprecated": "1", 857ecd94f1bSKan Liang "MSRValue": "0x0090000002", 858ecd94f1bSKan Liang "Counter": "0,1,2,3", 859ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=DEMAND_RFO:response=L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE", 860ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 861ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 862ecd94f1bSKan Liang "SampleAfterValue": "100003", 863ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 864ecd94f1bSKan Liang }, 865ecd94f1bSKan Liang { 866ecd94f1bSKan Liang "Offcore": "1", 867ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 868ecd94f1bSKan Liang "UMask": "0x1", 869ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED", 870ecd94f1bSKan Liang "Deprecated": "1", 871ecd94f1bSKan Liang "MSRValue": "0x0110000002", 872ecd94f1bSKan Liang "Counter": "0,1,2,3", 873ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=DEMAND_RFO:response=L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED", 874ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 875ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 876ecd94f1bSKan Liang "SampleAfterValue": "100003", 877ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 878ecd94f1bSKan Liang }, 879ecd94f1bSKan Liang { 880ecd94f1bSKan Liang "Offcore": "1", 881ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 882ecd94f1bSKan Liang "UMask": "0x1", 883ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS", 884ecd94f1bSKan Liang "Deprecated": "1", 885ecd94f1bSKan Liang "MSRValue": "0x0210000002", 886ecd94f1bSKan Liang "Counter": "0,1,2,3", 887ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=DEMAND_RFO:response=L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS", 888ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 889ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 890ecd94f1bSKan Liang "SampleAfterValue": "100003", 891ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 892ecd94f1bSKan Liang }, 893ecd94f1bSKan Liang { 894ecd94f1bSKan Liang "Offcore": "1", 895ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 896ecd94f1bSKan Liang "UMask": "0x1", 897ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD", 898ecd94f1bSKan Liang "Deprecated": "1", 899ecd94f1bSKan Liang "MSRValue": "0x0410000002", 900ecd94f1bSKan Liang "Counter": "0,1,2,3", 901ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=DEMAND_RFO:response=L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD", 902ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 903ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 904ecd94f1bSKan Liang "SampleAfterValue": "100003", 905ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 906ecd94f1bSKan Liang }, 907ecd94f1bSKan Liang { 908ecd94f1bSKan Liang "Offcore": "1", 909ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 910ecd94f1bSKan Liang "UMask": "0x1", 911ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD", 912ecd94f1bSKan Liang "Deprecated": "1", 913ecd94f1bSKan Liang "MSRValue": "0x0810000002", 914ecd94f1bSKan Liang "Counter": "0,1,2,3", 915ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=DEMAND_RFO:response=L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD", 916ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 917ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 918ecd94f1bSKan Liang "SampleAfterValue": "100003", 919ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 920ecd94f1bSKan Liang }, 921ecd94f1bSKan Liang { 922ecd94f1bSKan Liang "Offcore": "1", 923ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 924ecd94f1bSKan Liang "UMask": "0x1", 925ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE", 926ecd94f1bSKan Liang "Deprecated": "1", 927ecd94f1bSKan Liang "MSRValue": "0x1010000002", 928ecd94f1bSKan Liang "Counter": "0,1,2,3", 929ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=DEMAND_RFO:response=L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE", 930ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 931ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 932ecd94f1bSKan Liang "SampleAfterValue": "100003", 933ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 934ecd94f1bSKan Liang }, 935ecd94f1bSKan Liang { 936ecd94f1bSKan Liang "Offcore": "1", 937ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 938ecd94f1bSKan Liang "UMask": "0x1", 939ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP", 940ecd94f1bSKan Liang "Deprecated": "1", 941ecd94f1bSKan Liang "MSRValue": "0x3F90000002", 942ecd94f1bSKan Liang "Counter": "0,1,2,3", 943ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=DEMAND_RFO:response=L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP", 944ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 945ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 946ecd94f1bSKan Liang "SampleAfterValue": "100003", 947ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 948ecd94f1bSKan Liang }, 949ecd94f1bSKan Liang { 950ecd94f1bSKan Liang "Offcore": "1", 951ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 952ecd94f1bSKan Liang "UMask": "0x1", 953ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS.SNOOP_NONE", 954ecd94f1bSKan Liang "Deprecated": "1", 955ecd94f1bSKan Liang "MSRValue": "0x00BC000002", 956ecd94f1bSKan Liang "Counter": "0,1,2,3", 957ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=DEMAND_RFO:response=L3_MISS.SNOOP_NONE", 958ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 959ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 960ecd94f1bSKan Liang "SampleAfterValue": "100003", 961ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 962ecd94f1bSKan Liang }, 963ecd94f1bSKan Liang { 964ecd94f1bSKan Liang "Offcore": "1", 965ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 966ecd94f1bSKan Liang "UMask": "0x1", 967ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS.NO_SNOOP_NEEDED", 968ecd94f1bSKan Liang "Deprecated": "1", 969ecd94f1bSKan Liang "MSRValue": "0x013C000002", 970ecd94f1bSKan Liang "Counter": "0,1,2,3", 971ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=DEMAND_RFO:response=L3_MISS.NO_SNOOP_NEEDED", 972ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 973ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 974ecd94f1bSKan Liang "SampleAfterValue": "100003", 975ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 976ecd94f1bSKan Liang }, 977ecd94f1bSKan Liang { 978ecd94f1bSKan Liang "Offcore": "1", 979ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 980ecd94f1bSKan Liang "UMask": "0x1", 981ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS.SNOOP_MISS", 982ecd94f1bSKan Liang "Deprecated": "1", 983ecd94f1bSKan Liang "MSRValue": "0x023C000002", 984ecd94f1bSKan Liang "Counter": "0,1,2,3", 985ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=DEMAND_RFO:response=L3_MISS.SNOOP_MISS", 986ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 987ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 988ecd94f1bSKan Liang "SampleAfterValue": "100003", 989ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 990ecd94f1bSKan Liang }, 991ecd94f1bSKan Liang { 992ecd94f1bSKan Liang "Offcore": "1", 993ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 994ecd94f1bSKan Liang "UMask": "0x1", 995ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS.HIT_OTHER_CORE_NO_FWD", 996ecd94f1bSKan Liang "Deprecated": "1", 997ecd94f1bSKan Liang "MSRValue": "0x043C000002", 998ecd94f1bSKan Liang "Counter": "0,1,2,3", 999ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=DEMAND_RFO:response=L3_MISS.HIT_OTHER_CORE_NO_FWD", 1000ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 1001ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1002ecd94f1bSKan Liang "SampleAfterValue": "100003", 1003ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 1004ecd94f1bSKan Liang }, 1005ecd94f1bSKan Liang { 1006ecd94f1bSKan Liang "Offcore": "1", 1007ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 1008ecd94f1bSKan Liang "UMask": "0x1", 1009ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS.HIT_OTHER_CORE_FWD", 1010ecd94f1bSKan Liang "Deprecated": "1", 1011ecd94f1bSKan Liang "MSRValue": "0x083C000002", 1012ecd94f1bSKan Liang "Counter": "0,1,2,3", 1013ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=DEMAND_RFO:response=L3_MISS.HIT_OTHER_CORE_FWD", 1014ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 1015ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1016ecd94f1bSKan Liang "SampleAfterValue": "100003", 1017ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 1018ecd94f1bSKan Liang }, 1019ecd94f1bSKan Liang { 1020ecd94f1bSKan Liang "Offcore": "1", 1021ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 1022ecd94f1bSKan Liang "UMask": "0x1", 1023ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS.HITM_OTHER_CORE", 1024ecd94f1bSKan Liang "Deprecated": "1", 1025ecd94f1bSKan Liang "MSRValue": "0x103C000002", 1026ecd94f1bSKan Liang "Counter": "0,1,2,3", 1027ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=DEMAND_RFO:response=L3_MISS.HITM_OTHER_CORE", 1028ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 1029ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1030ecd94f1bSKan Liang "SampleAfterValue": "100003", 1031ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 1032ecd94f1bSKan Liang }, 1033ecd94f1bSKan Liang { 1034ecd94f1bSKan Liang "Offcore": "1", 1035ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 1036ecd94f1bSKan Liang "UMask": "0x1", 1037ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS.ANY_SNOOP", 1038ecd94f1bSKan Liang "Deprecated": "1", 1039ecd94f1bSKan Liang "MSRValue": "0x3FBC000002", 1040ecd94f1bSKan Liang "Counter": "0,1,2,3", 1041ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=DEMAND_RFO:response=L3_MISS.ANY_SNOOP", 1042ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 1043ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1044ecd94f1bSKan Liang "SampleAfterValue": "100003", 1045ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 1046ecd94f1bSKan Liang }, 1047ecd94f1bSKan Liang { 1048ecd94f1bSKan Liang "Offcore": "1", 1049ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 1050ecd94f1bSKan Liang "UMask": "0x1", 1051ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_NONE", 1052ecd94f1bSKan Liang "Deprecated": "1", 1053ecd94f1bSKan Liang "MSRValue": "0x0084000004", 1054ecd94f1bSKan Liang "Counter": "0,1,2,3", 1055ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=DEMAND_CODE_RD:response=L3_MISS_LOCAL_DRAM.SNOOP_NONE", 1056ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 1057ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1058ecd94f1bSKan Liang "SampleAfterValue": "100003", 1059ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 1060ecd94f1bSKan Liang }, 1061ecd94f1bSKan Liang { 1062ecd94f1bSKan Liang "Offcore": "1", 1063ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 1064ecd94f1bSKan Liang "UMask": "0x1", 1065ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED", 1066ecd94f1bSKan Liang "Deprecated": "1", 1067ecd94f1bSKan Liang "MSRValue": "0x0104000004", 1068ecd94f1bSKan Liang "Counter": "0,1,2,3", 1069ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=DEMAND_CODE_RD:response=L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED", 1070ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 1071ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1072ecd94f1bSKan Liang "SampleAfterValue": "100003", 1073ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 1074ecd94f1bSKan Liang }, 1075ecd94f1bSKan Liang { 1076ecd94f1bSKan Liang "Offcore": "1", 1077ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 1078ecd94f1bSKan Liang "UMask": "0x1", 1079ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS", 1080ecd94f1bSKan Liang "Deprecated": "1", 1081ecd94f1bSKan Liang "MSRValue": "0x0204000004", 1082ecd94f1bSKan Liang "Counter": "0,1,2,3", 1083ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=DEMAND_CODE_RD:response=L3_MISS_LOCAL_DRAM.SNOOP_MISS", 1084ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 1085ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1086ecd94f1bSKan Liang "SampleAfterValue": "100003", 1087ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 1088ecd94f1bSKan Liang }, 1089ecd94f1bSKan Liang { 1090ecd94f1bSKan Liang "Offcore": "1", 1091ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 1092ecd94f1bSKan Liang "UMask": "0x1", 1093ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD", 1094ecd94f1bSKan Liang "Deprecated": "1", 1095ecd94f1bSKan Liang "MSRValue": "0x0404000004", 1096ecd94f1bSKan Liang "Counter": "0,1,2,3", 1097ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=DEMAND_CODE_RD:response=L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD", 1098ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 1099ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1100ecd94f1bSKan Liang "SampleAfterValue": "100003", 1101ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 1102ecd94f1bSKan Liang }, 1103ecd94f1bSKan Liang { 1104ecd94f1bSKan Liang "Offcore": "1", 1105ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 1106ecd94f1bSKan Liang "UMask": "0x1", 1107ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD", 1108ecd94f1bSKan Liang "Deprecated": "1", 1109ecd94f1bSKan Liang "MSRValue": "0x0804000004", 1110ecd94f1bSKan Liang "Counter": "0,1,2,3", 1111ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=DEMAND_CODE_RD:response=L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD", 1112ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 1113ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1114ecd94f1bSKan Liang "SampleAfterValue": "100003", 1115ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 1116ecd94f1bSKan Liang }, 1117ecd94f1bSKan Liang { 1118ecd94f1bSKan Liang "Offcore": "1", 1119ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 1120ecd94f1bSKan Liang "UMask": "0x1", 1121ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE", 1122ecd94f1bSKan Liang "Deprecated": "1", 1123ecd94f1bSKan Liang "MSRValue": "0x1004000004", 1124ecd94f1bSKan Liang "Counter": "0,1,2,3", 1125ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=DEMAND_CODE_RD:response=L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE", 1126ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 1127ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1128ecd94f1bSKan Liang "SampleAfterValue": "100003", 1129ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 1130ecd94f1bSKan Liang }, 1131ecd94f1bSKan Liang { 1132ecd94f1bSKan Liang "Offcore": "1", 1133ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 1134ecd94f1bSKan Liang "UMask": "0x1", 1135ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP", 1136ecd94f1bSKan Liang "Deprecated": "1", 1137ecd94f1bSKan Liang "MSRValue": "0x3F84000004", 1138ecd94f1bSKan Liang "Counter": "0,1,2,3", 1139ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=DEMAND_CODE_RD:response=L3_MISS_LOCAL_DRAM.ANY_SNOOP", 1140ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 1141ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1142ecd94f1bSKan Liang "SampleAfterValue": "100003", 1143ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 1144ecd94f1bSKan Liang }, 1145ecd94f1bSKan Liang { 1146ecd94f1bSKan Liang "Offcore": "1", 1147ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 1148ecd94f1bSKan Liang "UMask": "0x1", 1149ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE", 1150ecd94f1bSKan Liang "Deprecated": "1", 1151ecd94f1bSKan Liang "MSRValue": "0x0090000004", 1152ecd94f1bSKan Liang "Counter": "0,1,2,3", 1153ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=DEMAND_CODE_RD:response=L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE", 1154ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 1155ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1156ecd94f1bSKan Liang "SampleAfterValue": "100003", 1157ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 1158ecd94f1bSKan Liang }, 1159ecd94f1bSKan Liang { 1160ecd94f1bSKan Liang "Offcore": "1", 1161ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 1162ecd94f1bSKan Liang "UMask": "0x1", 1163ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED", 1164ecd94f1bSKan Liang "Deprecated": "1", 1165ecd94f1bSKan Liang "MSRValue": "0x0110000004", 1166ecd94f1bSKan Liang "Counter": "0,1,2,3", 1167ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=DEMAND_CODE_RD:response=L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED", 1168ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 1169ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1170ecd94f1bSKan Liang "SampleAfterValue": "100003", 1171ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 1172ecd94f1bSKan Liang }, 1173ecd94f1bSKan Liang { 1174ecd94f1bSKan Liang "Offcore": "1", 1175ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 1176ecd94f1bSKan Liang "UMask": "0x1", 1177ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS", 1178ecd94f1bSKan Liang "Deprecated": "1", 1179ecd94f1bSKan Liang "MSRValue": "0x0210000004", 1180ecd94f1bSKan Liang "Counter": "0,1,2,3", 1181ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=DEMAND_CODE_RD:response=L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS", 1182ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 1183ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1184ecd94f1bSKan Liang "SampleAfterValue": "100003", 1185ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 1186ecd94f1bSKan Liang }, 1187ecd94f1bSKan Liang { 1188ecd94f1bSKan Liang "Offcore": "1", 1189ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 1190ecd94f1bSKan Liang "UMask": "0x1", 1191ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD", 1192ecd94f1bSKan Liang "Deprecated": "1", 1193ecd94f1bSKan Liang "MSRValue": "0x0410000004", 1194ecd94f1bSKan Liang "Counter": "0,1,2,3", 1195ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=DEMAND_CODE_RD:response=L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD", 1196ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 1197ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1198ecd94f1bSKan Liang "SampleAfterValue": "100003", 1199ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 1200ecd94f1bSKan Liang }, 1201ecd94f1bSKan Liang { 1202ecd94f1bSKan Liang "Offcore": "1", 1203ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 1204ecd94f1bSKan Liang "UMask": "0x1", 1205ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD", 1206ecd94f1bSKan Liang "Deprecated": "1", 1207ecd94f1bSKan Liang "MSRValue": "0x0810000004", 1208ecd94f1bSKan Liang "Counter": "0,1,2,3", 1209ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=DEMAND_CODE_RD:response=L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD", 1210ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 1211ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1212ecd94f1bSKan Liang "SampleAfterValue": "100003", 1213ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 1214ecd94f1bSKan Liang }, 1215ecd94f1bSKan Liang { 1216ecd94f1bSKan Liang "Offcore": "1", 1217ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 1218ecd94f1bSKan Liang "UMask": "0x1", 1219ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE", 1220ecd94f1bSKan Liang "Deprecated": "1", 1221ecd94f1bSKan Liang "MSRValue": "0x1010000004", 1222ecd94f1bSKan Liang "Counter": "0,1,2,3", 1223ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=DEMAND_CODE_RD:response=L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE", 1224ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 1225ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1226ecd94f1bSKan Liang "SampleAfterValue": "100003", 1227ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 1228ecd94f1bSKan Liang }, 1229ecd94f1bSKan Liang { 1230ecd94f1bSKan Liang "Offcore": "1", 1231ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 1232ecd94f1bSKan Liang "UMask": "0x1", 1233ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP", 1234ecd94f1bSKan Liang "Deprecated": "1", 1235ecd94f1bSKan Liang "MSRValue": "0x3F90000004", 1236ecd94f1bSKan Liang "Counter": "0,1,2,3", 1237ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=DEMAND_CODE_RD:response=L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP", 1238ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 1239ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1240ecd94f1bSKan Liang "SampleAfterValue": "100003", 1241ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 1242ecd94f1bSKan Liang }, 1243ecd94f1bSKan Liang { 1244ecd94f1bSKan Liang "Offcore": "1", 1245ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 1246ecd94f1bSKan Liang "UMask": "0x1", 1247ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS.SNOOP_NONE", 1248ecd94f1bSKan Liang "Deprecated": "1", 1249ecd94f1bSKan Liang "MSRValue": "0x00BC000004", 1250ecd94f1bSKan Liang "Counter": "0,1,2,3", 1251ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=DEMAND_CODE_RD:response=L3_MISS.SNOOP_NONE", 1252ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 1253ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1254ecd94f1bSKan Liang "SampleAfterValue": "100003", 1255ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 1256ecd94f1bSKan Liang }, 1257ecd94f1bSKan Liang { 1258ecd94f1bSKan Liang "Offcore": "1", 1259ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 1260ecd94f1bSKan Liang "UMask": "0x1", 1261ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS.NO_SNOOP_NEEDED", 1262ecd94f1bSKan Liang "Deprecated": "1", 1263ecd94f1bSKan Liang "MSRValue": "0x013C000004", 1264ecd94f1bSKan Liang "Counter": "0,1,2,3", 1265ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=DEMAND_CODE_RD:response=L3_MISS.NO_SNOOP_NEEDED", 1266ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 1267ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1268ecd94f1bSKan Liang "SampleAfterValue": "100003", 1269ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 1270ecd94f1bSKan Liang }, 1271ecd94f1bSKan Liang { 1272ecd94f1bSKan Liang "Offcore": "1", 1273ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 1274ecd94f1bSKan Liang "UMask": "0x1", 1275ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS.SNOOP_MISS", 1276ecd94f1bSKan Liang "Deprecated": "1", 1277ecd94f1bSKan Liang "MSRValue": "0x023C000004", 1278ecd94f1bSKan Liang "Counter": "0,1,2,3", 1279ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=DEMAND_CODE_RD:response=L3_MISS.SNOOP_MISS", 1280ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 1281ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1282ecd94f1bSKan Liang "SampleAfterValue": "100003", 1283ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 1284ecd94f1bSKan Liang }, 1285ecd94f1bSKan Liang { 1286ecd94f1bSKan Liang "Offcore": "1", 1287ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 1288ecd94f1bSKan Liang "UMask": "0x1", 1289ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS.HIT_OTHER_CORE_NO_FWD", 1290ecd94f1bSKan Liang "Deprecated": "1", 1291ecd94f1bSKan Liang "MSRValue": "0x043C000004", 1292ecd94f1bSKan Liang "Counter": "0,1,2,3", 1293ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=DEMAND_CODE_RD:response=L3_MISS.HIT_OTHER_CORE_NO_FWD", 1294ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 1295ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1296ecd94f1bSKan Liang "SampleAfterValue": "100003", 1297ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 1298ecd94f1bSKan Liang }, 1299ecd94f1bSKan Liang { 1300ecd94f1bSKan Liang "Offcore": "1", 1301ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 1302ecd94f1bSKan Liang "UMask": "0x1", 1303ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS.HIT_OTHER_CORE_FWD", 1304ecd94f1bSKan Liang "Deprecated": "1", 1305ecd94f1bSKan Liang "MSRValue": "0x083C000004", 1306ecd94f1bSKan Liang "Counter": "0,1,2,3", 1307ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=DEMAND_CODE_RD:response=L3_MISS.HIT_OTHER_CORE_FWD", 1308ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 1309ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1310ecd94f1bSKan Liang "SampleAfterValue": "100003", 1311ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 1312ecd94f1bSKan Liang }, 1313ecd94f1bSKan Liang { 1314ecd94f1bSKan Liang "Offcore": "1", 1315ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 1316ecd94f1bSKan Liang "UMask": "0x1", 1317ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS.HITM_OTHER_CORE", 1318ecd94f1bSKan Liang "Deprecated": "1", 1319ecd94f1bSKan Liang "MSRValue": "0x103C000004", 1320ecd94f1bSKan Liang "Counter": "0,1,2,3", 1321ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=DEMAND_CODE_RD:response=L3_MISS.HITM_OTHER_CORE", 1322ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 1323ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1324ecd94f1bSKan Liang "SampleAfterValue": "100003", 1325ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 1326ecd94f1bSKan Liang }, 1327ecd94f1bSKan Liang { 1328ecd94f1bSKan Liang "Offcore": "1", 1329ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 1330ecd94f1bSKan Liang "UMask": "0x1", 1331ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS.ANY_SNOOP", 1332ecd94f1bSKan Liang "Deprecated": "1", 1333ecd94f1bSKan Liang "MSRValue": "0x3FBC000004", 1334ecd94f1bSKan Liang "Counter": "0,1,2,3", 1335ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=DEMAND_CODE_RD:response=L3_MISS.ANY_SNOOP", 1336ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 1337ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1338ecd94f1bSKan Liang "SampleAfterValue": "100003", 1339ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 1340ecd94f1bSKan Liang }, 1341ecd94f1bSKan Liang { 1342ecd94f1bSKan Liang "Offcore": "1", 1343ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 1344ecd94f1bSKan Liang "UMask": "0x1", 1345ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NONE", 1346ecd94f1bSKan Liang "Deprecated": "1", 1347ecd94f1bSKan Liang "MSRValue": "0x0084000010", 1348ecd94f1bSKan Liang "Counter": "0,1,2,3", 1349ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=PF_L2_DATA_RD:response=L3_MISS_LOCAL_DRAM.SNOOP_NONE", 1350ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 1351ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1352ecd94f1bSKan Liang "SampleAfterValue": "100003", 1353ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 1354ecd94f1bSKan Liang }, 1355ecd94f1bSKan Liang { 1356ecd94f1bSKan Liang "Offcore": "1", 1357ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 1358ecd94f1bSKan Liang "UMask": "0x1", 1359ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED", 1360ecd94f1bSKan Liang "Deprecated": "1", 1361ecd94f1bSKan Liang "MSRValue": "0x0104000010", 1362ecd94f1bSKan Liang "Counter": "0,1,2,3", 1363ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=PF_L2_DATA_RD:response=L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED", 1364ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 1365ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1366ecd94f1bSKan Liang "SampleAfterValue": "100003", 1367ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 1368ecd94f1bSKan Liang }, 1369ecd94f1bSKan Liang { 1370ecd94f1bSKan Liang "Offcore": "1", 1371ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 1372ecd94f1bSKan Liang "UMask": "0x1", 1373ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS", 1374ecd94f1bSKan Liang "Deprecated": "1", 1375ecd94f1bSKan Liang "MSRValue": "0x0204000010", 1376ecd94f1bSKan Liang "Counter": "0,1,2,3", 1377ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=PF_L2_DATA_RD:response=L3_MISS_LOCAL_DRAM.SNOOP_MISS", 1378ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 1379ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1380ecd94f1bSKan Liang "SampleAfterValue": "100003", 1381ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 1382ecd94f1bSKan Liang }, 1383ecd94f1bSKan Liang { 1384ecd94f1bSKan Liang "Offcore": "1", 1385ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 1386ecd94f1bSKan Liang "UMask": "0x1", 1387ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD", 1388ecd94f1bSKan Liang "Deprecated": "1", 1389ecd94f1bSKan Liang "MSRValue": "0x0404000010", 1390ecd94f1bSKan Liang "Counter": "0,1,2,3", 1391ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=PF_L2_DATA_RD:response=L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD", 1392ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 1393ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1394ecd94f1bSKan Liang "SampleAfterValue": "100003", 1395ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 1396ecd94f1bSKan Liang }, 1397ecd94f1bSKan Liang { 1398ecd94f1bSKan Liang "Offcore": "1", 1399ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 1400ecd94f1bSKan Liang "UMask": "0x1", 1401ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD", 1402ecd94f1bSKan Liang "Deprecated": "1", 1403ecd94f1bSKan Liang "MSRValue": "0x0804000010", 1404ecd94f1bSKan Liang "Counter": "0,1,2,3", 1405ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=PF_L2_DATA_RD:response=L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD", 1406ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 1407ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1408ecd94f1bSKan Liang "SampleAfterValue": "100003", 1409ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 1410ecd94f1bSKan Liang }, 1411ecd94f1bSKan Liang { 1412ecd94f1bSKan Liang "Offcore": "1", 1413ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 1414ecd94f1bSKan Liang "UMask": "0x1", 1415ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE", 1416ecd94f1bSKan Liang "Deprecated": "1", 1417ecd94f1bSKan Liang "MSRValue": "0x1004000010", 1418ecd94f1bSKan Liang "Counter": "0,1,2,3", 1419ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=PF_L2_DATA_RD:response=L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE", 1420ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 1421ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1422ecd94f1bSKan Liang "SampleAfterValue": "100003", 1423ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 1424ecd94f1bSKan Liang }, 1425ecd94f1bSKan Liang { 1426ecd94f1bSKan Liang "Offcore": "1", 1427ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 1428ecd94f1bSKan Liang "UMask": "0x1", 1429ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP", 1430ecd94f1bSKan Liang "Deprecated": "1", 1431ecd94f1bSKan Liang "MSRValue": "0x3F84000010", 1432ecd94f1bSKan Liang "Counter": "0,1,2,3", 1433ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=PF_L2_DATA_RD:response=L3_MISS_LOCAL_DRAM.ANY_SNOOP", 1434ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 1435ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1436ecd94f1bSKan Liang "SampleAfterValue": "100003", 1437ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 1438ecd94f1bSKan Liang }, 1439ecd94f1bSKan Liang { 1440ecd94f1bSKan Liang "Offcore": "1", 1441ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 1442ecd94f1bSKan Liang "UMask": "0x1", 1443ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE", 1444ecd94f1bSKan Liang "Deprecated": "1", 1445ecd94f1bSKan Liang "MSRValue": "0x0090000010", 1446ecd94f1bSKan Liang "Counter": "0,1,2,3", 1447ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=PF_L2_DATA_RD:response=L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE", 1448ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 1449ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1450ecd94f1bSKan Liang "SampleAfterValue": "100003", 1451ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 1452ecd94f1bSKan Liang }, 1453ecd94f1bSKan Liang { 1454ecd94f1bSKan Liang "Offcore": "1", 1455ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 1456ecd94f1bSKan Liang "UMask": "0x1", 1457ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED", 1458ecd94f1bSKan Liang "Deprecated": "1", 1459ecd94f1bSKan Liang "MSRValue": "0x0110000010", 1460ecd94f1bSKan Liang "Counter": "0,1,2,3", 1461ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=PF_L2_DATA_RD:response=L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED", 1462ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 1463ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1464ecd94f1bSKan Liang "SampleAfterValue": "100003", 1465ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 1466ecd94f1bSKan Liang }, 1467ecd94f1bSKan Liang { 1468ecd94f1bSKan Liang "Offcore": "1", 1469ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 1470ecd94f1bSKan Liang "UMask": "0x1", 1471ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS", 1472ecd94f1bSKan Liang "Deprecated": "1", 1473ecd94f1bSKan Liang "MSRValue": "0x0210000010", 1474ecd94f1bSKan Liang "Counter": "0,1,2,3", 1475ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=PF_L2_DATA_RD:response=L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS", 1476ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 1477ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1478ecd94f1bSKan Liang "SampleAfterValue": "100003", 1479ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 1480ecd94f1bSKan Liang }, 1481ecd94f1bSKan Liang { 1482ecd94f1bSKan Liang "Offcore": "1", 1483ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 1484ecd94f1bSKan Liang "UMask": "0x1", 1485ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD", 1486ecd94f1bSKan Liang "Deprecated": "1", 1487ecd94f1bSKan Liang "MSRValue": "0x0410000010", 1488ecd94f1bSKan Liang "Counter": "0,1,2,3", 1489ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=PF_L2_DATA_RD:response=L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD", 1490ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 1491ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1492ecd94f1bSKan Liang "SampleAfterValue": "100003", 1493ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 1494ecd94f1bSKan Liang }, 1495ecd94f1bSKan Liang { 1496ecd94f1bSKan Liang "Offcore": "1", 1497ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 1498ecd94f1bSKan Liang "UMask": "0x1", 1499ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD", 1500ecd94f1bSKan Liang "Deprecated": "1", 1501ecd94f1bSKan Liang "MSRValue": "0x0810000010", 1502ecd94f1bSKan Liang "Counter": "0,1,2,3", 1503ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=PF_L2_DATA_RD:response=L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD", 1504ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 1505ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1506ecd94f1bSKan Liang "SampleAfterValue": "100003", 1507ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 1508ecd94f1bSKan Liang }, 1509ecd94f1bSKan Liang { 1510ecd94f1bSKan Liang "Offcore": "1", 1511ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 1512ecd94f1bSKan Liang "UMask": "0x1", 1513ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE", 1514ecd94f1bSKan Liang "Deprecated": "1", 1515ecd94f1bSKan Liang "MSRValue": "0x1010000010", 1516ecd94f1bSKan Liang "Counter": "0,1,2,3", 1517ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=PF_L2_DATA_RD:response=L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE", 1518ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 1519ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1520ecd94f1bSKan Liang "SampleAfterValue": "100003", 1521ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 1522ecd94f1bSKan Liang }, 1523ecd94f1bSKan Liang { 1524ecd94f1bSKan Liang "Offcore": "1", 1525ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 1526ecd94f1bSKan Liang "UMask": "0x1", 1527ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP", 1528ecd94f1bSKan Liang "Deprecated": "1", 1529ecd94f1bSKan Liang "MSRValue": "0x3F90000010", 1530ecd94f1bSKan Liang "Counter": "0,1,2,3", 1531ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=PF_L2_DATA_RD:response=L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP", 1532ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 1533ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1534ecd94f1bSKan Liang "SampleAfterValue": "100003", 1535ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 1536ecd94f1bSKan Liang }, 1537ecd94f1bSKan Liang { 1538ecd94f1bSKan Liang "Offcore": "1", 1539ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 1540ecd94f1bSKan Liang "UMask": "0x1", 1541ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS.SNOOP_NONE", 1542ecd94f1bSKan Liang "Deprecated": "1", 1543ecd94f1bSKan Liang "MSRValue": "0x00BC000010", 1544ecd94f1bSKan Liang "Counter": "0,1,2,3", 1545ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=PF_L2_DATA_RD:response=L3_MISS.SNOOP_NONE", 1546ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 1547ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1548ecd94f1bSKan Liang "SampleAfterValue": "100003", 1549ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 1550ecd94f1bSKan Liang }, 1551ecd94f1bSKan Liang { 1552ecd94f1bSKan Liang "Offcore": "1", 1553ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 1554ecd94f1bSKan Liang "UMask": "0x1", 1555ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS.NO_SNOOP_NEEDED", 1556ecd94f1bSKan Liang "Deprecated": "1", 1557ecd94f1bSKan Liang "MSRValue": "0x013C000010", 1558ecd94f1bSKan Liang "Counter": "0,1,2,3", 1559ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=PF_L2_DATA_RD:response=L3_MISS.NO_SNOOP_NEEDED", 1560ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 1561ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1562ecd94f1bSKan Liang "SampleAfterValue": "100003", 1563ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 1564ecd94f1bSKan Liang }, 1565ecd94f1bSKan Liang { 1566ecd94f1bSKan Liang "Offcore": "1", 1567ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 1568ecd94f1bSKan Liang "UMask": "0x1", 1569ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS.SNOOP_MISS", 1570ecd94f1bSKan Liang "Deprecated": "1", 1571ecd94f1bSKan Liang "MSRValue": "0x023C000010", 1572ecd94f1bSKan Liang "Counter": "0,1,2,3", 1573ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=PF_L2_DATA_RD:response=L3_MISS.SNOOP_MISS", 1574ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 1575ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1576ecd94f1bSKan Liang "SampleAfterValue": "100003", 1577ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 1578ecd94f1bSKan Liang }, 1579ecd94f1bSKan Liang { 1580ecd94f1bSKan Liang "Offcore": "1", 1581ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 1582ecd94f1bSKan Liang "UMask": "0x1", 1583ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS.HIT_OTHER_CORE_NO_FWD", 1584ecd94f1bSKan Liang "Deprecated": "1", 1585ecd94f1bSKan Liang "MSRValue": "0x043C000010", 1586ecd94f1bSKan Liang "Counter": "0,1,2,3", 1587ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=PF_L2_DATA_RD:response=L3_MISS.HIT_OTHER_CORE_NO_FWD", 1588ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 1589ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1590ecd94f1bSKan Liang "SampleAfterValue": "100003", 1591ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 1592ecd94f1bSKan Liang }, 1593ecd94f1bSKan Liang { 1594ecd94f1bSKan Liang "Offcore": "1", 1595ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 1596ecd94f1bSKan Liang "UMask": "0x1", 1597ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS.HIT_OTHER_CORE_FWD", 1598ecd94f1bSKan Liang "Deprecated": "1", 1599ecd94f1bSKan Liang "MSRValue": "0x083C000010", 1600ecd94f1bSKan Liang "Counter": "0,1,2,3", 1601ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=PF_L2_DATA_RD:response=L3_MISS.HIT_OTHER_CORE_FWD", 1602ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 1603ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1604ecd94f1bSKan Liang "SampleAfterValue": "100003", 1605ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 1606ecd94f1bSKan Liang }, 1607ecd94f1bSKan Liang { 1608ecd94f1bSKan Liang "Offcore": "1", 1609ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 1610ecd94f1bSKan Liang "UMask": "0x1", 1611ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS.HITM_OTHER_CORE", 1612ecd94f1bSKan Liang "Deprecated": "1", 1613ecd94f1bSKan Liang "MSRValue": "0x103C000010", 1614ecd94f1bSKan Liang "Counter": "0,1,2,3", 1615ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=PF_L2_DATA_RD:response=L3_MISS.HITM_OTHER_CORE", 1616ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 1617ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1618ecd94f1bSKan Liang "SampleAfterValue": "100003", 1619ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 1620ecd94f1bSKan Liang }, 1621ecd94f1bSKan Liang { 1622ecd94f1bSKan Liang "Offcore": "1", 1623ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 1624ecd94f1bSKan Liang "UMask": "0x1", 1625ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS.ANY_SNOOP", 1626ecd94f1bSKan Liang "Deprecated": "1", 1627ecd94f1bSKan Liang "MSRValue": "0x3FBC000010", 1628ecd94f1bSKan Liang "Counter": "0,1,2,3", 1629ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=PF_L2_DATA_RD:response=L3_MISS.ANY_SNOOP", 1630ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 1631ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1632ecd94f1bSKan Liang "SampleAfterValue": "100003", 1633ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 1634ecd94f1bSKan Liang }, 1635ecd94f1bSKan Liang { 1636ecd94f1bSKan Liang "Offcore": "1", 1637ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 1638ecd94f1bSKan Liang "UMask": "0x1", 1639ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NONE", 1640ecd94f1bSKan Liang "Deprecated": "1", 1641ecd94f1bSKan Liang "MSRValue": "0x0084000020", 1642ecd94f1bSKan Liang "Counter": "0,1,2,3", 1643ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=PF_L2_RFO:response=L3_MISS_LOCAL_DRAM.SNOOP_NONE", 1644ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 1645ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1646ecd94f1bSKan Liang "SampleAfterValue": "100003", 1647ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 1648ecd94f1bSKan Liang }, 1649ecd94f1bSKan Liang { 1650ecd94f1bSKan Liang "Offcore": "1", 1651ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 1652ecd94f1bSKan Liang "UMask": "0x1", 1653ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED", 1654ecd94f1bSKan Liang "Deprecated": "1", 1655ecd94f1bSKan Liang "MSRValue": "0x0104000020", 1656ecd94f1bSKan Liang "Counter": "0,1,2,3", 1657ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=PF_L2_RFO:response=L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED", 1658ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 1659ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1660ecd94f1bSKan Liang "SampleAfterValue": "100003", 1661ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 1662ecd94f1bSKan Liang }, 1663ecd94f1bSKan Liang { 1664ecd94f1bSKan Liang "Offcore": "1", 1665ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 1666ecd94f1bSKan Liang "UMask": "0x1", 1667ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS", 1668ecd94f1bSKan Liang "Deprecated": "1", 1669ecd94f1bSKan Liang "MSRValue": "0x0204000020", 1670ecd94f1bSKan Liang "Counter": "0,1,2,3", 1671ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=PF_L2_RFO:response=L3_MISS_LOCAL_DRAM.SNOOP_MISS", 1672ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 1673ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1674ecd94f1bSKan Liang "SampleAfterValue": "100003", 1675ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 1676ecd94f1bSKan Liang }, 1677ecd94f1bSKan Liang { 1678ecd94f1bSKan Liang "Offcore": "1", 1679ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 1680ecd94f1bSKan Liang "UMask": "0x1", 1681ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD", 1682ecd94f1bSKan Liang "Deprecated": "1", 1683ecd94f1bSKan Liang "MSRValue": "0x0404000020", 1684ecd94f1bSKan Liang "Counter": "0,1,2,3", 1685ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=PF_L2_RFO:response=L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD", 1686ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 1687ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1688ecd94f1bSKan Liang "SampleAfterValue": "100003", 1689ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 1690ecd94f1bSKan Liang }, 1691ecd94f1bSKan Liang { 1692ecd94f1bSKan Liang "Offcore": "1", 1693ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 1694ecd94f1bSKan Liang "UMask": "0x1", 1695ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD", 1696ecd94f1bSKan Liang "Deprecated": "1", 1697ecd94f1bSKan Liang "MSRValue": "0x0804000020", 1698ecd94f1bSKan Liang "Counter": "0,1,2,3", 1699ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=PF_L2_RFO:response=L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD", 1700ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 1701ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1702ecd94f1bSKan Liang "SampleAfterValue": "100003", 1703ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 1704ecd94f1bSKan Liang }, 1705ecd94f1bSKan Liang { 1706ecd94f1bSKan Liang "Offcore": "1", 1707ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 1708ecd94f1bSKan Liang "UMask": "0x1", 1709ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE", 1710ecd94f1bSKan Liang "Deprecated": "1", 1711ecd94f1bSKan Liang "MSRValue": "0x1004000020", 1712ecd94f1bSKan Liang "Counter": "0,1,2,3", 1713ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=PF_L2_RFO:response=L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE", 1714ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 1715ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1716ecd94f1bSKan Liang "SampleAfterValue": "100003", 1717ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 1718ecd94f1bSKan Liang }, 1719ecd94f1bSKan Liang { 1720ecd94f1bSKan Liang "Offcore": "1", 1721ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 1722ecd94f1bSKan Liang "UMask": "0x1", 1723ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS_LOCAL_DRAM.ANY_SNOOP", 1724ecd94f1bSKan Liang "Deprecated": "1", 1725ecd94f1bSKan Liang "MSRValue": "0x3F84000020", 1726ecd94f1bSKan Liang "Counter": "0,1,2,3", 1727ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=PF_L2_RFO:response=L3_MISS_LOCAL_DRAM.ANY_SNOOP", 1728ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 1729ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1730ecd94f1bSKan Liang "SampleAfterValue": "100003", 1731ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 1732ecd94f1bSKan Liang }, 1733ecd94f1bSKan Liang { 1734ecd94f1bSKan Liang "Offcore": "1", 1735ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 1736ecd94f1bSKan Liang "UMask": "0x1", 1737ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE", 1738ecd94f1bSKan Liang "Deprecated": "1", 1739ecd94f1bSKan Liang "MSRValue": "0x0090000020", 1740ecd94f1bSKan Liang "Counter": "0,1,2,3", 1741ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=PF_L2_RFO:response=L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE", 1742ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 1743ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1744ecd94f1bSKan Liang "SampleAfterValue": "100003", 1745ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 1746ecd94f1bSKan Liang }, 1747ecd94f1bSKan Liang { 1748ecd94f1bSKan Liang "Offcore": "1", 1749ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 1750ecd94f1bSKan Liang "UMask": "0x1", 1751ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED", 1752ecd94f1bSKan Liang "Deprecated": "1", 1753ecd94f1bSKan Liang "MSRValue": "0x0110000020", 1754ecd94f1bSKan Liang "Counter": "0,1,2,3", 1755ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=PF_L2_RFO:response=L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED", 1756ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 1757ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1758ecd94f1bSKan Liang "SampleAfterValue": "100003", 1759ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 1760ecd94f1bSKan Liang }, 1761ecd94f1bSKan Liang { 1762ecd94f1bSKan Liang "Offcore": "1", 1763ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 1764ecd94f1bSKan Liang "UMask": "0x1", 1765ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS", 1766ecd94f1bSKan Liang "Deprecated": "1", 1767ecd94f1bSKan Liang "MSRValue": "0x0210000020", 1768ecd94f1bSKan Liang "Counter": "0,1,2,3", 1769ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=PF_L2_RFO:response=L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS", 1770ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 1771ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1772ecd94f1bSKan Liang "SampleAfterValue": "100003", 1773ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 1774ecd94f1bSKan Liang }, 1775ecd94f1bSKan Liang { 1776ecd94f1bSKan Liang "Offcore": "1", 1777ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 1778ecd94f1bSKan Liang "UMask": "0x1", 1779ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD", 1780ecd94f1bSKan Liang "Deprecated": "1", 1781ecd94f1bSKan Liang "MSRValue": "0x0410000020", 1782ecd94f1bSKan Liang "Counter": "0,1,2,3", 1783ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=PF_L2_RFO:response=L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD", 1784ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 1785ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1786ecd94f1bSKan Liang "SampleAfterValue": "100003", 1787ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 1788ecd94f1bSKan Liang }, 1789ecd94f1bSKan Liang { 1790ecd94f1bSKan Liang "Offcore": "1", 1791ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 1792ecd94f1bSKan Liang "UMask": "0x1", 1793ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD", 1794ecd94f1bSKan Liang "Deprecated": "1", 1795ecd94f1bSKan Liang "MSRValue": "0x0810000020", 1796ecd94f1bSKan Liang "Counter": "0,1,2,3", 1797ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=PF_L2_RFO:response=L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD", 1798ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 1799ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1800ecd94f1bSKan Liang "SampleAfterValue": "100003", 1801ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 1802ecd94f1bSKan Liang }, 1803ecd94f1bSKan Liang { 1804ecd94f1bSKan Liang "Offcore": "1", 1805ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 1806ecd94f1bSKan Liang "UMask": "0x1", 1807ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE", 1808ecd94f1bSKan Liang "Deprecated": "1", 1809ecd94f1bSKan Liang "MSRValue": "0x1010000020", 1810ecd94f1bSKan Liang "Counter": "0,1,2,3", 1811ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=PF_L2_RFO:response=L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE", 1812ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 1813ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1814ecd94f1bSKan Liang "SampleAfterValue": "100003", 1815ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 1816ecd94f1bSKan Liang }, 1817ecd94f1bSKan Liang { 1818ecd94f1bSKan Liang "Offcore": "1", 1819ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 1820ecd94f1bSKan Liang "UMask": "0x1", 1821ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP", 1822ecd94f1bSKan Liang "Deprecated": "1", 1823ecd94f1bSKan Liang "MSRValue": "0x3F90000020", 1824ecd94f1bSKan Liang "Counter": "0,1,2,3", 1825ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=PF_L2_RFO:response=L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP", 1826ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 1827ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1828ecd94f1bSKan Liang "SampleAfterValue": "100003", 1829ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 1830ecd94f1bSKan Liang }, 1831ecd94f1bSKan Liang { 1832ecd94f1bSKan Liang "Offcore": "1", 1833ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 1834ecd94f1bSKan Liang "UMask": "0x1", 1835ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS.SNOOP_NONE", 1836ecd94f1bSKan Liang "Deprecated": "1", 1837ecd94f1bSKan Liang "MSRValue": "0x00BC000020", 1838ecd94f1bSKan Liang "Counter": "0,1,2,3", 1839ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=PF_L2_RFO:response=L3_MISS.SNOOP_NONE", 1840ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 1841ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1842ecd94f1bSKan Liang "SampleAfterValue": "100003", 1843ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 1844ecd94f1bSKan Liang }, 1845ecd94f1bSKan Liang { 1846ecd94f1bSKan Liang "Offcore": "1", 1847ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 1848ecd94f1bSKan Liang "UMask": "0x1", 1849ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS.NO_SNOOP_NEEDED", 1850ecd94f1bSKan Liang "Deprecated": "1", 1851ecd94f1bSKan Liang "MSRValue": "0x013C000020", 1852ecd94f1bSKan Liang "Counter": "0,1,2,3", 1853ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=PF_L2_RFO:response=L3_MISS.NO_SNOOP_NEEDED", 1854ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 1855ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1856ecd94f1bSKan Liang "SampleAfterValue": "100003", 1857ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 1858ecd94f1bSKan Liang }, 1859ecd94f1bSKan Liang { 1860ecd94f1bSKan Liang "Offcore": "1", 1861ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 1862ecd94f1bSKan Liang "UMask": "0x1", 1863ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS.SNOOP_MISS", 1864ecd94f1bSKan Liang "Deprecated": "1", 1865ecd94f1bSKan Liang "MSRValue": "0x023C000020", 1866ecd94f1bSKan Liang "Counter": "0,1,2,3", 1867ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=PF_L2_RFO:response=L3_MISS.SNOOP_MISS", 1868ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 1869ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1870ecd94f1bSKan Liang "SampleAfterValue": "100003", 1871ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 1872ecd94f1bSKan Liang }, 1873ecd94f1bSKan Liang { 1874ecd94f1bSKan Liang "Offcore": "1", 1875ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 1876ecd94f1bSKan Liang "UMask": "0x1", 1877ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS.HIT_OTHER_CORE_NO_FWD", 1878ecd94f1bSKan Liang "Deprecated": "1", 1879ecd94f1bSKan Liang "MSRValue": "0x043C000020", 1880ecd94f1bSKan Liang "Counter": "0,1,2,3", 1881ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=PF_L2_RFO:response=L3_MISS.HIT_OTHER_CORE_NO_FWD", 1882ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 1883ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1884ecd94f1bSKan Liang "SampleAfterValue": "100003", 1885ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 1886ecd94f1bSKan Liang }, 1887ecd94f1bSKan Liang { 1888ecd94f1bSKan Liang "Offcore": "1", 1889ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 1890ecd94f1bSKan Liang "UMask": "0x1", 1891ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS.HIT_OTHER_CORE_FWD", 1892ecd94f1bSKan Liang "Deprecated": "1", 1893ecd94f1bSKan Liang "MSRValue": "0x083C000020", 1894ecd94f1bSKan Liang "Counter": "0,1,2,3", 1895ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=PF_L2_RFO:response=L3_MISS.HIT_OTHER_CORE_FWD", 1896ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 1897ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1898ecd94f1bSKan Liang "SampleAfterValue": "100003", 1899ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 1900ecd94f1bSKan Liang }, 1901ecd94f1bSKan Liang { 1902ecd94f1bSKan Liang "Offcore": "1", 1903ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 1904ecd94f1bSKan Liang "UMask": "0x1", 1905ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS.HITM_OTHER_CORE", 1906ecd94f1bSKan Liang "Deprecated": "1", 1907ecd94f1bSKan Liang "MSRValue": "0x103C000020", 1908ecd94f1bSKan Liang "Counter": "0,1,2,3", 1909ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=PF_L2_RFO:response=L3_MISS.HITM_OTHER_CORE", 1910ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 1911ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1912ecd94f1bSKan Liang "SampleAfterValue": "100003", 1913ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 1914ecd94f1bSKan Liang }, 1915ecd94f1bSKan Liang { 1916ecd94f1bSKan Liang "Offcore": "1", 1917ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 1918ecd94f1bSKan Liang "UMask": "0x1", 1919ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS.ANY_SNOOP", 1920ecd94f1bSKan Liang "Deprecated": "1", 1921ecd94f1bSKan Liang "MSRValue": "0x3FBC000020", 1922ecd94f1bSKan Liang "Counter": "0,1,2,3", 1923ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=PF_L2_RFO:response=L3_MISS.ANY_SNOOP", 1924ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 1925ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1926ecd94f1bSKan Liang "SampleAfterValue": "100003", 1927ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 1928ecd94f1bSKan Liang }, 1929ecd94f1bSKan Liang { 1930ecd94f1bSKan Liang "Offcore": "1", 1931ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 1932ecd94f1bSKan Liang "UMask": "0x1", 1933ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NONE", 1934ecd94f1bSKan Liang "Deprecated": "1", 1935ecd94f1bSKan Liang "MSRValue": "0x0084000080", 1936ecd94f1bSKan Liang "Counter": "0,1,2,3", 1937ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=PF_L3_DATA_RD:response=L3_MISS_LOCAL_DRAM.SNOOP_NONE", 1938ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 1939ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1940ecd94f1bSKan Liang "SampleAfterValue": "100003", 1941ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 1942ecd94f1bSKan Liang }, 1943ecd94f1bSKan Liang { 1944ecd94f1bSKan Liang "Offcore": "1", 1945ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 1946ecd94f1bSKan Liang "UMask": "0x1", 1947ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED", 1948ecd94f1bSKan Liang "Deprecated": "1", 1949ecd94f1bSKan Liang "MSRValue": "0x0104000080", 1950ecd94f1bSKan Liang "Counter": "0,1,2,3", 1951ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=PF_L3_DATA_RD:response=L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED", 1952ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 1953ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1954ecd94f1bSKan Liang "SampleAfterValue": "100003", 1955ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 1956ecd94f1bSKan Liang }, 1957ecd94f1bSKan Liang { 1958ecd94f1bSKan Liang "Offcore": "1", 1959ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 1960ecd94f1bSKan Liang "UMask": "0x1", 1961ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS", 1962ecd94f1bSKan Liang "Deprecated": "1", 1963ecd94f1bSKan Liang "MSRValue": "0x0204000080", 1964ecd94f1bSKan Liang "Counter": "0,1,2,3", 1965ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=PF_L3_DATA_RD:response=L3_MISS_LOCAL_DRAM.SNOOP_MISS", 1966ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 1967ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1968ecd94f1bSKan Liang "SampleAfterValue": "100003", 1969ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 1970ecd94f1bSKan Liang }, 1971ecd94f1bSKan Liang { 1972ecd94f1bSKan Liang "Offcore": "1", 1973ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 1974ecd94f1bSKan Liang "UMask": "0x1", 1975ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD", 1976ecd94f1bSKan Liang "Deprecated": "1", 1977ecd94f1bSKan Liang "MSRValue": "0x0404000080", 1978ecd94f1bSKan Liang "Counter": "0,1,2,3", 1979ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=PF_L3_DATA_RD:response=L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD", 1980ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 1981ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1982ecd94f1bSKan Liang "SampleAfterValue": "100003", 1983ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 1984ecd94f1bSKan Liang }, 1985ecd94f1bSKan Liang { 1986ecd94f1bSKan Liang "Offcore": "1", 1987ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 1988ecd94f1bSKan Liang "UMask": "0x1", 1989ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD", 1990ecd94f1bSKan Liang "Deprecated": "1", 1991ecd94f1bSKan Liang "MSRValue": "0x0804000080", 1992ecd94f1bSKan Liang "Counter": "0,1,2,3", 1993ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=PF_L3_DATA_RD:response=L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD", 1994ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 1995ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1996ecd94f1bSKan Liang "SampleAfterValue": "100003", 1997ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 1998ecd94f1bSKan Liang }, 1999ecd94f1bSKan Liang { 2000ecd94f1bSKan Liang "Offcore": "1", 2001ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 2002ecd94f1bSKan Liang "UMask": "0x1", 2003ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE", 2004ecd94f1bSKan Liang "Deprecated": "1", 2005ecd94f1bSKan Liang "MSRValue": "0x1004000080", 2006ecd94f1bSKan Liang "Counter": "0,1,2,3", 2007ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=PF_L3_DATA_RD:response=L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE", 2008ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 2009ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2010ecd94f1bSKan Liang "SampleAfterValue": "100003", 2011ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 2012ecd94f1bSKan Liang }, 2013ecd94f1bSKan Liang { 2014ecd94f1bSKan Liang "Offcore": "1", 2015ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 2016ecd94f1bSKan Liang "UMask": "0x1", 2017ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP", 2018ecd94f1bSKan Liang "Deprecated": "1", 2019ecd94f1bSKan Liang "MSRValue": "0x3F84000080", 2020ecd94f1bSKan Liang "Counter": "0,1,2,3", 2021ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=PF_L3_DATA_RD:response=L3_MISS_LOCAL_DRAM.ANY_SNOOP", 2022ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 2023ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2024ecd94f1bSKan Liang "SampleAfterValue": "100003", 2025ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 2026ecd94f1bSKan Liang }, 2027ecd94f1bSKan Liang { 2028ecd94f1bSKan Liang "Offcore": "1", 2029ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 2030ecd94f1bSKan Liang "UMask": "0x1", 2031ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE", 2032ecd94f1bSKan Liang "Deprecated": "1", 2033ecd94f1bSKan Liang "MSRValue": "0x0090000080", 2034ecd94f1bSKan Liang "Counter": "0,1,2,3", 2035ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=PF_L3_DATA_RD:response=L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE", 2036ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 2037ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2038ecd94f1bSKan Liang "SampleAfterValue": "100003", 2039ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 2040ecd94f1bSKan Liang }, 2041ecd94f1bSKan Liang { 2042ecd94f1bSKan Liang "Offcore": "1", 2043ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 2044ecd94f1bSKan Liang "UMask": "0x1", 2045ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED", 2046ecd94f1bSKan Liang "Deprecated": "1", 2047ecd94f1bSKan Liang "MSRValue": "0x0110000080", 2048ecd94f1bSKan Liang "Counter": "0,1,2,3", 2049ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=PF_L3_DATA_RD:response=L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED", 2050ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 2051ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2052ecd94f1bSKan Liang "SampleAfterValue": "100003", 2053ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 2054ecd94f1bSKan Liang }, 2055ecd94f1bSKan Liang { 2056ecd94f1bSKan Liang "Offcore": "1", 2057ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 2058ecd94f1bSKan Liang "UMask": "0x1", 2059ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS", 2060ecd94f1bSKan Liang "Deprecated": "1", 2061ecd94f1bSKan Liang "MSRValue": "0x0210000080", 2062ecd94f1bSKan Liang "Counter": "0,1,2,3", 2063ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=PF_L3_DATA_RD:response=L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS", 2064ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 2065ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2066ecd94f1bSKan Liang "SampleAfterValue": "100003", 2067ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 2068ecd94f1bSKan Liang }, 2069ecd94f1bSKan Liang { 2070ecd94f1bSKan Liang "Offcore": "1", 2071ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 2072ecd94f1bSKan Liang "UMask": "0x1", 2073ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD", 2074ecd94f1bSKan Liang "Deprecated": "1", 2075ecd94f1bSKan Liang "MSRValue": "0x0410000080", 2076ecd94f1bSKan Liang "Counter": "0,1,2,3", 2077ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=PF_L3_DATA_RD:response=L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD", 2078ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 2079ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2080ecd94f1bSKan Liang "SampleAfterValue": "100003", 2081ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 2082ecd94f1bSKan Liang }, 2083ecd94f1bSKan Liang { 2084ecd94f1bSKan Liang "Offcore": "1", 2085ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 2086ecd94f1bSKan Liang "UMask": "0x1", 2087ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD", 2088ecd94f1bSKan Liang "Deprecated": "1", 2089ecd94f1bSKan Liang "MSRValue": "0x0810000080", 2090ecd94f1bSKan Liang "Counter": "0,1,2,3", 2091ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=PF_L3_DATA_RD:response=L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD", 2092ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 2093ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2094ecd94f1bSKan Liang "SampleAfterValue": "100003", 2095ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 2096ecd94f1bSKan Liang }, 2097ecd94f1bSKan Liang { 2098ecd94f1bSKan Liang "Offcore": "1", 2099ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 2100ecd94f1bSKan Liang "UMask": "0x1", 2101ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE", 2102ecd94f1bSKan Liang "Deprecated": "1", 2103ecd94f1bSKan Liang "MSRValue": "0x1010000080", 2104ecd94f1bSKan Liang "Counter": "0,1,2,3", 2105ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=PF_L3_DATA_RD:response=L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE", 2106ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 2107ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2108ecd94f1bSKan Liang "SampleAfterValue": "100003", 2109ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 2110ecd94f1bSKan Liang }, 2111ecd94f1bSKan Liang { 2112ecd94f1bSKan Liang "Offcore": "1", 2113ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 2114ecd94f1bSKan Liang "UMask": "0x1", 2115ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP", 2116ecd94f1bSKan Liang "Deprecated": "1", 2117ecd94f1bSKan Liang "MSRValue": "0x3F90000080", 2118ecd94f1bSKan Liang "Counter": "0,1,2,3", 2119ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=PF_L3_DATA_RD:response=L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP", 2120ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 2121ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2122ecd94f1bSKan Liang "SampleAfterValue": "100003", 2123ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 2124ecd94f1bSKan Liang }, 2125ecd94f1bSKan Liang { 2126ecd94f1bSKan Liang "Offcore": "1", 2127ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 2128ecd94f1bSKan Liang "UMask": "0x1", 2129ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS.SNOOP_NONE", 2130ecd94f1bSKan Liang "Deprecated": "1", 2131ecd94f1bSKan Liang "MSRValue": "0x00BC000080", 2132ecd94f1bSKan Liang "Counter": "0,1,2,3", 2133ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=PF_L3_DATA_RD:response=L3_MISS.SNOOP_NONE", 2134ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 2135ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2136ecd94f1bSKan Liang "SampleAfterValue": "100003", 2137ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 2138ecd94f1bSKan Liang }, 2139ecd94f1bSKan Liang { 2140ecd94f1bSKan Liang "Offcore": "1", 2141ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 2142ecd94f1bSKan Liang "UMask": "0x1", 2143ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS.NO_SNOOP_NEEDED", 2144ecd94f1bSKan Liang "Deprecated": "1", 2145ecd94f1bSKan Liang "MSRValue": "0x013C000080", 2146ecd94f1bSKan Liang "Counter": "0,1,2,3", 2147ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=PF_L3_DATA_RD:response=L3_MISS.NO_SNOOP_NEEDED", 2148ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 2149ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2150ecd94f1bSKan Liang "SampleAfterValue": "100003", 2151ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 2152ecd94f1bSKan Liang }, 2153ecd94f1bSKan Liang { 2154ecd94f1bSKan Liang "Offcore": "1", 2155ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 2156ecd94f1bSKan Liang "UMask": "0x1", 2157ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS.SNOOP_MISS", 2158ecd94f1bSKan Liang "Deprecated": "1", 2159ecd94f1bSKan Liang "MSRValue": "0x023C000080", 2160ecd94f1bSKan Liang "Counter": "0,1,2,3", 2161ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=PF_L3_DATA_RD:response=L3_MISS.SNOOP_MISS", 2162ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 2163ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2164ecd94f1bSKan Liang "SampleAfterValue": "100003", 2165ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 2166ecd94f1bSKan Liang }, 2167ecd94f1bSKan Liang { 2168ecd94f1bSKan Liang "Offcore": "1", 2169ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 2170ecd94f1bSKan Liang "UMask": "0x1", 2171ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS.HIT_OTHER_CORE_NO_FWD", 2172ecd94f1bSKan Liang "Deprecated": "1", 2173ecd94f1bSKan Liang "MSRValue": "0x043C000080", 2174ecd94f1bSKan Liang "Counter": "0,1,2,3", 2175ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=PF_L3_DATA_RD:response=L3_MISS.HIT_OTHER_CORE_NO_FWD", 2176ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 2177ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2178ecd94f1bSKan Liang "SampleAfterValue": "100003", 2179ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 2180ecd94f1bSKan Liang }, 2181ecd94f1bSKan Liang { 2182ecd94f1bSKan Liang "Offcore": "1", 2183ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 2184ecd94f1bSKan Liang "UMask": "0x1", 2185ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS.HIT_OTHER_CORE_FWD", 2186ecd94f1bSKan Liang "Deprecated": "1", 2187ecd94f1bSKan Liang "MSRValue": "0x083C000080", 2188ecd94f1bSKan Liang "Counter": "0,1,2,3", 2189ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=PF_L3_DATA_RD:response=L3_MISS.HIT_OTHER_CORE_FWD", 2190ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 2191ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2192ecd94f1bSKan Liang "SampleAfterValue": "100003", 2193ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 2194ecd94f1bSKan Liang }, 2195ecd94f1bSKan Liang { 2196ecd94f1bSKan Liang "Offcore": "1", 2197ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 2198ecd94f1bSKan Liang "UMask": "0x1", 2199ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS.HITM_OTHER_CORE", 2200ecd94f1bSKan Liang "Deprecated": "1", 2201ecd94f1bSKan Liang "MSRValue": "0x103C000080", 2202ecd94f1bSKan Liang "Counter": "0,1,2,3", 2203ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=PF_L3_DATA_RD:response=L3_MISS.HITM_OTHER_CORE", 2204ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 2205ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2206ecd94f1bSKan Liang "SampleAfterValue": "100003", 2207ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 2208ecd94f1bSKan Liang }, 2209ecd94f1bSKan Liang { 2210ecd94f1bSKan Liang "Offcore": "1", 2211ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 2212ecd94f1bSKan Liang "UMask": "0x1", 2213ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS.ANY_SNOOP", 2214ecd94f1bSKan Liang "Deprecated": "1", 2215ecd94f1bSKan Liang "MSRValue": "0x3FBC000080", 2216ecd94f1bSKan Liang "Counter": "0,1,2,3", 2217ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=PF_L3_DATA_RD:response=L3_MISS.ANY_SNOOP", 2218ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 2219ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2220ecd94f1bSKan Liang "SampleAfterValue": "100003", 2221ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 2222ecd94f1bSKan Liang }, 2223ecd94f1bSKan Liang { 2224ecd94f1bSKan Liang "Offcore": "1", 2225ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 2226ecd94f1bSKan Liang "UMask": "0x1", 2227ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NONE", 2228ecd94f1bSKan Liang "Deprecated": "1", 2229ecd94f1bSKan Liang "MSRValue": "0x0084000100", 2230ecd94f1bSKan Liang "Counter": "0,1,2,3", 2231ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=PF_L3_RFO:response=L3_MISS_LOCAL_DRAM.SNOOP_NONE", 2232ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 2233ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2234ecd94f1bSKan Liang "SampleAfterValue": "100003", 2235ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 2236ecd94f1bSKan Liang }, 2237ecd94f1bSKan Liang { 2238ecd94f1bSKan Liang "Offcore": "1", 2239ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 2240ecd94f1bSKan Liang "UMask": "0x1", 2241ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED", 2242ecd94f1bSKan Liang "Deprecated": "1", 2243ecd94f1bSKan Liang "MSRValue": "0x0104000100", 2244ecd94f1bSKan Liang "Counter": "0,1,2,3", 2245ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=PF_L3_RFO:response=L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED", 2246ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 2247ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2248ecd94f1bSKan Liang "SampleAfterValue": "100003", 2249ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 2250ecd94f1bSKan Liang }, 2251ecd94f1bSKan Liang { 2252ecd94f1bSKan Liang "Offcore": "1", 2253ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 2254ecd94f1bSKan Liang "UMask": "0x1", 2255ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS", 2256ecd94f1bSKan Liang "Deprecated": "1", 2257ecd94f1bSKan Liang "MSRValue": "0x0204000100", 2258ecd94f1bSKan Liang "Counter": "0,1,2,3", 2259ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=PF_L3_RFO:response=L3_MISS_LOCAL_DRAM.SNOOP_MISS", 2260ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 2261ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2262ecd94f1bSKan Liang "SampleAfterValue": "100003", 2263ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 2264ecd94f1bSKan Liang }, 2265ecd94f1bSKan Liang { 2266ecd94f1bSKan Liang "Offcore": "1", 2267ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 2268ecd94f1bSKan Liang "UMask": "0x1", 2269ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD", 2270ecd94f1bSKan Liang "Deprecated": "1", 2271ecd94f1bSKan Liang "MSRValue": "0x0404000100", 2272ecd94f1bSKan Liang "Counter": "0,1,2,3", 2273ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=PF_L3_RFO:response=L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD", 2274ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 2275ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2276ecd94f1bSKan Liang "SampleAfterValue": "100003", 2277ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 2278ecd94f1bSKan Liang }, 2279ecd94f1bSKan Liang { 2280ecd94f1bSKan Liang "Offcore": "1", 2281ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 2282ecd94f1bSKan Liang "UMask": "0x1", 2283ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD", 2284ecd94f1bSKan Liang "Deprecated": "1", 2285ecd94f1bSKan Liang "MSRValue": "0x0804000100", 2286ecd94f1bSKan Liang "Counter": "0,1,2,3", 2287ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=PF_L3_RFO:response=L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD", 2288ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 2289ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2290ecd94f1bSKan Liang "SampleAfterValue": "100003", 2291ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 2292ecd94f1bSKan Liang }, 2293ecd94f1bSKan Liang { 2294ecd94f1bSKan Liang "Offcore": "1", 2295ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 2296ecd94f1bSKan Liang "UMask": "0x1", 2297ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE", 2298ecd94f1bSKan Liang "Deprecated": "1", 2299ecd94f1bSKan Liang "MSRValue": "0x1004000100", 2300ecd94f1bSKan Liang "Counter": "0,1,2,3", 2301ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=PF_L3_RFO:response=L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE", 2302ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 2303ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2304ecd94f1bSKan Liang "SampleAfterValue": "100003", 2305ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 2306ecd94f1bSKan Liang }, 2307ecd94f1bSKan Liang { 2308ecd94f1bSKan Liang "Offcore": "1", 2309ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 2310ecd94f1bSKan Liang "UMask": "0x1", 2311ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS_LOCAL_DRAM.ANY_SNOOP", 2312ecd94f1bSKan Liang "Deprecated": "1", 2313ecd94f1bSKan Liang "MSRValue": "0x3F84000100", 2314ecd94f1bSKan Liang "Counter": "0,1,2,3", 2315ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=PF_L3_RFO:response=L3_MISS_LOCAL_DRAM.ANY_SNOOP", 2316ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 2317ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2318ecd94f1bSKan Liang "SampleAfterValue": "100003", 2319ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 2320ecd94f1bSKan Liang }, 2321ecd94f1bSKan Liang { 2322ecd94f1bSKan Liang "Offcore": "1", 2323ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 2324ecd94f1bSKan Liang "UMask": "0x1", 2325ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE", 2326ecd94f1bSKan Liang "Deprecated": "1", 2327ecd94f1bSKan Liang "MSRValue": "0x0090000100", 2328ecd94f1bSKan Liang "Counter": "0,1,2,3", 2329ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=PF_L3_RFO:response=L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE", 2330ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 2331ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2332ecd94f1bSKan Liang "SampleAfterValue": "100003", 2333ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 2334ecd94f1bSKan Liang }, 2335ecd94f1bSKan Liang { 2336ecd94f1bSKan Liang "Offcore": "1", 2337ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 2338ecd94f1bSKan Liang "UMask": "0x1", 2339ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED", 2340ecd94f1bSKan Liang "Deprecated": "1", 2341ecd94f1bSKan Liang "MSRValue": "0x0110000100", 2342ecd94f1bSKan Liang "Counter": "0,1,2,3", 2343ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=PF_L3_RFO:response=L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED", 2344ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 2345ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2346ecd94f1bSKan Liang "SampleAfterValue": "100003", 2347ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 2348ecd94f1bSKan Liang }, 2349ecd94f1bSKan Liang { 2350ecd94f1bSKan Liang "Offcore": "1", 2351ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 2352ecd94f1bSKan Liang "UMask": "0x1", 2353ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS", 2354ecd94f1bSKan Liang "Deprecated": "1", 2355ecd94f1bSKan Liang "MSRValue": "0x0210000100", 2356ecd94f1bSKan Liang "Counter": "0,1,2,3", 2357ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=PF_L3_RFO:response=L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS", 2358ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 2359ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2360ecd94f1bSKan Liang "SampleAfterValue": "100003", 2361ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 2362ecd94f1bSKan Liang }, 2363ecd94f1bSKan Liang { 2364ecd94f1bSKan Liang "Offcore": "1", 2365ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 2366ecd94f1bSKan Liang "UMask": "0x1", 2367ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD", 2368ecd94f1bSKan Liang "Deprecated": "1", 2369ecd94f1bSKan Liang "MSRValue": "0x0410000100", 2370ecd94f1bSKan Liang "Counter": "0,1,2,3", 2371ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=PF_L3_RFO:response=L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD", 2372ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 2373ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2374ecd94f1bSKan Liang "SampleAfterValue": "100003", 2375ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 2376ecd94f1bSKan Liang }, 2377ecd94f1bSKan Liang { 2378ecd94f1bSKan Liang "Offcore": "1", 2379ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 2380ecd94f1bSKan Liang "UMask": "0x1", 2381ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD", 2382ecd94f1bSKan Liang "Deprecated": "1", 2383ecd94f1bSKan Liang "MSRValue": "0x0810000100", 2384ecd94f1bSKan Liang "Counter": "0,1,2,3", 2385ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=PF_L3_RFO:response=L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD", 2386ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 2387ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2388ecd94f1bSKan Liang "SampleAfterValue": "100003", 2389ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 2390ecd94f1bSKan Liang }, 2391ecd94f1bSKan Liang { 2392ecd94f1bSKan Liang "Offcore": "1", 2393ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 2394ecd94f1bSKan Liang "UMask": "0x1", 2395ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE", 2396ecd94f1bSKan Liang "Deprecated": "1", 2397ecd94f1bSKan Liang "MSRValue": "0x1010000100", 2398ecd94f1bSKan Liang "Counter": "0,1,2,3", 2399ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=PF_L3_RFO:response=L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE", 2400ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 2401ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2402ecd94f1bSKan Liang "SampleAfterValue": "100003", 2403ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 2404ecd94f1bSKan Liang }, 2405ecd94f1bSKan Liang { 2406ecd94f1bSKan Liang "Offcore": "1", 2407ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 2408ecd94f1bSKan Liang "UMask": "0x1", 2409ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP", 2410ecd94f1bSKan Liang "Deprecated": "1", 2411ecd94f1bSKan Liang "MSRValue": "0x3F90000100", 2412ecd94f1bSKan Liang "Counter": "0,1,2,3", 2413ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=PF_L3_RFO:response=L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP", 2414ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 2415ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2416ecd94f1bSKan Liang "SampleAfterValue": "100003", 2417ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 2418ecd94f1bSKan Liang }, 2419ecd94f1bSKan Liang { 2420ecd94f1bSKan Liang "Offcore": "1", 2421ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 2422ecd94f1bSKan Liang "UMask": "0x1", 2423ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS.SNOOP_NONE", 2424ecd94f1bSKan Liang "Deprecated": "1", 2425ecd94f1bSKan Liang "MSRValue": "0x00BC000100", 2426ecd94f1bSKan Liang "Counter": "0,1,2,3", 2427ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=PF_L3_RFO:response=L3_MISS.SNOOP_NONE", 2428ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 2429ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2430ecd94f1bSKan Liang "SampleAfterValue": "100003", 2431ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 2432ecd94f1bSKan Liang }, 2433ecd94f1bSKan Liang { 2434ecd94f1bSKan Liang "Offcore": "1", 2435ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 2436ecd94f1bSKan Liang "UMask": "0x1", 2437ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS.NO_SNOOP_NEEDED", 2438ecd94f1bSKan Liang "Deprecated": "1", 2439ecd94f1bSKan Liang "MSRValue": "0x013C000100", 2440ecd94f1bSKan Liang "Counter": "0,1,2,3", 2441ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=PF_L3_RFO:response=L3_MISS.NO_SNOOP_NEEDED", 2442ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 2443ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2444ecd94f1bSKan Liang "SampleAfterValue": "100003", 2445ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 2446ecd94f1bSKan Liang }, 2447ecd94f1bSKan Liang { 2448ecd94f1bSKan Liang "Offcore": "1", 2449ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 2450ecd94f1bSKan Liang "UMask": "0x1", 2451ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS.SNOOP_MISS", 2452ecd94f1bSKan Liang "Deprecated": "1", 2453ecd94f1bSKan Liang "MSRValue": "0x023C000100", 2454ecd94f1bSKan Liang "Counter": "0,1,2,3", 2455ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=PF_L3_RFO:response=L3_MISS.SNOOP_MISS", 2456ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 2457ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2458ecd94f1bSKan Liang "SampleAfterValue": "100003", 2459ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 2460ecd94f1bSKan Liang }, 2461ecd94f1bSKan Liang { 2462ecd94f1bSKan Liang "Offcore": "1", 2463ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 2464ecd94f1bSKan Liang "UMask": "0x1", 2465ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS.HIT_OTHER_CORE_NO_FWD", 2466ecd94f1bSKan Liang "Deprecated": "1", 2467ecd94f1bSKan Liang "MSRValue": "0x043C000100", 2468ecd94f1bSKan Liang "Counter": "0,1,2,3", 2469ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=PF_L3_RFO:response=L3_MISS.HIT_OTHER_CORE_NO_FWD", 2470ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 2471ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2472ecd94f1bSKan Liang "SampleAfterValue": "100003", 2473ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 2474ecd94f1bSKan Liang }, 2475ecd94f1bSKan Liang { 2476ecd94f1bSKan Liang "Offcore": "1", 2477ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 2478ecd94f1bSKan Liang "UMask": "0x1", 2479ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS.HIT_OTHER_CORE_FWD", 2480ecd94f1bSKan Liang "Deprecated": "1", 2481ecd94f1bSKan Liang "MSRValue": "0x083C000100", 2482ecd94f1bSKan Liang "Counter": "0,1,2,3", 2483ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=PF_L3_RFO:response=L3_MISS.HIT_OTHER_CORE_FWD", 2484ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 2485ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2486ecd94f1bSKan Liang "SampleAfterValue": "100003", 2487ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 2488ecd94f1bSKan Liang }, 2489ecd94f1bSKan Liang { 2490ecd94f1bSKan Liang "Offcore": "1", 2491ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 2492ecd94f1bSKan Liang "UMask": "0x1", 2493ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS.HITM_OTHER_CORE", 2494ecd94f1bSKan Liang "Deprecated": "1", 2495ecd94f1bSKan Liang "MSRValue": "0x103C000100", 2496ecd94f1bSKan Liang "Counter": "0,1,2,3", 2497ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=PF_L3_RFO:response=L3_MISS.HITM_OTHER_CORE", 2498ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 2499ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2500ecd94f1bSKan Liang "SampleAfterValue": "100003", 2501ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 2502ecd94f1bSKan Liang }, 2503ecd94f1bSKan Liang { 2504ecd94f1bSKan Liang "Offcore": "1", 2505ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 2506ecd94f1bSKan Liang "UMask": "0x1", 2507ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS.ANY_SNOOP", 2508ecd94f1bSKan Liang "Deprecated": "1", 2509ecd94f1bSKan Liang "MSRValue": "0x3FBC000100", 2510ecd94f1bSKan Liang "Counter": "0,1,2,3", 2511ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=PF_L3_RFO:response=L3_MISS.ANY_SNOOP", 2512ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 2513ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2514ecd94f1bSKan Liang "SampleAfterValue": "100003", 2515ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 2516ecd94f1bSKan Liang }, 2517ecd94f1bSKan Liang { 2518ecd94f1bSKan Liang "Offcore": "1", 2519ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 2520ecd94f1bSKan Liang "UMask": "0x1", 2521ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.SNOOP_NONE", 2522ecd94f1bSKan Liang "Deprecated": "1", 2523ecd94f1bSKan Liang "MSRValue": "0x0084000400", 2524ecd94f1bSKan Liang "Counter": "0,1,2,3", 2525ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=PF_L1D_AND_SW:response=L3_MISS_LOCAL_DRAM.SNOOP_NONE", 2526ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 2527ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2528ecd94f1bSKan Liang "SampleAfterValue": "100003", 2529ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 2530ecd94f1bSKan Liang }, 2531ecd94f1bSKan Liang { 2532ecd94f1bSKan Liang "Offcore": "1", 2533ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 2534ecd94f1bSKan Liang "UMask": "0x1", 2535ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED", 2536ecd94f1bSKan Liang "Deprecated": "1", 2537ecd94f1bSKan Liang "MSRValue": "0x0104000400", 2538ecd94f1bSKan Liang "Counter": "0,1,2,3", 2539ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=PF_L1D_AND_SW:response=L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED", 2540ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 2541ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2542ecd94f1bSKan Liang "SampleAfterValue": "100003", 2543ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 2544ecd94f1bSKan Liang }, 2545ecd94f1bSKan Liang { 2546ecd94f1bSKan Liang "Offcore": "1", 2547ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 2548ecd94f1bSKan Liang "UMask": "0x1", 2549ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.SNOOP_MISS", 2550ecd94f1bSKan Liang "Deprecated": "1", 2551ecd94f1bSKan Liang "MSRValue": "0x0204000400", 2552ecd94f1bSKan Liang "Counter": "0,1,2,3", 2553ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=PF_L1D_AND_SW:response=L3_MISS_LOCAL_DRAM.SNOOP_MISS", 2554ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 2555ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2556ecd94f1bSKan Liang "SampleAfterValue": "100003", 2557ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 2558ecd94f1bSKan Liang }, 2559ecd94f1bSKan Liang { 2560ecd94f1bSKan Liang "Offcore": "1", 2561ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 2562ecd94f1bSKan Liang "UMask": "0x1", 2563ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD", 2564ecd94f1bSKan Liang "Deprecated": "1", 2565ecd94f1bSKan Liang "MSRValue": "0x0404000400", 2566ecd94f1bSKan Liang "Counter": "0,1,2,3", 2567ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=PF_L1D_AND_SW:response=L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD", 2568ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 2569ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2570ecd94f1bSKan Liang "SampleAfterValue": "100003", 2571ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 2572ecd94f1bSKan Liang }, 2573ecd94f1bSKan Liang { 2574ecd94f1bSKan Liang "Offcore": "1", 2575ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 2576ecd94f1bSKan Liang "UMask": "0x1", 2577ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD", 2578ecd94f1bSKan Liang "Deprecated": "1", 2579ecd94f1bSKan Liang "MSRValue": "0x0804000400", 2580ecd94f1bSKan Liang "Counter": "0,1,2,3", 2581ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=PF_L1D_AND_SW:response=L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD", 2582ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 2583ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2584ecd94f1bSKan Liang "SampleAfterValue": "100003", 2585ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 2586ecd94f1bSKan Liang }, 2587ecd94f1bSKan Liang { 2588ecd94f1bSKan Liang "Offcore": "1", 2589ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 2590ecd94f1bSKan Liang "UMask": "0x1", 2591ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE", 2592ecd94f1bSKan Liang "Deprecated": "1", 2593ecd94f1bSKan Liang "MSRValue": "0x1004000400", 2594ecd94f1bSKan Liang "Counter": "0,1,2,3", 2595ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=PF_L1D_AND_SW:response=L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE", 2596ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 2597ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2598ecd94f1bSKan Liang "SampleAfterValue": "100003", 2599ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 2600ecd94f1bSKan Liang }, 2601ecd94f1bSKan Liang { 2602ecd94f1bSKan Liang "Offcore": "1", 2603ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 2604ecd94f1bSKan Liang "UMask": "0x1", 2605ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.ANY_SNOOP", 2606ecd94f1bSKan Liang "Deprecated": "1", 2607ecd94f1bSKan Liang "MSRValue": "0x3F84000400", 2608ecd94f1bSKan Liang "Counter": "0,1,2,3", 2609ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=PF_L1D_AND_SW:response=L3_MISS_LOCAL_DRAM.ANY_SNOOP", 2610ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 2611ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2612ecd94f1bSKan Liang "SampleAfterValue": "100003", 2613ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 2614ecd94f1bSKan Liang }, 2615ecd94f1bSKan Liang { 2616ecd94f1bSKan Liang "Offcore": "1", 2617ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 2618ecd94f1bSKan Liang "UMask": "0x1", 2619ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE", 2620ecd94f1bSKan Liang "Deprecated": "1", 2621ecd94f1bSKan Liang "MSRValue": "0x0090000400", 2622ecd94f1bSKan Liang "Counter": "0,1,2,3", 2623ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=PF_L1D_AND_SW:response=L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE", 2624ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 2625ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2626ecd94f1bSKan Liang "SampleAfterValue": "100003", 2627ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 2628ecd94f1bSKan Liang }, 2629ecd94f1bSKan Liang { 2630ecd94f1bSKan Liang "Offcore": "1", 2631ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 2632ecd94f1bSKan Liang "UMask": "0x1", 2633ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED", 2634ecd94f1bSKan Liang "Deprecated": "1", 2635ecd94f1bSKan Liang "MSRValue": "0x0110000400", 2636ecd94f1bSKan Liang "Counter": "0,1,2,3", 2637ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=PF_L1D_AND_SW:response=L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED", 2638ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 2639ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2640ecd94f1bSKan Liang "SampleAfterValue": "100003", 2641ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 2642ecd94f1bSKan Liang }, 2643ecd94f1bSKan Liang { 2644ecd94f1bSKan Liang "Offcore": "1", 2645ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 2646ecd94f1bSKan Liang "UMask": "0x1", 2647ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS", 2648ecd94f1bSKan Liang "Deprecated": "1", 2649ecd94f1bSKan Liang "MSRValue": "0x0210000400", 2650ecd94f1bSKan Liang "Counter": "0,1,2,3", 2651ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=PF_L1D_AND_SW:response=L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS", 2652ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 2653ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2654ecd94f1bSKan Liang "SampleAfterValue": "100003", 2655ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 2656ecd94f1bSKan Liang }, 2657ecd94f1bSKan Liang { 2658ecd94f1bSKan Liang "Offcore": "1", 2659ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 2660ecd94f1bSKan Liang "UMask": "0x1", 2661ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD", 2662ecd94f1bSKan Liang "Deprecated": "1", 2663ecd94f1bSKan Liang "MSRValue": "0x0410000400", 2664ecd94f1bSKan Liang "Counter": "0,1,2,3", 2665ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=PF_L1D_AND_SW:response=L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD", 2666ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 2667ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2668ecd94f1bSKan Liang "SampleAfterValue": "100003", 2669ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 2670ecd94f1bSKan Liang }, 2671ecd94f1bSKan Liang { 2672ecd94f1bSKan Liang "Offcore": "1", 2673ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 2674ecd94f1bSKan Liang "UMask": "0x1", 2675ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD", 2676ecd94f1bSKan Liang "Deprecated": "1", 2677ecd94f1bSKan Liang "MSRValue": "0x0810000400", 2678ecd94f1bSKan Liang "Counter": "0,1,2,3", 2679ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=PF_L1D_AND_SW:response=L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD", 2680ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 2681ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2682ecd94f1bSKan Liang "SampleAfterValue": "100003", 2683ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 2684ecd94f1bSKan Liang }, 2685ecd94f1bSKan Liang { 2686ecd94f1bSKan Liang "Offcore": "1", 2687ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 2688ecd94f1bSKan Liang "UMask": "0x1", 2689ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE", 2690ecd94f1bSKan Liang "Deprecated": "1", 2691ecd94f1bSKan Liang "MSRValue": "0x1010000400", 2692ecd94f1bSKan Liang "Counter": "0,1,2,3", 2693ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=PF_L1D_AND_SW:response=L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE", 2694ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 2695ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2696ecd94f1bSKan Liang "SampleAfterValue": "100003", 2697ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 2698ecd94f1bSKan Liang }, 2699ecd94f1bSKan Liang { 2700ecd94f1bSKan Liang "Offcore": "1", 2701ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 2702ecd94f1bSKan Liang "UMask": "0x1", 2703ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP", 2704ecd94f1bSKan Liang "Deprecated": "1", 2705ecd94f1bSKan Liang "MSRValue": "0x3F90000400", 2706ecd94f1bSKan Liang "Counter": "0,1,2,3", 2707ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=PF_L1D_AND_SW:response=L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP", 2708ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 2709ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2710ecd94f1bSKan Liang "SampleAfterValue": "100003", 2711ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 2712ecd94f1bSKan Liang }, 2713ecd94f1bSKan Liang { 2714ecd94f1bSKan Liang "Offcore": "1", 2715ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 2716ecd94f1bSKan Liang "UMask": "0x1", 2717ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS.SNOOP_NONE", 2718ecd94f1bSKan Liang "Deprecated": "1", 2719ecd94f1bSKan Liang "MSRValue": "0x00BC000400", 2720ecd94f1bSKan Liang "Counter": "0,1,2,3", 2721ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=PF_L1D_AND_SW:response=L3_MISS.SNOOP_NONE", 2722ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 2723ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2724ecd94f1bSKan Liang "SampleAfterValue": "100003", 2725ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 2726ecd94f1bSKan Liang }, 2727ecd94f1bSKan Liang { 2728ecd94f1bSKan Liang "Offcore": "1", 2729ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 2730ecd94f1bSKan Liang "UMask": "0x1", 2731ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS.NO_SNOOP_NEEDED", 2732ecd94f1bSKan Liang "Deprecated": "1", 2733ecd94f1bSKan Liang "MSRValue": "0x013C000400", 2734ecd94f1bSKan Liang "Counter": "0,1,2,3", 2735ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=PF_L1D_AND_SW:response=L3_MISS.NO_SNOOP_NEEDED", 2736ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 2737ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2738ecd94f1bSKan Liang "SampleAfterValue": "100003", 2739ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 2740ecd94f1bSKan Liang }, 2741ecd94f1bSKan Liang { 2742ecd94f1bSKan Liang "Offcore": "1", 2743ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 2744ecd94f1bSKan Liang "UMask": "0x1", 2745ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS.SNOOP_MISS", 2746ecd94f1bSKan Liang "Deprecated": "1", 2747ecd94f1bSKan Liang "MSRValue": "0x023C000400", 2748ecd94f1bSKan Liang "Counter": "0,1,2,3", 2749ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=PF_L1D_AND_SW:response=L3_MISS.SNOOP_MISS", 2750ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 2751ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2752ecd94f1bSKan Liang "SampleAfterValue": "100003", 2753ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 2754ecd94f1bSKan Liang }, 2755ecd94f1bSKan Liang { 2756ecd94f1bSKan Liang "Offcore": "1", 2757ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 2758ecd94f1bSKan Liang "UMask": "0x1", 2759ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS.HIT_OTHER_CORE_NO_FWD", 2760ecd94f1bSKan Liang "Deprecated": "1", 2761ecd94f1bSKan Liang "MSRValue": "0x043C000400", 2762ecd94f1bSKan Liang "Counter": "0,1,2,3", 2763ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=PF_L1D_AND_SW:response=L3_MISS.HIT_OTHER_CORE_NO_FWD", 2764ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 2765ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2766ecd94f1bSKan Liang "SampleAfterValue": "100003", 2767ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 2768ecd94f1bSKan Liang }, 2769ecd94f1bSKan Liang { 2770ecd94f1bSKan Liang "Offcore": "1", 2771ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 2772ecd94f1bSKan Liang "UMask": "0x1", 2773ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS.HIT_OTHER_CORE_FWD", 2774ecd94f1bSKan Liang "Deprecated": "1", 2775ecd94f1bSKan Liang "MSRValue": "0x083C000400", 2776ecd94f1bSKan Liang "Counter": "0,1,2,3", 2777ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=PF_L1D_AND_SW:response=L3_MISS.HIT_OTHER_CORE_FWD", 2778ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 2779ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2780ecd94f1bSKan Liang "SampleAfterValue": "100003", 2781ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 2782ecd94f1bSKan Liang }, 2783ecd94f1bSKan Liang { 2784ecd94f1bSKan Liang "Offcore": "1", 2785ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 2786ecd94f1bSKan Liang "UMask": "0x1", 2787ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS.HITM_OTHER_CORE", 2788ecd94f1bSKan Liang "Deprecated": "1", 2789ecd94f1bSKan Liang "MSRValue": "0x103C000400", 2790ecd94f1bSKan Liang "Counter": "0,1,2,3", 2791ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=PF_L1D_AND_SW:response=L3_MISS.HITM_OTHER_CORE", 2792ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 2793ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2794ecd94f1bSKan Liang "SampleAfterValue": "100003", 2795ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 2796ecd94f1bSKan Liang }, 2797ecd94f1bSKan Liang { 2798ecd94f1bSKan Liang "Offcore": "1", 2799ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 2800ecd94f1bSKan Liang "UMask": "0x1", 2801ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS.ANY_SNOOP", 2802ecd94f1bSKan Liang "Deprecated": "1", 2803ecd94f1bSKan Liang "MSRValue": "0x3FBC000400", 2804ecd94f1bSKan Liang "Counter": "0,1,2,3", 2805ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=PF_L1D_AND_SW:response=L3_MISS.ANY_SNOOP", 2806ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 2807ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2808ecd94f1bSKan Liang "SampleAfterValue": "100003", 2809ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 2810ecd94f1bSKan Liang }, 2811ecd94f1bSKan Liang { 2812ecd94f1bSKan Liang "Offcore": "1", 2813ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 2814ecd94f1bSKan Liang "UMask": "0x1", 2815ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.OTHER.L3_MISS_LOCAL_DRAM.SNOOP_NONE", 2816ecd94f1bSKan Liang "Deprecated": "1", 2817ecd94f1bSKan Liang "MSRValue": "0x0084008000", 2818ecd94f1bSKan Liang "Counter": "0,1,2,3", 2819ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=OTHER:response=L3_MISS_LOCAL_DRAM.SNOOP_NONE", 2820ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 2821ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2822ecd94f1bSKan Liang "SampleAfterValue": "100003", 2823ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 2824ecd94f1bSKan Liang }, 2825ecd94f1bSKan Liang { 2826ecd94f1bSKan Liang "Offcore": "1", 2827ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 2828ecd94f1bSKan Liang "UMask": "0x1", 2829ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.OTHER.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED", 2830ecd94f1bSKan Liang "Deprecated": "1", 2831ecd94f1bSKan Liang "MSRValue": "0x0104008000", 2832ecd94f1bSKan Liang "Counter": "0,1,2,3", 2833ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=OTHER:response=L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED", 2834ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 2835ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2836ecd94f1bSKan Liang "SampleAfterValue": "100003", 2837ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 2838ecd94f1bSKan Liang }, 2839ecd94f1bSKan Liang { 2840ecd94f1bSKan Liang "Offcore": "1", 2841ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 2842ecd94f1bSKan Liang "UMask": "0x1", 2843ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.OTHER.L3_MISS_LOCAL_DRAM.SNOOP_MISS", 2844ecd94f1bSKan Liang "Deprecated": "1", 2845ecd94f1bSKan Liang "MSRValue": "0x0204008000", 2846ecd94f1bSKan Liang "Counter": "0,1,2,3", 2847ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=OTHER:response=L3_MISS_LOCAL_DRAM.SNOOP_MISS", 2848ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 2849ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2850ecd94f1bSKan Liang "SampleAfterValue": "100003", 2851ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 2852ecd94f1bSKan Liang }, 2853ecd94f1bSKan Liang { 2854ecd94f1bSKan Liang "Offcore": "1", 2855ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 2856ecd94f1bSKan Liang "UMask": "0x1", 2857ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.OTHER.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD", 2858ecd94f1bSKan Liang "Deprecated": "1", 2859ecd94f1bSKan Liang "MSRValue": "0x0404008000", 2860ecd94f1bSKan Liang "Counter": "0,1,2,3", 2861ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=OTHER:response=L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD", 2862ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 2863ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2864ecd94f1bSKan Liang "SampleAfterValue": "100003", 2865ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 2866ecd94f1bSKan Liang }, 2867ecd94f1bSKan Liang { 2868ecd94f1bSKan Liang "Offcore": "1", 2869ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 2870ecd94f1bSKan Liang "UMask": "0x1", 2871ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.OTHER.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD", 2872ecd94f1bSKan Liang "Deprecated": "1", 2873ecd94f1bSKan Liang "MSRValue": "0x0804008000", 2874ecd94f1bSKan Liang "Counter": "0,1,2,3", 2875ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=OTHER:response=L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD", 2876ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 2877ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2878ecd94f1bSKan Liang "SampleAfterValue": "100003", 2879ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 2880ecd94f1bSKan Liang }, 2881ecd94f1bSKan Liang { 2882ecd94f1bSKan Liang "Offcore": "1", 2883ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 2884ecd94f1bSKan Liang "UMask": "0x1", 2885ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.OTHER.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE", 2886ecd94f1bSKan Liang "Deprecated": "1", 2887ecd94f1bSKan Liang "MSRValue": "0x1004008000", 2888ecd94f1bSKan Liang "Counter": "0,1,2,3", 2889ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=OTHER:response=L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE", 2890ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 2891ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2892ecd94f1bSKan Liang "SampleAfterValue": "100003", 2893ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 2894ecd94f1bSKan Liang }, 2895ecd94f1bSKan Liang { 2896ecd94f1bSKan Liang "Offcore": "1", 2897ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 2898ecd94f1bSKan Liang "UMask": "0x1", 2899ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.OTHER.L3_MISS_LOCAL_DRAM.ANY_SNOOP", 2900ecd94f1bSKan Liang "Deprecated": "1", 2901ecd94f1bSKan Liang "MSRValue": "0x3F84008000", 2902ecd94f1bSKan Liang "Counter": "0,1,2,3", 2903ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=OTHER:response=L3_MISS_LOCAL_DRAM.ANY_SNOOP", 2904ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 2905ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2906ecd94f1bSKan Liang "SampleAfterValue": "100003", 2907ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 2908ecd94f1bSKan Liang }, 2909ecd94f1bSKan Liang { 2910ecd94f1bSKan Liang "Offcore": "1", 2911ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 2912ecd94f1bSKan Liang "UMask": "0x1", 2913ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.OTHER.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE", 2914ecd94f1bSKan Liang "Deprecated": "1", 2915ecd94f1bSKan Liang "MSRValue": "0x0090008000", 2916ecd94f1bSKan Liang "Counter": "0,1,2,3", 2917ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=OTHER:response=L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE", 2918ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 2919ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2920ecd94f1bSKan Liang "SampleAfterValue": "100003", 2921ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 2922ecd94f1bSKan Liang }, 2923ecd94f1bSKan Liang { 2924ecd94f1bSKan Liang "Offcore": "1", 2925ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 2926ecd94f1bSKan Liang "UMask": "0x1", 2927ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.OTHER.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED", 2928ecd94f1bSKan Liang "Deprecated": "1", 2929ecd94f1bSKan Liang "MSRValue": "0x0110008000", 2930ecd94f1bSKan Liang "Counter": "0,1,2,3", 2931ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=OTHER:response=L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED", 2932ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 2933ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2934ecd94f1bSKan Liang "SampleAfterValue": "100003", 2935ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 2936ecd94f1bSKan Liang }, 2937ecd94f1bSKan Liang { 2938ecd94f1bSKan Liang "Offcore": "1", 2939ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 2940ecd94f1bSKan Liang "UMask": "0x1", 2941ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.OTHER.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS", 2942ecd94f1bSKan Liang "Deprecated": "1", 2943ecd94f1bSKan Liang "MSRValue": "0x0210008000", 2944ecd94f1bSKan Liang "Counter": "0,1,2,3", 2945ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=OTHER:response=L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS", 2946ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 2947ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2948ecd94f1bSKan Liang "SampleAfterValue": "100003", 2949ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 2950ecd94f1bSKan Liang }, 2951ecd94f1bSKan Liang { 2952ecd94f1bSKan Liang "Offcore": "1", 2953ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 2954ecd94f1bSKan Liang "UMask": "0x1", 2955ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.OTHER.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD", 2956ecd94f1bSKan Liang "Deprecated": "1", 2957ecd94f1bSKan Liang "MSRValue": "0x0410008000", 2958ecd94f1bSKan Liang "Counter": "0,1,2,3", 2959ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=OTHER:response=L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD", 2960ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 2961ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2962ecd94f1bSKan Liang "SampleAfterValue": "100003", 2963ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 2964ecd94f1bSKan Liang }, 2965ecd94f1bSKan Liang { 2966ecd94f1bSKan Liang "Offcore": "1", 2967ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 2968ecd94f1bSKan Liang "UMask": "0x1", 2969ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.OTHER.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD", 2970ecd94f1bSKan Liang "Deprecated": "1", 2971ecd94f1bSKan Liang "MSRValue": "0x0810008000", 2972ecd94f1bSKan Liang "Counter": "0,1,2,3", 2973ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=OTHER:response=L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD", 2974ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 2975ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2976ecd94f1bSKan Liang "SampleAfterValue": "100003", 2977ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 2978ecd94f1bSKan Liang }, 2979ecd94f1bSKan Liang { 2980ecd94f1bSKan Liang "Offcore": "1", 2981ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 2982ecd94f1bSKan Liang "UMask": "0x1", 2983ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.OTHER.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE", 2984ecd94f1bSKan Liang "Deprecated": "1", 2985ecd94f1bSKan Liang "MSRValue": "0x1010008000", 2986ecd94f1bSKan Liang "Counter": "0,1,2,3", 2987ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=OTHER:response=L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE", 2988ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 2989ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2990ecd94f1bSKan Liang "SampleAfterValue": "100003", 2991ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 2992ecd94f1bSKan Liang }, 2993ecd94f1bSKan Liang { 2994ecd94f1bSKan Liang "Offcore": "1", 2995ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 2996ecd94f1bSKan Liang "UMask": "0x1", 2997ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.OTHER.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP", 2998ecd94f1bSKan Liang "Deprecated": "1", 2999ecd94f1bSKan Liang "MSRValue": "0x3F90008000", 3000ecd94f1bSKan Liang "Counter": "0,1,2,3", 3001ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=OTHER:response=L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP", 3002ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 3003ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3004ecd94f1bSKan Liang "SampleAfterValue": "100003", 3005ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 3006ecd94f1bSKan Liang }, 3007ecd94f1bSKan Liang { 3008ecd94f1bSKan Liang "Offcore": "1", 3009ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 3010ecd94f1bSKan Liang "UMask": "0x1", 3011ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.OTHER.L3_MISS.SNOOP_NONE", 3012ecd94f1bSKan Liang "Deprecated": "1", 3013ecd94f1bSKan Liang "MSRValue": "0x00BC008000", 3014ecd94f1bSKan Liang "Counter": "0,1,2,3", 3015ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=OTHER:response=L3_MISS.SNOOP_NONE", 3016ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 3017ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3018ecd94f1bSKan Liang "SampleAfterValue": "100003", 3019ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 3020ecd94f1bSKan Liang }, 3021ecd94f1bSKan Liang { 3022ecd94f1bSKan Liang "Offcore": "1", 3023ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 3024ecd94f1bSKan Liang "UMask": "0x1", 3025ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.OTHER.L3_MISS.NO_SNOOP_NEEDED", 3026ecd94f1bSKan Liang "Deprecated": "1", 3027ecd94f1bSKan Liang "MSRValue": "0x013C008000", 3028ecd94f1bSKan Liang "Counter": "0,1,2,3", 3029ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=OTHER:response=L3_MISS.NO_SNOOP_NEEDED", 3030ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 3031ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3032ecd94f1bSKan Liang "SampleAfterValue": "100003", 3033ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 3034ecd94f1bSKan Liang }, 3035ecd94f1bSKan Liang { 3036ecd94f1bSKan Liang "Offcore": "1", 3037ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 3038ecd94f1bSKan Liang "UMask": "0x1", 3039ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.OTHER.L3_MISS.SNOOP_MISS", 3040ecd94f1bSKan Liang "Deprecated": "1", 3041ecd94f1bSKan Liang "MSRValue": "0x023C008000", 3042ecd94f1bSKan Liang "Counter": "0,1,2,3", 3043ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=OTHER:response=L3_MISS.SNOOP_MISS", 3044ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 3045ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3046ecd94f1bSKan Liang "SampleAfterValue": "100003", 3047ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 3048ecd94f1bSKan Liang }, 3049ecd94f1bSKan Liang { 3050ecd94f1bSKan Liang "Offcore": "1", 3051ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 3052ecd94f1bSKan Liang "UMask": "0x1", 3053ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.OTHER.L3_MISS.HIT_OTHER_CORE_NO_FWD", 3054ecd94f1bSKan Liang "Deprecated": "1", 3055ecd94f1bSKan Liang "MSRValue": "0x043C008000", 3056ecd94f1bSKan Liang "Counter": "0,1,2,3", 3057ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=OTHER:response=L3_MISS.HIT_OTHER_CORE_NO_FWD", 3058ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 3059ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3060ecd94f1bSKan Liang "SampleAfterValue": "100003", 3061ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 3062ecd94f1bSKan Liang }, 3063ecd94f1bSKan Liang { 3064ecd94f1bSKan Liang "Offcore": "1", 3065ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 3066ecd94f1bSKan Liang "UMask": "0x1", 3067ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.OTHER.L3_MISS.HIT_OTHER_CORE_FWD", 3068ecd94f1bSKan Liang "Deprecated": "1", 3069ecd94f1bSKan Liang "MSRValue": "0x083C008000", 3070ecd94f1bSKan Liang "Counter": "0,1,2,3", 3071ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=OTHER:response=L3_MISS.HIT_OTHER_CORE_FWD", 3072ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 3073ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3074ecd94f1bSKan Liang "SampleAfterValue": "100003", 3075ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 3076ecd94f1bSKan Liang }, 3077ecd94f1bSKan Liang { 3078ecd94f1bSKan Liang "Offcore": "1", 3079ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 3080ecd94f1bSKan Liang "UMask": "0x1", 3081ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.OTHER.L3_MISS.HITM_OTHER_CORE", 3082ecd94f1bSKan Liang "Deprecated": "1", 3083ecd94f1bSKan Liang "MSRValue": "0x103C008000", 3084ecd94f1bSKan Liang "Counter": "0,1,2,3", 3085ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=OTHER:response=L3_MISS.HITM_OTHER_CORE", 3086ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 3087ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3088ecd94f1bSKan Liang "SampleAfterValue": "100003", 3089ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 3090ecd94f1bSKan Liang }, 3091ecd94f1bSKan Liang { 3092ecd94f1bSKan Liang "Offcore": "1", 3093ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 3094ecd94f1bSKan Liang "UMask": "0x1", 3095ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.OTHER.L3_MISS.ANY_SNOOP", 3096ecd94f1bSKan Liang "Deprecated": "1", 3097ecd94f1bSKan Liang "MSRValue": "0x3FBC008000", 3098ecd94f1bSKan Liang "Counter": "0,1,2,3", 3099ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=OTHER:response=L3_MISS.ANY_SNOOP", 3100ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 3101ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3102ecd94f1bSKan Liang "SampleAfterValue": "100003", 3103ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 3104ecd94f1bSKan Liang }, 3105ecd94f1bSKan Liang { 3106ecd94f1bSKan Liang "Offcore": "1", 3107ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 3108ecd94f1bSKan Liang "UMask": "0x1", 3109ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NONE", 3110ecd94f1bSKan Liang "Deprecated": "1", 3111ecd94f1bSKan Liang "MSRValue": "0x0084000490", 3112ecd94f1bSKan Liang "Counter": "0,1,2,3", 3113ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=ALL_PF_DATA_RD:response=L3_MISS_LOCAL_DRAM.SNOOP_NONE", 3114ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 3115ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3116ecd94f1bSKan Liang "SampleAfterValue": "100003", 3117ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 3118ecd94f1bSKan Liang }, 3119ecd94f1bSKan Liang { 3120ecd94f1bSKan Liang "Offcore": "1", 3121ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 3122ecd94f1bSKan Liang "UMask": "0x1", 3123ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED", 3124ecd94f1bSKan Liang "Deprecated": "1", 3125ecd94f1bSKan Liang "MSRValue": "0x0104000490", 3126ecd94f1bSKan Liang "Counter": "0,1,2,3", 3127ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=ALL_PF_DATA_RD:response=L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED", 3128ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 3129ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3130ecd94f1bSKan Liang "SampleAfterValue": "100003", 3131ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 3132ecd94f1bSKan Liang }, 3133ecd94f1bSKan Liang { 3134ecd94f1bSKan Liang "Offcore": "1", 3135ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 3136ecd94f1bSKan Liang "UMask": "0x1", 3137ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS", 3138ecd94f1bSKan Liang "Deprecated": "1", 3139ecd94f1bSKan Liang "MSRValue": "0x0204000490", 3140ecd94f1bSKan Liang "Counter": "0,1,2,3", 3141ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=ALL_PF_DATA_RD:response=L3_MISS_LOCAL_DRAM.SNOOP_MISS", 3142ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 3143ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3144ecd94f1bSKan Liang "SampleAfterValue": "100003", 3145ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 3146ecd94f1bSKan Liang }, 3147ecd94f1bSKan Liang { 3148ecd94f1bSKan Liang "Offcore": "1", 3149ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 3150ecd94f1bSKan Liang "UMask": "0x1", 3151ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD", 3152ecd94f1bSKan Liang "Deprecated": "1", 3153ecd94f1bSKan Liang "MSRValue": "0x0404000490", 3154ecd94f1bSKan Liang "Counter": "0,1,2,3", 3155ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=ALL_PF_DATA_RD:response=L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD", 3156ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 3157ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3158ecd94f1bSKan Liang "SampleAfterValue": "100003", 3159ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 3160ecd94f1bSKan Liang }, 3161ecd94f1bSKan Liang { 3162ecd94f1bSKan Liang "Offcore": "1", 3163ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 3164ecd94f1bSKan Liang "UMask": "0x1", 3165ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD", 3166ecd94f1bSKan Liang "Deprecated": "1", 3167ecd94f1bSKan Liang "MSRValue": "0x0804000490", 3168ecd94f1bSKan Liang "Counter": "0,1,2,3", 3169ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=ALL_PF_DATA_RD:response=L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD", 3170ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 3171ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3172ecd94f1bSKan Liang "SampleAfterValue": "100003", 3173ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 3174ecd94f1bSKan Liang }, 3175ecd94f1bSKan Liang { 3176ecd94f1bSKan Liang "Offcore": "1", 3177ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 3178ecd94f1bSKan Liang "UMask": "0x1", 3179ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE", 3180ecd94f1bSKan Liang "Deprecated": "1", 3181ecd94f1bSKan Liang "MSRValue": "0x1004000490", 3182ecd94f1bSKan Liang "Counter": "0,1,2,3", 3183ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=ALL_PF_DATA_RD:response=L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE", 3184ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 3185ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3186ecd94f1bSKan Liang "SampleAfterValue": "100003", 3187ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 3188ecd94f1bSKan Liang }, 3189ecd94f1bSKan Liang { 3190ecd94f1bSKan Liang "Offcore": "1", 3191ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 3192ecd94f1bSKan Liang "UMask": "0x1", 3193ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP", 3194ecd94f1bSKan Liang "Deprecated": "1", 3195ecd94f1bSKan Liang "MSRValue": "0x3F84000490", 3196ecd94f1bSKan Liang "Counter": "0,1,2,3", 3197ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=ALL_PF_DATA_RD:response=L3_MISS_LOCAL_DRAM.ANY_SNOOP", 3198ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 3199ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3200ecd94f1bSKan Liang "SampleAfterValue": "100003", 3201ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 3202ecd94f1bSKan Liang }, 3203ecd94f1bSKan Liang { 3204ecd94f1bSKan Liang "Offcore": "1", 3205ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 3206ecd94f1bSKan Liang "UMask": "0x1", 3207ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE", 3208ecd94f1bSKan Liang "Deprecated": "1", 3209ecd94f1bSKan Liang "MSRValue": "0x0090000490", 3210ecd94f1bSKan Liang "Counter": "0,1,2,3", 3211ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=ALL_PF_DATA_RD:response=L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE", 3212ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 3213ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3214ecd94f1bSKan Liang "SampleAfterValue": "100003", 3215ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 3216ecd94f1bSKan Liang }, 3217ecd94f1bSKan Liang { 3218ecd94f1bSKan Liang "Offcore": "1", 3219ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 3220ecd94f1bSKan Liang "UMask": "0x1", 3221ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED", 3222ecd94f1bSKan Liang "Deprecated": "1", 3223ecd94f1bSKan Liang "MSRValue": "0x0110000490", 3224ecd94f1bSKan Liang "Counter": "0,1,2,3", 3225ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=ALL_PF_DATA_RD:response=L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED", 3226ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 3227ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3228ecd94f1bSKan Liang "SampleAfterValue": "100003", 3229ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 3230ecd94f1bSKan Liang }, 3231ecd94f1bSKan Liang { 3232ecd94f1bSKan Liang "Offcore": "1", 3233ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 3234ecd94f1bSKan Liang "UMask": "0x1", 3235ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS", 3236ecd94f1bSKan Liang "Deprecated": "1", 3237ecd94f1bSKan Liang "MSRValue": "0x0210000490", 3238ecd94f1bSKan Liang "Counter": "0,1,2,3", 3239ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=ALL_PF_DATA_RD:response=L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS", 3240ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 3241ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3242ecd94f1bSKan Liang "SampleAfterValue": "100003", 3243ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 3244ecd94f1bSKan Liang }, 3245ecd94f1bSKan Liang { 3246ecd94f1bSKan Liang "Offcore": "1", 3247ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 3248ecd94f1bSKan Liang "UMask": "0x1", 3249ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD", 3250ecd94f1bSKan Liang "Deprecated": "1", 3251ecd94f1bSKan Liang "MSRValue": "0x0410000490", 3252ecd94f1bSKan Liang "Counter": "0,1,2,3", 3253ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=ALL_PF_DATA_RD:response=L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD", 3254ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 3255ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3256ecd94f1bSKan Liang "SampleAfterValue": "100003", 3257ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 3258ecd94f1bSKan Liang }, 3259ecd94f1bSKan Liang { 3260ecd94f1bSKan Liang "Offcore": "1", 3261ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 3262ecd94f1bSKan Liang "UMask": "0x1", 3263ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD", 3264ecd94f1bSKan Liang "Deprecated": "1", 3265ecd94f1bSKan Liang "MSRValue": "0x0810000490", 3266ecd94f1bSKan Liang "Counter": "0,1,2,3", 3267ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=ALL_PF_DATA_RD:response=L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD", 3268ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 3269ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3270ecd94f1bSKan Liang "SampleAfterValue": "100003", 3271ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 3272ecd94f1bSKan Liang }, 3273ecd94f1bSKan Liang { 3274ecd94f1bSKan Liang "Offcore": "1", 3275ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 3276ecd94f1bSKan Liang "UMask": "0x1", 3277ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE", 3278ecd94f1bSKan Liang "Deprecated": "1", 3279ecd94f1bSKan Liang "MSRValue": "0x1010000490", 3280ecd94f1bSKan Liang "Counter": "0,1,2,3", 3281ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=ALL_PF_DATA_RD:response=L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE", 3282ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 3283ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3284ecd94f1bSKan Liang "SampleAfterValue": "100003", 3285ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 3286ecd94f1bSKan Liang }, 3287ecd94f1bSKan Liang { 3288ecd94f1bSKan Liang "Offcore": "1", 3289ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 3290ecd94f1bSKan Liang "UMask": "0x1", 3291ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP", 3292ecd94f1bSKan Liang "Deprecated": "1", 3293ecd94f1bSKan Liang "MSRValue": "0x3F90000490", 3294ecd94f1bSKan Liang "Counter": "0,1,2,3", 3295ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=ALL_PF_DATA_RD:response=L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP", 3296ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 3297ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3298ecd94f1bSKan Liang "SampleAfterValue": "100003", 3299ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 3300ecd94f1bSKan Liang }, 3301ecd94f1bSKan Liang { 3302ecd94f1bSKan Liang "Offcore": "1", 3303ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 3304ecd94f1bSKan Liang "UMask": "0x1", 3305ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS.SNOOP_NONE", 3306ecd94f1bSKan Liang "Deprecated": "1", 3307ecd94f1bSKan Liang "MSRValue": "0x00BC000490", 3308ecd94f1bSKan Liang "Counter": "0,1,2,3", 3309ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=ALL_PF_DATA_RD:response=L3_MISS.SNOOP_NONE", 3310ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 3311ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3312ecd94f1bSKan Liang "SampleAfterValue": "100003", 3313ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 3314ecd94f1bSKan Liang }, 3315ecd94f1bSKan Liang { 3316ecd94f1bSKan Liang "Offcore": "1", 3317ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 3318ecd94f1bSKan Liang "UMask": "0x1", 3319ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS.NO_SNOOP_NEEDED", 3320ecd94f1bSKan Liang "Deprecated": "1", 3321ecd94f1bSKan Liang "MSRValue": "0x013C000490", 3322ecd94f1bSKan Liang "Counter": "0,1,2,3", 3323ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=ALL_PF_DATA_RD:response=L3_MISS.NO_SNOOP_NEEDED", 3324ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 3325ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3326ecd94f1bSKan Liang "SampleAfterValue": "100003", 3327ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 3328ecd94f1bSKan Liang }, 3329ecd94f1bSKan Liang { 3330ecd94f1bSKan Liang "Offcore": "1", 3331ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 3332ecd94f1bSKan Liang "UMask": "0x1", 3333ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS.SNOOP_MISS", 3334ecd94f1bSKan Liang "Deprecated": "1", 3335ecd94f1bSKan Liang "MSRValue": "0x023C000490", 3336ecd94f1bSKan Liang "Counter": "0,1,2,3", 3337ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=ALL_PF_DATA_RD:response=L3_MISS.SNOOP_MISS", 3338ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 3339ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3340ecd94f1bSKan Liang "SampleAfterValue": "100003", 3341ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 3342ecd94f1bSKan Liang }, 3343ecd94f1bSKan Liang { 3344ecd94f1bSKan Liang "Offcore": "1", 3345ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 3346ecd94f1bSKan Liang "UMask": "0x1", 3347ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS.HIT_OTHER_CORE_NO_FWD", 3348ecd94f1bSKan Liang "Deprecated": "1", 3349ecd94f1bSKan Liang "MSRValue": "0x043C000490", 3350ecd94f1bSKan Liang "Counter": "0,1,2,3", 3351ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=ALL_PF_DATA_RD:response=L3_MISS.HIT_OTHER_CORE_NO_FWD", 3352ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 3353ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3354ecd94f1bSKan Liang "SampleAfterValue": "100003", 3355ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 3356ecd94f1bSKan Liang }, 3357ecd94f1bSKan Liang { 3358ecd94f1bSKan Liang "Offcore": "1", 3359ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 3360ecd94f1bSKan Liang "UMask": "0x1", 3361ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS.HIT_OTHER_CORE_FWD", 3362ecd94f1bSKan Liang "Deprecated": "1", 3363ecd94f1bSKan Liang "MSRValue": "0x083C000490", 3364ecd94f1bSKan Liang "Counter": "0,1,2,3", 3365ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=ALL_PF_DATA_RD:response=L3_MISS.HIT_OTHER_CORE_FWD", 3366ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 3367ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3368ecd94f1bSKan Liang "SampleAfterValue": "100003", 3369ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 3370ecd94f1bSKan Liang }, 3371ecd94f1bSKan Liang { 3372ecd94f1bSKan Liang "Offcore": "1", 3373ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 3374ecd94f1bSKan Liang "UMask": "0x1", 3375ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS.HITM_OTHER_CORE", 3376ecd94f1bSKan Liang "Deprecated": "1", 3377ecd94f1bSKan Liang "MSRValue": "0x103C000490", 3378ecd94f1bSKan Liang "Counter": "0,1,2,3", 3379ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=ALL_PF_DATA_RD:response=L3_MISS.HITM_OTHER_CORE", 3380ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 3381ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3382ecd94f1bSKan Liang "SampleAfterValue": "100003", 3383ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 3384ecd94f1bSKan Liang }, 3385ecd94f1bSKan Liang { 3386ecd94f1bSKan Liang "Offcore": "1", 3387ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 3388ecd94f1bSKan Liang "UMask": "0x1", 3389ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS.ANY_SNOOP", 3390ecd94f1bSKan Liang "Deprecated": "1", 3391ecd94f1bSKan Liang "MSRValue": "0x3FBC000490", 3392ecd94f1bSKan Liang "Counter": "0,1,2,3", 3393ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=ALL_PF_DATA_RD:response=L3_MISS.ANY_SNOOP", 3394ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 3395ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3396ecd94f1bSKan Liang "SampleAfterValue": "100003", 3397ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 3398ecd94f1bSKan Liang }, 3399ecd94f1bSKan Liang { 3400ecd94f1bSKan Liang "Offcore": "1", 3401ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 3402ecd94f1bSKan Liang "UMask": "0x1", 3403ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NONE", 3404ecd94f1bSKan Liang "Deprecated": "1", 3405ecd94f1bSKan Liang "MSRValue": "0x0084000120", 3406ecd94f1bSKan Liang "Counter": "0,1,2,3", 3407ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=ALL_PF_RFO:response=L3_MISS_LOCAL_DRAM.SNOOP_NONE", 3408ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 3409ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3410ecd94f1bSKan Liang "SampleAfterValue": "100003", 3411ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 3412ecd94f1bSKan Liang }, 3413ecd94f1bSKan Liang { 3414ecd94f1bSKan Liang "Offcore": "1", 3415ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 3416ecd94f1bSKan Liang "UMask": "0x1", 3417ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED", 3418ecd94f1bSKan Liang "Deprecated": "1", 3419ecd94f1bSKan Liang "MSRValue": "0x0104000120", 3420ecd94f1bSKan Liang "Counter": "0,1,2,3", 3421ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=ALL_PF_RFO:response=L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED", 3422ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 3423ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3424ecd94f1bSKan Liang "SampleAfterValue": "100003", 3425ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 3426ecd94f1bSKan Liang }, 3427ecd94f1bSKan Liang { 3428ecd94f1bSKan Liang "Offcore": "1", 3429ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 3430ecd94f1bSKan Liang "UMask": "0x1", 3431ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS", 3432ecd94f1bSKan Liang "Deprecated": "1", 3433ecd94f1bSKan Liang "MSRValue": "0x0204000120", 3434ecd94f1bSKan Liang "Counter": "0,1,2,3", 3435ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=ALL_PF_RFO:response=L3_MISS_LOCAL_DRAM.SNOOP_MISS", 3436ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 3437ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3438ecd94f1bSKan Liang "SampleAfterValue": "100003", 3439ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 3440ecd94f1bSKan Liang }, 3441ecd94f1bSKan Liang { 3442ecd94f1bSKan Liang "Offcore": "1", 3443ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 3444ecd94f1bSKan Liang "UMask": "0x1", 3445ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD", 3446ecd94f1bSKan Liang "Deprecated": "1", 3447ecd94f1bSKan Liang "MSRValue": "0x0404000120", 3448ecd94f1bSKan Liang "Counter": "0,1,2,3", 3449ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=ALL_PF_RFO:response=L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD", 3450ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 3451ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3452ecd94f1bSKan Liang "SampleAfterValue": "100003", 3453ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 3454ecd94f1bSKan Liang }, 3455ecd94f1bSKan Liang { 3456ecd94f1bSKan Liang "Offcore": "1", 3457ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 3458ecd94f1bSKan Liang "UMask": "0x1", 3459ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD", 3460ecd94f1bSKan Liang "Deprecated": "1", 3461ecd94f1bSKan Liang "MSRValue": "0x0804000120", 3462ecd94f1bSKan Liang "Counter": "0,1,2,3", 3463ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=ALL_PF_RFO:response=L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD", 3464ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 3465ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3466ecd94f1bSKan Liang "SampleAfterValue": "100003", 3467ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 3468ecd94f1bSKan Liang }, 3469ecd94f1bSKan Liang { 3470ecd94f1bSKan Liang "Offcore": "1", 3471ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 3472ecd94f1bSKan Liang "UMask": "0x1", 3473ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE", 3474ecd94f1bSKan Liang "Deprecated": "1", 3475ecd94f1bSKan Liang "MSRValue": "0x1004000120", 3476ecd94f1bSKan Liang "Counter": "0,1,2,3", 3477ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=ALL_PF_RFO:response=L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE", 3478ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 3479ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3480ecd94f1bSKan Liang "SampleAfterValue": "100003", 3481ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 3482ecd94f1bSKan Liang }, 3483ecd94f1bSKan Liang { 3484ecd94f1bSKan Liang "Offcore": "1", 3485ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 3486ecd94f1bSKan Liang "UMask": "0x1", 3487ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.ANY_SNOOP", 3488ecd94f1bSKan Liang "Deprecated": "1", 3489ecd94f1bSKan Liang "MSRValue": "0x3F84000120", 3490ecd94f1bSKan Liang "Counter": "0,1,2,3", 3491ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=ALL_PF_RFO:response=L3_MISS_LOCAL_DRAM.ANY_SNOOP", 3492ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 3493ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3494ecd94f1bSKan Liang "SampleAfterValue": "100003", 3495ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 3496ecd94f1bSKan Liang }, 3497ecd94f1bSKan Liang { 3498ecd94f1bSKan Liang "Offcore": "1", 3499ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 3500ecd94f1bSKan Liang "UMask": "0x1", 3501ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE", 3502ecd94f1bSKan Liang "Deprecated": "1", 3503ecd94f1bSKan Liang "MSRValue": "0x0090000120", 3504ecd94f1bSKan Liang "Counter": "0,1,2,3", 3505ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=ALL_PF_RFO:response=L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE", 3506ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 3507ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3508ecd94f1bSKan Liang "SampleAfterValue": "100003", 3509ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 3510ecd94f1bSKan Liang }, 3511ecd94f1bSKan Liang { 3512ecd94f1bSKan Liang "Offcore": "1", 3513ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 3514ecd94f1bSKan Liang "UMask": "0x1", 3515ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED", 3516ecd94f1bSKan Liang "Deprecated": "1", 3517ecd94f1bSKan Liang "MSRValue": "0x0110000120", 3518ecd94f1bSKan Liang "Counter": "0,1,2,3", 3519ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=ALL_PF_RFO:response=L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED", 3520ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 3521ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3522ecd94f1bSKan Liang "SampleAfterValue": "100003", 3523ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 3524ecd94f1bSKan Liang }, 3525ecd94f1bSKan Liang { 3526ecd94f1bSKan Liang "Offcore": "1", 3527ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 3528ecd94f1bSKan Liang "UMask": "0x1", 3529ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS", 3530ecd94f1bSKan Liang "Deprecated": "1", 3531ecd94f1bSKan Liang "MSRValue": "0x0210000120", 3532ecd94f1bSKan Liang "Counter": "0,1,2,3", 3533ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=ALL_PF_RFO:response=L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS", 3534ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 3535ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3536ecd94f1bSKan Liang "SampleAfterValue": "100003", 3537ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 3538ecd94f1bSKan Liang }, 3539ecd94f1bSKan Liang { 3540ecd94f1bSKan Liang "Offcore": "1", 3541ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 3542ecd94f1bSKan Liang "UMask": "0x1", 3543ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD", 3544ecd94f1bSKan Liang "Deprecated": "1", 3545ecd94f1bSKan Liang "MSRValue": "0x0410000120", 3546ecd94f1bSKan Liang "Counter": "0,1,2,3", 3547ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=ALL_PF_RFO:response=L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD", 3548ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 3549ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3550ecd94f1bSKan Liang "SampleAfterValue": "100003", 3551ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 3552ecd94f1bSKan Liang }, 3553ecd94f1bSKan Liang { 3554ecd94f1bSKan Liang "Offcore": "1", 3555ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 3556ecd94f1bSKan Liang "UMask": "0x1", 3557ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD", 3558ecd94f1bSKan Liang "Deprecated": "1", 3559ecd94f1bSKan Liang "MSRValue": "0x0810000120", 3560ecd94f1bSKan Liang "Counter": "0,1,2,3", 3561ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=ALL_PF_RFO:response=L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD", 3562ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 3563ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3564ecd94f1bSKan Liang "SampleAfterValue": "100003", 3565ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 3566ecd94f1bSKan Liang }, 3567ecd94f1bSKan Liang { 3568ecd94f1bSKan Liang "Offcore": "1", 3569ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 3570ecd94f1bSKan Liang "UMask": "0x1", 3571ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE", 3572ecd94f1bSKan Liang "Deprecated": "1", 3573ecd94f1bSKan Liang "MSRValue": "0x1010000120", 3574ecd94f1bSKan Liang "Counter": "0,1,2,3", 3575ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=ALL_PF_RFO:response=L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE", 3576ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 3577ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3578ecd94f1bSKan Liang "SampleAfterValue": "100003", 3579ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 3580ecd94f1bSKan Liang }, 3581ecd94f1bSKan Liang { 3582ecd94f1bSKan Liang "Offcore": "1", 3583ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 3584ecd94f1bSKan Liang "UMask": "0x1", 3585ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP", 3586ecd94f1bSKan Liang "Deprecated": "1", 3587ecd94f1bSKan Liang "MSRValue": "0x3F90000120", 3588ecd94f1bSKan Liang "Counter": "0,1,2,3", 3589ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=ALL_PF_RFO:response=L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP", 3590ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 3591ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3592ecd94f1bSKan Liang "SampleAfterValue": "100003", 3593ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 3594ecd94f1bSKan Liang }, 3595ecd94f1bSKan Liang { 3596ecd94f1bSKan Liang "Offcore": "1", 3597ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 3598ecd94f1bSKan Liang "UMask": "0x1", 3599ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS.SNOOP_NONE", 3600ecd94f1bSKan Liang "Deprecated": "1", 3601ecd94f1bSKan Liang "MSRValue": "0x00BC000120", 3602ecd94f1bSKan Liang "Counter": "0,1,2,3", 3603ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=ALL_PF_RFO:response=L3_MISS.SNOOP_NONE", 3604ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 3605ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3606ecd94f1bSKan Liang "SampleAfterValue": "100003", 3607ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 3608ecd94f1bSKan Liang }, 3609ecd94f1bSKan Liang { 3610ecd94f1bSKan Liang "Offcore": "1", 3611ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 3612ecd94f1bSKan Liang "UMask": "0x1", 3613ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS.NO_SNOOP_NEEDED", 3614ecd94f1bSKan Liang "Deprecated": "1", 3615ecd94f1bSKan Liang "MSRValue": "0x013C000120", 3616ecd94f1bSKan Liang "Counter": "0,1,2,3", 3617ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=ALL_PF_RFO:response=L3_MISS.NO_SNOOP_NEEDED", 3618ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 3619ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3620ecd94f1bSKan Liang "SampleAfterValue": "100003", 3621ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 3622ecd94f1bSKan Liang }, 3623ecd94f1bSKan Liang { 3624ecd94f1bSKan Liang "Offcore": "1", 3625ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 3626ecd94f1bSKan Liang "UMask": "0x1", 3627ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS.SNOOP_MISS", 3628ecd94f1bSKan Liang "Deprecated": "1", 3629ecd94f1bSKan Liang "MSRValue": "0x023C000120", 3630ecd94f1bSKan Liang "Counter": "0,1,2,3", 3631ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=ALL_PF_RFO:response=L3_MISS.SNOOP_MISS", 3632ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 3633ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3634ecd94f1bSKan Liang "SampleAfterValue": "100003", 3635ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 3636ecd94f1bSKan Liang }, 3637ecd94f1bSKan Liang { 3638ecd94f1bSKan Liang "Offcore": "1", 3639ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 3640ecd94f1bSKan Liang "UMask": "0x1", 3641ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS.HIT_OTHER_CORE_NO_FWD", 3642ecd94f1bSKan Liang "Deprecated": "1", 3643ecd94f1bSKan Liang "MSRValue": "0x043C000120", 3644ecd94f1bSKan Liang "Counter": "0,1,2,3", 3645ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=ALL_PF_RFO:response=L3_MISS.HIT_OTHER_CORE_NO_FWD", 3646ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 3647ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3648ecd94f1bSKan Liang "SampleAfterValue": "100003", 3649ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 3650ecd94f1bSKan Liang }, 3651ecd94f1bSKan Liang { 3652ecd94f1bSKan Liang "Offcore": "1", 3653ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 3654ecd94f1bSKan Liang "UMask": "0x1", 3655ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS.HIT_OTHER_CORE_FWD", 3656ecd94f1bSKan Liang "Deprecated": "1", 3657ecd94f1bSKan Liang "MSRValue": "0x083C000120", 3658ecd94f1bSKan Liang "Counter": "0,1,2,3", 3659ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=ALL_PF_RFO:response=L3_MISS.HIT_OTHER_CORE_FWD", 3660ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 3661ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3662ecd94f1bSKan Liang "SampleAfterValue": "100003", 3663ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 3664ecd94f1bSKan Liang }, 3665ecd94f1bSKan Liang { 3666ecd94f1bSKan Liang "Offcore": "1", 3667ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 3668ecd94f1bSKan Liang "UMask": "0x1", 3669ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS.HITM_OTHER_CORE", 3670ecd94f1bSKan Liang "Deprecated": "1", 3671ecd94f1bSKan Liang "MSRValue": "0x103C000120", 3672ecd94f1bSKan Liang "Counter": "0,1,2,3", 3673ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=ALL_PF_RFO:response=L3_MISS.HITM_OTHER_CORE", 3674ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 3675ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3676ecd94f1bSKan Liang "SampleAfterValue": "100003", 3677ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 3678ecd94f1bSKan Liang }, 3679ecd94f1bSKan Liang { 3680ecd94f1bSKan Liang "Offcore": "1", 3681ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 3682ecd94f1bSKan Liang "UMask": "0x1", 3683ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS.ANY_SNOOP", 3684ecd94f1bSKan Liang "Deprecated": "1", 3685ecd94f1bSKan Liang "MSRValue": "0x3FBC000120", 3686ecd94f1bSKan Liang "Counter": "0,1,2,3", 3687ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=ALL_PF_RFO:response=L3_MISS.ANY_SNOOP", 3688ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 3689ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3690ecd94f1bSKan Liang "SampleAfterValue": "100003", 3691ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 3692ecd94f1bSKan Liang }, 3693ecd94f1bSKan Liang { 3694ecd94f1bSKan Liang "Offcore": "1", 3695ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 3696ecd94f1bSKan Liang "UMask": "0x1", 3697ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NONE", 3698ecd94f1bSKan Liang "Deprecated": "1", 3699ecd94f1bSKan Liang "MSRValue": "0x0084000491", 3700ecd94f1bSKan Liang "Counter": "0,1,2,3", 3701ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=ALL_DATA_RD:response=L3_MISS_LOCAL_DRAM.SNOOP_NONE", 3702ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 3703ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3704ecd94f1bSKan Liang "SampleAfterValue": "100003", 3705ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 3706ecd94f1bSKan Liang }, 3707ecd94f1bSKan Liang { 3708ecd94f1bSKan Liang "Offcore": "1", 3709ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 3710ecd94f1bSKan Liang "UMask": "0x1", 3711ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED", 3712ecd94f1bSKan Liang "Deprecated": "1", 3713ecd94f1bSKan Liang "MSRValue": "0x0104000491", 3714ecd94f1bSKan Liang "Counter": "0,1,2,3", 3715ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=ALL_DATA_RD:response=L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED", 3716ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 3717ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3718ecd94f1bSKan Liang "SampleAfterValue": "100003", 3719ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 3720ecd94f1bSKan Liang }, 3721ecd94f1bSKan Liang { 3722ecd94f1bSKan Liang "Offcore": "1", 3723ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 3724ecd94f1bSKan Liang "UMask": "0x1", 3725ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS", 3726ecd94f1bSKan Liang "Deprecated": "1", 3727ecd94f1bSKan Liang "MSRValue": "0x0204000491", 3728ecd94f1bSKan Liang "Counter": "0,1,2,3", 3729ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=ALL_DATA_RD:response=L3_MISS_LOCAL_DRAM.SNOOP_MISS", 3730ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 3731ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3732ecd94f1bSKan Liang "SampleAfterValue": "100003", 3733ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 3734ecd94f1bSKan Liang }, 3735ecd94f1bSKan Liang { 3736ecd94f1bSKan Liang "Offcore": "1", 3737ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 3738ecd94f1bSKan Liang "UMask": "0x1", 3739ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD", 3740ecd94f1bSKan Liang "Deprecated": "1", 3741ecd94f1bSKan Liang "MSRValue": "0x0404000491", 3742ecd94f1bSKan Liang "Counter": "0,1,2,3", 3743ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=ALL_DATA_RD:response=L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD", 3744ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 3745ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3746ecd94f1bSKan Liang "SampleAfterValue": "100003", 3747ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 3748ecd94f1bSKan Liang }, 3749ecd94f1bSKan Liang { 3750ecd94f1bSKan Liang "Offcore": "1", 3751ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 3752ecd94f1bSKan Liang "UMask": "0x1", 3753ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD", 3754ecd94f1bSKan Liang "Deprecated": "1", 3755ecd94f1bSKan Liang "MSRValue": "0x0804000491", 3756ecd94f1bSKan Liang "Counter": "0,1,2,3", 3757ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=ALL_DATA_RD:response=L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD", 3758ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 3759ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3760ecd94f1bSKan Liang "SampleAfterValue": "100003", 3761ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 3762ecd94f1bSKan Liang }, 3763ecd94f1bSKan Liang { 3764ecd94f1bSKan Liang "Offcore": "1", 3765ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 3766ecd94f1bSKan Liang "UMask": "0x1", 3767ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE", 3768ecd94f1bSKan Liang "Deprecated": "1", 3769ecd94f1bSKan Liang "MSRValue": "0x1004000491", 3770ecd94f1bSKan Liang "Counter": "0,1,2,3", 3771ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=ALL_DATA_RD:response=L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE", 3772ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 3773ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3774ecd94f1bSKan Liang "SampleAfterValue": "100003", 3775ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 3776ecd94f1bSKan Liang }, 3777ecd94f1bSKan Liang { 3778ecd94f1bSKan Liang "Offcore": "1", 3779ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 3780ecd94f1bSKan Liang "UMask": "0x1", 3781ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP", 3782ecd94f1bSKan Liang "Deprecated": "1", 3783ecd94f1bSKan Liang "MSRValue": "0x3F84000491", 3784ecd94f1bSKan Liang "Counter": "0,1,2,3", 3785ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=ALL_DATA_RD:response=L3_MISS_LOCAL_DRAM.ANY_SNOOP", 3786ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 3787ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3788ecd94f1bSKan Liang "SampleAfterValue": "100003", 3789ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 3790ecd94f1bSKan Liang }, 3791ecd94f1bSKan Liang { 3792ecd94f1bSKan Liang "Offcore": "1", 3793ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 3794ecd94f1bSKan Liang "UMask": "0x1", 3795ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE", 3796ecd94f1bSKan Liang "Deprecated": "1", 3797ecd94f1bSKan Liang "MSRValue": "0x0090000491", 3798ecd94f1bSKan Liang "Counter": "0,1,2,3", 3799ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=ALL_DATA_RD:response=L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE", 3800ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 3801ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3802ecd94f1bSKan Liang "SampleAfterValue": "100003", 3803ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 3804ecd94f1bSKan Liang }, 3805ecd94f1bSKan Liang { 3806ecd94f1bSKan Liang "Offcore": "1", 3807ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 3808ecd94f1bSKan Liang "UMask": "0x1", 3809ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED", 3810ecd94f1bSKan Liang "Deprecated": "1", 3811ecd94f1bSKan Liang "MSRValue": "0x0110000491", 3812ecd94f1bSKan Liang "Counter": "0,1,2,3", 3813ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=ALL_DATA_RD:response=L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED", 3814ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 3815ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3816ecd94f1bSKan Liang "SampleAfterValue": "100003", 3817ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 3818ecd94f1bSKan Liang }, 3819ecd94f1bSKan Liang { 3820ecd94f1bSKan Liang "Offcore": "1", 3821ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 3822ecd94f1bSKan Liang "UMask": "0x1", 3823ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS", 3824ecd94f1bSKan Liang "Deprecated": "1", 3825ecd94f1bSKan Liang "MSRValue": "0x0210000491", 3826ecd94f1bSKan Liang "Counter": "0,1,2,3", 3827ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=ALL_DATA_RD:response=L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS", 3828ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 3829ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3830ecd94f1bSKan Liang "SampleAfterValue": "100003", 3831ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 3832ecd94f1bSKan Liang }, 3833ecd94f1bSKan Liang { 3834ecd94f1bSKan Liang "Offcore": "1", 3835ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 3836ecd94f1bSKan Liang "UMask": "0x1", 3837ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD", 3838ecd94f1bSKan Liang "Deprecated": "1", 3839ecd94f1bSKan Liang "MSRValue": "0x0410000491", 3840ecd94f1bSKan Liang "Counter": "0,1,2,3", 3841ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=ALL_DATA_RD:response=L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD", 3842ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 3843ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3844ecd94f1bSKan Liang "SampleAfterValue": "100003", 3845ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 3846ecd94f1bSKan Liang }, 3847ecd94f1bSKan Liang { 3848ecd94f1bSKan Liang "Offcore": "1", 3849ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 3850ecd94f1bSKan Liang "UMask": "0x1", 3851ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD", 3852ecd94f1bSKan Liang "Deprecated": "1", 3853ecd94f1bSKan Liang "MSRValue": "0x0810000491", 3854ecd94f1bSKan Liang "Counter": "0,1,2,3", 3855ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=ALL_DATA_RD:response=L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD", 3856ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 3857ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3858ecd94f1bSKan Liang "SampleAfterValue": "100003", 3859ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 3860ecd94f1bSKan Liang }, 3861ecd94f1bSKan Liang { 3862ecd94f1bSKan Liang "Offcore": "1", 3863ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 3864ecd94f1bSKan Liang "UMask": "0x1", 3865ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE", 3866ecd94f1bSKan Liang "Deprecated": "1", 3867ecd94f1bSKan Liang "MSRValue": "0x1010000491", 3868ecd94f1bSKan Liang "Counter": "0,1,2,3", 3869ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=ALL_DATA_RD:response=L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE", 3870ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 3871ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3872ecd94f1bSKan Liang "SampleAfterValue": "100003", 3873ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 3874ecd94f1bSKan Liang }, 3875ecd94f1bSKan Liang { 3876ecd94f1bSKan Liang "Offcore": "1", 3877ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 3878ecd94f1bSKan Liang "UMask": "0x1", 3879ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP", 3880ecd94f1bSKan Liang "Deprecated": "1", 3881ecd94f1bSKan Liang "MSRValue": "0x3F90000491", 3882ecd94f1bSKan Liang "Counter": "0,1,2,3", 3883ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=ALL_DATA_RD:response=L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP", 3884ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 3885ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3886ecd94f1bSKan Liang "SampleAfterValue": "100003", 3887ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 3888ecd94f1bSKan Liang }, 3889ecd94f1bSKan Liang { 3890ecd94f1bSKan Liang "Offcore": "1", 3891ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 3892ecd94f1bSKan Liang "UMask": "0x1", 3893ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS.SNOOP_NONE", 3894ecd94f1bSKan Liang "Deprecated": "1", 3895ecd94f1bSKan Liang "MSRValue": "0x00BC000491", 3896ecd94f1bSKan Liang "Counter": "0,1,2,3", 3897ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=ALL_DATA_RD:response=L3_MISS.SNOOP_NONE", 3898ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 3899ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3900ecd94f1bSKan Liang "SampleAfterValue": "100003", 3901ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 3902ecd94f1bSKan Liang }, 3903ecd94f1bSKan Liang { 3904ecd94f1bSKan Liang "Offcore": "1", 3905ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 3906ecd94f1bSKan Liang "UMask": "0x1", 3907ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS.NO_SNOOP_NEEDED", 3908ecd94f1bSKan Liang "Deprecated": "1", 3909ecd94f1bSKan Liang "MSRValue": "0x013C000491", 3910ecd94f1bSKan Liang "Counter": "0,1,2,3", 3911ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=ALL_DATA_RD:response=L3_MISS.NO_SNOOP_NEEDED", 3912ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 3913ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3914ecd94f1bSKan Liang "SampleAfterValue": "100003", 3915ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 3916ecd94f1bSKan Liang }, 3917ecd94f1bSKan Liang { 3918ecd94f1bSKan Liang "Offcore": "1", 3919ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 3920ecd94f1bSKan Liang "UMask": "0x1", 3921ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS.SNOOP_MISS", 3922ecd94f1bSKan Liang "Deprecated": "1", 3923ecd94f1bSKan Liang "MSRValue": "0x023C000491", 3924ecd94f1bSKan Liang "Counter": "0,1,2,3", 3925ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=ALL_DATA_RD:response=L3_MISS.SNOOP_MISS", 3926ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 3927ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3928ecd94f1bSKan Liang "SampleAfterValue": "100003", 3929ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 3930ecd94f1bSKan Liang }, 3931ecd94f1bSKan Liang { 3932ecd94f1bSKan Liang "Offcore": "1", 3933ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 3934ecd94f1bSKan Liang "UMask": "0x1", 3935ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS.HIT_OTHER_CORE_NO_FWD", 3936ecd94f1bSKan Liang "Deprecated": "1", 3937ecd94f1bSKan Liang "MSRValue": "0x043C000491", 3938ecd94f1bSKan Liang "Counter": "0,1,2,3", 3939ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=ALL_DATA_RD:response=L3_MISS.HIT_OTHER_CORE_NO_FWD", 3940ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 3941ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3942ecd94f1bSKan Liang "SampleAfterValue": "100003", 3943ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 3944ecd94f1bSKan Liang }, 3945ecd94f1bSKan Liang { 3946ecd94f1bSKan Liang "Offcore": "1", 3947ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 3948ecd94f1bSKan Liang "UMask": "0x1", 3949ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS.HIT_OTHER_CORE_FWD", 3950ecd94f1bSKan Liang "Deprecated": "1", 3951ecd94f1bSKan Liang "MSRValue": "0x083C000491", 3952ecd94f1bSKan Liang "Counter": "0,1,2,3", 3953ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=ALL_DATA_RD:response=L3_MISS.HIT_OTHER_CORE_FWD", 3954ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 3955ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3956ecd94f1bSKan Liang "SampleAfterValue": "100003", 3957ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 3958ecd94f1bSKan Liang }, 3959ecd94f1bSKan Liang { 3960ecd94f1bSKan Liang "Offcore": "1", 3961ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 3962ecd94f1bSKan Liang "UMask": "0x1", 3963ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS.HITM_OTHER_CORE", 3964ecd94f1bSKan Liang "Deprecated": "1", 3965ecd94f1bSKan Liang "MSRValue": "0x103C000491", 3966ecd94f1bSKan Liang "Counter": "0,1,2,3", 3967ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=ALL_DATA_RD:response=L3_MISS.HITM_OTHER_CORE", 3968ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 3969ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3970ecd94f1bSKan Liang "SampleAfterValue": "100003", 3971ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 3972ecd94f1bSKan Liang }, 3973ecd94f1bSKan Liang { 3974ecd94f1bSKan Liang "Offcore": "1", 3975ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 3976ecd94f1bSKan Liang "UMask": "0x1", 3977ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS.ANY_SNOOP", 3978ecd94f1bSKan Liang "Deprecated": "1", 3979ecd94f1bSKan Liang "MSRValue": "0x3FBC000491", 3980ecd94f1bSKan Liang "Counter": "0,1,2,3", 3981ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=ALL_DATA_RD:response=L3_MISS.ANY_SNOOP", 3982ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 3983ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3984ecd94f1bSKan Liang "SampleAfterValue": "100003", 3985ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 3986ecd94f1bSKan Liang }, 3987ecd94f1bSKan Liang { 3988ecd94f1bSKan Liang "Offcore": "1", 3989ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 3990ecd94f1bSKan Liang "UMask": "0x1", 3991ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NONE", 3992ecd94f1bSKan Liang "Deprecated": "1", 3993ecd94f1bSKan Liang "MSRValue": "0x0084000122", 3994ecd94f1bSKan Liang "Counter": "0,1,2,3", 3995ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=ALL_RFO:response=L3_MISS_LOCAL_DRAM.SNOOP_NONE", 3996ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 3997ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3998ecd94f1bSKan Liang "SampleAfterValue": "100003", 3999ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 4000ecd94f1bSKan Liang }, 4001ecd94f1bSKan Liang { 4002ecd94f1bSKan Liang "Offcore": "1", 4003ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 4004ecd94f1bSKan Liang "UMask": "0x1", 4005ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED", 4006ecd94f1bSKan Liang "Deprecated": "1", 4007ecd94f1bSKan Liang "MSRValue": "0x0104000122", 4008ecd94f1bSKan Liang "Counter": "0,1,2,3", 4009ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=ALL_RFO:response=L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED", 4010ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 4011ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4012ecd94f1bSKan Liang "SampleAfterValue": "100003", 4013ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 4014ecd94f1bSKan Liang }, 4015ecd94f1bSKan Liang { 4016ecd94f1bSKan Liang "Offcore": "1", 4017ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 4018ecd94f1bSKan Liang "UMask": "0x1", 4019ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS", 4020ecd94f1bSKan Liang "Deprecated": "1", 4021ecd94f1bSKan Liang "MSRValue": "0x0204000122", 4022ecd94f1bSKan Liang "Counter": "0,1,2,3", 4023ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=ALL_RFO:response=L3_MISS_LOCAL_DRAM.SNOOP_MISS", 4024ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 4025ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4026ecd94f1bSKan Liang "SampleAfterValue": "100003", 4027ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 4028ecd94f1bSKan Liang }, 4029ecd94f1bSKan Liang { 4030ecd94f1bSKan Liang "Offcore": "1", 4031ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 4032ecd94f1bSKan Liang "UMask": "0x1", 4033ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD", 4034ecd94f1bSKan Liang "Deprecated": "1", 4035ecd94f1bSKan Liang "MSRValue": "0x0404000122", 4036ecd94f1bSKan Liang "Counter": "0,1,2,3", 4037ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=ALL_RFO:response=L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD", 4038ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 4039ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4040ecd94f1bSKan Liang "SampleAfterValue": "100003", 4041ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 4042ecd94f1bSKan Liang }, 4043ecd94f1bSKan Liang { 4044ecd94f1bSKan Liang "Offcore": "1", 4045ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 4046ecd94f1bSKan Liang "UMask": "0x1", 4047ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD", 4048ecd94f1bSKan Liang "Deprecated": "1", 4049ecd94f1bSKan Liang "MSRValue": "0x0804000122", 4050ecd94f1bSKan Liang "Counter": "0,1,2,3", 4051ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=ALL_RFO:response=L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD", 4052ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 4053ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4054ecd94f1bSKan Liang "SampleAfterValue": "100003", 4055ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 4056ecd94f1bSKan Liang }, 4057ecd94f1bSKan Liang { 4058ecd94f1bSKan Liang "Offcore": "1", 4059ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 4060ecd94f1bSKan Liang "UMask": "0x1", 4061ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE", 4062ecd94f1bSKan Liang "Deprecated": "1", 4063ecd94f1bSKan Liang "MSRValue": "0x1004000122", 4064ecd94f1bSKan Liang "Counter": "0,1,2,3", 4065ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=ALL_RFO:response=L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE", 4066ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 4067ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4068ecd94f1bSKan Liang "SampleAfterValue": "100003", 4069ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 4070ecd94f1bSKan Liang }, 4071ecd94f1bSKan Liang { 4072ecd94f1bSKan Liang "Offcore": "1", 4073ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 4074ecd94f1bSKan Liang "UMask": "0x1", 4075ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.ANY_SNOOP", 4076ecd94f1bSKan Liang "Deprecated": "1", 4077ecd94f1bSKan Liang "MSRValue": "0x3F84000122", 4078ecd94f1bSKan Liang "Counter": "0,1,2,3", 4079ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=ALL_RFO:response=L3_MISS_LOCAL_DRAM.ANY_SNOOP", 4080ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 4081ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4082ecd94f1bSKan Liang "SampleAfterValue": "100003", 4083ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 4084ecd94f1bSKan Liang }, 4085ecd94f1bSKan Liang { 4086ecd94f1bSKan Liang "Offcore": "1", 4087ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 4088ecd94f1bSKan Liang "UMask": "0x1", 4089ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE", 4090ecd94f1bSKan Liang "Deprecated": "1", 4091ecd94f1bSKan Liang "MSRValue": "0x0090000122", 4092ecd94f1bSKan Liang "Counter": "0,1,2,3", 4093ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=ALL_RFO:response=L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE", 4094ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 4095ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4096ecd94f1bSKan Liang "SampleAfterValue": "100003", 4097ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 4098ecd94f1bSKan Liang }, 4099ecd94f1bSKan Liang { 4100ecd94f1bSKan Liang "Offcore": "1", 4101ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 4102ecd94f1bSKan Liang "UMask": "0x1", 4103ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED", 4104ecd94f1bSKan Liang "Deprecated": "1", 4105ecd94f1bSKan Liang "MSRValue": "0x0110000122", 4106ecd94f1bSKan Liang "Counter": "0,1,2,3", 4107ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=ALL_RFO:response=L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED", 4108ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 4109ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4110ecd94f1bSKan Liang "SampleAfterValue": "100003", 4111ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 4112ecd94f1bSKan Liang }, 4113ecd94f1bSKan Liang { 4114ecd94f1bSKan Liang "Offcore": "1", 4115ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 4116ecd94f1bSKan Liang "UMask": "0x1", 4117ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS", 4118ecd94f1bSKan Liang "Deprecated": "1", 4119ecd94f1bSKan Liang "MSRValue": "0x0210000122", 4120ecd94f1bSKan Liang "Counter": "0,1,2,3", 4121ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=ALL_RFO:response=L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS", 4122ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 4123ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4124ecd94f1bSKan Liang "SampleAfterValue": "100003", 4125ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 4126ecd94f1bSKan Liang }, 4127ecd94f1bSKan Liang { 4128ecd94f1bSKan Liang "Offcore": "1", 4129ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 4130ecd94f1bSKan Liang "UMask": "0x1", 4131ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD", 4132ecd94f1bSKan Liang "Deprecated": "1", 4133ecd94f1bSKan Liang "MSRValue": "0x0410000122", 4134ecd94f1bSKan Liang "Counter": "0,1,2,3", 4135ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=ALL_RFO:response=L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD", 4136ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 4137ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4138ecd94f1bSKan Liang "SampleAfterValue": "100003", 4139ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 4140ecd94f1bSKan Liang }, 4141ecd94f1bSKan Liang { 4142ecd94f1bSKan Liang "Offcore": "1", 4143ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 4144ecd94f1bSKan Liang "UMask": "0x1", 4145ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD", 4146ecd94f1bSKan Liang "Deprecated": "1", 4147ecd94f1bSKan Liang "MSRValue": "0x0810000122", 4148ecd94f1bSKan Liang "Counter": "0,1,2,3", 4149ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=ALL_RFO:response=L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD", 4150ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 4151ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4152ecd94f1bSKan Liang "SampleAfterValue": "100003", 4153ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 4154ecd94f1bSKan Liang }, 4155ecd94f1bSKan Liang { 4156ecd94f1bSKan Liang "Offcore": "1", 4157ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 4158ecd94f1bSKan Liang "UMask": "0x1", 4159ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE", 4160ecd94f1bSKan Liang "Deprecated": "1", 4161ecd94f1bSKan Liang "MSRValue": "0x1010000122", 4162ecd94f1bSKan Liang "Counter": "0,1,2,3", 4163ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=ALL_RFO:response=L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE", 4164ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 4165ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4166ecd94f1bSKan Liang "SampleAfterValue": "100003", 4167ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 4168ecd94f1bSKan Liang }, 4169ecd94f1bSKan Liang { 4170ecd94f1bSKan Liang "Offcore": "1", 4171ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 4172ecd94f1bSKan Liang "UMask": "0x1", 4173ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP", 4174ecd94f1bSKan Liang "Deprecated": "1", 4175ecd94f1bSKan Liang "MSRValue": "0x3F90000122", 4176ecd94f1bSKan Liang "Counter": "0,1,2,3", 4177ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=ALL_RFO:response=L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP", 4178ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 4179ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4180ecd94f1bSKan Liang "SampleAfterValue": "100003", 4181ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 4182ecd94f1bSKan Liang }, 4183ecd94f1bSKan Liang { 4184ecd94f1bSKan Liang "Offcore": "1", 4185ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 4186ecd94f1bSKan Liang "UMask": "0x1", 4187ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS.SNOOP_NONE", 4188ecd94f1bSKan Liang "Deprecated": "1", 4189ecd94f1bSKan Liang "MSRValue": "0x00BC000122", 4190ecd94f1bSKan Liang "Counter": "0,1,2,3", 4191ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=ALL_RFO:response=L3_MISS.SNOOP_NONE", 4192ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 4193ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4194ecd94f1bSKan Liang "SampleAfterValue": "100003", 4195ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 4196ecd94f1bSKan Liang }, 4197ecd94f1bSKan Liang { 4198ecd94f1bSKan Liang "Offcore": "1", 4199ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 4200ecd94f1bSKan Liang "UMask": "0x1", 4201ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS.NO_SNOOP_NEEDED", 4202ecd94f1bSKan Liang "Deprecated": "1", 4203ecd94f1bSKan Liang "MSRValue": "0x013C000122", 4204ecd94f1bSKan Liang "Counter": "0,1,2,3", 4205ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=ALL_RFO:response=L3_MISS.NO_SNOOP_NEEDED", 4206ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 4207ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4208ecd94f1bSKan Liang "SampleAfterValue": "100003", 4209ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 4210ecd94f1bSKan Liang }, 4211ecd94f1bSKan Liang { 4212ecd94f1bSKan Liang "Offcore": "1", 4213ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 4214ecd94f1bSKan Liang "UMask": "0x1", 4215ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS.SNOOP_MISS", 4216ecd94f1bSKan Liang "Deprecated": "1", 4217ecd94f1bSKan Liang "MSRValue": "0x023C000122", 4218ecd94f1bSKan Liang "Counter": "0,1,2,3", 4219ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=ALL_RFO:response=L3_MISS.SNOOP_MISS", 4220ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 4221ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4222ecd94f1bSKan Liang "SampleAfterValue": "100003", 4223ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 4224ecd94f1bSKan Liang }, 4225ecd94f1bSKan Liang { 4226ecd94f1bSKan Liang "Offcore": "1", 4227ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 4228ecd94f1bSKan Liang "UMask": "0x1", 4229ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS.HIT_OTHER_CORE_NO_FWD", 4230ecd94f1bSKan Liang "Deprecated": "1", 4231ecd94f1bSKan Liang "MSRValue": "0x043C000122", 4232ecd94f1bSKan Liang "Counter": "0,1,2,3", 4233ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=ALL_RFO:response=L3_MISS.HIT_OTHER_CORE_NO_FWD", 4234ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 4235ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4236ecd94f1bSKan Liang "SampleAfterValue": "100003", 4237ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 4238ecd94f1bSKan Liang }, 4239ecd94f1bSKan Liang { 4240ecd94f1bSKan Liang "Offcore": "1", 4241ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 4242ecd94f1bSKan Liang "UMask": "0x1", 4243ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS.HIT_OTHER_CORE_FWD", 4244ecd94f1bSKan Liang "Deprecated": "1", 4245ecd94f1bSKan Liang "MSRValue": "0x083C000122", 4246ecd94f1bSKan Liang "Counter": "0,1,2,3", 4247ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=ALL_RFO:response=L3_MISS.HIT_OTHER_CORE_FWD", 4248ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 4249ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4250ecd94f1bSKan Liang "SampleAfterValue": "100003", 4251ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 4252ecd94f1bSKan Liang }, 4253ecd94f1bSKan Liang { 4254ecd94f1bSKan Liang "Offcore": "1", 4255ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 4256ecd94f1bSKan Liang "UMask": "0x1", 4257ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS.HITM_OTHER_CORE", 4258ecd94f1bSKan Liang "Deprecated": "1", 4259ecd94f1bSKan Liang "MSRValue": "0x103C000122", 4260ecd94f1bSKan Liang "Counter": "0,1,2,3", 4261ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=ALL_RFO:response=L3_MISS.HITM_OTHER_CORE", 4262ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 4263ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4264ecd94f1bSKan Liang "SampleAfterValue": "100003", 4265ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 4266ecd94f1bSKan Liang }, 4267ecd94f1bSKan Liang { 4268ecd94f1bSKan Liang "Offcore": "1", 4269ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 4270ecd94f1bSKan Liang "UMask": "0x1", 4271ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS.ANY_SNOOP", 4272ecd94f1bSKan Liang "Deprecated": "1", 4273ecd94f1bSKan Liang "MSRValue": "0x3FBC000122", 4274ecd94f1bSKan Liang "Counter": "0,1,2,3", 4275ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=ALL_RFO:response=L3_MISS.ANY_SNOOP", 4276ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 4277ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4278ecd94f1bSKan Liang "SampleAfterValue": "100003", 4279ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 4280ecd94f1bSKan Liang }, 4281ecd94f1bSKan Liang { 4282ecd94f1bSKan Liang "Offcore": "1", 4283ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 4284ecd94f1bSKan Liang "UMask": "0x1", 4285ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS_LOCAL_DRAM.SNOOP_NONE", 4286ecd94f1bSKan Liang "Deprecated": "1", 4287ecd94f1bSKan Liang "MSRValue": "0x00840007F7", 4288ecd94f1bSKan Liang "Counter": "0,1,2,3", 4289ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=ALL_READS:response=L3_MISS_LOCAL_DRAM.SNOOP_NONE", 4290ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 4291ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4292ecd94f1bSKan Liang "SampleAfterValue": "100003", 4293ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 4294ecd94f1bSKan Liang }, 4295ecd94f1bSKan Liang { 4296ecd94f1bSKan Liang "Offcore": "1", 4297ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 4298ecd94f1bSKan Liang "UMask": "0x1", 4299ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED", 4300ecd94f1bSKan Liang "Deprecated": "1", 4301ecd94f1bSKan Liang "MSRValue": "0x01040007F7", 4302ecd94f1bSKan Liang "Counter": "0,1,2,3", 4303ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=ALL_READS:response=L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED", 4304ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 4305ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4306ecd94f1bSKan Liang "SampleAfterValue": "100003", 4307ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 4308ecd94f1bSKan Liang }, 4309ecd94f1bSKan Liang { 4310ecd94f1bSKan Liang "Offcore": "1", 4311ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 4312ecd94f1bSKan Liang "UMask": "0x1", 4313ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS_LOCAL_DRAM.SNOOP_MISS", 4314ecd94f1bSKan Liang "Deprecated": "1", 4315ecd94f1bSKan Liang "MSRValue": "0x02040007F7", 4316ecd94f1bSKan Liang "Counter": "0,1,2,3", 4317ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=ALL_READS:response=L3_MISS_LOCAL_DRAM.SNOOP_MISS", 4318ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 4319ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4320ecd94f1bSKan Liang "SampleAfterValue": "100003", 4321ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 4322ecd94f1bSKan Liang }, 4323ecd94f1bSKan Liang { 4324ecd94f1bSKan Liang "Offcore": "1", 4325ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 4326ecd94f1bSKan Liang "UMask": "0x1", 4327ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD", 4328ecd94f1bSKan Liang "Deprecated": "1", 4329ecd94f1bSKan Liang "MSRValue": "0x04040007F7", 4330ecd94f1bSKan Liang "Counter": "0,1,2,3", 4331ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=ALL_READS:response=L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD", 4332ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 4333ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4334ecd94f1bSKan Liang "SampleAfterValue": "100003", 4335ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 4336ecd94f1bSKan Liang }, 4337ecd94f1bSKan Liang { 4338ecd94f1bSKan Liang "Offcore": "1", 4339ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 4340ecd94f1bSKan Liang "UMask": "0x1", 4341ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD", 4342ecd94f1bSKan Liang "Deprecated": "1", 4343ecd94f1bSKan Liang "MSRValue": "0x08040007F7", 4344ecd94f1bSKan Liang "Counter": "0,1,2,3", 4345ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=ALL_READS:response=L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD", 4346ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 4347ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4348ecd94f1bSKan Liang "SampleAfterValue": "100003", 4349ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 4350ecd94f1bSKan Liang }, 4351ecd94f1bSKan Liang { 4352ecd94f1bSKan Liang "Offcore": "1", 4353ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 4354ecd94f1bSKan Liang "UMask": "0x1", 4355ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE", 4356ecd94f1bSKan Liang "Deprecated": "1", 4357ecd94f1bSKan Liang "MSRValue": "0x10040007F7", 4358ecd94f1bSKan Liang "Counter": "0,1,2,3", 4359ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=ALL_READS:response=L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE", 4360ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 4361ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4362ecd94f1bSKan Liang "SampleAfterValue": "100003", 4363ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 4364ecd94f1bSKan Liang }, 4365ecd94f1bSKan Liang { 4366ecd94f1bSKan Liang "Offcore": "1", 4367ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 4368ecd94f1bSKan Liang "UMask": "0x1", 4369ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS_LOCAL_DRAM.ANY_SNOOP", 4370ecd94f1bSKan Liang "Deprecated": "1", 4371ecd94f1bSKan Liang "MSRValue": "0x3F840007F7", 4372ecd94f1bSKan Liang "Counter": "0,1,2,3", 4373ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=ALL_READS:response=L3_MISS_LOCAL_DRAM.ANY_SNOOP", 4374ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 4375ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4376ecd94f1bSKan Liang "SampleAfterValue": "100003", 4377ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 4378ecd94f1bSKan Liang }, 4379ecd94f1bSKan Liang { 4380ecd94f1bSKan Liang "Offcore": "1", 4381ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 4382ecd94f1bSKan Liang "UMask": "0x1", 4383ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE", 4384ecd94f1bSKan Liang "Deprecated": "1", 4385ecd94f1bSKan Liang "MSRValue": "0x00900007F7", 4386ecd94f1bSKan Liang "Counter": "0,1,2,3", 4387ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=ALL_READS:response=L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE", 4388ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 4389ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4390ecd94f1bSKan Liang "SampleAfterValue": "100003", 4391ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 4392ecd94f1bSKan Liang }, 4393ecd94f1bSKan Liang { 4394ecd94f1bSKan Liang "Offcore": "1", 4395ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 4396ecd94f1bSKan Liang "UMask": "0x1", 4397ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED", 4398ecd94f1bSKan Liang "Deprecated": "1", 4399ecd94f1bSKan Liang "MSRValue": "0x01100007F7", 4400ecd94f1bSKan Liang "Counter": "0,1,2,3", 4401ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=ALL_READS:response=L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED", 4402ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 4403ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4404ecd94f1bSKan Liang "SampleAfterValue": "100003", 4405ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 4406ecd94f1bSKan Liang }, 4407ecd94f1bSKan Liang { 4408ecd94f1bSKan Liang "Offcore": "1", 4409ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 4410ecd94f1bSKan Liang "UMask": "0x1", 4411ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS", 4412ecd94f1bSKan Liang "Deprecated": "1", 4413ecd94f1bSKan Liang "MSRValue": "0x02100007F7", 4414ecd94f1bSKan Liang "Counter": "0,1,2,3", 4415ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=ALL_READS:response=L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS", 4416ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 4417ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4418ecd94f1bSKan Liang "SampleAfterValue": "100003", 4419ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 4420ecd94f1bSKan Liang }, 4421ecd94f1bSKan Liang { 4422ecd94f1bSKan Liang "Offcore": "1", 4423ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 4424ecd94f1bSKan Liang "UMask": "0x1", 4425ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD", 4426ecd94f1bSKan Liang "Deprecated": "1", 4427ecd94f1bSKan Liang "MSRValue": "0x04100007F7", 4428ecd94f1bSKan Liang "Counter": "0,1,2,3", 4429ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=ALL_READS:response=L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD", 4430ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 4431ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4432ecd94f1bSKan Liang "SampleAfterValue": "100003", 4433ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 4434ecd94f1bSKan Liang }, 4435ecd94f1bSKan Liang { 4436ecd94f1bSKan Liang "Offcore": "1", 4437ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 4438ecd94f1bSKan Liang "UMask": "0x1", 4439ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD", 4440ecd94f1bSKan Liang "Deprecated": "1", 4441ecd94f1bSKan Liang "MSRValue": "0x08100007F7", 4442ecd94f1bSKan Liang "Counter": "0,1,2,3", 4443ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=ALL_READS:response=L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD", 4444ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 4445ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4446ecd94f1bSKan Liang "SampleAfterValue": "100003", 4447ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 4448ecd94f1bSKan Liang }, 4449ecd94f1bSKan Liang { 4450ecd94f1bSKan Liang "Offcore": "1", 4451ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 4452ecd94f1bSKan Liang "UMask": "0x1", 4453ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE", 4454ecd94f1bSKan Liang "Deprecated": "1", 4455ecd94f1bSKan Liang "MSRValue": "0x10100007F7", 4456ecd94f1bSKan Liang "Counter": "0,1,2,3", 4457ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=ALL_READS:response=L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE", 4458ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 4459ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4460ecd94f1bSKan Liang "SampleAfterValue": "100003", 4461ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 4462ecd94f1bSKan Liang }, 4463ecd94f1bSKan Liang { 4464ecd94f1bSKan Liang "Offcore": "1", 4465ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 4466ecd94f1bSKan Liang "UMask": "0x1", 4467ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP", 4468ecd94f1bSKan Liang "Deprecated": "1", 4469ecd94f1bSKan Liang "MSRValue": "0x3F900007F7", 4470ecd94f1bSKan Liang "Counter": "0,1,2,3", 4471ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=ALL_READS:response=L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP", 4472ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 4473ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4474ecd94f1bSKan Liang "SampleAfterValue": "100003", 4475ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 4476ecd94f1bSKan Liang }, 4477ecd94f1bSKan Liang { 4478ecd94f1bSKan Liang "Offcore": "1", 4479ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 4480ecd94f1bSKan Liang "UMask": "0x1", 4481ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS.SNOOP_NONE", 4482ecd94f1bSKan Liang "Deprecated": "1", 4483ecd94f1bSKan Liang "MSRValue": "0x00BC0007F7", 4484ecd94f1bSKan Liang "Counter": "0,1,2,3", 4485ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=ALL_READS:response=L3_MISS.SNOOP_NONE", 4486ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 4487ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4488ecd94f1bSKan Liang "SampleAfterValue": "100003", 4489ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 4490ecd94f1bSKan Liang }, 4491ecd94f1bSKan Liang { 4492ecd94f1bSKan Liang "Offcore": "1", 4493ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 4494ecd94f1bSKan Liang "UMask": "0x1", 4495ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS.NO_SNOOP_NEEDED", 4496ecd94f1bSKan Liang "Deprecated": "1", 4497ecd94f1bSKan Liang "MSRValue": "0x013C0007F7", 4498ecd94f1bSKan Liang "Counter": "0,1,2,3", 4499ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=ALL_READS:response=L3_MISS.NO_SNOOP_NEEDED", 4500ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 4501ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4502ecd94f1bSKan Liang "SampleAfterValue": "100003", 4503ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 4504ecd94f1bSKan Liang }, 4505ecd94f1bSKan Liang { 4506ecd94f1bSKan Liang "Offcore": "1", 4507ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 4508ecd94f1bSKan Liang "UMask": "0x1", 4509ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS.SNOOP_MISS", 4510ecd94f1bSKan Liang "Deprecated": "1", 4511ecd94f1bSKan Liang "MSRValue": "0x023C0007F7", 4512ecd94f1bSKan Liang "Counter": "0,1,2,3", 4513ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=ALL_READS:response=L3_MISS.SNOOP_MISS", 4514ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 4515ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4516ecd94f1bSKan Liang "SampleAfterValue": "100003", 4517ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 4518ecd94f1bSKan Liang }, 4519ecd94f1bSKan Liang { 4520ecd94f1bSKan Liang "Offcore": "1", 4521ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 4522ecd94f1bSKan Liang "UMask": "0x1", 4523ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS.HIT_OTHER_CORE_NO_FWD", 4524ecd94f1bSKan Liang "Deprecated": "1", 4525ecd94f1bSKan Liang "MSRValue": "0x043C0007F7", 4526ecd94f1bSKan Liang "Counter": "0,1,2,3", 4527ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=ALL_READS:response=L3_MISS.HIT_OTHER_CORE_NO_FWD", 4528ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 4529ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4530ecd94f1bSKan Liang "SampleAfterValue": "100003", 4531ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 4532ecd94f1bSKan Liang }, 4533ecd94f1bSKan Liang { 4534ecd94f1bSKan Liang "Offcore": "1", 4535ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 4536ecd94f1bSKan Liang "UMask": "0x1", 4537ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS.HIT_OTHER_CORE_FWD", 4538ecd94f1bSKan Liang "Deprecated": "1", 4539ecd94f1bSKan Liang "MSRValue": "0x083C0007F7", 4540ecd94f1bSKan Liang "Counter": "0,1,2,3", 4541ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=ALL_READS:response=L3_MISS.HIT_OTHER_CORE_FWD", 4542ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 4543ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4544ecd94f1bSKan Liang "SampleAfterValue": "100003", 4545ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 4546ecd94f1bSKan Liang }, 4547ecd94f1bSKan Liang { 4548ecd94f1bSKan Liang "Offcore": "1", 4549ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 4550ecd94f1bSKan Liang "UMask": "0x1", 4551ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS.HITM_OTHER_CORE", 4552ecd94f1bSKan Liang "Deprecated": "1", 4553ecd94f1bSKan Liang "MSRValue": "0x103C0007F7", 4554ecd94f1bSKan Liang "Counter": "0,1,2,3", 4555ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=ALL_READS:response=L3_MISS.HITM_OTHER_CORE", 4556ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 4557ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4558ecd94f1bSKan Liang "SampleAfterValue": "100003", 4559ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 4560ecd94f1bSKan Liang }, 4561ecd94f1bSKan Liang { 4562ecd94f1bSKan Liang "Offcore": "1", 4563ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 4564ecd94f1bSKan Liang "UMask": "0x1", 4565ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS.ANY_SNOOP", 4566ecd94f1bSKan Liang "Deprecated": "1", 4567ecd94f1bSKan Liang "MSRValue": "0x3FBC0007F7", 4568ecd94f1bSKan Liang "Counter": "0,1,2,3", 4569ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=ALL_READS:response=L3_MISS.ANY_SNOOP", 4570ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 4571ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4572ecd94f1bSKan Liang "SampleAfterValue": "100003", 4573ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 4574ecd94f1bSKan Liang }, 4575ecd94f1bSKan Liang { 4576ecd94f1bSKan Liang "Offcore": "1", 4577ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 4578ecd94f1bSKan Liang "UMask": "0x1", 4579ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", 4580ecd94f1bSKan Liang "Deprecated": "1", 4581ecd94f1bSKan Liang "MSRValue": "0x063B800001", 4582ecd94f1bSKan Liang "Counter": "0,1,2,3", 4583ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=DEMAND_DATA_RD:response=L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", 4584ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 4585ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4586ecd94f1bSKan Liang "SampleAfterValue": "100003", 4587ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 4588ecd94f1bSKan Liang }, 4589ecd94f1bSKan Liang { 4590ecd94f1bSKan Liang "Offcore": "1", 4591ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 4592ecd94f1bSKan Liang "UMask": "0x1", 4593ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", 4594ecd94f1bSKan Liang "Deprecated": "1", 4595ecd94f1bSKan Liang "MSRValue": "0x0604000001", 4596ecd94f1bSKan Liang "Counter": "0,1,2,3", 4597ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=DEMAND_DATA_RD:response=L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", 4598ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 4599ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4600ecd94f1bSKan Liang "SampleAfterValue": "100003", 4601ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 4602ecd94f1bSKan Liang }, 4603ecd94f1bSKan Liang { 4604ecd94f1bSKan Liang "Offcore": "1", 4605ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 4606ecd94f1bSKan Liang "UMask": "0x1", 4607ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", 4608ecd94f1bSKan Liang "Deprecated": "1", 4609ecd94f1bSKan Liang "MSRValue": "0x063B800002", 4610ecd94f1bSKan Liang "Counter": "0,1,2,3", 4611ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=DEMAND_RFO:response=L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", 4612ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 4613ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4614ecd94f1bSKan Liang "SampleAfterValue": "100003", 4615ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 4616ecd94f1bSKan Liang }, 4617ecd94f1bSKan Liang { 4618ecd94f1bSKan Liang "Offcore": "1", 4619ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 4620ecd94f1bSKan Liang "UMask": "0x1", 4621ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", 4622ecd94f1bSKan Liang "Deprecated": "1", 4623ecd94f1bSKan Liang "MSRValue": "0x0604000002", 4624ecd94f1bSKan Liang "Counter": "0,1,2,3", 4625ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=DEMAND_RFO:response=L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", 4626ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 4627ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4628ecd94f1bSKan Liang "SampleAfterValue": "100003", 4629ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 4630ecd94f1bSKan Liang }, 4631ecd94f1bSKan Liang { 4632ecd94f1bSKan Liang "Offcore": "1", 4633ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 4634ecd94f1bSKan Liang "UMask": "0x1", 4635ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", 4636ecd94f1bSKan Liang "Deprecated": "1", 4637ecd94f1bSKan Liang "MSRValue": "0x063B800004", 4638ecd94f1bSKan Liang "Counter": "0,1,2,3", 4639ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=DEMAND_CODE_RD:response=L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", 4640ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 4641ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4642ecd94f1bSKan Liang "SampleAfterValue": "100003", 4643ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 4644ecd94f1bSKan Liang }, 4645ecd94f1bSKan Liang { 4646ecd94f1bSKan Liang "Offcore": "1", 4647ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 4648ecd94f1bSKan Liang "UMask": "0x1", 4649ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", 4650ecd94f1bSKan Liang "Deprecated": "1", 4651ecd94f1bSKan Liang "MSRValue": "0x0604000004", 4652ecd94f1bSKan Liang "Counter": "0,1,2,3", 4653ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=DEMAND_CODE_RD:response=L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", 4654ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 4655ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4656ecd94f1bSKan Liang "SampleAfterValue": "100003", 4657ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 4658ecd94f1bSKan Liang }, 4659ecd94f1bSKan Liang { 4660ecd94f1bSKan Liang "Offcore": "1", 4661ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 4662ecd94f1bSKan Liang "UMask": "0x1", 4663ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", 4664ecd94f1bSKan Liang "Deprecated": "1", 4665ecd94f1bSKan Liang "MSRValue": "0x063B800010", 4666ecd94f1bSKan Liang "Counter": "0,1,2,3", 4667ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=PF_L2_DATA_RD:response=L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", 4668ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 4669ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4670ecd94f1bSKan Liang "SampleAfterValue": "100003", 4671ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 4672ecd94f1bSKan Liang }, 4673ecd94f1bSKan Liang { 4674ecd94f1bSKan Liang "Offcore": "1", 4675ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 4676ecd94f1bSKan Liang "UMask": "0x1", 4677ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", 4678ecd94f1bSKan Liang "Deprecated": "1", 4679ecd94f1bSKan Liang "MSRValue": "0x0604000010", 4680ecd94f1bSKan Liang "Counter": "0,1,2,3", 4681ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=PF_L2_DATA_RD:response=L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", 4682ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 4683ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4684ecd94f1bSKan Liang "SampleAfterValue": "100003", 4685ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 4686ecd94f1bSKan Liang }, 4687ecd94f1bSKan Liang { 4688ecd94f1bSKan Liang "Offcore": "1", 4689ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 4690ecd94f1bSKan Liang "UMask": "0x1", 4691ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", 4692ecd94f1bSKan Liang "Deprecated": "1", 4693ecd94f1bSKan Liang "MSRValue": "0x063B800020", 4694ecd94f1bSKan Liang "Counter": "0,1,2,3", 4695ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=PF_L2_RFO:response=L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", 4696ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 4697ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4698ecd94f1bSKan Liang "SampleAfterValue": "100003", 4699ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 4700ecd94f1bSKan Liang }, 4701ecd94f1bSKan Liang { 4702ecd94f1bSKan Liang "Offcore": "1", 4703ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 4704ecd94f1bSKan Liang "UMask": "0x1", 4705ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", 4706ecd94f1bSKan Liang "Deprecated": "1", 4707ecd94f1bSKan Liang "MSRValue": "0x0604000020", 4708ecd94f1bSKan Liang "Counter": "0,1,2,3", 4709ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=PF_L2_RFO:response=L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", 4710ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 4711ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4712ecd94f1bSKan Liang "SampleAfterValue": "100003", 4713ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 4714ecd94f1bSKan Liang }, 4715ecd94f1bSKan Liang { 4716ecd94f1bSKan Liang "Offcore": "1", 4717ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 4718ecd94f1bSKan Liang "UMask": "0x1", 4719ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", 4720ecd94f1bSKan Liang "Deprecated": "1", 4721ecd94f1bSKan Liang "MSRValue": "0x063B800080", 4722ecd94f1bSKan Liang "Counter": "0,1,2,3", 4723ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=PF_L3_DATA_RD:response=L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", 4724ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 4725ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4726ecd94f1bSKan Liang "SampleAfterValue": "100003", 4727ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 4728ecd94f1bSKan Liang }, 4729ecd94f1bSKan Liang { 4730ecd94f1bSKan Liang "Offcore": "1", 4731ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 4732ecd94f1bSKan Liang "UMask": "0x1", 4733ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", 4734ecd94f1bSKan Liang "Deprecated": "1", 4735ecd94f1bSKan Liang "MSRValue": "0x0604000080", 4736ecd94f1bSKan Liang "Counter": "0,1,2,3", 4737ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=PF_L3_DATA_RD:response=L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", 4738ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 4739ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4740ecd94f1bSKan Liang "SampleAfterValue": "100003", 4741ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 4742ecd94f1bSKan Liang }, 4743ecd94f1bSKan Liang { 4744ecd94f1bSKan Liang "Offcore": "1", 4745ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 4746ecd94f1bSKan Liang "UMask": "0x1", 4747ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", 4748ecd94f1bSKan Liang "Deprecated": "1", 4749ecd94f1bSKan Liang "MSRValue": "0x063B800100", 4750ecd94f1bSKan Liang "Counter": "0,1,2,3", 4751ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=PF_L3_RFO:response=L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", 4752ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 4753ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4754ecd94f1bSKan Liang "SampleAfterValue": "100003", 4755ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 4756ecd94f1bSKan Liang }, 4757ecd94f1bSKan Liang { 4758ecd94f1bSKan Liang "Offcore": "1", 4759ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 4760ecd94f1bSKan Liang "UMask": "0x1", 4761ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", 4762ecd94f1bSKan Liang "Deprecated": "1", 4763ecd94f1bSKan Liang "MSRValue": "0x0604000100", 4764ecd94f1bSKan Liang "Counter": "0,1,2,3", 4765ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=PF_L3_RFO:response=L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", 4766ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 4767ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4768ecd94f1bSKan Liang "SampleAfterValue": "100003", 4769ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 4770ecd94f1bSKan Liang }, 4771ecd94f1bSKan Liang { 4772ecd94f1bSKan Liang "Offcore": "1", 4773ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 4774ecd94f1bSKan Liang "UMask": "0x1", 4775ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", 4776ecd94f1bSKan Liang "Deprecated": "1", 4777ecd94f1bSKan Liang "MSRValue": "0x063B800400", 4778ecd94f1bSKan Liang "Counter": "0,1,2,3", 4779ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=PF_L1D_AND_SW:response=L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", 4780ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 4781ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4782ecd94f1bSKan Liang "SampleAfterValue": "100003", 4783ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 4784ecd94f1bSKan Liang }, 4785ecd94f1bSKan Liang { 4786ecd94f1bSKan Liang "Offcore": "1", 4787ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 4788ecd94f1bSKan Liang "UMask": "0x1", 4789ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", 4790ecd94f1bSKan Liang "Deprecated": "1", 4791ecd94f1bSKan Liang "MSRValue": "0x0604000400", 4792ecd94f1bSKan Liang "Counter": "0,1,2,3", 4793ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=PF_L1D_AND_SW:response=L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", 4794ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 4795ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4796ecd94f1bSKan Liang "SampleAfterValue": "100003", 4797ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 4798ecd94f1bSKan Liang }, 4799ecd94f1bSKan Liang { 4800ecd94f1bSKan Liang "Offcore": "1", 4801ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 4802ecd94f1bSKan Liang "UMask": "0x1", 4803ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.OTHER.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", 4804ecd94f1bSKan Liang "Deprecated": "1", 4805ecd94f1bSKan Liang "MSRValue": "0x063B808000", 4806ecd94f1bSKan Liang "Counter": "0,1,2,3", 4807ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=OTHER:response=L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", 4808ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 4809ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4810ecd94f1bSKan Liang "SampleAfterValue": "100003", 4811ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 4812ecd94f1bSKan Liang }, 4813ecd94f1bSKan Liang { 4814ecd94f1bSKan Liang "Offcore": "1", 4815ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 4816ecd94f1bSKan Liang "UMask": "0x1", 4817ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.OTHER.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", 4818ecd94f1bSKan Liang "Deprecated": "1", 4819ecd94f1bSKan Liang "MSRValue": "0x0604008000", 4820ecd94f1bSKan Liang "Counter": "0,1,2,3", 4821ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=OTHER:response=L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", 4822ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 4823ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4824ecd94f1bSKan Liang "SampleAfterValue": "100003", 4825ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 4826ecd94f1bSKan Liang }, 4827ecd94f1bSKan Liang { 4828ecd94f1bSKan Liang "Offcore": "1", 4829ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 4830ecd94f1bSKan Liang "UMask": "0x1", 4831ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", 4832ecd94f1bSKan Liang "Deprecated": "1", 4833ecd94f1bSKan Liang "MSRValue": "0x063B800490", 4834ecd94f1bSKan Liang "Counter": "0,1,2,3", 4835ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=ALL_PF_DATA_RD:response=L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", 4836ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 4837ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4838ecd94f1bSKan Liang "SampleAfterValue": "100003", 4839ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 4840ecd94f1bSKan Liang }, 4841ecd94f1bSKan Liang { 4842ecd94f1bSKan Liang "Offcore": "1", 4843ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 4844ecd94f1bSKan Liang "UMask": "0x1", 4845ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", 4846ecd94f1bSKan Liang "Deprecated": "1", 4847ecd94f1bSKan Liang "MSRValue": "0x0604000490", 4848ecd94f1bSKan Liang "Counter": "0,1,2,3", 4849ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=ALL_PF_DATA_RD:response=L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", 4850ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 4851ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4852ecd94f1bSKan Liang "SampleAfterValue": "100003", 4853ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 4854ecd94f1bSKan Liang }, 4855ecd94f1bSKan Liang { 4856ecd94f1bSKan Liang "Offcore": "1", 4857ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 4858ecd94f1bSKan Liang "UMask": "0x1", 4859ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", 4860ecd94f1bSKan Liang "Deprecated": "1", 4861ecd94f1bSKan Liang "MSRValue": "0x063B800120", 4862ecd94f1bSKan Liang "Counter": "0,1,2,3", 4863ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=ALL_PF_RFO:response=L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", 4864ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 4865ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4866ecd94f1bSKan Liang "SampleAfterValue": "100003", 4867ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 4868ecd94f1bSKan Liang }, 4869ecd94f1bSKan Liang { 4870ecd94f1bSKan Liang "Offcore": "1", 4871ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 4872ecd94f1bSKan Liang "UMask": "0x1", 4873ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", 4874ecd94f1bSKan Liang "Deprecated": "1", 4875ecd94f1bSKan Liang "MSRValue": "0x0604000120", 4876ecd94f1bSKan Liang "Counter": "0,1,2,3", 4877ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=ALL_PF_RFO:response=L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", 4878ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 4879ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4880ecd94f1bSKan Liang "SampleAfterValue": "100003", 4881ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 4882ecd94f1bSKan Liang }, 4883ecd94f1bSKan Liang { 4884ecd94f1bSKan Liang "Offcore": "1", 4885ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 4886ecd94f1bSKan Liang "UMask": "0x1", 4887ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", 4888ecd94f1bSKan Liang "Deprecated": "1", 4889ecd94f1bSKan Liang "MSRValue": "0x063B800491", 4890ecd94f1bSKan Liang "Counter": "0,1,2,3", 4891ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=ALL_DATA_RD:response=L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", 4892ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 4893ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4894ecd94f1bSKan Liang "SampleAfterValue": "100003", 4895ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 4896ecd94f1bSKan Liang }, 4897ecd94f1bSKan Liang { 4898ecd94f1bSKan Liang "Offcore": "1", 4899ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 4900ecd94f1bSKan Liang "UMask": "0x1", 4901ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", 4902ecd94f1bSKan Liang "Deprecated": "1", 4903ecd94f1bSKan Liang "MSRValue": "0x0604000491", 4904ecd94f1bSKan Liang "Counter": "0,1,2,3", 4905ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=ALL_DATA_RD:response=L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", 4906ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 4907ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4908ecd94f1bSKan Liang "SampleAfterValue": "100003", 4909ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 4910ecd94f1bSKan Liang }, 4911ecd94f1bSKan Liang { 4912ecd94f1bSKan Liang "Offcore": "1", 4913ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 4914ecd94f1bSKan Liang "UMask": "0x1", 4915ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", 4916ecd94f1bSKan Liang "Deprecated": "1", 4917ecd94f1bSKan Liang "MSRValue": "0x063B800122", 4918ecd94f1bSKan Liang "Counter": "0,1,2,3", 4919ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=ALL_RFO:response=L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", 4920ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 4921ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4922ecd94f1bSKan Liang "SampleAfterValue": "100003", 4923ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 4924ecd94f1bSKan Liang }, 4925ecd94f1bSKan Liang { 4926ecd94f1bSKan Liang "Offcore": "1", 4927ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 4928ecd94f1bSKan Liang "UMask": "0x1", 4929ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", 4930ecd94f1bSKan Liang "Deprecated": "1", 4931ecd94f1bSKan Liang "MSRValue": "0x0604000122", 4932ecd94f1bSKan Liang "Counter": "0,1,2,3", 4933ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=ALL_RFO:response=L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", 4934ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 4935ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4936ecd94f1bSKan Liang "SampleAfterValue": "100003", 4937ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 4938ecd94f1bSKan Liang }, 4939ecd94f1bSKan Liang { 4940ecd94f1bSKan Liang "Offcore": "1", 4941ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 4942ecd94f1bSKan Liang "UMask": "0x1", 4943ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", 4944ecd94f1bSKan Liang "Deprecated": "1", 4945ecd94f1bSKan Liang "MSRValue": "0x063B8007F7", 4946ecd94f1bSKan Liang "Counter": "0,1,2,3", 4947ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=ALL_READS:response=L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", 4948ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 4949ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4950ecd94f1bSKan Liang "SampleAfterValue": "100003", 4951ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 4952ecd94f1bSKan Liang }, 4953ecd94f1bSKan Liang { 4954ecd94f1bSKan Liang "Offcore": "1", 4955ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 4956ecd94f1bSKan Liang "UMask": "0x1", 4957ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", 4958ecd94f1bSKan Liang "Deprecated": "1", 4959ecd94f1bSKan Liang "MSRValue": "0x06040007F7", 4960ecd94f1bSKan Liang "Counter": "0,1,2,3", 4961ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=ALL_READS:response=L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", 4962ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 4963ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4964ecd94f1bSKan Liang "SampleAfterValue": "100003", 4965ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 4966ecd94f1bSKan Liang }, 4967ecd94f1bSKan Liang { 4968ecd94f1bSKan Liang "Offcore": "1", 4969ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 4970ecd94f1bSKan Liang "UMask": "0x1", 4971ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS.REMOTE_HITM", 4972ecd94f1bSKan Liang "Deprecated": "1", 4973ecd94f1bSKan Liang "MSRValue": "0x103FC00001", 4974ecd94f1bSKan Liang "Counter": "0,1,2,3", 4975ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=DEMAND_DATA_RD:response=L3_MISS.REMOTE_HITM", 4976ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 4977ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4978ecd94f1bSKan Liang "SampleAfterValue": "100003", 4979ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 4980ecd94f1bSKan Liang }, 4981ecd94f1bSKan Liang { 4982ecd94f1bSKan Liang "Offcore": "1", 4983ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 4984ecd94f1bSKan Liang "UMask": "0x1", 4985ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS.REMOTE_HITM", 4986ecd94f1bSKan Liang "Deprecated": "1", 4987ecd94f1bSKan Liang "MSRValue": "0x103FC00002", 4988ecd94f1bSKan Liang "Counter": "0,1,2,3", 4989ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=DEMAND_RFO:response=L3_MISS.REMOTE_HITM", 4990ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 4991ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4992ecd94f1bSKan Liang "SampleAfterValue": "100003", 4993ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 4994ecd94f1bSKan Liang }, 4995ecd94f1bSKan Liang { 4996ecd94f1bSKan Liang "Offcore": "1", 4997ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 4998ecd94f1bSKan Liang "UMask": "0x1", 4999ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS.REMOTE_HITM", 5000ecd94f1bSKan Liang "Deprecated": "1", 5001ecd94f1bSKan Liang "MSRValue": "0x103FC00004", 5002ecd94f1bSKan Liang "Counter": "0,1,2,3", 5003ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=DEMAND_CODE_RD:response=L3_MISS.REMOTE_HITM", 5004ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 5005ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5006ecd94f1bSKan Liang "SampleAfterValue": "100003", 5007ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 5008ecd94f1bSKan Liang }, 5009ecd94f1bSKan Liang { 5010ecd94f1bSKan Liang "Offcore": "1", 5011ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 5012ecd94f1bSKan Liang "UMask": "0x1", 5013ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS.REMOTE_HITM", 5014ecd94f1bSKan Liang "Deprecated": "1", 5015ecd94f1bSKan Liang "MSRValue": "0x103FC00010", 5016ecd94f1bSKan Liang "Counter": "0,1,2,3", 5017ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=PF_L2_DATA_RD:response=L3_MISS.REMOTE_HITM", 5018ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 5019ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5020ecd94f1bSKan Liang "SampleAfterValue": "100003", 5021ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 5022ecd94f1bSKan Liang }, 5023ecd94f1bSKan Liang { 5024ecd94f1bSKan Liang "Offcore": "1", 5025ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 5026ecd94f1bSKan Liang "UMask": "0x1", 5027ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS.REMOTE_HITM", 5028ecd94f1bSKan Liang "Deprecated": "1", 5029ecd94f1bSKan Liang "MSRValue": "0x103FC00020", 5030ecd94f1bSKan Liang "Counter": "0,1,2,3", 5031ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=PF_L2_RFO:response=L3_MISS.REMOTE_HITM", 5032ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 5033ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5034ecd94f1bSKan Liang "SampleAfterValue": "100003", 5035ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 5036ecd94f1bSKan Liang }, 5037ecd94f1bSKan Liang { 5038ecd94f1bSKan Liang "Offcore": "1", 5039ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 5040ecd94f1bSKan Liang "UMask": "0x1", 5041ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS.REMOTE_HITM", 5042ecd94f1bSKan Liang "Deprecated": "1", 5043ecd94f1bSKan Liang "MSRValue": "0x103FC00080", 5044ecd94f1bSKan Liang "Counter": "0,1,2,3", 5045ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=PF_L3_DATA_RD:response=L3_MISS.REMOTE_HITM", 5046ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 5047ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5048ecd94f1bSKan Liang "SampleAfterValue": "100003", 5049ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 5050ecd94f1bSKan Liang }, 5051ecd94f1bSKan Liang { 5052ecd94f1bSKan Liang "Offcore": "1", 5053ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 5054ecd94f1bSKan Liang "UMask": "0x1", 5055ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS.REMOTE_HITM", 5056ecd94f1bSKan Liang "Deprecated": "1", 5057ecd94f1bSKan Liang "MSRValue": "0x103FC00100", 5058ecd94f1bSKan Liang "Counter": "0,1,2,3", 5059ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=PF_L3_RFO:response=L3_MISS.REMOTE_HITM", 5060ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 5061ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5062ecd94f1bSKan Liang "SampleAfterValue": "100003", 5063ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 5064ecd94f1bSKan Liang }, 5065ecd94f1bSKan Liang { 5066ecd94f1bSKan Liang "Offcore": "1", 5067ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 5068ecd94f1bSKan Liang "UMask": "0x1", 5069ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS.REMOTE_HITM", 5070ecd94f1bSKan Liang "Deprecated": "1", 5071ecd94f1bSKan Liang "MSRValue": "0x103FC00400", 5072ecd94f1bSKan Liang "Counter": "0,1,2,3", 5073ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=PF_L1D_AND_SW:response=L3_MISS.REMOTE_HITM", 5074ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 5075ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5076ecd94f1bSKan Liang "SampleAfterValue": "100003", 5077ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 5078ecd94f1bSKan Liang }, 5079ecd94f1bSKan Liang { 5080ecd94f1bSKan Liang "Offcore": "1", 5081ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 5082ecd94f1bSKan Liang "UMask": "0x1", 5083ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.OTHER.L3_MISS.REMOTE_HITM", 5084ecd94f1bSKan Liang "Deprecated": "1", 5085ecd94f1bSKan Liang "MSRValue": "0x103FC08000", 5086ecd94f1bSKan Liang "Counter": "0,1,2,3", 5087ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=OTHER:response=L3_MISS.REMOTE_HITM", 5088ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 5089ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5090ecd94f1bSKan Liang "SampleAfterValue": "100003", 5091ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 5092ecd94f1bSKan Liang }, 5093ecd94f1bSKan Liang { 5094ecd94f1bSKan Liang "Offcore": "1", 5095ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 5096ecd94f1bSKan Liang "UMask": "0x1", 5097ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS.REMOTE_HITM", 5098ecd94f1bSKan Liang "Deprecated": "1", 5099ecd94f1bSKan Liang "MSRValue": "0x103FC00490", 5100ecd94f1bSKan Liang "Counter": "0,1,2,3", 5101ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=ALL_PF_DATA_RD:response=L3_MISS.REMOTE_HITM", 5102ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 5103ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5104ecd94f1bSKan Liang "SampleAfterValue": "100003", 5105ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 5106ecd94f1bSKan Liang }, 5107ecd94f1bSKan Liang { 5108ecd94f1bSKan Liang "Offcore": "1", 5109ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 5110ecd94f1bSKan Liang "UMask": "0x1", 5111ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS.REMOTE_HITM", 5112ecd94f1bSKan Liang "Deprecated": "1", 5113ecd94f1bSKan Liang "MSRValue": "0x103FC00120", 5114ecd94f1bSKan Liang "Counter": "0,1,2,3", 5115ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=ALL_PF_RFO:response=L3_MISS.REMOTE_HITM", 5116ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 5117ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5118ecd94f1bSKan Liang "SampleAfterValue": "100003", 5119ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 5120ecd94f1bSKan Liang }, 5121ecd94f1bSKan Liang { 5122ecd94f1bSKan Liang "Offcore": "1", 5123ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 5124ecd94f1bSKan Liang "UMask": "0x1", 5125ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS.REMOTE_HITM", 5126ecd94f1bSKan Liang "Deprecated": "1", 5127ecd94f1bSKan Liang "MSRValue": "0x103FC00491", 5128ecd94f1bSKan Liang "Counter": "0,1,2,3", 5129ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=ALL_DATA_RD:response=L3_MISS.REMOTE_HITM", 5130ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 5131ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5132ecd94f1bSKan Liang "SampleAfterValue": "100003", 5133ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 5134ecd94f1bSKan Liang }, 5135ecd94f1bSKan Liang { 5136ecd94f1bSKan Liang "Offcore": "1", 5137ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 5138ecd94f1bSKan Liang "UMask": "0x1", 5139ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS.REMOTE_HITM", 5140ecd94f1bSKan Liang "Deprecated": "1", 5141ecd94f1bSKan Liang "MSRValue": "0x103FC00122", 5142ecd94f1bSKan Liang "Counter": "0,1,2,3", 5143ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=ALL_RFO:response=L3_MISS.REMOTE_HITM", 5144ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 5145ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5146ecd94f1bSKan Liang "SampleAfterValue": "100003", 5147ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 5148ecd94f1bSKan Liang }, 5149ecd94f1bSKan Liang { 5150ecd94f1bSKan Liang "Offcore": "1", 5151ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 5152ecd94f1bSKan Liang "UMask": "0x1", 5153ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS.REMOTE_HITM", 5154ecd94f1bSKan Liang "Deprecated": "1", 5155ecd94f1bSKan Liang "MSRValue": "0x103FC007F7", 5156ecd94f1bSKan Liang "Counter": "0,1,2,3", 5157ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=ALL_READS:response=L3_MISS.REMOTE_HITM", 5158ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 5159ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5160ecd94f1bSKan Liang "SampleAfterValue": "100003", 5161ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 5162ecd94f1bSKan Liang }, 5163ecd94f1bSKan Liang { 5164ecd94f1bSKan Liang "Offcore": "1", 5165ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 5166ecd94f1bSKan Liang "UMask": "0x1", 5167ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS.REMOTE_HIT_FORWARD", 5168ecd94f1bSKan Liang "Deprecated": "1", 5169ecd94f1bSKan Liang "MSRValue": "0x083FC00001", 5170ecd94f1bSKan Liang "Counter": "0,1,2,3", 5171ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=DEMAND_DATA_RD:response=L3_MISS.REMOTE_HIT_FORWARD", 5172ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 5173ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5174ecd94f1bSKan Liang "SampleAfterValue": "100003", 5175ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 5176ecd94f1bSKan Liang }, 5177ecd94f1bSKan Liang { 5178ecd94f1bSKan Liang "Offcore": "1", 5179ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 5180ecd94f1bSKan Liang "UMask": "0x1", 5181ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS.REMOTE_HIT_FORWARD", 5182ecd94f1bSKan Liang "Deprecated": "1", 5183ecd94f1bSKan Liang "MSRValue": "0x083FC00002", 5184ecd94f1bSKan Liang "Counter": "0,1,2,3", 5185ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=DEMAND_RFO:response=L3_MISS.REMOTE_HIT_FORWARD", 5186ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 5187ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5188ecd94f1bSKan Liang "SampleAfterValue": "100003", 5189ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 5190ecd94f1bSKan Liang }, 5191ecd94f1bSKan Liang { 5192ecd94f1bSKan Liang "Offcore": "1", 5193ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 5194ecd94f1bSKan Liang "UMask": "0x1", 5195ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS.REMOTE_HIT_FORWARD", 5196ecd94f1bSKan Liang "Deprecated": "1", 5197ecd94f1bSKan Liang "MSRValue": "0x083FC00004", 5198ecd94f1bSKan Liang "Counter": "0,1,2,3", 5199ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=DEMAND_CODE_RD:response=L3_MISS.REMOTE_HIT_FORWARD", 5200ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 5201ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5202ecd94f1bSKan Liang "SampleAfterValue": "100003", 5203ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 5204ecd94f1bSKan Liang }, 5205ecd94f1bSKan Liang { 5206ecd94f1bSKan Liang "Offcore": "1", 5207ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 5208ecd94f1bSKan Liang "UMask": "0x1", 5209ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS.REMOTE_HIT_FORWARD", 5210ecd94f1bSKan Liang "Deprecated": "1", 5211ecd94f1bSKan Liang "MSRValue": "0x083FC00010", 5212ecd94f1bSKan Liang "Counter": "0,1,2,3", 5213ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=PF_L2_DATA_RD:response=L3_MISS.REMOTE_HIT_FORWARD", 5214ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 5215ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5216ecd94f1bSKan Liang "SampleAfterValue": "100003", 5217ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 5218ecd94f1bSKan Liang }, 5219ecd94f1bSKan Liang { 5220ecd94f1bSKan Liang "Offcore": "1", 5221ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 5222ecd94f1bSKan Liang "UMask": "0x1", 5223ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS.REMOTE_HIT_FORWARD", 5224ecd94f1bSKan Liang "Deprecated": "1", 5225ecd94f1bSKan Liang "MSRValue": "0x083FC00020", 5226ecd94f1bSKan Liang "Counter": "0,1,2,3", 5227ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=PF_L2_RFO:response=L3_MISS.REMOTE_HIT_FORWARD", 5228ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 5229ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5230ecd94f1bSKan Liang "SampleAfterValue": "100003", 5231ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 5232ecd94f1bSKan Liang }, 5233ecd94f1bSKan Liang { 5234ecd94f1bSKan Liang "Offcore": "1", 5235ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 5236ecd94f1bSKan Liang "UMask": "0x1", 5237ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS.REMOTE_HIT_FORWARD", 5238ecd94f1bSKan Liang "Deprecated": "1", 5239ecd94f1bSKan Liang "MSRValue": "0x083FC00080", 5240ecd94f1bSKan Liang "Counter": "0,1,2,3", 5241ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=PF_L3_DATA_RD:response=L3_MISS.REMOTE_HIT_FORWARD", 5242ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 5243ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5244ecd94f1bSKan Liang "SampleAfterValue": "100003", 5245ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 5246ecd94f1bSKan Liang }, 5247ecd94f1bSKan Liang { 5248ecd94f1bSKan Liang "Offcore": "1", 5249ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 5250ecd94f1bSKan Liang "UMask": "0x1", 5251ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS.REMOTE_HIT_FORWARD", 5252ecd94f1bSKan Liang "Deprecated": "1", 5253ecd94f1bSKan Liang "MSRValue": "0x083FC00100", 5254ecd94f1bSKan Liang "Counter": "0,1,2,3", 5255ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=PF_L3_RFO:response=L3_MISS.REMOTE_HIT_FORWARD", 5256ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 5257ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5258ecd94f1bSKan Liang "SampleAfterValue": "100003", 5259ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 5260ecd94f1bSKan Liang }, 5261ecd94f1bSKan Liang { 5262ecd94f1bSKan Liang "Offcore": "1", 5263ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 5264ecd94f1bSKan Liang "UMask": "0x1", 5265ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS.REMOTE_HIT_FORWARD", 5266ecd94f1bSKan Liang "Deprecated": "1", 5267ecd94f1bSKan Liang "MSRValue": "0x083FC00400", 5268ecd94f1bSKan Liang "Counter": "0,1,2,3", 5269ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=PF_L1D_AND_SW:response=L3_MISS.REMOTE_HIT_FORWARD", 5270ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 5271ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5272ecd94f1bSKan Liang "SampleAfterValue": "100003", 5273ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 5274ecd94f1bSKan Liang }, 5275ecd94f1bSKan Liang { 5276ecd94f1bSKan Liang "Offcore": "1", 5277ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 5278ecd94f1bSKan Liang "UMask": "0x1", 5279ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.OTHER.L3_MISS.REMOTE_HIT_FORWARD", 5280ecd94f1bSKan Liang "Deprecated": "1", 5281ecd94f1bSKan Liang "MSRValue": "0x083FC08000", 5282ecd94f1bSKan Liang "Counter": "0,1,2,3", 5283ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=OTHER:response=L3_MISS.REMOTE_HIT_FORWARD", 5284ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 5285ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5286ecd94f1bSKan Liang "SampleAfterValue": "100003", 5287ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 5288ecd94f1bSKan Liang }, 5289ecd94f1bSKan Liang { 5290ecd94f1bSKan Liang "Offcore": "1", 5291ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 5292ecd94f1bSKan Liang "UMask": "0x1", 5293ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS.REMOTE_HIT_FORWARD", 5294ecd94f1bSKan Liang "Deprecated": "1", 5295ecd94f1bSKan Liang "MSRValue": "0x083FC00490", 5296ecd94f1bSKan Liang "Counter": "0,1,2,3", 5297ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=ALL_PF_DATA_RD:response=L3_MISS.REMOTE_HIT_FORWARD", 5298ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 5299ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5300ecd94f1bSKan Liang "SampleAfterValue": "100003", 5301ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 5302ecd94f1bSKan Liang }, 5303ecd94f1bSKan Liang { 5304ecd94f1bSKan Liang "Offcore": "1", 5305ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 5306ecd94f1bSKan Liang "UMask": "0x1", 5307ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS.REMOTE_HIT_FORWARD", 5308ecd94f1bSKan Liang "Deprecated": "1", 5309ecd94f1bSKan Liang "MSRValue": "0x083FC00120", 5310ecd94f1bSKan Liang "Counter": "0,1,2,3", 5311ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=ALL_PF_RFO:response=L3_MISS.REMOTE_HIT_FORWARD", 5312ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 5313ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5314ecd94f1bSKan Liang "SampleAfterValue": "100003", 5315ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 5316ecd94f1bSKan Liang }, 5317ecd94f1bSKan Liang { 5318ecd94f1bSKan Liang "Offcore": "1", 5319ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 5320ecd94f1bSKan Liang "UMask": "0x1", 5321ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS.REMOTE_HIT_FORWARD", 5322ecd94f1bSKan Liang "Deprecated": "1", 5323ecd94f1bSKan Liang "MSRValue": "0x083FC00491", 5324ecd94f1bSKan Liang "Counter": "0,1,2,3", 5325ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=ALL_DATA_RD:response=L3_MISS.REMOTE_HIT_FORWARD", 5326ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 5327ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5328ecd94f1bSKan Liang "SampleAfterValue": "100003", 5329ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 5330ecd94f1bSKan Liang }, 5331ecd94f1bSKan Liang { 5332ecd94f1bSKan Liang "Offcore": "1", 5333ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 5334ecd94f1bSKan Liang "UMask": "0x1", 5335ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS.REMOTE_HIT_FORWARD", 5336ecd94f1bSKan Liang "Deprecated": "1", 5337ecd94f1bSKan Liang "MSRValue": "0x083FC00122", 5338ecd94f1bSKan Liang "Counter": "0,1,2,3", 5339ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=ALL_RFO:response=L3_MISS.REMOTE_HIT_FORWARD", 5340ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 5341ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5342ecd94f1bSKan Liang "SampleAfterValue": "100003", 5343ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 5344ecd94f1bSKan Liang }, 5345ecd94f1bSKan Liang { 5346ecd94f1bSKan Liang "Offcore": "1", 5347ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 5348ecd94f1bSKan Liang "UMask": "0x1", 5349ecd94f1bSKan Liang "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS.REMOTE_HIT_FORWARD", 5350ecd94f1bSKan Liang "Deprecated": "1", 5351ecd94f1bSKan Liang "MSRValue": "0x083FC007F7", 5352ecd94f1bSKan Liang "Counter": "0,1,2,3", 5353ecd94f1bSKan Liang "EventName": "OFFCORE_RESPONSE:request=ALL_READS:response=L3_MISS.REMOTE_HIT_FORWARD", 5354ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 5355ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5356ecd94f1bSKan Liang "SampleAfterValue": "100003", 5357ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 5358ecd94f1bSKan Liang }, 5359ecd94f1bSKan Liang { 5360ecd94f1bSKan Liang "Offcore": "1", 5361ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 5362ecd94f1bSKan Liang "UMask": "0x1", 5363ecd94f1bSKan Liang "BriefDescription": "Counts demand data reads", 5364ecd94f1bSKan Liang "MSRValue": "0x0084000001", 5365ecd94f1bSKan Liang "Counter": "0,1,2,3", 5366ecd94f1bSKan Liang "EventName": "OCR.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NONE", 5367ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 5368ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5369ecd94f1bSKan Liang "SampleAfterValue": "100003", 5370ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 5371ecd94f1bSKan Liang }, 5372ecd94f1bSKan Liang { 5373ecd94f1bSKan Liang "Offcore": "1", 5374ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 5375ecd94f1bSKan Liang "UMask": "0x1", 5376ecd94f1bSKan Liang "BriefDescription": "Counts demand data reads TBD", 5377ecd94f1bSKan Liang "MSRValue": "0x0104000001", 5378ecd94f1bSKan Liang "Counter": "0,1,2,3", 5379ecd94f1bSKan Liang "EventName": "OCR.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED", 5380ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 5381ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5382ecd94f1bSKan Liang "SampleAfterValue": "100003", 5383ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 5384ecd94f1bSKan Liang }, 5385ecd94f1bSKan Liang { 5386ecd94f1bSKan Liang "Offcore": "1", 5387ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 5388ecd94f1bSKan Liang "UMask": "0x1", 5389ecd94f1bSKan Liang "BriefDescription": "Counts demand data reads", 5390ecd94f1bSKan Liang "MSRValue": "0x0204000001", 5391ecd94f1bSKan Liang "Counter": "0,1,2,3", 5392ecd94f1bSKan Liang "EventName": "OCR.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS", 5393ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 5394ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5395ecd94f1bSKan Liang "SampleAfterValue": "100003", 5396ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 5397ecd94f1bSKan Liang }, 5398ecd94f1bSKan Liang { 5399ecd94f1bSKan Liang "Offcore": "1", 5400ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 5401ecd94f1bSKan Liang "UMask": "0x1", 5402ecd94f1bSKan Liang "BriefDescription": "Counts demand data reads TBD", 5403ecd94f1bSKan Liang "MSRValue": "0x0404000001", 5404ecd94f1bSKan Liang "Counter": "0,1,2,3", 5405ecd94f1bSKan Liang "EventName": "OCR.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD", 5406ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 5407ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5408ecd94f1bSKan Liang "SampleAfterValue": "100003", 5409ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 5410ecd94f1bSKan Liang }, 5411ecd94f1bSKan Liang { 5412ecd94f1bSKan Liang "Offcore": "1", 5413ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 5414ecd94f1bSKan Liang "UMask": "0x1", 5415ecd94f1bSKan Liang "BriefDescription": "Counts demand data reads TBD", 5416ecd94f1bSKan Liang "MSRValue": "0x0804000001", 5417ecd94f1bSKan Liang "Counter": "0,1,2,3", 5418ecd94f1bSKan Liang "EventName": "OCR.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD", 5419ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 5420ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5421ecd94f1bSKan Liang "SampleAfterValue": "100003", 5422ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 5423ecd94f1bSKan Liang }, 5424ecd94f1bSKan Liang { 5425ecd94f1bSKan Liang "Offcore": "1", 5426ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 5427ecd94f1bSKan Liang "UMask": "0x1", 5428ecd94f1bSKan Liang "BriefDescription": "Counts demand data reads TBD", 5429ecd94f1bSKan Liang "MSRValue": "0x1004000001", 5430ecd94f1bSKan Liang "Counter": "0,1,2,3", 5431ecd94f1bSKan Liang "EventName": "OCR.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE", 5432ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 5433ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5434ecd94f1bSKan Liang "SampleAfterValue": "100003", 5435ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 5436ecd94f1bSKan Liang }, 5437ecd94f1bSKan Liang { 5438ecd94f1bSKan Liang "Offcore": "1", 5439ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 5440ecd94f1bSKan Liang "UMask": "0x1", 5441ecd94f1bSKan Liang "BriefDescription": "Counts demand data reads TBD", 5442ecd94f1bSKan Liang "MSRValue": "0x3F84000001", 5443ecd94f1bSKan Liang "Counter": "0,1,2,3", 5444ecd94f1bSKan Liang "EventName": "OCR.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP", 5445ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 5446ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5447ecd94f1bSKan Liang "SampleAfterValue": "100003", 5448ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 5449ecd94f1bSKan Liang }, 5450ecd94f1bSKan Liang { 5451ecd94f1bSKan Liang "Offcore": "1", 5452ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 5453ecd94f1bSKan Liang "UMask": "0x1", 5454ecd94f1bSKan Liang "BriefDescription": "Counts demand data reads", 5455ecd94f1bSKan Liang "MSRValue": "0x0090000001", 5456ecd94f1bSKan Liang "Counter": "0,1,2,3", 5457ecd94f1bSKan Liang "EventName": "OCR.DEMAND_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE", 5458ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 5459ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5460ecd94f1bSKan Liang "SampleAfterValue": "100003", 5461ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 5462ecd94f1bSKan Liang }, 5463ecd94f1bSKan Liang { 5464ecd94f1bSKan Liang "Offcore": "1", 5465ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 5466ecd94f1bSKan Liang "UMask": "0x1", 5467ecd94f1bSKan Liang "BriefDescription": "Counts demand data reads TBD", 5468ecd94f1bSKan Liang "MSRValue": "0x0110000001", 5469ecd94f1bSKan Liang "Counter": "0,1,2,3", 5470ecd94f1bSKan Liang "EventName": "OCR.DEMAND_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED", 5471ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 5472ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5473ecd94f1bSKan Liang "SampleAfterValue": "100003", 5474ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 5475ecd94f1bSKan Liang }, 5476ecd94f1bSKan Liang { 5477ecd94f1bSKan Liang "Offcore": "1", 5478ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 5479ecd94f1bSKan Liang "UMask": "0x1", 5480ecd94f1bSKan Liang "BriefDescription": "Counts demand data reads", 5481ecd94f1bSKan Liang "MSRValue": "0x0210000001", 5482ecd94f1bSKan Liang "Counter": "0,1,2,3", 5483ecd94f1bSKan Liang "EventName": "OCR.DEMAND_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS", 5484ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 5485ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5486ecd94f1bSKan Liang "SampleAfterValue": "100003", 5487ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 5488ecd94f1bSKan Liang }, 5489ecd94f1bSKan Liang { 5490ecd94f1bSKan Liang "Offcore": "1", 5491ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 5492ecd94f1bSKan Liang "UMask": "0x1", 5493ecd94f1bSKan Liang "BriefDescription": "Counts demand data reads TBD", 5494ecd94f1bSKan Liang "MSRValue": "0x0410000001", 5495ecd94f1bSKan Liang "Counter": "0,1,2,3", 5496ecd94f1bSKan Liang "EventName": "OCR.DEMAND_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD", 5497ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 5498ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5499ecd94f1bSKan Liang "SampleAfterValue": "100003", 5500ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 5501ecd94f1bSKan Liang }, 5502ecd94f1bSKan Liang { 5503ecd94f1bSKan Liang "Offcore": "1", 5504ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 5505ecd94f1bSKan Liang "UMask": "0x1", 5506ecd94f1bSKan Liang "BriefDescription": "Counts demand data reads TBD", 5507ecd94f1bSKan Liang "MSRValue": "0x0810000001", 5508ecd94f1bSKan Liang "Counter": "0,1,2,3", 5509ecd94f1bSKan Liang "EventName": "OCR.DEMAND_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD", 5510ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 5511ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5512ecd94f1bSKan Liang "SampleAfterValue": "100003", 5513ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 5514ecd94f1bSKan Liang }, 5515ecd94f1bSKan Liang { 5516ecd94f1bSKan Liang "Offcore": "1", 5517ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 5518ecd94f1bSKan Liang "UMask": "0x1", 5519ecd94f1bSKan Liang "BriefDescription": "Counts demand data reads TBD", 5520ecd94f1bSKan Liang "MSRValue": "0x1010000001", 5521ecd94f1bSKan Liang "Counter": "0,1,2,3", 5522ecd94f1bSKan Liang "EventName": "OCR.DEMAND_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE", 5523ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 5524ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5525ecd94f1bSKan Liang "SampleAfterValue": "100003", 5526ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 5527ecd94f1bSKan Liang }, 5528ecd94f1bSKan Liang { 5529ecd94f1bSKan Liang "Offcore": "1", 5530ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 5531ecd94f1bSKan Liang "UMask": "0x1", 5532ecd94f1bSKan Liang "BriefDescription": "Counts demand data reads TBD", 5533ecd94f1bSKan Liang "MSRValue": "0x3F90000001", 5534ecd94f1bSKan Liang "Counter": "0,1,2,3", 5535ecd94f1bSKan Liang "EventName": "OCR.DEMAND_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP", 5536ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 5537ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5538ecd94f1bSKan Liang "SampleAfterValue": "100003", 5539ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 5540ecd94f1bSKan Liang }, 5541ecd94f1bSKan Liang { 5542ecd94f1bSKan Liang "Offcore": "1", 5543ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 5544ecd94f1bSKan Liang "UMask": "0x1", 5545ecd94f1bSKan Liang "BriefDescription": "Counts demand data reads TBD", 5546ecd94f1bSKan Liang "MSRValue": "0x00BC000001", 5547ecd94f1bSKan Liang "Counter": "0,1,2,3", 5548ecd94f1bSKan Liang "EventName": "OCR.DEMAND_DATA_RD.L3_MISS.SNOOP_NONE", 5549ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 5550ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5551ecd94f1bSKan Liang "SampleAfterValue": "100003", 5552ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 5553ecd94f1bSKan Liang }, 5554ecd94f1bSKan Liang { 5555ecd94f1bSKan Liang "Offcore": "1", 5556ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 5557ecd94f1bSKan Liang "UMask": "0x1", 5558ecd94f1bSKan Liang "BriefDescription": "Counts demand data reads TBD TBD", 5559ecd94f1bSKan Liang "MSRValue": "0x013C000001", 5560ecd94f1bSKan Liang "Counter": "0,1,2,3", 5561ecd94f1bSKan Liang "EventName": "OCR.DEMAND_DATA_RD.L3_MISS.NO_SNOOP_NEEDED", 5562ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 5563ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5564ecd94f1bSKan Liang "SampleAfterValue": "100003", 5565ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 5566ecd94f1bSKan Liang }, 5567ecd94f1bSKan Liang { 5568ecd94f1bSKan Liang "Offcore": "1", 5569ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 5570ecd94f1bSKan Liang "UMask": "0x1", 5571ecd94f1bSKan Liang "BriefDescription": "Counts demand data reads TBD", 5572ecd94f1bSKan Liang "MSRValue": "0x023C000001", 5573ecd94f1bSKan Liang "Counter": "0,1,2,3", 5574ecd94f1bSKan Liang "EventName": "OCR.DEMAND_DATA_RD.L3_MISS.SNOOP_MISS", 5575ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 5576ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5577ecd94f1bSKan Liang "SampleAfterValue": "100003", 5578ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 5579ecd94f1bSKan Liang }, 5580ecd94f1bSKan Liang { 5581ecd94f1bSKan Liang "Offcore": "1", 5582ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 5583ecd94f1bSKan Liang "UMask": "0x1", 5584ecd94f1bSKan Liang "BriefDescription": "Counts demand data reads TBD TBD", 5585ecd94f1bSKan Liang "MSRValue": "0x043C000001", 5586ecd94f1bSKan Liang "Counter": "0,1,2,3", 5587ecd94f1bSKan Liang "EventName": "OCR.DEMAND_DATA_RD.L3_MISS.HIT_OTHER_CORE_NO_FWD", 5588ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 5589ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5590ecd94f1bSKan Liang "SampleAfterValue": "100003", 5591ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 5592ecd94f1bSKan Liang }, 5593ecd94f1bSKan Liang { 5594ecd94f1bSKan Liang "Offcore": "1", 5595ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 5596ecd94f1bSKan Liang "UMask": "0x1", 5597ecd94f1bSKan Liang "BriefDescription": "Counts demand data reads TBD TBD", 5598ecd94f1bSKan Liang "MSRValue": "0x083C000001", 5599ecd94f1bSKan Liang "Counter": "0,1,2,3", 5600ecd94f1bSKan Liang "EventName": "OCR.DEMAND_DATA_RD.L3_MISS.HIT_OTHER_CORE_FWD", 5601ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 5602ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5603ecd94f1bSKan Liang "SampleAfterValue": "100003", 5604ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 5605ecd94f1bSKan Liang }, 5606ecd94f1bSKan Liang { 5607ecd94f1bSKan Liang "Offcore": "1", 5608ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 5609ecd94f1bSKan Liang "UMask": "0x1", 5610ecd94f1bSKan Liang "BriefDescription": "Counts demand data reads TBD TBD", 5611ecd94f1bSKan Liang "MSRValue": "0x103C000001", 5612ecd94f1bSKan Liang "Counter": "0,1,2,3", 5613ecd94f1bSKan Liang "EventName": "OCR.DEMAND_DATA_RD.L3_MISS.HITM_OTHER_CORE", 5614ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 5615ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5616ecd94f1bSKan Liang "SampleAfterValue": "100003", 5617ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 5618ecd94f1bSKan Liang }, 5619ecd94f1bSKan Liang { 5620ecd94f1bSKan Liang "Offcore": "1", 5621ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 5622ecd94f1bSKan Liang "UMask": "0x1", 5623ecd94f1bSKan Liang "BriefDescription": "Counts demand data reads TBD TBD", 5624ecd94f1bSKan Liang "MSRValue": "0x3FBC000001", 5625ecd94f1bSKan Liang "Counter": "0,1,2,3", 5626ecd94f1bSKan Liang "EventName": "OCR.DEMAND_DATA_RD.L3_MISS.ANY_SNOOP", 5627ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 5628ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5629ecd94f1bSKan Liang "SampleAfterValue": "100003", 5630ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 5631ecd94f1bSKan Liang }, 5632ecd94f1bSKan Liang { 5633ecd94f1bSKan Liang "Offcore": "1", 5634ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 5635ecd94f1bSKan Liang "UMask": "0x1", 5636ecd94f1bSKan Liang "BriefDescription": "Counts all demand data writes (RFOs)", 5637ecd94f1bSKan Liang "MSRValue": "0x0084000002", 5638ecd94f1bSKan Liang "Counter": "0,1,2,3", 5639ecd94f1bSKan Liang "EventName": "OCR.DEMAND_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NONE", 5640ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 5641ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5642ecd94f1bSKan Liang "SampleAfterValue": "100003", 5643ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 5644ecd94f1bSKan Liang }, 5645ecd94f1bSKan Liang { 5646ecd94f1bSKan Liang "Offcore": "1", 5647ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 5648ecd94f1bSKan Liang "UMask": "0x1", 5649ecd94f1bSKan Liang "BriefDescription": "Counts all demand data writes (RFOs) TBD", 5650ecd94f1bSKan Liang "MSRValue": "0x0104000002", 5651ecd94f1bSKan Liang "Counter": "0,1,2,3", 5652ecd94f1bSKan Liang "EventName": "OCR.DEMAND_RFO.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED", 5653ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 5654ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5655ecd94f1bSKan Liang "SampleAfterValue": "100003", 5656ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 5657ecd94f1bSKan Liang }, 5658ecd94f1bSKan Liang { 5659ecd94f1bSKan Liang "Offcore": "1", 5660ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 5661ecd94f1bSKan Liang "UMask": "0x1", 5662ecd94f1bSKan Liang "BriefDescription": "Counts all demand data writes (RFOs)", 5663ecd94f1bSKan Liang "MSRValue": "0x0204000002", 5664ecd94f1bSKan Liang "Counter": "0,1,2,3", 5665ecd94f1bSKan Liang "EventName": "OCR.DEMAND_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS", 5666ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 5667ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5668ecd94f1bSKan Liang "SampleAfterValue": "100003", 5669ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 5670ecd94f1bSKan Liang }, 5671ecd94f1bSKan Liang { 5672ecd94f1bSKan Liang "Offcore": "1", 5673ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 5674ecd94f1bSKan Liang "UMask": "0x1", 5675ecd94f1bSKan Liang "BriefDescription": "Counts all demand data writes (RFOs) TBD", 5676ecd94f1bSKan Liang "MSRValue": "0x0404000002", 5677ecd94f1bSKan Liang "Counter": "0,1,2,3", 5678ecd94f1bSKan Liang "EventName": "OCR.DEMAND_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD", 5679ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 5680ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5681ecd94f1bSKan Liang "SampleAfterValue": "100003", 5682ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 5683ecd94f1bSKan Liang }, 5684ecd94f1bSKan Liang { 5685ecd94f1bSKan Liang "Offcore": "1", 5686ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 5687ecd94f1bSKan Liang "UMask": "0x1", 5688ecd94f1bSKan Liang "BriefDescription": "Counts all demand data writes (RFOs) TBD", 5689ecd94f1bSKan Liang "MSRValue": "0x0804000002", 5690ecd94f1bSKan Liang "Counter": "0,1,2,3", 5691ecd94f1bSKan Liang "EventName": "OCR.DEMAND_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD", 5692ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 5693ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5694ecd94f1bSKan Liang "SampleAfterValue": "100003", 5695ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 5696ecd94f1bSKan Liang }, 5697ecd94f1bSKan Liang { 5698ecd94f1bSKan Liang "Offcore": "1", 5699ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 5700ecd94f1bSKan Liang "UMask": "0x1", 5701ecd94f1bSKan Liang "BriefDescription": "Counts all demand data writes (RFOs) TBD", 5702ecd94f1bSKan Liang "MSRValue": "0x1004000002", 5703ecd94f1bSKan Liang "Counter": "0,1,2,3", 5704ecd94f1bSKan Liang "EventName": "OCR.DEMAND_RFO.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE", 5705ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 5706ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5707ecd94f1bSKan Liang "SampleAfterValue": "100003", 5708ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 5709ecd94f1bSKan Liang }, 5710ecd94f1bSKan Liang { 5711ecd94f1bSKan Liang "Offcore": "1", 5712ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 5713ecd94f1bSKan Liang "UMask": "0x1", 5714ecd94f1bSKan Liang "BriefDescription": "Counts all demand data writes (RFOs) TBD", 5715ecd94f1bSKan Liang "MSRValue": "0x3F84000002", 5716ecd94f1bSKan Liang "Counter": "0,1,2,3", 5717ecd94f1bSKan Liang "EventName": "OCR.DEMAND_RFO.L3_MISS_LOCAL_DRAM.ANY_SNOOP", 5718ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 5719ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5720ecd94f1bSKan Liang "SampleAfterValue": "100003", 5721ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 5722ecd94f1bSKan Liang }, 5723ecd94f1bSKan Liang { 5724ecd94f1bSKan Liang "Offcore": "1", 5725ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 5726ecd94f1bSKan Liang "UMask": "0x1", 5727ecd94f1bSKan Liang "BriefDescription": "Counts all demand data writes (RFOs)", 5728ecd94f1bSKan Liang "MSRValue": "0x0090000002", 5729ecd94f1bSKan Liang "Counter": "0,1,2,3", 5730ecd94f1bSKan Liang "EventName": "OCR.DEMAND_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE", 5731ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 5732ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5733ecd94f1bSKan Liang "SampleAfterValue": "100003", 5734ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 5735ecd94f1bSKan Liang }, 5736ecd94f1bSKan Liang { 5737ecd94f1bSKan Liang "Offcore": "1", 5738ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 5739ecd94f1bSKan Liang "UMask": "0x1", 5740ecd94f1bSKan Liang "BriefDescription": "Counts all demand data writes (RFOs) TBD", 5741ecd94f1bSKan Liang "MSRValue": "0x0110000002", 5742ecd94f1bSKan Liang "Counter": "0,1,2,3", 5743ecd94f1bSKan Liang "EventName": "OCR.DEMAND_RFO.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED", 5744ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 5745ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5746ecd94f1bSKan Liang "SampleAfterValue": "100003", 5747ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 5748ecd94f1bSKan Liang }, 5749ecd94f1bSKan Liang { 5750ecd94f1bSKan Liang "Offcore": "1", 5751ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 5752ecd94f1bSKan Liang "UMask": "0x1", 5753ecd94f1bSKan Liang "BriefDescription": "Counts all demand data writes (RFOs)", 5754ecd94f1bSKan Liang "MSRValue": "0x0210000002", 5755ecd94f1bSKan Liang "Counter": "0,1,2,3", 5756ecd94f1bSKan Liang "EventName": "OCR.DEMAND_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS", 5757ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 5758ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5759ecd94f1bSKan Liang "SampleAfterValue": "100003", 5760ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 5761ecd94f1bSKan Liang }, 5762ecd94f1bSKan Liang { 5763ecd94f1bSKan Liang "Offcore": "1", 5764ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 5765ecd94f1bSKan Liang "UMask": "0x1", 5766ecd94f1bSKan Liang "BriefDescription": "Counts all demand data writes (RFOs) TBD", 5767ecd94f1bSKan Liang "MSRValue": "0x0410000002", 5768ecd94f1bSKan Liang "Counter": "0,1,2,3", 5769ecd94f1bSKan Liang "EventName": "OCR.DEMAND_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD", 5770ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 5771ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5772ecd94f1bSKan Liang "SampleAfterValue": "100003", 5773ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 5774ecd94f1bSKan Liang }, 5775ecd94f1bSKan Liang { 5776ecd94f1bSKan Liang "Offcore": "1", 5777ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 5778ecd94f1bSKan Liang "UMask": "0x1", 5779ecd94f1bSKan Liang "BriefDescription": "Counts all demand data writes (RFOs) TBD", 5780ecd94f1bSKan Liang "MSRValue": "0x0810000002", 5781ecd94f1bSKan Liang "Counter": "0,1,2,3", 5782ecd94f1bSKan Liang "EventName": "OCR.DEMAND_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD", 5783ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 5784ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5785ecd94f1bSKan Liang "SampleAfterValue": "100003", 5786ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 5787ecd94f1bSKan Liang }, 5788ecd94f1bSKan Liang { 5789ecd94f1bSKan Liang "Offcore": "1", 5790ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 5791ecd94f1bSKan Liang "UMask": "0x1", 5792ecd94f1bSKan Liang "BriefDescription": "Counts all demand data writes (RFOs) TBD", 5793ecd94f1bSKan Liang "MSRValue": "0x1010000002", 5794ecd94f1bSKan Liang "Counter": "0,1,2,3", 5795ecd94f1bSKan Liang "EventName": "OCR.DEMAND_RFO.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE", 5796ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 5797ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5798ecd94f1bSKan Liang "SampleAfterValue": "100003", 5799ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 5800ecd94f1bSKan Liang }, 5801ecd94f1bSKan Liang { 5802ecd94f1bSKan Liang "Offcore": "1", 5803ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 5804ecd94f1bSKan Liang "UMask": "0x1", 5805ecd94f1bSKan Liang "BriefDescription": "Counts all demand data writes (RFOs) TBD", 5806ecd94f1bSKan Liang "MSRValue": "0x3F90000002", 5807ecd94f1bSKan Liang "Counter": "0,1,2,3", 5808ecd94f1bSKan Liang "EventName": "OCR.DEMAND_RFO.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP", 5809ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 5810ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5811ecd94f1bSKan Liang "SampleAfterValue": "100003", 5812ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 5813ecd94f1bSKan Liang }, 5814ecd94f1bSKan Liang { 5815ecd94f1bSKan Liang "Offcore": "1", 5816ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 5817ecd94f1bSKan Liang "UMask": "0x1", 5818ecd94f1bSKan Liang "BriefDescription": "Counts all demand data writes (RFOs) TBD", 5819ecd94f1bSKan Liang "MSRValue": "0x00BC000002", 5820ecd94f1bSKan Liang "Counter": "0,1,2,3", 5821ecd94f1bSKan Liang "EventName": "OCR.DEMAND_RFO.L3_MISS.SNOOP_NONE", 5822ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 5823ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5824ecd94f1bSKan Liang "SampleAfterValue": "100003", 5825ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 5826ecd94f1bSKan Liang }, 5827ecd94f1bSKan Liang { 5828ecd94f1bSKan Liang "Offcore": "1", 5829ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 5830ecd94f1bSKan Liang "UMask": "0x1", 5831ecd94f1bSKan Liang "BriefDescription": "Counts all demand data writes (RFOs) TBD TBD", 5832ecd94f1bSKan Liang "MSRValue": "0x013C000002", 5833ecd94f1bSKan Liang "Counter": "0,1,2,3", 5834ecd94f1bSKan Liang "EventName": "OCR.DEMAND_RFO.L3_MISS.NO_SNOOP_NEEDED", 5835ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 5836ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5837ecd94f1bSKan Liang "SampleAfterValue": "100003", 5838ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 5839ecd94f1bSKan Liang }, 5840ecd94f1bSKan Liang { 5841ecd94f1bSKan Liang "Offcore": "1", 5842ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 5843ecd94f1bSKan Liang "UMask": "0x1", 5844ecd94f1bSKan Liang "BriefDescription": "Counts all demand data writes (RFOs) TBD", 5845ecd94f1bSKan Liang "MSRValue": "0x023C000002", 5846ecd94f1bSKan Liang "Counter": "0,1,2,3", 5847ecd94f1bSKan Liang "EventName": "OCR.DEMAND_RFO.L3_MISS.SNOOP_MISS", 5848ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 5849ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5850ecd94f1bSKan Liang "SampleAfterValue": "100003", 5851ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 5852ecd94f1bSKan Liang }, 5853ecd94f1bSKan Liang { 5854ecd94f1bSKan Liang "Offcore": "1", 5855ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 5856ecd94f1bSKan Liang "UMask": "0x1", 5857ecd94f1bSKan Liang "BriefDescription": "Counts all demand data writes (RFOs) TBD TBD", 5858ecd94f1bSKan Liang "MSRValue": "0x043C000002", 5859ecd94f1bSKan Liang "Counter": "0,1,2,3", 5860ecd94f1bSKan Liang "EventName": "OCR.DEMAND_RFO.L3_MISS.HIT_OTHER_CORE_NO_FWD", 5861ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 5862ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5863ecd94f1bSKan Liang "SampleAfterValue": "100003", 5864ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 5865ecd94f1bSKan Liang }, 5866ecd94f1bSKan Liang { 5867ecd94f1bSKan Liang "Offcore": "1", 5868ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 5869ecd94f1bSKan Liang "UMask": "0x1", 5870ecd94f1bSKan Liang "BriefDescription": "Counts all demand data writes (RFOs) TBD TBD", 5871ecd94f1bSKan Liang "MSRValue": "0x083C000002", 5872ecd94f1bSKan Liang "Counter": "0,1,2,3", 5873ecd94f1bSKan Liang "EventName": "OCR.DEMAND_RFO.L3_MISS.HIT_OTHER_CORE_FWD", 5874ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 5875ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5876ecd94f1bSKan Liang "SampleAfterValue": "100003", 5877ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 5878ecd94f1bSKan Liang }, 5879ecd94f1bSKan Liang { 5880ecd94f1bSKan Liang "Offcore": "1", 5881ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 5882ecd94f1bSKan Liang "UMask": "0x1", 5883ecd94f1bSKan Liang "BriefDescription": "Counts all demand data writes (RFOs) TBD TBD", 5884ecd94f1bSKan Liang "MSRValue": "0x103C000002", 5885ecd94f1bSKan Liang "Counter": "0,1,2,3", 5886ecd94f1bSKan Liang "EventName": "OCR.DEMAND_RFO.L3_MISS.HITM_OTHER_CORE", 5887ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 5888ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5889ecd94f1bSKan Liang "SampleAfterValue": "100003", 5890ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 5891ecd94f1bSKan Liang }, 5892ecd94f1bSKan Liang { 5893ecd94f1bSKan Liang "Offcore": "1", 5894ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 5895ecd94f1bSKan Liang "UMask": "0x1", 5896ecd94f1bSKan Liang "BriefDescription": "Counts all demand data writes (RFOs) TBD TBD", 5897ecd94f1bSKan Liang "MSRValue": "0x3FBC000002", 5898ecd94f1bSKan Liang "Counter": "0,1,2,3", 5899ecd94f1bSKan Liang "EventName": "OCR.DEMAND_RFO.L3_MISS.ANY_SNOOP", 5900ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 5901ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5902ecd94f1bSKan Liang "SampleAfterValue": "100003", 5903ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 5904ecd94f1bSKan Liang }, 5905ecd94f1bSKan Liang { 5906ecd94f1bSKan Liang "Offcore": "1", 5907ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 5908ecd94f1bSKan Liang "UMask": "0x1", 5909ecd94f1bSKan Liang "BriefDescription": "Counts all demand code reads", 5910ecd94f1bSKan Liang "MSRValue": "0x0084000004", 5911ecd94f1bSKan Liang "Counter": "0,1,2,3", 5912ecd94f1bSKan Liang "EventName": "OCR.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_NONE", 5913ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 5914ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5915ecd94f1bSKan Liang "SampleAfterValue": "100003", 5916ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 5917ecd94f1bSKan Liang }, 5918ecd94f1bSKan Liang { 5919ecd94f1bSKan Liang "Offcore": "1", 5920ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 5921ecd94f1bSKan Liang "UMask": "0x1", 5922ecd94f1bSKan Liang "BriefDescription": "Counts all demand code reads TBD", 5923ecd94f1bSKan Liang "MSRValue": "0x0104000004", 5924ecd94f1bSKan Liang "Counter": "0,1,2,3", 5925ecd94f1bSKan Liang "EventName": "OCR.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED", 5926ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 5927ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5928ecd94f1bSKan Liang "SampleAfterValue": "100003", 5929ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 5930ecd94f1bSKan Liang }, 5931ecd94f1bSKan Liang { 5932ecd94f1bSKan Liang "Offcore": "1", 5933ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 5934ecd94f1bSKan Liang "UMask": "0x1", 5935ecd94f1bSKan Liang "BriefDescription": "Counts all demand code reads", 5936ecd94f1bSKan Liang "MSRValue": "0x0204000004", 5937ecd94f1bSKan Liang "Counter": "0,1,2,3", 5938ecd94f1bSKan Liang "EventName": "OCR.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS", 5939ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 5940ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5941ecd94f1bSKan Liang "SampleAfterValue": "100003", 5942ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 5943ecd94f1bSKan Liang }, 5944ecd94f1bSKan Liang { 5945ecd94f1bSKan Liang "Offcore": "1", 5946ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 5947ecd94f1bSKan Liang "UMask": "0x1", 5948ecd94f1bSKan Liang "BriefDescription": "Counts all demand code reads TBD", 5949ecd94f1bSKan Liang "MSRValue": "0x0404000004", 5950ecd94f1bSKan Liang "Counter": "0,1,2,3", 5951ecd94f1bSKan Liang "EventName": "OCR.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD", 5952ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 5953ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5954ecd94f1bSKan Liang "SampleAfterValue": "100003", 5955ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 5956ecd94f1bSKan Liang }, 5957ecd94f1bSKan Liang { 5958ecd94f1bSKan Liang "Offcore": "1", 5959ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 5960ecd94f1bSKan Liang "UMask": "0x1", 5961ecd94f1bSKan Liang "BriefDescription": "Counts all demand code reads TBD", 5962ecd94f1bSKan Liang "MSRValue": "0x0804000004", 5963ecd94f1bSKan Liang "Counter": "0,1,2,3", 5964ecd94f1bSKan Liang "EventName": "OCR.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD", 5965ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 5966ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5967ecd94f1bSKan Liang "SampleAfterValue": "100003", 5968ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 5969ecd94f1bSKan Liang }, 5970ecd94f1bSKan Liang { 5971ecd94f1bSKan Liang "Offcore": "1", 5972ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 5973ecd94f1bSKan Liang "UMask": "0x1", 5974ecd94f1bSKan Liang "BriefDescription": "Counts all demand code reads TBD", 5975ecd94f1bSKan Liang "MSRValue": "0x1004000004", 5976ecd94f1bSKan Liang "Counter": "0,1,2,3", 5977ecd94f1bSKan Liang "EventName": "OCR.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE", 5978ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 5979ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5980ecd94f1bSKan Liang "SampleAfterValue": "100003", 5981ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 5982ecd94f1bSKan Liang }, 5983ecd94f1bSKan Liang { 5984ecd94f1bSKan Liang "Offcore": "1", 5985ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 5986ecd94f1bSKan Liang "UMask": "0x1", 5987ecd94f1bSKan Liang "BriefDescription": "Counts all demand code reads TBD", 5988ecd94f1bSKan Liang "MSRValue": "0x3F84000004", 5989ecd94f1bSKan Liang "Counter": "0,1,2,3", 5990ecd94f1bSKan Liang "EventName": "OCR.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP", 5991ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 5992ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5993ecd94f1bSKan Liang "SampleAfterValue": "100003", 5994ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 5995ecd94f1bSKan Liang }, 5996ecd94f1bSKan Liang { 5997ecd94f1bSKan Liang "Offcore": "1", 5998ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 5999ecd94f1bSKan Liang "UMask": "0x1", 6000ecd94f1bSKan Liang "BriefDescription": "Counts all demand code reads", 6001ecd94f1bSKan Liang "MSRValue": "0x0090000004", 6002ecd94f1bSKan Liang "Counter": "0,1,2,3", 6003ecd94f1bSKan Liang "EventName": "OCR.DEMAND_CODE_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE", 6004ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 6005ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6006ecd94f1bSKan Liang "SampleAfterValue": "100003", 6007ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 6008ecd94f1bSKan Liang }, 6009ecd94f1bSKan Liang { 6010ecd94f1bSKan Liang "Offcore": "1", 6011ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 6012ecd94f1bSKan Liang "UMask": "0x1", 6013ecd94f1bSKan Liang "BriefDescription": "Counts all demand code reads TBD", 6014ecd94f1bSKan Liang "MSRValue": "0x0110000004", 6015ecd94f1bSKan Liang "Counter": "0,1,2,3", 6016ecd94f1bSKan Liang "EventName": "OCR.DEMAND_CODE_RD.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED", 6017ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 6018ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6019ecd94f1bSKan Liang "SampleAfterValue": "100003", 6020ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 6021ecd94f1bSKan Liang }, 6022ecd94f1bSKan Liang { 6023ecd94f1bSKan Liang "Offcore": "1", 6024ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 6025ecd94f1bSKan Liang "UMask": "0x1", 6026ecd94f1bSKan Liang "BriefDescription": "Counts all demand code reads", 6027ecd94f1bSKan Liang "MSRValue": "0x0210000004", 6028ecd94f1bSKan Liang "Counter": "0,1,2,3", 6029ecd94f1bSKan Liang "EventName": "OCR.DEMAND_CODE_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS", 6030ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 6031ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6032ecd94f1bSKan Liang "SampleAfterValue": "100003", 6033ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 6034ecd94f1bSKan Liang }, 6035ecd94f1bSKan Liang { 6036ecd94f1bSKan Liang "Offcore": "1", 6037ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 6038ecd94f1bSKan Liang "UMask": "0x1", 6039ecd94f1bSKan Liang "BriefDescription": "Counts all demand code reads TBD", 6040ecd94f1bSKan Liang "MSRValue": "0x0410000004", 6041ecd94f1bSKan Liang "Counter": "0,1,2,3", 6042ecd94f1bSKan Liang "EventName": "OCR.DEMAND_CODE_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD", 6043ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 6044ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6045ecd94f1bSKan Liang "SampleAfterValue": "100003", 6046ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 6047ecd94f1bSKan Liang }, 6048ecd94f1bSKan Liang { 6049ecd94f1bSKan Liang "Offcore": "1", 6050ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 6051ecd94f1bSKan Liang "UMask": "0x1", 6052ecd94f1bSKan Liang "BriefDescription": "Counts all demand code reads TBD", 6053ecd94f1bSKan Liang "MSRValue": "0x0810000004", 6054ecd94f1bSKan Liang "Counter": "0,1,2,3", 6055ecd94f1bSKan Liang "EventName": "OCR.DEMAND_CODE_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD", 6056ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 6057ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6058ecd94f1bSKan Liang "SampleAfterValue": "100003", 6059ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 6060ecd94f1bSKan Liang }, 6061ecd94f1bSKan Liang { 6062ecd94f1bSKan Liang "Offcore": "1", 6063ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 6064ecd94f1bSKan Liang "UMask": "0x1", 6065ecd94f1bSKan Liang "BriefDescription": "Counts all demand code reads TBD", 6066ecd94f1bSKan Liang "MSRValue": "0x1010000004", 6067ecd94f1bSKan Liang "Counter": "0,1,2,3", 6068ecd94f1bSKan Liang "EventName": "OCR.DEMAND_CODE_RD.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE", 6069ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 6070ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6071ecd94f1bSKan Liang "SampleAfterValue": "100003", 6072ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 6073ecd94f1bSKan Liang }, 6074ecd94f1bSKan Liang { 6075ecd94f1bSKan Liang "Offcore": "1", 6076ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 6077ecd94f1bSKan Liang "UMask": "0x1", 6078ecd94f1bSKan Liang "BriefDescription": "Counts all demand code reads TBD", 6079ecd94f1bSKan Liang "MSRValue": "0x3F90000004", 6080ecd94f1bSKan Liang "Counter": "0,1,2,3", 6081ecd94f1bSKan Liang "EventName": "OCR.DEMAND_CODE_RD.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP", 6082ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 6083ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6084ecd94f1bSKan Liang "SampleAfterValue": "100003", 6085ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 6086ecd94f1bSKan Liang }, 6087ecd94f1bSKan Liang { 6088ecd94f1bSKan Liang "Offcore": "1", 6089ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 6090ecd94f1bSKan Liang "UMask": "0x1", 6091ecd94f1bSKan Liang "BriefDescription": "Counts all demand code reads TBD", 6092ecd94f1bSKan Liang "MSRValue": "0x00BC000004", 6093ecd94f1bSKan Liang "Counter": "0,1,2,3", 6094ecd94f1bSKan Liang "EventName": "OCR.DEMAND_CODE_RD.L3_MISS.SNOOP_NONE", 6095ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 6096ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6097ecd94f1bSKan Liang "SampleAfterValue": "100003", 6098ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 6099ecd94f1bSKan Liang }, 6100ecd94f1bSKan Liang { 6101ecd94f1bSKan Liang "Offcore": "1", 6102ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 6103ecd94f1bSKan Liang "UMask": "0x1", 6104ecd94f1bSKan Liang "BriefDescription": "Counts all demand code reads TBD TBD", 6105ecd94f1bSKan Liang "MSRValue": "0x013C000004", 6106ecd94f1bSKan Liang "Counter": "0,1,2,3", 6107ecd94f1bSKan Liang "EventName": "OCR.DEMAND_CODE_RD.L3_MISS.NO_SNOOP_NEEDED", 6108ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 6109ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6110ecd94f1bSKan Liang "SampleAfterValue": "100003", 6111ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 6112ecd94f1bSKan Liang }, 6113ecd94f1bSKan Liang { 6114ecd94f1bSKan Liang "Offcore": "1", 6115ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 6116ecd94f1bSKan Liang "UMask": "0x1", 6117ecd94f1bSKan Liang "BriefDescription": "Counts all demand code reads TBD", 6118ecd94f1bSKan Liang "MSRValue": "0x023C000004", 6119ecd94f1bSKan Liang "Counter": "0,1,2,3", 6120ecd94f1bSKan Liang "EventName": "OCR.DEMAND_CODE_RD.L3_MISS.SNOOP_MISS", 6121ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 6122ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6123ecd94f1bSKan Liang "SampleAfterValue": "100003", 6124ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 6125ecd94f1bSKan Liang }, 6126ecd94f1bSKan Liang { 6127ecd94f1bSKan Liang "Offcore": "1", 6128ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 6129ecd94f1bSKan Liang "UMask": "0x1", 6130ecd94f1bSKan Liang "BriefDescription": "Counts all demand code reads TBD TBD", 6131ecd94f1bSKan Liang "MSRValue": "0x043C000004", 6132ecd94f1bSKan Liang "Counter": "0,1,2,3", 6133ecd94f1bSKan Liang "EventName": "OCR.DEMAND_CODE_RD.L3_MISS.HIT_OTHER_CORE_NO_FWD", 6134ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 6135ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6136ecd94f1bSKan Liang "SampleAfterValue": "100003", 6137ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 6138ecd94f1bSKan Liang }, 6139ecd94f1bSKan Liang { 6140ecd94f1bSKan Liang "Offcore": "1", 6141ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 6142ecd94f1bSKan Liang "UMask": "0x1", 6143ecd94f1bSKan Liang "BriefDescription": "Counts all demand code reads TBD TBD", 6144ecd94f1bSKan Liang "MSRValue": "0x083C000004", 6145ecd94f1bSKan Liang "Counter": "0,1,2,3", 6146ecd94f1bSKan Liang "EventName": "OCR.DEMAND_CODE_RD.L3_MISS.HIT_OTHER_CORE_FWD", 6147ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 6148ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6149ecd94f1bSKan Liang "SampleAfterValue": "100003", 6150ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 6151ecd94f1bSKan Liang }, 6152ecd94f1bSKan Liang { 6153ecd94f1bSKan Liang "Offcore": "1", 6154ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 6155ecd94f1bSKan Liang "UMask": "0x1", 6156ecd94f1bSKan Liang "BriefDescription": "Counts all demand code reads TBD TBD", 6157ecd94f1bSKan Liang "MSRValue": "0x103C000004", 6158ecd94f1bSKan Liang "Counter": "0,1,2,3", 6159ecd94f1bSKan Liang "EventName": "OCR.DEMAND_CODE_RD.L3_MISS.HITM_OTHER_CORE", 6160ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 6161ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6162ecd94f1bSKan Liang "SampleAfterValue": "100003", 6163ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 6164ecd94f1bSKan Liang }, 6165ecd94f1bSKan Liang { 6166ecd94f1bSKan Liang "Offcore": "1", 6167ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 6168ecd94f1bSKan Liang "UMask": "0x1", 6169ecd94f1bSKan Liang "BriefDescription": "Counts all demand code reads TBD TBD", 6170ecd94f1bSKan Liang "MSRValue": "0x3FBC000004", 6171ecd94f1bSKan Liang "Counter": "0,1,2,3", 6172ecd94f1bSKan Liang "EventName": "OCR.DEMAND_CODE_RD.L3_MISS.ANY_SNOOP", 6173ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 6174ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6175ecd94f1bSKan Liang "SampleAfterValue": "100003", 6176ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 6177ecd94f1bSKan Liang }, 6178ecd94f1bSKan Liang { 6179ecd94f1bSKan Liang "Offcore": "1", 6180ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 6181ecd94f1bSKan Liang "UMask": "0x1", 6182ecd94f1bSKan Liang "BriefDescription": "Counts prefetch (that bring data to L2) data reads", 6183ecd94f1bSKan Liang "MSRValue": "0x0084000010", 6184ecd94f1bSKan Liang "Counter": "0,1,2,3", 6185ecd94f1bSKan Liang "EventName": "OCR.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NONE", 6186ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 6187ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6188ecd94f1bSKan Liang "SampleAfterValue": "100003", 6189ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 6190ecd94f1bSKan Liang }, 6191ecd94f1bSKan Liang { 6192ecd94f1bSKan Liang "Offcore": "1", 6193ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 6194ecd94f1bSKan Liang "UMask": "0x1", 6195ecd94f1bSKan Liang "BriefDescription": "Counts prefetch (that bring data to L2) data reads TBD", 6196ecd94f1bSKan Liang "MSRValue": "0x0104000010", 6197ecd94f1bSKan Liang "Counter": "0,1,2,3", 6198ecd94f1bSKan Liang "EventName": "OCR.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED", 6199ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 6200ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6201ecd94f1bSKan Liang "SampleAfterValue": "100003", 6202ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 6203ecd94f1bSKan Liang }, 6204ecd94f1bSKan Liang { 6205ecd94f1bSKan Liang "Offcore": "1", 6206ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 6207ecd94f1bSKan Liang "UMask": "0x1", 6208ecd94f1bSKan Liang "BriefDescription": "Counts prefetch (that bring data to L2) data reads", 6209ecd94f1bSKan Liang "MSRValue": "0x0204000010", 6210ecd94f1bSKan Liang "Counter": "0,1,2,3", 6211ecd94f1bSKan Liang "EventName": "OCR.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS", 6212ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 6213ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6214ecd94f1bSKan Liang "SampleAfterValue": "100003", 6215ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 6216ecd94f1bSKan Liang }, 6217ecd94f1bSKan Liang { 6218ecd94f1bSKan Liang "Offcore": "1", 6219ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 6220ecd94f1bSKan Liang "UMask": "0x1", 6221ecd94f1bSKan Liang "BriefDescription": "Counts prefetch (that bring data to L2) data reads TBD", 6222ecd94f1bSKan Liang "MSRValue": "0x0404000010", 6223ecd94f1bSKan Liang "Counter": "0,1,2,3", 6224ecd94f1bSKan Liang "EventName": "OCR.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD", 6225ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 6226ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6227ecd94f1bSKan Liang "SampleAfterValue": "100003", 6228ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 6229ecd94f1bSKan Liang }, 6230ecd94f1bSKan Liang { 6231ecd94f1bSKan Liang "Offcore": "1", 6232ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 6233ecd94f1bSKan Liang "UMask": "0x1", 6234ecd94f1bSKan Liang "BriefDescription": "Counts prefetch (that bring data to L2) data reads TBD", 6235ecd94f1bSKan Liang "MSRValue": "0x0804000010", 6236ecd94f1bSKan Liang "Counter": "0,1,2,3", 6237ecd94f1bSKan Liang "EventName": "OCR.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD", 6238ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 6239ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6240ecd94f1bSKan Liang "SampleAfterValue": "100003", 6241ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 6242ecd94f1bSKan Liang }, 6243ecd94f1bSKan Liang { 6244ecd94f1bSKan Liang "Offcore": "1", 6245ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 6246ecd94f1bSKan Liang "UMask": "0x1", 6247ecd94f1bSKan Liang "BriefDescription": "Counts prefetch (that bring data to L2) data reads TBD", 6248ecd94f1bSKan Liang "MSRValue": "0x1004000010", 6249ecd94f1bSKan Liang "Counter": "0,1,2,3", 6250ecd94f1bSKan Liang "EventName": "OCR.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE", 6251ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 6252ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6253ecd94f1bSKan Liang "SampleAfterValue": "100003", 6254ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 6255ecd94f1bSKan Liang }, 6256ecd94f1bSKan Liang { 6257ecd94f1bSKan Liang "Offcore": "1", 6258ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 6259ecd94f1bSKan Liang "UMask": "0x1", 6260ecd94f1bSKan Liang "BriefDescription": "Counts prefetch (that bring data to L2) data reads TBD", 6261ecd94f1bSKan Liang "MSRValue": "0x3F84000010", 6262ecd94f1bSKan Liang "Counter": "0,1,2,3", 6263ecd94f1bSKan Liang "EventName": "OCR.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP", 6264ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 6265ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6266ecd94f1bSKan Liang "SampleAfterValue": "100003", 6267ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 6268ecd94f1bSKan Liang }, 6269ecd94f1bSKan Liang { 6270ecd94f1bSKan Liang "Offcore": "1", 6271ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 6272ecd94f1bSKan Liang "UMask": "0x1", 6273ecd94f1bSKan Liang "BriefDescription": "Counts prefetch (that bring data to L2) data reads", 6274ecd94f1bSKan Liang "MSRValue": "0x0090000010", 6275ecd94f1bSKan Liang "Counter": "0,1,2,3", 6276ecd94f1bSKan Liang "EventName": "OCR.PF_L2_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE", 6277ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 6278ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6279ecd94f1bSKan Liang "SampleAfterValue": "100003", 6280ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 6281ecd94f1bSKan Liang }, 6282ecd94f1bSKan Liang { 6283ecd94f1bSKan Liang "Offcore": "1", 6284ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 6285ecd94f1bSKan Liang "UMask": "0x1", 6286ecd94f1bSKan Liang "BriefDescription": "Counts prefetch (that bring data to L2) data reads TBD", 6287ecd94f1bSKan Liang "MSRValue": "0x0110000010", 6288ecd94f1bSKan Liang "Counter": "0,1,2,3", 6289ecd94f1bSKan Liang "EventName": "OCR.PF_L2_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED", 6290ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 6291ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6292ecd94f1bSKan Liang "SampleAfterValue": "100003", 6293ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 6294ecd94f1bSKan Liang }, 6295ecd94f1bSKan Liang { 6296ecd94f1bSKan Liang "Offcore": "1", 6297ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 6298ecd94f1bSKan Liang "UMask": "0x1", 6299ecd94f1bSKan Liang "BriefDescription": "Counts prefetch (that bring data to L2) data reads", 6300ecd94f1bSKan Liang "MSRValue": "0x0210000010", 6301ecd94f1bSKan Liang "Counter": "0,1,2,3", 6302ecd94f1bSKan Liang "EventName": "OCR.PF_L2_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS", 6303ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 6304ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6305ecd94f1bSKan Liang "SampleAfterValue": "100003", 6306ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 6307ecd94f1bSKan Liang }, 6308ecd94f1bSKan Liang { 6309ecd94f1bSKan Liang "Offcore": "1", 6310ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 6311ecd94f1bSKan Liang "UMask": "0x1", 6312ecd94f1bSKan Liang "BriefDescription": "Counts prefetch (that bring data to L2) data reads TBD", 6313ecd94f1bSKan Liang "MSRValue": "0x0410000010", 6314ecd94f1bSKan Liang "Counter": "0,1,2,3", 6315ecd94f1bSKan Liang "EventName": "OCR.PF_L2_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD", 6316ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 6317ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6318ecd94f1bSKan Liang "SampleAfterValue": "100003", 6319ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 6320ecd94f1bSKan Liang }, 6321ecd94f1bSKan Liang { 6322ecd94f1bSKan Liang "Offcore": "1", 6323ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 6324ecd94f1bSKan Liang "UMask": "0x1", 6325ecd94f1bSKan Liang "BriefDescription": "Counts prefetch (that bring data to L2) data reads TBD", 6326ecd94f1bSKan Liang "MSRValue": "0x0810000010", 6327ecd94f1bSKan Liang "Counter": "0,1,2,3", 6328ecd94f1bSKan Liang "EventName": "OCR.PF_L2_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD", 6329ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 6330ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6331ecd94f1bSKan Liang "SampleAfterValue": "100003", 6332ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 6333ecd94f1bSKan Liang }, 6334ecd94f1bSKan Liang { 6335ecd94f1bSKan Liang "Offcore": "1", 6336ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 6337ecd94f1bSKan Liang "UMask": "0x1", 6338ecd94f1bSKan Liang "BriefDescription": "Counts prefetch (that bring data to L2) data reads TBD", 6339ecd94f1bSKan Liang "MSRValue": "0x1010000010", 6340ecd94f1bSKan Liang "Counter": "0,1,2,3", 6341ecd94f1bSKan Liang "EventName": "OCR.PF_L2_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE", 6342ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 6343ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6344ecd94f1bSKan Liang "SampleAfterValue": "100003", 6345ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 6346ecd94f1bSKan Liang }, 6347ecd94f1bSKan Liang { 6348ecd94f1bSKan Liang "Offcore": "1", 6349ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 6350ecd94f1bSKan Liang "UMask": "0x1", 6351ecd94f1bSKan Liang "BriefDescription": "Counts prefetch (that bring data to L2) data reads TBD", 6352ecd94f1bSKan Liang "MSRValue": "0x3F90000010", 6353ecd94f1bSKan Liang "Counter": "0,1,2,3", 6354ecd94f1bSKan Liang "EventName": "OCR.PF_L2_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP", 6355ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 6356ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6357ecd94f1bSKan Liang "SampleAfterValue": "100003", 6358ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 6359ecd94f1bSKan Liang }, 6360ecd94f1bSKan Liang { 6361ecd94f1bSKan Liang "Offcore": "1", 6362ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 6363ecd94f1bSKan Liang "UMask": "0x1", 6364ecd94f1bSKan Liang "BriefDescription": "Counts prefetch (that bring data to L2) data reads TBD", 6365ecd94f1bSKan Liang "MSRValue": "0x00BC000010", 6366ecd94f1bSKan Liang "Counter": "0,1,2,3", 6367ecd94f1bSKan Liang "EventName": "OCR.PF_L2_DATA_RD.L3_MISS.SNOOP_NONE", 6368ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 6369ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6370ecd94f1bSKan Liang "SampleAfterValue": "100003", 6371ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 6372ecd94f1bSKan Liang }, 6373ecd94f1bSKan Liang { 6374ecd94f1bSKan Liang "Offcore": "1", 6375ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 6376ecd94f1bSKan Liang "UMask": "0x1", 6377ecd94f1bSKan Liang "BriefDescription": "Counts prefetch (that bring data to L2) data reads TBD TBD", 6378ecd94f1bSKan Liang "MSRValue": "0x013C000010", 6379ecd94f1bSKan Liang "Counter": "0,1,2,3", 6380ecd94f1bSKan Liang "EventName": "OCR.PF_L2_DATA_RD.L3_MISS.NO_SNOOP_NEEDED", 6381ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 6382ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6383ecd94f1bSKan Liang "SampleAfterValue": "100003", 6384ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 6385ecd94f1bSKan Liang }, 6386ecd94f1bSKan Liang { 6387ecd94f1bSKan Liang "Offcore": "1", 6388ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 6389ecd94f1bSKan Liang "UMask": "0x1", 6390ecd94f1bSKan Liang "BriefDescription": "Counts prefetch (that bring data to L2) data reads TBD", 6391ecd94f1bSKan Liang "MSRValue": "0x023C000010", 6392ecd94f1bSKan Liang "Counter": "0,1,2,3", 6393ecd94f1bSKan Liang "EventName": "OCR.PF_L2_DATA_RD.L3_MISS.SNOOP_MISS", 6394ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 6395ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6396ecd94f1bSKan Liang "SampleAfterValue": "100003", 6397ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 6398ecd94f1bSKan Liang }, 6399ecd94f1bSKan Liang { 6400ecd94f1bSKan Liang "Offcore": "1", 6401ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 6402ecd94f1bSKan Liang "UMask": "0x1", 6403ecd94f1bSKan Liang "BriefDescription": "Counts prefetch (that bring data to L2) data reads TBD TBD", 6404ecd94f1bSKan Liang "MSRValue": "0x043C000010", 6405ecd94f1bSKan Liang "Counter": "0,1,2,3", 6406ecd94f1bSKan Liang "EventName": "OCR.PF_L2_DATA_RD.L3_MISS.HIT_OTHER_CORE_NO_FWD", 6407ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 6408ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6409ecd94f1bSKan Liang "SampleAfterValue": "100003", 6410ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 6411ecd94f1bSKan Liang }, 6412ecd94f1bSKan Liang { 6413ecd94f1bSKan Liang "Offcore": "1", 6414ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 6415ecd94f1bSKan Liang "UMask": "0x1", 6416ecd94f1bSKan Liang "BriefDescription": "Counts prefetch (that bring data to L2) data reads TBD TBD", 6417ecd94f1bSKan Liang "MSRValue": "0x083C000010", 6418ecd94f1bSKan Liang "Counter": "0,1,2,3", 6419ecd94f1bSKan Liang "EventName": "OCR.PF_L2_DATA_RD.L3_MISS.HIT_OTHER_CORE_FWD", 6420ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 6421ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6422ecd94f1bSKan Liang "SampleAfterValue": "100003", 6423ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 6424ecd94f1bSKan Liang }, 6425ecd94f1bSKan Liang { 6426ecd94f1bSKan Liang "Offcore": "1", 6427ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 6428ecd94f1bSKan Liang "UMask": "0x1", 6429ecd94f1bSKan Liang "BriefDescription": "Counts prefetch (that bring data to L2) data reads TBD TBD", 6430ecd94f1bSKan Liang "MSRValue": "0x103C000010", 6431ecd94f1bSKan Liang "Counter": "0,1,2,3", 6432ecd94f1bSKan Liang "EventName": "OCR.PF_L2_DATA_RD.L3_MISS.HITM_OTHER_CORE", 6433ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 6434ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6435ecd94f1bSKan Liang "SampleAfterValue": "100003", 6436ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 6437ecd94f1bSKan Liang }, 6438ecd94f1bSKan Liang { 6439ecd94f1bSKan Liang "Offcore": "1", 6440ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 6441ecd94f1bSKan Liang "UMask": "0x1", 6442ecd94f1bSKan Liang "BriefDescription": "Counts prefetch (that bring data to L2) data reads TBD TBD", 6443ecd94f1bSKan Liang "MSRValue": "0x3FBC000010", 6444ecd94f1bSKan Liang "Counter": "0,1,2,3", 6445ecd94f1bSKan Liang "EventName": "OCR.PF_L2_DATA_RD.L3_MISS.ANY_SNOOP", 6446ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 6447ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6448ecd94f1bSKan Liang "SampleAfterValue": "100003", 6449ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 6450ecd94f1bSKan Liang }, 6451ecd94f1bSKan Liang { 6452ecd94f1bSKan Liang "Offcore": "1", 6453ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 6454ecd94f1bSKan Liang "UMask": "0x1", 6455ecd94f1bSKan Liang "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs", 6456ecd94f1bSKan Liang "MSRValue": "0x0084000020", 6457ecd94f1bSKan Liang "Counter": "0,1,2,3", 6458ecd94f1bSKan Liang "EventName": "OCR.PF_L2_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NONE", 6459ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 6460ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6461ecd94f1bSKan Liang "SampleAfterValue": "100003", 6462ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 6463ecd94f1bSKan Liang }, 6464ecd94f1bSKan Liang { 6465ecd94f1bSKan Liang "Offcore": "1", 6466ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 6467ecd94f1bSKan Liang "UMask": "0x1", 6468ecd94f1bSKan Liang "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs TBD", 6469ecd94f1bSKan Liang "MSRValue": "0x0104000020", 6470ecd94f1bSKan Liang "Counter": "0,1,2,3", 6471ecd94f1bSKan Liang "EventName": "OCR.PF_L2_RFO.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED", 6472ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 6473ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6474ecd94f1bSKan Liang "SampleAfterValue": "100003", 6475ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 6476ecd94f1bSKan Liang }, 6477ecd94f1bSKan Liang { 6478ecd94f1bSKan Liang "Offcore": "1", 6479ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 6480ecd94f1bSKan Liang "UMask": "0x1", 6481ecd94f1bSKan Liang "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs", 6482ecd94f1bSKan Liang "MSRValue": "0x0204000020", 6483ecd94f1bSKan Liang "Counter": "0,1,2,3", 6484ecd94f1bSKan Liang "EventName": "OCR.PF_L2_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS", 6485ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 6486ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6487ecd94f1bSKan Liang "SampleAfterValue": "100003", 6488ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 6489ecd94f1bSKan Liang }, 6490ecd94f1bSKan Liang { 6491ecd94f1bSKan Liang "Offcore": "1", 6492ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 6493ecd94f1bSKan Liang "UMask": "0x1", 6494ecd94f1bSKan Liang "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs TBD", 6495ecd94f1bSKan Liang "MSRValue": "0x0404000020", 6496ecd94f1bSKan Liang "Counter": "0,1,2,3", 6497ecd94f1bSKan Liang "EventName": "OCR.PF_L2_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD", 6498ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 6499ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6500ecd94f1bSKan Liang "SampleAfterValue": "100003", 6501ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 6502ecd94f1bSKan Liang }, 6503ecd94f1bSKan Liang { 6504ecd94f1bSKan Liang "Offcore": "1", 6505ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 6506ecd94f1bSKan Liang "UMask": "0x1", 6507ecd94f1bSKan Liang "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs TBD", 6508ecd94f1bSKan Liang "MSRValue": "0x0804000020", 6509ecd94f1bSKan Liang "Counter": "0,1,2,3", 6510ecd94f1bSKan Liang "EventName": "OCR.PF_L2_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD", 6511ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 6512ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6513ecd94f1bSKan Liang "SampleAfterValue": "100003", 6514ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 6515ecd94f1bSKan Liang }, 6516ecd94f1bSKan Liang { 6517ecd94f1bSKan Liang "Offcore": "1", 6518ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 6519ecd94f1bSKan Liang "UMask": "0x1", 6520ecd94f1bSKan Liang "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs TBD", 6521ecd94f1bSKan Liang "MSRValue": "0x1004000020", 6522ecd94f1bSKan Liang "Counter": "0,1,2,3", 6523ecd94f1bSKan Liang "EventName": "OCR.PF_L2_RFO.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE", 6524ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 6525ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6526ecd94f1bSKan Liang "SampleAfterValue": "100003", 6527ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 6528ecd94f1bSKan Liang }, 6529ecd94f1bSKan Liang { 6530ecd94f1bSKan Liang "Offcore": "1", 6531ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 6532ecd94f1bSKan Liang "UMask": "0x1", 6533ecd94f1bSKan Liang "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs TBD", 6534ecd94f1bSKan Liang "MSRValue": "0x3F84000020", 6535ecd94f1bSKan Liang "Counter": "0,1,2,3", 6536ecd94f1bSKan Liang "EventName": "OCR.PF_L2_RFO.L3_MISS_LOCAL_DRAM.ANY_SNOOP", 6537ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 6538ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6539ecd94f1bSKan Liang "SampleAfterValue": "100003", 6540ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 6541ecd94f1bSKan Liang }, 6542ecd94f1bSKan Liang { 6543ecd94f1bSKan Liang "Offcore": "1", 6544ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 6545ecd94f1bSKan Liang "UMask": "0x1", 6546ecd94f1bSKan Liang "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs", 6547ecd94f1bSKan Liang "MSRValue": "0x0090000020", 6548ecd94f1bSKan Liang "Counter": "0,1,2,3", 6549ecd94f1bSKan Liang "EventName": "OCR.PF_L2_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE", 6550ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 6551ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6552ecd94f1bSKan Liang "SampleAfterValue": "100003", 6553ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 6554ecd94f1bSKan Liang }, 6555ecd94f1bSKan Liang { 6556ecd94f1bSKan Liang "Offcore": "1", 6557ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 6558ecd94f1bSKan Liang "UMask": "0x1", 6559ecd94f1bSKan Liang "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs TBD", 6560ecd94f1bSKan Liang "MSRValue": "0x0110000020", 6561ecd94f1bSKan Liang "Counter": "0,1,2,3", 6562ecd94f1bSKan Liang "EventName": "OCR.PF_L2_RFO.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED", 6563ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 6564ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6565ecd94f1bSKan Liang "SampleAfterValue": "100003", 6566ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 6567ecd94f1bSKan Liang }, 6568ecd94f1bSKan Liang { 6569ecd94f1bSKan Liang "Offcore": "1", 6570ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 6571ecd94f1bSKan Liang "UMask": "0x1", 6572ecd94f1bSKan Liang "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs", 6573ecd94f1bSKan Liang "MSRValue": "0x0210000020", 6574ecd94f1bSKan Liang "Counter": "0,1,2,3", 6575ecd94f1bSKan Liang "EventName": "OCR.PF_L2_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS", 6576ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 6577ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6578ecd94f1bSKan Liang "SampleAfterValue": "100003", 6579ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 6580ecd94f1bSKan Liang }, 6581ecd94f1bSKan Liang { 6582ecd94f1bSKan Liang "Offcore": "1", 6583ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 6584ecd94f1bSKan Liang "UMask": "0x1", 6585ecd94f1bSKan Liang "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs TBD", 6586ecd94f1bSKan Liang "MSRValue": "0x0410000020", 6587ecd94f1bSKan Liang "Counter": "0,1,2,3", 6588ecd94f1bSKan Liang "EventName": "OCR.PF_L2_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD", 6589ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 6590ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6591ecd94f1bSKan Liang "SampleAfterValue": "100003", 6592ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 6593ecd94f1bSKan Liang }, 6594ecd94f1bSKan Liang { 6595ecd94f1bSKan Liang "Offcore": "1", 6596ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 6597ecd94f1bSKan Liang "UMask": "0x1", 6598ecd94f1bSKan Liang "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs TBD", 6599ecd94f1bSKan Liang "MSRValue": "0x0810000020", 6600ecd94f1bSKan Liang "Counter": "0,1,2,3", 6601ecd94f1bSKan Liang "EventName": "OCR.PF_L2_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD", 6602ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 6603ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6604ecd94f1bSKan Liang "SampleAfterValue": "100003", 6605ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 6606ecd94f1bSKan Liang }, 6607ecd94f1bSKan Liang { 6608ecd94f1bSKan Liang "Offcore": "1", 6609ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 6610ecd94f1bSKan Liang "UMask": "0x1", 6611ecd94f1bSKan Liang "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs TBD", 6612ecd94f1bSKan Liang "MSRValue": "0x1010000020", 6613ecd94f1bSKan Liang "Counter": "0,1,2,3", 6614ecd94f1bSKan Liang "EventName": "OCR.PF_L2_RFO.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE", 6615ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 6616ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6617ecd94f1bSKan Liang "SampleAfterValue": "100003", 6618ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 6619ecd94f1bSKan Liang }, 6620ecd94f1bSKan Liang { 6621ecd94f1bSKan Liang "Offcore": "1", 6622ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 6623ecd94f1bSKan Liang "UMask": "0x1", 6624ecd94f1bSKan Liang "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs TBD", 6625ecd94f1bSKan Liang "MSRValue": "0x3F90000020", 6626ecd94f1bSKan Liang "Counter": "0,1,2,3", 6627ecd94f1bSKan Liang "EventName": "OCR.PF_L2_RFO.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP", 6628ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 6629ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6630ecd94f1bSKan Liang "SampleAfterValue": "100003", 6631ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 6632ecd94f1bSKan Liang }, 6633ecd94f1bSKan Liang { 6634ecd94f1bSKan Liang "Offcore": "1", 6635ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 6636ecd94f1bSKan Liang "UMask": "0x1", 6637ecd94f1bSKan Liang "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs TBD", 6638ecd94f1bSKan Liang "MSRValue": "0x00BC000020", 6639ecd94f1bSKan Liang "Counter": "0,1,2,3", 6640ecd94f1bSKan Liang "EventName": "OCR.PF_L2_RFO.L3_MISS.SNOOP_NONE", 6641ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 6642ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6643ecd94f1bSKan Liang "SampleAfterValue": "100003", 6644ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 6645ecd94f1bSKan Liang }, 6646ecd94f1bSKan Liang { 6647ecd94f1bSKan Liang "Offcore": "1", 6648ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 6649ecd94f1bSKan Liang "UMask": "0x1", 6650ecd94f1bSKan Liang "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs TBD TBD", 6651ecd94f1bSKan Liang "MSRValue": "0x013C000020", 6652ecd94f1bSKan Liang "Counter": "0,1,2,3", 6653ecd94f1bSKan Liang "EventName": "OCR.PF_L2_RFO.L3_MISS.NO_SNOOP_NEEDED", 6654ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 6655ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6656ecd94f1bSKan Liang "SampleAfterValue": "100003", 6657ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 6658ecd94f1bSKan Liang }, 6659ecd94f1bSKan Liang { 6660ecd94f1bSKan Liang "Offcore": "1", 6661ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 6662ecd94f1bSKan Liang "UMask": "0x1", 6663ecd94f1bSKan Liang "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs TBD", 6664ecd94f1bSKan Liang "MSRValue": "0x023C000020", 6665ecd94f1bSKan Liang "Counter": "0,1,2,3", 6666ecd94f1bSKan Liang "EventName": "OCR.PF_L2_RFO.L3_MISS.SNOOP_MISS", 6667ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 6668ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6669ecd94f1bSKan Liang "SampleAfterValue": "100003", 6670ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 6671ecd94f1bSKan Liang }, 6672ecd94f1bSKan Liang { 6673ecd94f1bSKan Liang "Offcore": "1", 6674ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 6675ecd94f1bSKan Liang "UMask": "0x1", 6676ecd94f1bSKan Liang "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs TBD TBD", 6677ecd94f1bSKan Liang "MSRValue": "0x043C000020", 6678ecd94f1bSKan Liang "Counter": "0,1,2,3", 6679ecd94f1bSKan Liang "EventName": "OCR.PF_L2_RFO.L3_MISS.HIT_OTHER_CORE_NO_FWD", 6680ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 6681ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6682ecd94f1bSKan Liang "SampleAfterValue": "100003", 6683ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 6684ecd94f1bSKan Liang }, 6685ecd94f1bSKan Liang { 6686ecd94f1bSKan Liang "Offcore": "1", 6687ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 6688ecd94f1bSKan Liang "UMask": "0x1", 6689ecd94f1bSKan Liang "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs TBD TBD", 6690ecd94f1bSKan Liang "MSRValue": "0x083C000020", 6691ecd94f1bSKan Liang "Counter": "0,1,2,3", 6692ecd94f1bSKan Liang "EventName": "OCR.PF_L2_RFO.L3_MISS.HIT_OTHER_CORE_FWD", 6693ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 6694ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6695ecd94f1bSKan Liang "SampleAfterValue": "100003", 6696ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 6697ecd94f1bSKan Liang }, 6698ecd94f1bSKan Liang { 6699ecd94f1bSKan Liang "Offcore": "1", 6700ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 6701ecd94f1bSKan Liang "UMask": "0x1", 6702ecd94f1bSKan Liang "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs TBD TBD", 6703ecd94f1bSKan Liang "MSRValue": "0x103C000020", 6704ecd94f1bSKan Liang "Counter": "0,1,2,3", 6705ecd94f1bSKan Liang "EventName": "OCR.PF_L2_RFO.L3_MISS.HITM_OTHER_CORE", 6706ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 6707ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6708ecd94f1bSKan Liang "SampleAfterValue": "100003", 6709ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 6710ecd94f1bSKan Liang }, 6711ecd94f1bSKan Liang { 6712ecd94f1bSKan Liang "Offcore": "1", 6713ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 6714ecd94f1bSKan Liang "UMask": "0x1", 6715ecd94f1bSKan Liang "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs TBD TBD", 6716ecd94f1bSKan Liang "MSRValue": "0x3FBC000020", 6717ecd94f1bSKan Liang "Counter": "0,1,2,3", 6718ecd94f1bSKan Liang "EventName": "OCR.PF_L2_RFO.L3_MISS.ANY_SNOOP", 6719ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 6720ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6721ecd94f1bSKan Liang "SampleAfterValue": "100003", 6722ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 6723ecd94f1bSKan Liang }, 6724ecd94f1bSKan Liang { 6725ecd94f1bSKan Liang "Offcore": "1", 6726ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 6727ecd94f1bSKan Liang "UMask": "0x1", 6728ecd94f1bSKan Liang "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads", 6729ecd94f1bSKan Liang "MSRValue": "0x0084000080", 6730ecd94f1bSKan Liang "Counter": "0,1,2,3", 6731ecd94f1bSKan Liang "EventName": "OCR.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NONE", 6732ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 6733ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6734ecd94f1bSKan Liang "SampleAfterValue": "100003", 6735ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 6736ecd94f1bSKan Liang }, 6737ecd94f1bSKan Liang { 6738ecd94f1bSKan Liang "Offcore": "1", 6739ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 6740ecd94f1bSKan Liang "UMask": "0x1", 6741ecd94f1bSKan Liang "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads TBD", 6742ecd94f1bSKan Liang "MSRValue": "0x0104000080", 6743ecd94f1bSKan Liang "Counter": "0,1,2,3", 6744ecd94f1bSKan Liang "EventName": "OCR.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED", 6745ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 6746ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6747ecd94f1bSKan Liang "SampleAfterValue": "100003", 6748ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 6749ecd94f1bSKan Liang }, 6750ecd94f1bSKan Liang { 6751ecd94f1bSKan Liang "Offcore": "1", 6752ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 6753ecd94f1bSKan Liang "UMask": "0x1", 6754ecd94f1bSKan Liang "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads", 6755ecd94f1bSKan Liang "MSRValue": "0x0204000080", 6756ecd94f1bSKan Liang "Counter": "0,1,2,3", 6757ecd94f1bSKan Liang "EventName": "OCR.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS", 6758ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 6759ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6760ecd94f1bSKan Liang "SampleAfterValue": "100003", 6761ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 6762ecd94f1bSKan Liang }, 6763ecd94f1bSKan Liang { 6764ecd94f1bSKan Liang "Offcore": "1", 6765ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 6766ecd94f1bSKan Liang "UMask": "0x1", 6767ecd94f1bSKan Liang "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads TBD", 6768ecd94f1bSKan Liang "MSRValue": "0x0404000080", 6769ecd94f1bSKan Liang "Counter": "0,1,2,3", 6770ecd94f1bSKan Liang "EventName": "OCR.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD", 6771ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 6772ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6773ecd94f1bSKan Liang "SampleAfterValue": "100003", 6774ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 6775ecd94f1bSKan Liang }, 6776ecd94f1bSKan Liang { 6777ecd94f1bSKan Liang "Offcore": "1", 6778ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 6779ecd94f1bSKan Liang "UMask": "0x1", 6780ecd94f1bSKan Liang "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads TBD", 6781ecd94f1bSKan Liang "MSRValue": "0x0804000080", 6782ecd94f1bSKan Liang "Counter": "0,1,2,3", 6783ecd94f1bSKan Liang "EventName": "OCR.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD", 6784ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 6785ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6786ecd94f1bSKan Liang "SampleAfterValue": "100003", 6787ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 6788ecd94f1bSKan Liang }, 6789ecd94f1bSKan Liang { 6790ecd94f1bSKan Liang "Offcore": "1", 6791ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 6792ecd94f1bSKan Liang "UMask": "0x1", 6793ecd94f1bSKan Liang "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads TBD", 6794ecd94f1bSKan Liang "MSRValue": "0x1004000080", 6795ecd94f1bSKan Liang "Counter": "0,1,2,3", 6796ecd94f1bSKan Liang "EventName": "OCR.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE", 6797ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 6798ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6799ecd94f1bSKan Liang "SampleAfterValue": "100003", 6800ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 6801ecd94f1bSKan Liang }, 6802ecd94f1bSKan Liang { 6803ecd94f1bSKan Liang "Offcore": "1", 6804ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 6805ecd94f1bSKan Liang "UMask": "0x1", 6806ecd94f1bSKan Liang "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads TBD", 6807ecd94f1bSKan Liang "MSRValue": "0x3F84000080", 6808ecd94f1bSKan Liang "Counter": "0,1,2,3", 6809ecd94f1bSKan Liang "EventName": "OCR.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP", 6810ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 6811ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6812ecd94f1bSKan Liang "SampleAfterValue": "100003", 6813ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 6814ecd94f1bSKan Liang }, 6815ecd94f1bSKan Liang { 6816ecd94f1bSKan Liang "Offcore": "1", 6817ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 6818ecd94f1bSKan Liang "UMask": "0x1", 6819ecd94f1bSKan Liang "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads", 6820ecd94f1bSKan Liang "MSRValue": "0x0090000080", 6821ecd94f1bSKan Liang "Counter": "0,1,2,3", 6822ecd94f1bSKan Liang "EventName": "OCR.PF_L3_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE", 6823ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 6824ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6825ecd94f1bSKan Liang "SampleAfterValue": "100003", 6826ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 6827ecd94f1bSKan Liang }, 6828ecd94f1bSKan Liang { 6829ecd94f1bSKan Liang "Offcore": "1", 6830ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 6831ecd94f1bSKan Liang "UMask": "0x1", 6832ecd94f1bSKan Liang "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads TBD", 6833ecd94f1bSKan Liang "MSRValue": "0x0110000080", 6834ecd94f1bSKan Liang "Counter": "0,1,2,3", 6835ecd94f1bSKan Liang "EventName": "OCR.PF_L3_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED", 6836ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 6837ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6838ecd94f1bSKan Liang "SampleAfterValue": "100003", 6839ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 6840ecd94f1bSKan Liang }, 6841ecd94f1bSKan Liang { 6842ecd94f1bSKan Liang "Offcore": "1", 6843ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 6844ecd94f1bSKan Liang "UMask": "0x1", 6845ecd94f1bSKan Liang "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads", 6846ecd94f1bSKan Liang "MSRValue": "0x0210000080", 6847ecd94f1bSKan Liang "Counter": "0,1,2,3", 6848ecd94f1bSKan Liang "EventName": "OCR.PF_L3_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS", 6849ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 6850ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6851ecd94f1bSKan Liang "SampleAfterValue": "100003", 6852ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 6853ecd94f1bSKan Liang }, 6854ecd94f1bSKan Liang { 6855ecd94f1bSKan Liang "Offcore": "1", 6856ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 6857ecd94f1bSKan Liang "UMask": "0x1", 6858ecd94f1bSKan Liang "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads TBD", 6859ecd94f1bSKan Liang "MSRValue": "0x0410000080", 6860ecd94f1bSKan Liang "Counter": "0,1,2,3", 6861ecd94f1bSKan Liang "EventName": "OCR.PF_L3_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD", 6862ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 6863ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6864ecd94f1bSKan Liang "SampleAfterValue": "100003", 6865ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 6866ecd94f1bSKan Liang }, 6867ecd94f1bSKan Liang { 6868ecd94f1bSKan Liang "Offcore": "1", 6869ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 6870ecd94f1bSKan Liang "UMask": "0x1", 6871ecd94f1bSKan Liang "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads TBD", 6872ecd94f1bSKan Liang "MSRValue": "0x0810000080", 6873ecd94f1bSKan Liang "Counter": "0,1,2,3", 6874ecd94f1bSKan Liang "EventName": "OCR.PF_L3_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD", 6875ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 6876ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6877ecd94f1bSKan Liang "SampleAfterValue": "100003", 6878ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 6879ecd94f1bSKan Liang }, 6880ecd94f1bSKan Liang { 6881ecd94f1bSKan Liang "Offcore": "1", 6882ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 6883ecd94f1bSKan Liang "UMask": "0x1", 6884ecd94f1bSKan Liang "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads TBD", 6885ecd94f1bSKan Liang "MSRValue": "0x1010000080", 6886ecd94f1bSKan Liang "Counter": "0,1,2,3", 6887ecd94f1bSKan Liang "EventName": "OCR.PF_L3_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE", 6888ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 6889ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6890ecd94f1bSKan Liang "SampleAfterValue": "100003", 6891ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 6892ecd94f1bSKan Liang }, 6893ecd94f1bSKan Liang { 6894ecd94f1bSKan Liang "Offcore": "1", 6895ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 6896ecd94f1bSKan Liang "UMask": "0x1", 6897ecd94f1bSKan Liang "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads TBD", 6898ecd94f1bSKan Liang "MSRValue": "0x3F90000080", 6899ecd94f1bSKan Liang "Counter": "0,1,2,3", 6900ecd94f1bSKan Liang "EventName": "OCR.PF_L3_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP", 6901ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 6902ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6903ecd94f1bSKan Liang "SampleAfterValue": "100003", 6904ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 6905ecd94f1bSKan Liang }, 6906ecd94f1bSKan Liang { 6907ecd94f1bSKan Liang "Offcore": "1", 6908ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 6909ecd94f1bSKan Liang "UMask": "0x1", 6910ecd94f1bSKan Liang "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads TBD", 6911ecd94f1bSKan Liang "MSRValue": "0x00BC000080", 6912ecd94f1bSKan Liang "Counter": "0,1,2,3", 6913ecd94f1bSKan Liang "EventName": "OCR.PF_L3_DATA_RD.L3_MISS.SNOOP_NONE", 6914ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 6915ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6916ecd94f1bSKan Liang "SampleAfterValue": "100003", 6917ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 6918ecd94f1bSKan Liang }, 6919ecd94f1bSKan Liang { 6920ecd94f1bSKan Liang "Offcore": "1", 6921ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 6922ecd94f1bSKan Liang "UMask": "0x1", 6923ecd94f1bSKan Liang "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads TBD TBD", 6924ecd94f1bSKan Liang "MSRValue": "0x013C000080", 6925ecd94f1bSKan Liang "Counter": "0,1,2,3", 6926ecd94f1bSKan Liang "EventName": "OCR.PF_L3_DATA_RD.L3_MISS.NO_SNOOP_NEEDED", 6927ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 6928ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6929ecd94f1bSKan Liang "SampleAfterValue": "100003", 6930ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 6931ecd94f1bSKan Liang }, 6932ecd94f1bSKan Liang { 6933ecd94f1bSKan Liang "Offcore": "1", 6934ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 6935ecd94f1bSKan Liang "UMask": "0x1", 6936ecd94f1bSKan Liang "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads TBD", 6937ecd94f1bSKan Liang "MSRValue": "0x023C000080", 6938ecd94f1bSKan Liang "Counter": "0,1,2,3", 6939ecd94f1bSKan Liang "EventName": "OCR.PF_L3_DATA_RD.L3_MISS.SNOOP_MISS", 6940ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 6941ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6942ecd94f1bSKan Liang "SampleAfterValue": "100003", 6943ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 6944ecd94f1bSKan Liang }, 6945ecd94f1bSKan Liang { 6946ecd94f1bSKan Liang "Offcore": "1", 6947ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 6948ecd94f1bSKan Liang "UMask": "0x1", 6949ecd94f1bSKan Liang "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads TBD TBD", 6950ecd94f1bSKan Liang "MSRValue": "0x043C000080", 6951ecd94f1bSKan Liang "Counter": "0,1,2,3", 6952ecd94f1bSKan Liang "EventName": "OCR.PF_L3_DATA_RD.L3_MISS.HIT_OTHER_CORE_NO_FWD", 6953ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 6954ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6955ecd94f1bSKan Liang "SampleAfterValue": "100003", 6956ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 6957ecd94f1bSKan Liang }, 6958ecd94f1bSKan Liang { 6959ecd94f1bSKan Liang "Offcore": "1", 6960ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 6961ecd94f1bSKan Liang "UMask": "0x1", 6962ecd94f1bSKan Liang "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads TBD TBD", 6963ecd94f1bSKan Liang "MSRValue": "0x083C000080", 6964ecd94f1bSKan Liang "Counter": "0,1,2,3", 6965ecd94f1bSKan Liang "EventName": "OCR.PF_L3_DATA_RD.L3_MISS.HIT_OTHER_CORE_FWD", 6966ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 6967ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6968ecd94f1bSKan Liang "SampleAfterValue": "100003", 6969ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 6970ecd94f1bSKan Liang }, 6971ecd94f1bSKan Liang { 6972ecd94f1bSKan Liang "Offcore": "1", 6973ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 6974ecd94f1bSKan Liang "UMask": "0x1", 6975ecd94f1bSKan Liang "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads TBD TBD", 6976ecd94f1bSKan Liang "MSRValue": "0x103C000080", 6977ecd94f1bSKan Liang "Counter": "0,1,2,3", 6978ecd94f1bSKan Liang "EventName": "OCR.PF_L3_DATA_RD.L3_MISS.HITM_OTHER_CORE", 6979ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 6980ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6981ecd94f1bSKan Liang "SampleAfterValue": "100003", 6982ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 6983ecd94f1bSKan Liang }, 6984ecd94f1bSKan Liang { 6985ecd94f1bSKan Liang "Offcore": "1", 6986ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 6987ecd94f1bSKan Liang "UMask": "0x1", 6988ecd94f1bSKan Liang "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads TBD TBD", 6989ecd94f1bSKan Liang "MSRValue": "0x3FBC000080", 6990ecd94f1bSKan Liang "Counter": "0,1,2,3", 6991ecd94f1bSKan Liang "EventName": "OCR.PF_L3_DATA_RD.L3_MISS.ANY_SNOOP", 6992ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 6993ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6994ecd94f1bSKan Liang "SampleAfterValue": "100003", 6995ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 6996ecd94f1bSKan Liang }, 6997ecd94f1bSKan Liang { 6998ecd94f1bSKan Liang "Offcore": "1", 6999ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 7000ecd94f1bSKan Liang "UMask": "0x1", 7001ecd94f1bSKan Liang "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs", 7002ecd94f1bSKan Liang "MSRValue": "0x0084000100", 7003ecd94f1bSKan Liang "Counter": "0,1,2,3", 7004ecd94f1bSKan Liang "EventName": "OCR.PF_L3_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NONE", 7005ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 7006ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7007ecd94f1bSKan Liang "SampleAfterValue": "100003", 7008ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 7009ecd94f1bSKan Liang }, 7010ecd94f1bSKan Liang { 7011ecd94f1bSKan Liang "Offcore": "1", 7012ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 7013ecd94f1bSKan Liang "UMask": "0x1", 7014ecd94f1bSKan Liang "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs TBD", 7015ecd94f1bSKan Liang "MSRValue": "0x0104000100", 7016ecd94f1bSKan Liang "Counter": "0,1,2,3", 7017ecd94f1bSKan Liang "EventName": "OCR.PF_L3_RFO.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED", 7018ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 7019ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7020ecd94f1bSKan Liang "SampleAfterValue": "100003", 7021ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 7022ecd94f1bSKan Liang }, 7023ecd94f1bSKan Liang { 7024ecd94f1bSKan Liang "Offcore": "1", 7025ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 7026ecd94f1bSKan Liang "UMask": "0x1", 7027ecd94f1bSKan Liang "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs", 7028ecd94f1bSKan Liang "MSRValue": "0x0204000100", 7029ecd94f1bSKan Liang "Counter": "0,1,2,3", 7030ecd94f1bSKan Liang "EventName": "OCR.PF_L3_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS", 7031ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 7032ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7033ecd94f1bSKan Liang "SampleAfterValue": "100003", 7034ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 7035ecd94f1bSKan Liang }, 7036ecd94f1bSKan Liang { 7037ecd94f1bSKan Liang "Offcore": "1", 7038ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 7039ecd94f1bSKan Liang "UMask": "0x1", 7040ecd94f1bSKan Liang "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs TBD", 7041ecd94f1bSKan Liang "MSRValue": "0x0404000100", 7042ecd94f1bSKan Liang "Counter": "0,1,2,3", 7043ecd94f1bSKan Liang "EventName": "OCR.PF_L3_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD", 7044ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 7045ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7046ecd94f1bSKan Liang "SampleAfterValue": "100003", 7047ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 7048ecd94f1bSKan Liang }, 7049ecd94f1bSKan Liang { 7050ecd94f1bSKan Liang "Offcore": "1", 7051ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 7052ecd94f1bSKan Liang "UMask": "0x1", 7053ecd94f1bSKan Liang "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs TBD", 7054ecd94f1bSKan Liang "MSRValue": "0x0804000100", 7055ecd94f1bSKan Liang "Counter": "0,1,2,3", 7056ecd94f1bSKan Liang "EventName": "OCR.PF_L3_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD", 7057ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 7058ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7059ecd94f1bSKan Liang "SampleAfterValue": "100003", 7060ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 7061ecd94f1bSKan Liang }, 7062ecd94f1bSKan Liang { 7063ecd94f1bSKan Liang "Offcore": "1", 7064ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 7065ecd94f1bSKan Liang "UMask": "0x1", 7066ecd94f1bSKan Liang "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs TBD", 7067ecd94f1bSKan Liang "MSRValue": "0x1004000100", 7068ecd94f1bSKan Liang "Counter": "0,1,2,3", 7069ecd94f1bSKan Liang "EventName": "OCR.PF_L3_RFO.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE", 7070ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 7071ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7072ecd94f1bSKan Liang "SampleAfterValue": "100003", 7073ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 7074ecd94f1bSKan Liang }, 7075ecd94f1bSKan Liang { 7076ecd94f1bSKan Liang "Offcore": "1", 7077ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 7078ecd94f1bSKan Liang "UMask": "0x1", 7079ecd94f1bSKan Liang "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs TBD", 7080ecd94f1bSKan Liang "MSRValue": "0x3F84000100", 7081ecd94f1bSKan Liang "Counter": "0,1,2,3", 7082ecd94f1bSKan Liang "EventName": "OCR.PF_L3_RFO.L3_MISS_LOCAL_DRAM.ANY_SNOOP", 7083ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 7084ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7085ecd94f1bSKan Liang "SampleAfterValue": "100003", 7086ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 7087ecd94f1bSKan Liang }, 7088ecd94f1bSKan Liang { 7089ecd94f1bSKan Liang "Offcore": "1", 7090ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 7091ecd94f1bSKan Liang "UMask": "0x1", 7092ecd94f1bSKan Liang "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs", 7093ecd94f1bSKan Liang "MSRValue": "0x0090000100", 7094ecd94f1bSKan Liang "Counter": "0,1,2,3", 7095ecd94f1bSKan Liang "EventName": "OCR.PF_L3_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE", 7096ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 7097ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7098ecd94f1bSKan Liang "SampleAfterValue": "100003", 7099ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 7100ecd94f1bSKan Liang }, 7101ecd94f1bSKan Liang { 7102ecd94f1bSKan Liang "Offcore": "1", 7103ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 7104ecd94f1bSKan Liang "UMask": "0x1", 7105ecd94f1bSKan Liang "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs TBD", 7106ecd94f1bSKan Liang "MSRValue": "0x0110000100", 7107ecd94f1bSKan Liang "Counter": "0,1,2,3", 7108ecd94f1bSKan Liang "EventName": "OCR.PF_L3_RFO.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED", 7109ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 7110ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7111ecd94f1bSKan Liang "SampleAfterValue": "100003", 7112ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 7113ecd94f1bSKan Liang }, 7114ecd94f1bSKan Liang { 7115ecd94f1bSKan Liang "Offcore": "1", 7116ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 7117ecd94f1bSKan Liang "UMask": "0x1", 7118ecd94f1bSKan Liang "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs", 7119ecd94f1bSKan Liang "MSRValue": "0x0210000100", 7120ecd94f1bSKan Liang "Counter": "0,1,2,3", 7121ecd94f1bSKan Liang "EventName": "OCR.PF_L3_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS", 7122ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 7123ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7124ecd94f1bSKan Liang "SampleAfterValue": "100003", 7125ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 7126ecd94f1bSKan Liang }, 7127ecd94f1bSKan Liang { 7128ecd94f1bSKan Liang "Offcore": "1", 7129ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 7130ecd94f1bSKan Liang "UMask": "0x1", 7131ecd94f1bSKan Liang "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs TBD", 7132ecd94f1bSKan Liang "MSRValue": "0x0410000100", 7133ecd94f1bSKan Liang "Counter": "0,1,2,3", 7134ecd94f1bSKan Liang "EventName": "OCR.PF_L3_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD", 7135ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 7136ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7137ecd94f1bSKan Liang "SampleAfterValue": "100003", 7138ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 7139ecd94f1bSKan Liang }, 7140ecd94f1bSKan Liang { 7141ecd94f1bSKan Liang "Offcore": "1", 7142ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 7143ecd94f1bSKan Liang "UMask": "0x1", 7144ecd94f1bSKan Liang "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs TBD", 7145ecd94f1bSKan Liang "MSRValue": "0x0810000100", 7146ecd94f1bSKan Liang "Counter": "0,1,2,3", 7147ecd94f1bSKan Liang "EventName": "OCR.PF_L3_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD", 7148ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 7149ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7150ecd94f1bSKan Liang "SampleAfterValue": "100003", 7151ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 7152ecd94f1bSKan Liang }, 7153ecd94f1bSKan Liang { 7154ecd94f1bSKan Liang "Offcore": "1", 7155ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 7156ecd94f1bSKan Liang "UMask": "0x1", 7157ecd94f1bSKan Liang "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs TBD", 7158ecd94f1bSKan Liang "MSRValue": "0x1010000100", 7159ecd94f1bSKan Liang "Counter": "0,1,2,3", 7160ecd94f1bSKan Liang "EventName": "OCR.PF_L3_RFO.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE", 7161ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 7162ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7163ecd94f1bSKan Liang "SampleAfterValue": "100003", 7164ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 7165ecd94f1bSKan Liang }, 7166ecd94f1bSKan Liang { 7167ecd94f1bSKan Liang "Offcore": "1", 7168ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 7169ecd94f1bSKan Liang "UMask": "0x1", 7170ecd94f1bSKan Liang "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs TBD", 7171ecd94f1bSKan Liang "MSRValue": "0x3F90000100", 7172ecd94f1bSKan Liang "Counter": "0,1,2,3", 7173ecd94f1bSKan Liang "EventName": "OCR.PF_L3_RFO.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP", 7174ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 7175ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7176ecd94f1bSKan Liang "SampleAfterValue": "100003", 7177ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 7178ecd94f1bSKan Liang }, 7179ecd94f1bSKan Liang { 7180ecd94f1bSKan Liang "Offcore": "1", 7181ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 7182ecd94f1bSKan Liang "UMask": "0x1", 7183ecd94f1bSKan Liang "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs TBD", 7184ecd94f1bSKan Liang "MSRValue": "0x00BC000100", 7185ecd94f1bSKan Liang "Counter": "0,1,2,3", 7186ecd94f1bSKan Liang "EventName": "OCR.PF_L3_RFO.L3_MISS.SNOOP_NONE", 7187ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 7188ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7189ecd94f1bSKan Liang "SampleAfterValue": "100003", 7190ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 7191ecd94f1bSKan Liang }, 7192ecd94f1bSKan Liang { 7193ecd94f1bSKan Liang "Offcore": "1", 7194ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 7195ecd94f1bSKan Liang "UMask": "0x1", 7196ecd94f1bSKan Liang "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs TBD TBD", 7197ecd94f1bSKan Liang "MSRValue": "0x013C000100", 7198ecd94f1bSKan Liang "Counter": "0,1,2,3", 7199ecd94f1bSKan Liang "EventName": "OCR.PF_L3_RFO.L3_MISS.NO_SNOOP_NEEDED", 7200ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 7201ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7202ecd94f1bSKan Liang "SampleAfterValue": "100003", 7203ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 7204ecd94f1bSKan Liang }, 7205ecd94f1bSKan Liang { 7206ecd94f1bSKan Liang "Offcore": "1", 7207ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 7208ecd94f1bSKan Liang "UMask": "0x1", 7209ecd94f1bSKan Liang "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs TBD", 7210ecd94f1bSKan Liang "MSRValue": "0x023C000100", 7211ecd94f1bSKan Liang "Counter": "0,1,2,3", 7212ecd94f1bSKan Liang "EventName": "OCR.PF_L3_RFO.L3_MISS.SNOOP_MISS", 7213ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 7214ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7215ecd94f1bSKan Liang "SampleAfterValue": "100003", 7216ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 7217ecd94f1bSKan Liang }, 7218ecd94f1bSKan Liang { 7219ecd94f1bSKan Liang "Offcore": "1", 7220ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 7221ecd94f1bSKan Liang "UMask": "0x1", 7222ecd94f1bSKan Liang "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs TBD TBD", 7223ecd94f1bSKan Liang "MSRValue": "0x043C000100", 7224ecd94f1bSKan Liang "Counter": "0,1,2,3", 7225ecd94f1bSKan Liang "EventName": "OCR.PF_L3_RFO.L3_MISS.HIT_OTHER_CORE_NO_FWD", 7226ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 7227ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7228ecd94f1bSKan Liang "SampleAfterValue": "100003", 7229ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 7230ecd94f1bSKan Liang }, 7231ecd94f1bSKan Liang { 7232ecd94f1bSKan Liang "Offcore": "1", 7233ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 7234ecd94f1bSKan Liang "UMask": "0x1", 7235ecd94f1bSKan Liang "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs TBD TBD", 7236ecd94f1bSKan Liang "MSRValue": "0x083C000100", 7237ecd94f1bSKan Liang "Counter": "0,1,2,3", 7238ecd94f1bSKan Liang "EventName": "OCR.PF_L3_RFO.L3_MISS.HIT_OTHER_CORE_FWD", 7239ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 7240ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7241ecd94f1bSKan Liang "SampleAfterValue": "100003", 7242ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 7243ecd94f1bSKan Liang }, 7244ecd94f1bSKan Liang { 7245ecd94f1bSKan Liang "Offcore": "1", 7246ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 7247ecd94f1bSKan Liang "UMask": "0x1", 7248ecd94f1bSKan Liang "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs TBD TBD", 7249ecd94f1bSKan Liang "MSRValue": "0x103C000100", 7250ecd94f1bSKan Liang "Counter": "0,1,2,3", 7251ecd94f1bSKan Liang "EventName": "OCR.PF_L3_RFO.L3_MISS.HITM_OTHER_CORE", 7252ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 7253ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7254ecd94f1bSKan Liang "SampleAfterValue": "100003", 7255ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 7256ecd94f1bSKan Liang }, 7257ecd94f1bSKan Liang { 7258ecd94f1bSKan Liang "Offcore": "1", 7259ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 7260ecd94f1bSKan Liang "UMask": "0x1", 7261ecd94f1bSKan Liang "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs TBD TBD", 7262ecd94f1bSKan Liang "MSRValue": "0x3FBC000100", 7263ecd94f1bSKan Liang "Counter": "0,1,2,3", 7264ecd94f1bSKan Liang "EventName": "OCR.PF_L3_RFO.L3_MISS.ANY_SNOOP", 7265ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 7266ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7267ecd94f1bSKan Liang "SampleAfterValue": "100003", 7268ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 7269ecd94f1bSKan Liang }, 7270ecd94f1bSKan Liang { 7271ecd94f1bSKan Liang "Offcore": "1", 7272ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 7273ecd94f1bSKan Liang "UMask": "0x1", 7274ecd94f1bSKan Liang "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests", 7275ecd94f1bSKan Liang "MSRValue": "0x0084000400", 7276ecd94f1bSKan Liang "Counter": "0,1,2,3", 7277ecd94f1bSKan Liang "EventName": "OCR.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.SNOOP_NONE", 7278ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 7279ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7280ecd94f1bSKan Liang "SampleAfterValue": "100003", 7281ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 7282ecd94f1bSKan Liang }, 7283ecd94f1bSKan Liang { 7284ecd94f1bSKan Liang "Offcore": "1", 7285ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 7286ecd94f1bSKan Liang "UMask": "0x1", 7287ecd94f1bSKan Liang "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests TBD", 7288ecd94f1bSKan Liang "MSRValue": "0x0104000400", 7289ecd94f1bSKan Liang "Counter": "0,1,2,3", 7290ecd94f1bSKan Liang "EventName": "OCR.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED", 7291ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 7292ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7293ecd94f1bSKan Liang "SampleAfterValue": "100003", 7294ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 7295ecd94f1bSKan Liang }, 7296ecd94f1bSKan Liang { 7297ecd94f1bSKan Liang "Offcore": "1", 7298ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 7299ecd94f1bSKan Liang "UMask": "0x1", 7300ecd94f1bSKan Liang "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests", 7301ecd94f1bSKan Liang "MSRValue": "0x0204000400", 7302ecd94f1bSKan Liang "Counter": "0,1,2,3", 7303ecd94f1bSKan Liang "EventName": "OCR.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.SNOOP_MISS", 7304ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 7305ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7306ecd94f1bSKan Liang "SampleAfterValue": "100003", 7307ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 7308ecd94f1bSKan Liang }, 7309ecd94f1bSKan Liang { 7310ecd94f1bSKan Liang "Offcore": "1", 7311ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 7312ecd94f1bSKan Liang "UMask": "0x1", 7313ecd94f1bSKan Liang "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests TBD", 7314ecd94f1bSKan Liang "MSRValue": "0x0404000400", 7315ecd94f1bSKan Liang "Counter": "0,1,2,3", 7316ecd94f1bSKan Liang "EventName": "OCR.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD", 7317ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 7318ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7319ecd94f1bSKan Liang "SampleAfterValue": "100003", 7320ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 7321ecd94f1bSKan Liang }, 7322ecd94f1bSKan Liang { 7323ecd94f1bSKan Liang "Offcore": "1", 7324ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 7325ecd94f1bSKan Liang "UMask": "0x1", 7326ecd94f1bSKan Liang "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests TBD", 7327ecd94f1bSKan Liang "MSRValue": "0x0804000400", 7328ecd94f1bSKan Liang "Counter": "0,1,2,3", 7329ecd94f1bSKan Liang "EventName": "OCR.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD", 7330ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 7331ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7332ecd94f1bSKan Liang "SampleAfterValue": "100003", 7333ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 7334ecd94f1bSKan Liang }, 7335ecd94f1bSKan Liang { 7336ecd94f1bSKan Liang "Offcore": "1", 7337ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 7338ecd94f1bSKan Liang "UMask": "0x1", 7339ecd94f1bSKan Liang "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests TBD", 7340ecd94f1bSKan Liang "MSRValue": "0x1004000400", 7341ecd94f1bSKan Liang "Counter": "0,1,2,3", 7342ecd94f1bSKan Liang "EventName": "OCR.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE", 7343ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 7344ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7345ecd94f1bSKan Liang "SampleAfterValue": "100003", 7346ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 7347ecd94f1bSKan Liang }, 7348ecd94f1bSKan Liang { 7349ecd94f1bSKan Liang "Offcore": "1", 7350ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 7351ecd94f1bSKan Liang "UMask": "0x1", 7352ecd94f1bSKan Liang "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests TBD", 7353ecd94f1bSKan Liang "MSRValue": "0x3F84000400", 7354ecd94f1bSKan Liang "Counter": "0,1,2,3", 7355ecd94f1bSKan Liang "EventName": "OCR.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.ANY_SNOOP", 7356ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 7357ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7358ecd94f1bSKan Liang "SampleAfterValue": "100003", 7359ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 7360ecd94f1bSKan Liang }, 7361ecd94f1bSKan Liang { 7362ecd94f1bSKan Liang "Offcore": "1", 7363ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 7364ecd94f1bSKan Liang "UMask": "0x1", 7365ecd94f1bSKan Liang "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests", 7366ecd94f1bSKan Liang "MSRValue": "0x0090000400", 7367ecd94f1bSKan Liang "Counter": "0,1,2,3", 7368ecd94f1bSKan Liang "EventName": "OCR.PF_L1D_AND_SW.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE", 7369ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 7370ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7371ecd94f1bSKan Liang "SampleAfterValue": "100003", 7372ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 7373ecd94f1bSKan Liang }, 7374ecd94f1bSKan Liang { 7375ecd94f1bSKan Liang "Offcore": "1", 7376ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 7377ecd94f1bSKan Liang "UMask": "0x1", 7378ecd94f1bSKan Liang "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests TBD", 7379ecd94f1bSKan Liang "MSRValue": "0x0110000400", 7380ecd94f1bSKan Liang "Counter": "0,1,2,3", 7381ecd94f1bSKan Liang "EventName": "OCR.PF_L1D_AND_SW.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED", 7382ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 7383ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7384ecd94f1bSKan Liang "SampleAfterValue": "100003", 7385ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 7386ecd94f1bSKan Liang }, 7387ecd94f1bSKan Liang { 7388ecd94f1bSKan Liang "Offcore": "1", 7389ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 7390ecd94f1bSKan Liang "UMask": "0x1", 7391ecd94f1bSKan Liang "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests", 7392ecd94f1bSKan Liang "MSRValue": "0x0210000400", 7393ecd94f1bSKan Liang "Counter": "0,1,2,3", 7394ecd94f1bSKan Liang "EventName": "OCR.PF_L1D_AND_SW.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS", 7395ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 7396ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7397ecd94f1bSKan Liang "SampleAfterValue": "100003", 7398ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 7399ecd94f1bSKan Liang }, 7400ecd94f1bSKan Liang { 7401ecd94f1bSKan Liang "Offcore": "1", 7402ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 7403ecd94f1bSKan Liang "UMask": "0x1", 7404ecd94f1bSKan Liang "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests TBD", 7405ecd94f1bSKan Liang "MSRValue": "0x0410000400", 7406ecd94f1bSKan Liang "Counter": "0,1,2,3", 7407ecd94f1bSKan Liang "EventName": "OCR.PF_L1D_AND_SW.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD", 7408ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 7409ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7410ecd94f1bSKan Liang "SampleAfterValue": "100003", 7411ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 7412ecd94f1bSKan Liang }, 7413ecd94f1bSKan Liang { 7414ecd94f1bSKan Liang "Offcore": "1", 7415ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 7416ecd94f1bSKan Liang "UMask": "0x1", 7417ecd94f1bSKan Liang "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests TBD", 7418ecd94f1bSKan Liang "MSRValue": "0x0810000400", 7419ecd94f1bSKan Liang "Counter": "0,1,2,3", 7420ecd94f1bSKan Liang "EventName": "OCR.PF_L1D_AND_SW.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD", 7421ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 7422ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7423ecd94f1bSKan Liang "SampleAfterValue": "100003", 7424ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 7425ecd94f1bSKan Liang }, 7426ecd94f1bSKan Liang { 7427ecd94f1bSKan Liang "Offcore": "1", 7428ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 7429ecd94f1bSKan Liang "UMask": "0x1", 7430ecd94f1bSKan Liang "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests TBD", 7431ecd94f1bSKan Liang "MSRValue": "0x1010000400", 7432ecd94f1bSKan Liang "Counter": "0,1,2,3", 7433ecd94f1bSKan Liang "EventName": "OCR.PF_L1D_AND_SW.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE", 7434ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 7435ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7436ecd94f1bSKan Liang "SampleAfterValue": "100003", 7437ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 7438ecd94f1bSKan Liang }, 7439ecd94f1bSKan Liang { 7440ecd94f1bSKan Liang "Offcore": "1", 7441ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 7442ecd94f1bSKan Liang "UMask": "0x1", 7443ecd94f1bSKan Liang "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests TBD", 7444ecd94f1bSKan Liang "MSRValue": "0x3F90000400", 7445ecd94f1bSKan Liang "Counter": "0,1,2,3", 7446ecd94f1bSKan Liang "EventName": "OCR.PF_L1D_AND_SW.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP", 7447ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 7448ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7449ecd94f1bSKan Liang "SampleAfterValue": "100003", 7450ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 7451ecd94f1bSKan Liang }, 7452ecd94f1bSKan Liang { 7453ecd94f1bSKan Liang "Offcore": "1", 7454ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 7455ecd94f1bSKan Liang "UMask": "0x1", 7456ecd94f1bSKan Liang "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests TBD", 7457ecd94f1bSKan Liang "MSRValue": "0x00BC000400", 7458ecd94f1bSKan Liang "Counter": "0,1,2,3", 7459ecd94f1bSKan Liang "EventName": "OCR.PF_L1D_AND_SW.L3_MISS.SNOOP_NONE", 7460ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 7461ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7462ecd94f1bSKan Liang "SampleAfterValue": "100003", 7463ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 7464ecd94f1bSKan Liang }, 7465ecd94f1bSKan Liang { 7466ecd94f1bSKan Liang "Offcore": "1", 7467ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 7468ecd94f1bSKan Liang "UMask": "0x1", 7469ecd94f1bSKan Liang "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests TBD TBD", 7470ecd94f1bSKan Liang "MSRValue": "0x013C000400", 7471ecd94f1bSKan Liang "Counter": "0,1,2,3", 7472ecd94f1bSKan Liang "EventName": "OCR.PF_L1D_AND_SW.L3_MISS.NO_SNOOP_NEEDED", 7473ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 7474ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7475ecd94f1bSKan Liang "SampleAfterValue": "100003", 7476ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 7477ecd94f1bSKan Liang }, 7478ecd94f1bSKan Liang { 7479ecd94f1bSKan Liang "Offcore": "1", 7480ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 7481ecd94f1bSKan Liang "UMask": "0x1", 7482ecd94f1bSKan Liang "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests TBD", 7483ecd94f1bSKan Liang "MSRValue": "0x023C000400", 7484ecd94f1bSKan Liang "Counter": "0,1,2,3", 7485ecd94f1bSKan Liang "EventName": "OCR.PF_L1D_AND_SW.L3_MISS.SNOOP_MISS", 7486ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 7487ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7488ecd94f1bSKan Liang "SampleAfterValue": "100003", 7489ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 7490ecd94f1bSKan Liang }, 7491ecd94f1bSKan Liang { 7492ecd94f1bSKan Liang "Offcore": "1", 7493ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 7494ecd94f1bSKan Liang "UMask": "0x1", 7495ecd94f1bSKan Liang "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests TBD TBD", 7496ecd94f1bSKan Liang "MSRValue": "0x043C000400", 7497ecd94f1bSKan Liang "Counter": "0,1,2,3", 7498ecd94f1bSKan Liang "EventName": "OCR.PF_L1D_AND_SW.L3_MISS.HIT_OTHER_CORE_NO_FWD", 7499ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 7500ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7501ecd94f1bSKan Liang "SampleAfterValue": "100003", 7502ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 7503ecd94f1bSKan Liang }, 7504ecd94f1bSKan Liang { 7505ecd94f1bSKan Liang "Offcore": "1", 7506ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 7507ecd94f1bSKan Liang "UMask": "0x1", 7508ecd94f1bSKan Liang "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests TBD TBD", 7509ecd94f1bSKan Liang "MSRValue": "0x083C000400", 7510ecd94f1bSKan Liang "Counter": "0,1,2,3", 7511ecd94f1bSKan Liang "EventName": "OCR.PF_L1D_AND_SW.L3_MISS.HIT_OTHER_CORE_FWD", 7512ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 7513ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7514ecd94f1bSKan Liang "SampleAfterValue": "100003", 7515ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 7516ecd94f1bSKan Liang }, 7517ecd94f1bSKan Liang { 7518ecd94f1bSKan Liang "Offcore": "1", 7519ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 7520ecd94f1bSKan Liang "UMask": "0x1", 7521ecd94f1bSKan Liang "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests TBD TBD", 7522ecd94f1bSKan Liang "MSRValue": "0x103C000400", 7523ecd94f1bSKan Liang "Counter": "0,1,2,3", 7524ecd94f1bSKan Liang "EventName": "OCR.PF_L1D_AND_SW.L3_MISS.HITM_OTHER_CORE", 7525ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 7526ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7527ecd94f1bSKan Liang "SampleAfterValue": "100003", 7528ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 7529ecd94f1bSKan Liang }, 7530ecd94f1bSKan Liang { 7531ecd94f1bSKan Liang "Offcore": "1", 7532ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 7533ecd94f1bSKan Liang "UMask": "0x1", 7534ecd94f1bSKan Liang "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests TBD TBD", 7535ecd94f1bSKan Liang "MSRValue": "0x3FBC000400", 7536ecd94f1bSKan Liang "Counter": "0,1,2,3", 7537ecd94f1bSKan Liang "EventName": "OCR.PF_L1D_AND_SW.L3_MISS.ANY_SNOOP", 7538ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 7539ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7540ecd94f1bSKan Liang "SampleAfterValue": "100003", 7541ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 7542ecd94f1bSKan Liang }, 7543ecd94f1bSKan Liang { 7544ecd94f1bSKan Liang "Offcore": "1", 7545ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 7546ecd94f1bSKan Liang "UMask": "0x1", 7547ecd94f1bSKan Liang "BriefDescription": "Counts any other requests", 7548ecd94f1bSKan Liang "MSRValue": "0x0084008000", 7549ecd94f1bSKan Liang "Counter": "0,1,2,3", 7550ecd94f1bSKan Liang "EventName": "OCR.OTHER.L3_MISS_LOCAL_DRAM.SNOOP_NONE", 7551ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 7552ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7553ecd94f1bSKan Liang "SampleAfterValue": "100003", 7554ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 7555ecd94f1bSKan Liang }, 7556ecd94f1bSKan Liang { 7557ecd94f1bSKan Liang "Offcore": "1", 7558ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 7559ecd94f1bSKan Liang "UMask": "0x1", 7560ecd94f1bSKan Liang "BriefDescription": "Counts any other requests TBD", 7561ecd94f1bSKan Liang "MSRValue": "0x0104008000", 7562ecd94f1bSKan Liang "Counter": "0,1,2,3", 7563ecd94f1bSKan Liang "EventName": "OCR.OTHER.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED", 7564ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 7565ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7566ecd94f1bSKan Liang "SampleAfterValue": "100003", 7567ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 7568ecd94f1bSKan Liang }, 7569ecd94f1bSKan Liang { 7570ecd94f1bSKan Liang "Offcore": "1", 7571ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 7572ecd94f1bSKan Liang "UMask": "0x1", 7573ecd94f1bSKan Liang "BriefDescription": "Counts any other requests", 7574ecd94f1bSKan Liang "MSRValue": "0x0204008000", 7575ecd94f1bSKan Liang "Counter": "0,1,2,3", 7576ecd94f1bSKan Liang "EventName": "OCR.OTHER.L3_MISS_LOCAL_DRAM.SNOOP_MISS", 7577ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 7578ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7579ecd94f1bSKan Liang "SampleAfterValue": "100003", 7580ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 7581ecd94f1bSKan Liang }, 7582ecd94f1bSKan Liang { 7583ecd94f1bSKan Liang "Offcore": "1", 7584ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 7585ecd94f1bSKan Liang "UMask": "0x1", 7586ecd94f1bSKan Liang "BriefDescription": "Counts any other requests TBD", 7587ecd94f1bSKan Liang "MSRValue": "0x0404008000", 7588ecd94f1bSKan Liang "Counter": "0,1,2,3", 7589ecd94f1bSKan Liang "EventName": "OCR.OTHER.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD", 7590ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 7591ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7592ecd94f1bSKan Liang "SampleAfterValue": "100003", 7593ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 7594ecd94f1bSKan Liang }, 7595ecd94f1bSKan Liang { 7596ecd94f1bSKan Liang "Offcore": "1", 7597ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 7598ecd94f1bSKan Liang "UMask": "0x1", 7599ecd94f1bSKan Liang "BriefDescription": "Counts any other requests TBD", 7600ecd94f1bSKan Liang "MSRValue": "0x0804008000", 7601ecd94f1bSKan Liang "Counter": "0,1,2,3", 7602ecd94f1bSKan Liang "EventName": "OCR.OTHER.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD", 7603ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 7604ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7605ecd94f1bSKan Liang "SampleAfterValue": "100003", 7606ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 7607ecd94f1bSKan Liang }, 7608ecd94f1bSKan Liang { 7609ecd94f1bSKan Liang "Offcore": "1", 7610ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 7611ecd94f1bSKan Liang "UMask": "0x1", 7612ecd94f1bSKan Liang "BriefDescription": "Counts any other requests TBD", 7613ecd94f1bSKan Liang "MSRValue": "0x1004008000", 7614ecd94f1bSKan Liang "Counter": "0,1,2,3", 7615ecd94f1bSKan Liang "EventName": "OCR.OTHER.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE", 7616ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 7617ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7618ecd94f1bSKan Liang "SampleAfterValue": "100003", 7619ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 7620ecd94f1bSKan Liang }, 7621ecd94f1bSKan Liang { 7622ecd94f1bSKan Liang "Offcore": "1", 7623ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 7624ecd94f1bSKan Liang "UMask": "0x1", 7625ecd94f1bSKan Liang "BriefDescription": "Counts any other requests TBD", 7626ecd94f1bSKan Liang "MSRValue": "0x3F84008000", 7627ecd94f1bSKan Liang "Counter": "0,1,2,3", 7628ecd94f1bSKan Liang "EventName": "OCR.OTHER.L3_MISS_LOCAL_DRAM.ANY_SNOOP", 7629ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 7630ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7631ecd94f1bSKan Liang "SampleAfterValue": "100003", 7632ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 7633ecd94f1bSKan Liang }, 7634ecd94f1bSKan Liang { 7635ecd94f1bSKan Liang "Offcore": "1", 7636ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 7637ecd94f1bSKan Liang "UMask": "0x1", 7638ecd94f1bSKan Liang "BriefDescription": "Counts any other requests", 7639ecd94f1bSKan Liang "MSRValue": "0x0090008000", 7640ecd94f1bSKan Liang "Counter": "0,1,2,3", 7641ecd94f1bSKan Liang "EventName": "OCR.OTHER.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE", 7642ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 7643ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7644ecd94f1bSKan Liang "SampleAfterValue": "100003", 7645ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 7646ecd94f1bSKan Liang }, 7647ecd94f1bSKan Liang { 7648ecd94f1bSKan Liang "Offcore": "1", 7649ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 7650ecd94f1bSKan Liang "UMask": "0x1", 7651ecd94f1bSKan Liang "BriefDescription": "Counts any other requests TBD", 7652ecd94f1bSKan Liang "MSRValue": "0x0110008000", 7653ecd94f1bSKan Liang "Counter": "0,1,2,3", 7654ecd94f1bSKan Liang "EventName": "OCR.OTHER.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED", 7655ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 7656ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7657ecd94f1bSKan Liang "SampleAfterValue": "100003", 7658ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 7659ecd94f1bSKan Liang }, 7660ecd94f1bSKan Liang { 7661ecd94f1bSKan Liang "Offcore": "1", 7662ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 7663ecd94f1bSKan Liang "UMask": "0x1", 7664ecd94f1bSKan Liang "BriefDescription": "Counts any other requests", 7665ecd94f1bSKan Liang "MSRValue": "0x0210008000", 7666ecd94f1bSKan Liang "Counter": "0,1,2,3", 7667ecd94f1bSKan Liang "EventName": "OCR.OTHER.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS", 7668ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 7669ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7670ecd94f1bSKan Liang "SampleAfterValue": "100003", 7671ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 7672ecd94f1bSKan Liang }, 7673ecd94f1bSKan Liang { 7674ecd94f1bSKan Liang "Offcore": "1", 7675ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 7676ecd94f1bSKan Liang "UMask": "0x1", 7677ecd94f1bSKan Liang "BriefDescription": "Counts any other requests TBD", 7678ecd94f1bSKan Liang "MSRValue": "0x0410008000", 7679ecd94f1bSKan Liang "Counter": "0,1,2,3", 7680ecd94f1bSKan Liang "EventName": "OCR.OTHER.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD", 7681ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 7682ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7683ecd94f1bSKan Liang "SampleAfterValue": "100003", 7684ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 7685ecd94f1bSKan Liang }, 7686ecd94f1bSKan Liang { 7687ecd94f1bSKan Liang "Offcore": "1", 7688ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 7689ecd94f1bSKan Liang "UMask": "0x1", 7690ecd94f1bSKan Liang "BriefDescription": "Counts any other requests TBD", 7691ecd94f1bSKan Liang "MSRValue": "0x0810008000", 7692ecd94f1bSKan Liang "Counter": "0,1,2,3", 7693ecd94f1bSKan Liang "EventName": "OCR.OTHER.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD", 7694ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 7695ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7696ecd94f1bSKan Liang "SampleAfterValue": "100003", 7697ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 7698ecd94f1bSKan Liang }, 7699ecd94f1bSKan Liang { 7700ecd94f1bSKan Liang "Offcore": "1", 7701ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 7702ecd94f1bSKan Liang "UMask": "0x1", 7703ecd94f1bSKan Liang "BriefDescription": "Counts any other requests TBD", 7704ecd94f1bSKan Liang "MSRValue": "0x1010008000", 7705ecd94f1bSKan Liang "Counter": "0,1,2,3", 7706ecd94f1bSKan Liang "EventName": "OCR.OTHER.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE", 7707ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 7708ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7709ecd94f1bSKan Liang "SampleAfterValue": "100003", 7710ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 7711ecd94f1bSKan Liang }, 7712ecd94f1bSKan Liang { 7713ecd94f1bSKan Liang "Offcore": "1", 7714ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 7715ecd94f1bSKan Liang "UMask": "0x1", 7716ecd94f1bSKan Liang "BriefDescription": "Counts any other requests TBD", 7717ecd94f1bSKan Liang "MSRValue": "0x3F90008000", 7718ecd94f1bSKan Liang "Counter": "0,1,2,3", 7719ecd94f1bSKan Liang "EventName": "OCR.OTHER.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP", 7720ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 7721ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7722ecd94f1bSKan Liang "SampleAfterValue": "100003", 7723ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 7724ecd94f1bSKan Liang }, 7725ecd94f1bSKan Liang { 7726ecd94f1bSKan Liang "Offcore": "1", 7727ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 7728ecd94f1bSKan Liang "UMask": "0x1", 7729ecd94f1bSKan Liang "BriefDescription": "Counts any other requests TBD", 7730ecd94f1bSKan Liang "MSRValue": "0x00BC008000", 7731ecd94f1bSKan Liang "Counter": "0,1,2,3", 7732ecd94f1bSKan Liang "EventName": "OCR.OTHER.L3_MISS.SNOOP_NONE", 7733ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 7734ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7735ecd94f1bSKan Liang "SampleAfterValue": "100003", 7736ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 7737ecd94f1bSKan Liang }, 7738ecd94f1bSKan Liang { 7739ecd94f1bSKan Liang "Offcore": "1", 7740ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 7741ecd94f1bSKan Liang "UMask": "0x1", 7742ecd94f1bSKan Liang "BriefDescription": "Counts any other requests TBD TBD", 7743ecd94f1bSKan Liang "MSRValue": "0x013C008000", 7744ecd94f1bSKan Liang "Counter": "0,1,2,3", 7745ecd94f1bSKan Liang "EventName": "OCR.OTHER.L3_MISS.NO_SNOOP_NEEDED", 7746ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 7747ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7748ecd94f1bSKan Liang "SampleAfterValue": "100003", 7749ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 7750ecd94f1bSKan Liang }, 7751ecd94f1bSKan Liang { 7752ecd94f1bSKan Liang "Offcore": "1", 7753ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 7754ecd94f1bSKan Liang "UMask": "0x1", 7755ecd94f1bSKan Liang "BriefDescription": "Counts any other requests TBD", 7756ecd94f1bSKan Liang "MSRValue": "0x023C008000", 7757ecd94f1bSKan Liang "Counter": "0,1,2,3", 7758ecd94f1bSKan Liang "EventName": "OCR.OTHER.L3_MISS.SNOOP_MISS", 7759ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 7760ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7761ecd94f1bSKan Liang "SampleAfterValue": "100003", 7762ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 7763ecd94f1bSKan Liang }, 7764ecd94f1bSKan Liang { 7765ecd94f1bSKan Liang "Offcore": "1", 7766ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 7767ecd94f1bSKan Liang "UMask": "0x1", 7768ecd94f1bSKan Liang "BriefDescription": "Counts any other requests TBD TBD", 7769ecd94f1bSKan Liang "MSRValue": "0x043C008000", 7770ecd94f1bSKan Liang "Counter": "0,1,2,3", 7771ecd94f1bSKan Liang "EventName": "OCR.OTHER.L3_MISS.HIT_OTHER_CORE_NO_FWD", 7772ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 7773ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7774ecd94f1bSKan Liang "SampleAfterValue": "100003", 7775ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 7776ecd94f1bSKan Liang }, 7777ecd94f1bSKan Liang { 7778ecd94f1bSKan Liang "Offcore": "1", 7779ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 7780ecd94f1bSKan Liang "UMask": "0x1", 7781ecd94f1bSKan Liang "BriefDescription": "Counts any other requests TBD TBD", 7782ecd94f1bSKan Liang "MSRValue": "0x083C008000", 7783ecd94f1bSKan Liang "Counter": "0,1,2,3", 7784ecd94f1bSKan Liang "EventName": "OCR.OTHER.L3_MISS.HIT_OTHER_CORE_FWD", 7785ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 7786ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7787ecd94f1bSKan Liang "SampleAfterValue": "100003", 7788ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 7789ecd94f1bSKan Liang }, 7790ecd94f1bSKan Liang { 7791ecd94f1bSKan Liang "Offcore": "1", 7792ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 7793ecd94f1bSKan Liang "UMask": "0x1", 7794ecd94f1bSKan Liang "BriefDescription": "Counts any other requests TBD TBD", 7795ecd94f1bSKan Liang "MSRValue": "0x103C008000", 7796ecd94f1bSKan Liang "Counter": "0,1,2,3", 7797ecd94f1bSKan Liang "EventName": "OCR.OTHER.L3_MISS.HITM_OTHER_CORE", 7798ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 7799ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7800ecd94f1bSKan Liang "SampleAfterValue": "100003", 7801ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 7802ecd94f1bSKan Liang }, 7803ecd94f1bSKan Liang { 7804ecd94f1bSKan Liang "Offcore": "1", 7805ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 7806ecd94f1bSKan Liang "UMask": "0x1", 7807ecd94f1bSKan Liang "BriefDescription": "Counts any other requests TBD TBD", 7808ecd94f1bSKan Liang "MSRValue": "0x3FBC008000", 7809ecd94f1bSKan Liang "Counter": "0,1,2,3", 7810ecd94f1bSKan Liang "EventName": "OCR.OTHER.L3_MISS.ANY_SNOOP", 7811ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 7812ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7813ecd94f1bSKan Liang "SampleAfterValue": "100003", 7814ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 7815ecd94f1bSKan Liang }, 7816ecd94f1bSKan Liang { 7817ecd94f1bSKan Liang "Offcore": "1", 7818ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 7819ecd94f1bSKan Liang "UMask": "0x1", 7820ecd94f1bSKan Liang "BriefDescription": "TBD", 7821ecd94f1bSKan Liang "MSRValue": "0x0084000490", 7822ecd94f1bSKan Liang "Counter": "0,1,2,3", 7823ecd94f1bSKan Liang "EventName": "OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NONE", 7824ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 7825ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7826ecd94f1bSKan Liang "SampleAfterValue": "100003", 7827ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 7828ecd94f1bSKan Liang }, 7829ecd94f1bSKan Liang { 7830ecd94f1bSKan Liang "Offcore": "1", 7831ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 7832ecd94f1bSKan Liang "UMask": "0x1", 7833ecd94f1bSKan Liang "BriefDescription": "TBD TBD", 7834ecd94f1bSKan Liang "MSRValue": "0x0104000490", 7835ecd94f1bSKan Liang "Counter": "0,1,2,3", 7836ecd94f1bSKan Liang "EventName": "OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED", 7837ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 7838ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7839ecd94f1bSKan Liang "SampleAfterValue": "100003", 7840ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 7841ecd94f1bSKan Liang }, 7842ecd94f1bSKan Liang { 7843ecd94f1bSKan Liang "Offcore": "1", 7844ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 7845ecd94f1bSKan Liang "UMask": "0x1", 7846ecd94f1bSKan Liang "BriefDescription": "TBD", 7847ecd94f1bSKan Liang "MSRValue": "0x0204000490", 7848ecd94f1bSKan Liang "Counter": "0,1,2,3", 7849ecd94f1bSKan Liang "EventName": "OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS", 7850ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 7851ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7852ecd94f1bSKan Liang "SampleAfterValue": "100003", 7853ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 7854ecd94f1bSKan Liang }, 7855ecd94f1bSKan Liang { 7856ecd94f1bSKan Liang "Offcore": "1", 7857ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 7858ecd94f1bSKan Liang "UMask": "0x1", 7859ecd94f1bSKan Liang "BriefDescription": "TBD TBD", 7860ecd94f1bSKan Liang "MSRValue": "0x0404000490", 7861ecd94f1bSKan Liang "Counter": "0,1,2,3", 7862ecd94f1bSKan Liang "EventName": "OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD", 7863ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 7864ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7865ecd94f1bSKan Liang "SampleAfterValue": "100003", 7866ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 7867ecd94f1bSKan Liang }, 7868ecd94f1bSKan Liang { 7869ecd94f1bSKan Liang "Offcore": "1", 7870ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 7871ecd94f1bSKan Liang "UMask": "0x1", 7872ecd94f1bSKan Liang "BriefDescription": "TBD TBD", 7873ecd94f1bSKan Liang "MSRValue": "0x0804000490", 7874ecd94f1bSKan Liang "Counter": "0,1,2,3", 7875ecd94f1bSKan Liang "EventName": "OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD", 7876ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 7877ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7878ecd94f1bSKan Liang "SampleAfterValue": "100003", 7879ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 7880ecd94f1bSKan Liang }, 7881ecd94f1bSKan Liang { 7882ecd94f1bSKan Liang "Offcore": "1", 7883ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 7884ecd94f1bSKan Liang "UMask": "0x1", 7885ecd94f1bSKan Liang "BriefDescription": "TBD TBD", 7886ecd94f1bSKan Liang "MSRValue": "0x1004000490", 7887ecd94f1bSKan Liang "Counter": "0,1,2,3", 7888ecd94f1bSKan Liang "EventName": "OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE", 7889ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 7890ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7891ecd94f1bSKan Liang "SampleAfterValue": "100003", 7892ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 7893ecd94f1bSKan Liang }, 7894ecd94f1bSKan Liang { 7895ecd94f1bSKan Liang "Offcore": "1", 7896ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 7897ecd94f1bSKan Liang "UMask": "0x1", 7898ecd94f1bSKan Liang "BriefDescription": "TBD TBD", 7899ecd94f1bSKan Liang "MSRValue": "0x3F84000490", 7900ecd94f1bSKan Liang "Counter": "0,1,2,3", 7901ecd94f1bSKan Liang "EventName": "OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP", 7902ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 7903ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7904ecd94f1bSKan Liang "SampleAfterValue": "100003", 7905ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 7906ecd94f1bSKan Liang }, 7907ecd94f1bSKan Liang { 7908ecd94f1bSKan Liang "Offcore": "1", 7909ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 7910ecd94f1bSKan Liang "UMask": "0x1", 7911ecd94f1bSKan Liang "BriefDescription": "TBD", 7912ecd94f1bSKan Liang "MSRValue": "0x0090000490", 7913ecd94f1bSKan Liang "Counter": "0,1,2,3", 7914ecd94f1bSKan Liang "EventName": "OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE", 7915ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 7916ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7917ecd94f1bSKan Liang "SampleAfterValue": "100003", 7918ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 7919ecd94f1bSKan Liang }, 7920ecd94f1bSKan Liang { 7921ecd94f1bSKan Liang "Offcore": "1", 7922ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 7923ecd94f1bSKan Liang "UMask": "0x1", 7924ecd94f1bSKan Liang "BriefDescription": "TBD TBD", 7925ecd94f1bSKan Liang "MSRValue": "0x0110000490", 7926ecd94f1bSKan Liang "Counter": "0,1,2,3", 7927ecd94f1bSKan Liang "EventName": "OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED", 7928ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 7929ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7930ecd94f1bSKan Liang "SampleAfterValue": "100003", 7931ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 7932ecd94f1bSKan Liang }, 7933ecd94f1bSKan Liang { 7934ecd94f1bSKan Liang "Offcore": "1", 7935ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 7936ecd94f1bSKan Liang "UMask": "0x1", 7937ecd94f1bSKan Liang "BriefDescription": "TBD", 7938ecd94f1bSKan Liang "MSRValue": "0x0210000490", 7939ecd94f1bSKan Liang "Counter": "0,1,2,3", 7940ecd94f1bSKan Liang "EventName": "OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS", 7941ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 7942ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7943ecd94f1bSKan Liang "SampleAfterValue": "100003", 7944ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 7945ecd94f1bSKan Liang }, 7946ecd94f1bSKan Liang { 7947ecd94f1bSKan Liang "Offcore": "1", 7948ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 7949ecd94f1bSKan Liang "UMask": "0x1", 7950ecd94f1bSKan Liang "BriefDescription": "TBD TBD", 7951ecd94f1bSKan Liang "MSRValue": "0x0410000490", 7952ecd94f1bSKan Liang "Counter": "0,1,2,3", 7953ecd94f1bSKan Liang "EventName": "OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD", 7954ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 7955ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7956ecd94f1bSKan Liang "SampleAfterValue": "100003", 7957ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 7958ecd94f1bSKan Liang }, 7959ecd94f1bSKan Liang { 7960ecd94f1bSKan Liang "Offcore": "1", 7961ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 7962ecd94f1bSKan Liang "UMask": "0x1", 7963ecd94f1bSKan Liang "BriefDescription": "TBD TBD", 7964ecd94f1bSKan Liang "MSRValue": "0x0810000490", 7965ecd94f1bSKan Liang "Counter": "0,1,2,3", 7966ecd94f1bSKan Liang "EventName": "OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD", 7967ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 7968ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7969ecd94f1bSKan Liang "SampleAfterValue": "100003", 7970ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 7971ecd94f1bSKan Liang }, 7972ecd94f1bSKan Liang { 7973ecd94f1bSKan Liang "Offcore": "1", 7974ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 7975ecd94f1bSKan Liang "UMask": "0x1", 7976ecd94f1bSKan Liang "BriefDescription": "TBD TBD", 7977ecd94f1bSKan Liang "MSRValue": "0x1010000490", 7978ecd94f1bSKan Liang "Counter": "0,1,2,3", 7979ecd94f1bSKan Liang "EventName": "OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE", 7980ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 7981ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7982ecd94f1bSKan Liang "SampleAfterValue": "100003", 7983ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 7984ecd94f1bSKan Liang }, 7985ecd94f1bSKan Liang { 7986ecd94f1bSKan Liang "Offcore": "1", 7987ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 7988ecd94f1bSKan Liang "UMask": "0x1", 7989ecd94f1bSKan Liang "BriefDescription": "TBD TBD", 7990ecd94f1bSKan Liang "MSRValue": "0x3F90000490", 7991ecd94f1bSKan Liang "Counter": "0,1,2,3", 7992ecd94f1bSKan Liang "EventName": "OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP", 7993ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 7994ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7995ecd94f1bSKan Liang "SampleAfterValue": "100003", 7996ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 7997ecd94f1bSKan Liang }, 7998ecd94f1bSKan Liang { 7999ecd94f1bSKan Liang "Offcore": "1", 8000ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 8001ecd94f1bSKan Liang "UMask": "0x1", 8002ecd94f1bSKan Liang "BriefDescription": "TBD TBD", 8003ecd94f1bSKan Liang "MSRValue": "0x00BC000490", 8004ecd94f1bSKan Liang "Counter": "0,1,2,3", 8005ecd94f1bSKan Liang "EventName": "OCR.ALL_PF_DATA_RD.L3_MISS.SNOOP_NONE", 8006ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 8007ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8008ecd94f1bSKan Liang "SampleAfterValue": "100003", 8009ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 8010ecd94f1bSKan Liang }, 8011ecd94f1bSKan Liang { 8012ecd94f1bSKan Liang "Offcore": "1", 8013ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 8014ecd94f1bSKan Liang "UMask": "0x1", 8015ecd94f1bSKan Liang "BriefDescription": "TBD TBD TBD", 8016ecd94f1bSKan Liang "MSRValue": "0x013C000490", 8017ecd94f1bSKan Liang "Counter": "0,1,2,3", 8018ecd94f1bSKan Liang "EventName": "OCR.ALL_PF_DATA_RD.L3_MISS.NO_SNOOP_NEEDED", 8019ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 8020ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8021ecd94f1bSKan Liang "SampleAfterValue": "100003", 8022ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 8023ecd94f1bSKan Liang }, 8024ecd94f1bSKan Liang { 8025ecd94f1bSKan Liang "Offcore": "1", 8026ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 8027ecd94f1bSKan Liang "UMask": "0x1", 8028ecd94f1bSKan Liang "BriefDescription": "TBD TBD", 8029ecd94f1bSKan Liang "MSRValue": "0x023C000490", 8030ecd94f1bSKan Liang "Counter": "0,1,2,3", 8031ecd94f1bSKan Liang "EventName": "OCR.ALL_PF_DATA_RD.L3_MISS.SNOOP_MISS", 8032ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 8033ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8034ecd94f1bSKan Liang "SampleAfterValue": "100003", 8035ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 8036ecd94f1bSKan Liang }, 8037ecd94f1bSKan Liang { 8038ecd94f1bSKan Liang "Offcore": "1", 8039ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 8040ecd94f1bSKan Liang "UMask": "0x1", 8041ecd94f1bSKan Liang "BriefDescription": "TBD TBD TBD", 8042ecd94f1bSKan Liang "MSRValue": "0x043C000490", 8043ecd94f1bSKan Liang "Counter": "0,1,2,3", 8044ecd94f1bSKan Liang "EventName": "OCR.ALL_PF_DATA_RD.L3_MISS.HIT_OTHER_CORE_NO_FWD", 8045ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 8046ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8047ecd94f1bSKan Liang "SampleAfterValue": "100003", 8048ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 8049ecd94f1bSKan Liang }, 8050ecd94f1bSKan Liang { 8051ecd94f1bSKan Liang "Offcore": "1", 8052ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 8053ecd94f1bSKan Liang "UMask": "0x1", 8054ecd94f1bSKan Liang "BriefDescription": "TBD TBD TBD", 8055ecd94f1bSKan Liang "MSRValue": "0x083C000490", 8056ecd94f1bSKan Liang "Counter": "0,1,2,3", 8057ecd94f1bSKan Liang "EventName": "OCR.ALL_PF_DATA_RD.L3_MISS.HIT_OTHER_CORE_FWD", 8058ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 8059ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8060ecd94f1bSKan Liang "SampleAfterValue": "100003", 8061ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 8062ecd94f1bSKan Liang }, 8063ecd94f1bSKan Liang { 8064ecd94f1bSKan Liang "Offcore": "1", 8065ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 8066ecd94f1bSKan Liang "UMask": "0x1", 8067ecd94f1bSKan Liang "BriefDescription": "TBD TBD TBD", 8068ecd94f1bSKan Liang "MSRValue": "0x103C000490", 8069ecd94f1bSKan Liang "Counter": "0,1,2,3", 8070ecd94f1bSKan Liang "EventName": "OCR.ALL_PF_DATA_RD.L3_MISS.HITM_OTHER_CORE", 8071ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 8072ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8073ecd94f1bSKan Liang "SampleAfterValue": "100003", 8074ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 8075ecd94f1bSKan Liang }, 8076ecd94f1bSKan Liang { 8077ecd94f1bSKan Liang "Offcore": "1", 8078ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 8079ecd94f1bSKan Liang "UMask": "0x1", 8080ecd94f1bSKan Liang "BriefDescription": "TBD TBD TBD", 8081ecd94f1bSKan Liang "MSRValue": "0x3FBC000490", 8082ecd94f1bSKan Liang "Counter": "0,1,2,3", 8083ecd94f1bSKan Liang "EventName": "OCR.ALL_PF_DATA_RD.L3_MISS.ANY_SNOOP", 8084ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 8085ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8086ecd94f1bSKan Liang "SampleAfterValue": "100003", 8087ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 8088ecd94f1bSKan Liang }, 8089ecd94f1bSKan Liang { 8090ecd94f1bSKan Liang "Offcore": "1", 8091ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 8092ecd94f1bSKan Liang "UMask": "0x1", 8093ecd94f1bSKan Liang "BriefDescription": "TBD", 8094ecd94f1bSKan Liang "MSRValue": "0x0084000120", 8095ecd94f1bSKan Liang "Counter": "0,1,2,3", 8096ecd94f1bSKan Liang "EventName": "OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NONE", 8097ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 8098ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8099ecd94f1bSKan Liang "SampleAfterValue": "100003", 8100ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 8101ecd94f1bSKan Liang }, 8102ecd94f1bSKan Liang { 8103ecd94f1bSKan Liang "Offcore": "1", 8104ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 8105ecd94f1bSKan Liang "UMask": "0x1", 8106ecd94f1bSKan Liang "BriefDescription": "TBD TBD", 8107ecd94f1bSKan Liang "MSRValue": "0x0104000120", 8108ecd94f1bSKan Liang "Counter": "0,1,2,3", 8109ecd94f1bSKan Liang "EventName": "OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED", 8110ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 8111ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8112ecd94f1bSKan Liang "SampleAfterValue": "100003", 8113ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 8114ecd94f1bSKan Liang }, 8115ecd94f1bSKan Liang { 8116ecd94f1bSKan Liang "Offcore": "1", 8117ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 8118ecd94f1bSKan Liang "UMask": "0x1", 8119ecd94f1bSKan Liang "BriefDescription": "TBD", 8120ecd94f1bSKan Liang "MSRValue": "0x0204000120", 8121ecd94f1bSKan Liang "Counter": "0,1,2,3", 8122ecd94f1bSKan Liang "EventName": "OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS", 8123ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 8124ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8125ecd94f1bSKan Liang "SampleAfterValue": "100003", 8126ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 8127ecd94f1bSKan Liang }, 8128ecd94f1bSKan Liang { 8129ecd94f1bSKan Liang "Offcore": "1", 8130ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 8131ecd94f1bSKan Liang "UMask": "0x1", 8132ecd94f1bSKan Liang "BriefDescription": "TBD TBD", 8133ecd94f1bSKan Liang "MSRValue": "0x0404000120", 8134ecd94f1bSKan Liang "Counter": "0,1,2,3", 8135ecd94f1bSKan Liang "EventName": "OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD", 8136ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 8137ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8138ecd94f1bSKan Liang "SampleAfterValue": "100003", 8139ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 8140ecd94f1bSKan Liang }, 8141ecd94f1bSKan Liang { 8142ecd94f1bSKan Liang "Offcore": "1", 8143ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 8144ecd94f1bSKan Liang "UMask": "0x1", 8145ecd94f1bSKan Liang "BriefDescription": "TBD TBD", 8146ecd94f1bSKan Liang "MSRValue": "0x0804000120", 8147ecd94f1bSKan Liang "Counter": "0,1,2,3", 8148ecd94f1bSKan Liang "EventName": "OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD", 8149ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 8150ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8151ecd94f1bSKan Liang "SampleAfterValue": "100003", 8152ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 8153ecd94f1bSKan Liang }, 8154ecd94f1bSKan Liang { 8155ecd94f1bSKan Liang "Offcore": "1", 8156ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 8157ecd94f1bSKan Liang "UMask": "0x1", 8158ecd94f1bSKan Liang "BriefDescription": "TBD TBD", 8159ecd94f1bSKan Liang "MSRValue": "0x1004000120", 8160ecd94f1bSKan Liang "Counter": "0,1,2,3", 8161ecd94f1bSKan Liang "EventName": "OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE", 8162ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 8163ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8164ecd94f1bSKan Liang "SampleAfterValue": "100003", 8165ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 8166ecd94f1bSKan Liang }, 8167ecd94f1bSKan Liang { 8168ecd94f1bSKan Liang "Offcore": "1", 8169ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 8170ecd94f1bSKan Liang "UMask": "0x1", 8171ecd94f1bSKan Liang "BriefDescription": "TBD TBD", 8172ecd94f1bSKan Liang "MSRValue": "0x3F84000120", 8173ecd94f1bSKan Liang "Counter": "0,1,2,3", 8174ecd94f1bSKan Liang "EventName": "OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.ANY_SNOOP", 8175ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 8176ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8177ecd94f1bSKan Liang "SampleAfterValue": "100003", 8178ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 8179ecd94f1bSKan Liang }, 8180ecd94f1bSKan Liang { 8181ecd94f1bSKan Liang "Offcore": "1", 8182ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 8183ecd94f1bSKan Liang "UMask": "0x1", 8184ecd94f1bSKan Liang "BriefDescription": "TBD", 8185ecd94f1bSKan Liang "MSRValue": "0x0090000120", 8186ecd94f1bSKan Liang "Counter": "0,1,2,3", 8187ecd94f1bSKan Liang "EventName": "OCR.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE", 8188ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 8189ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8190ecd94f1bSKan Liang "SampleAfterValue": "100003", 8191ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 8192ecd94f1bSKan Liang }, 8193ecd94f1bSKan Liang { 8194ecd94f1bSKan Liang "Offcore": "1", 8195ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 8196ecd94f1bSKan Liang "UMask": "0x1", 8197ecd94f1bSKan Liang "BriefDescription": "TBD TBD", 8198ecd94f1bSKan Liang "MSRValue": "0x0110000120", 8199ecd94f1bSKan Liang "Counter": "0,1,2,3", 8200ecd94f1bSKan Liang "EventName": "OCR.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED", 8201ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 8202ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8203ecd94f1bSKan Liang "SampleAfterValue": "100003", 8204ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 8205ecd94f1bSKan Liang }, 8206ecd94f1bSKan Liang { 8207ecd94f1bSKan Liang "Offcore": "1", 8208ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 8209ecd94f1bSKan Liang "UMask": "0x1", 8210ecd94f1bSKan Liang "BriefDescription": "TBD", 8211ecd94f1bSKan Liang "MSRValue": "0x0210000120", 8212ecd94f1bSKan Liang "Counter": "0,1,2,3", 8213ecd94f1bSKan Liang "EventName": "OCR.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS", 8214ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 8215ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8216ecd94f1bSKan Liang "SampleAfterValue": "100003", 8217ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 8218ecd94f1bSKan Liang }, 8219ecd94f1bSKan Liang { 8220ecd94f1bSKan Liang "Offcore": "1", 8221ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 8222ecd94f1bSKan Liang "UMask": "0x1", 8223ecd94f1bSKan Liang "BriefDescription": "TBD TBD", 8224ecd94f1bSKan Liang "MSRValue": "0x0410000120", 8225ecd94f1bSKan Liang "Counter": "0,1,2,3", 8226ecd94f1bSKan Liang "EventName": "OCR.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD", 8227ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 8228ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8229ecd94f1bSKan Liang "SampleAfterValue": "100003", 8230ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 8231ecd94f1bSKan Liang }, 8232ecd94f1bSKan Liang { 8233ecd94f1bSKan Liang "Offcore": "1", 8234ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 8235ecd94f1bSKan Liang "UMask": "0x1", 8236ecd94f1bSKan Liang "BriefDescription": "TBD TBD", 8237ecd94f1bSKan Liang "MSRValue": "0x0810000120", 8238ecd94f1bSKan Liang "Counter": "0,1,2,3", 8239ecd94f1bSKan Liang "EventName": "OCR.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD", 8240ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 8241ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8242ecd94f1bSKan Liang "SampleAfterValue": "100003", 8243ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 8244ecd94f1bSKan Liang }, 8245ecd94f1bSKan Liang { 8246ecd94f1bSKan Liang "Offcore": "1", 8247ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 8248ecd94f1bSKan Liang "UMask": "0x1", 8249ecd94f1bSKan Liang "BriefDescription": "TBD TBD", 8250ecd94f1bSKan Liang "MSRValue": "0x1010000120", 8251ecd94f1bSKan Liang "Counter": "0,1,2,3", 8252ecd94f1bSKan Liang "EventName": "OCR.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE", 8253ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 8254ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8255ecd94f1bSKan Liang "SampleAfterValue": "100003", 8256ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 8257ecd94f1bSKan Liang }, 8258ecd94f1bSKan Liang { 8259ecd94f1bSKan Liang "Offcore": "1", 8260ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 8261ecd94f1bSKan Liang "UMask": "0x1", 8262ecd94f1bSKan Liang "BriefDescription": "TBD TBD", 8263ecd94f1bSKan Liang "MSRValue": "0x3F90000120", 8264ecd94f1bSKan Liang "Counter": "0,1,2,3", 8265ecd94f1bSKan Liang "EventName": "OCR.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP", 8266ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 8267ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8268ecd94f1bSKan Liang "SampleAfterValue": "100003", 8269ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 8270ecd94f1bSKan Liang }, 8271ecd94f1bSKan Liang { 8272ecd94f1bSKan Liang "Offcore": "1", 8273ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 8274ecd94f1bSKan Liang "UMask": "0x1", 8275ecd94f1bSKan Liang "BriefDescription": "TBD TBD", 8276ecd94f1bSKan Liang "MSRValue": "0x00BC000120", 8277ecd94f1bSKan Liang "Counter": "0,1,2,3", 8278ecd94f1bSKan Liang "EventName": "OCR.ALL_PF_RFO.L3_MISS.SNOOP_NONE", 8279ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 8280ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8281ecd94f1bSKan Liang "SampleAfterValue": "100003", 8282ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 8283ecd94f1bSKan Liang }, 8284ecd94f1bSKan Liang { 8285ecd94f1bSKan Liang "Offcore": "1", 8286ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 8287ecd94f1bSKan Liang "UMask": "0x1", 8288ecd94f1bSKan Liang "BriefDescription": "TBD TBD TBD", 8289ecd94f1bSKan Liang "MSRValue": "0x013C000120", 8290ecd94f1bSKan Liang "Counter": "0,1,2,3", 8291ecd94f1bSKan Liang "EventName": "OCR.ALL_PF_RFO.L3_MISS.NO_SNOOP_NEEDED", 8292ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 8293ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8294ecd94f1bSKan Liang "SampleAfterValue": "100003", 8295ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 8296ecd94f1bSKan Liang }, 8297ecd94f1bSKan Liang { 8298ecd94f1bSKan Liang "Offcore": "1", 8299ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 8300ecd94f1bSKan Liang "UMask": "0x1", 8301ecd94f1bSKan Liang "BriefDescription": "TBD TBD", 8302ecd94f1bSKan Liang "MSRValue": "0x023C000120", 8303ecd94f1bSKan Liang "Counter": "0,1,2,3", 8304ecd94f1bSKan Liang "EventName": "OCR.ALL_PF_RFO.L3_MISS.SNOOP_MISS", 8305ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 8306ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8307ecd94f1bSKan Liang "SampleAfterValue": "100003", 8308ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 8309ecd94f1bSKan Liang }, 8310ecd94f1bSKan Liang { 8311ecd94f1bSKan Liang "Offcore": "1", 8312ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 8313ecd94f1bSKan Liang "UMask": "0x1", 8314ecd94f1bSKan Liang "BriefDescription": "TBD TBD TBD", 8315ecd94f1bSKan Liang "MSRValue": "0x043C000120", 8316ecd94f1bSKan Liang "Counter": "0,1,2,3", 8317ecd94f1bSKan Liang "EventName": "OCR.ALL_PF_RFO.L3_MISS.HIT_OTHER_CORE_NO_FWD", 8318ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 8319ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8320ecd94f1bSKan Liang "SampleAfterValue": "100003", 8321ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 8322ecd94f1bSKan Liang }, 8323ecd94f1bSKan Liang { 8324ecd94f1bSKan Liang "Offcore": "1", 8325ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 8326ecd94f1bSKan Liang "UMask": "0x1", 8327ecd94f1bSKan Liang "BriefDescription": "TBD TBD TBD", 8328ecd94f1bSKan Liang "MSRValue": "0x083C000120", 8329ecd94f1bSKan Liang "Counter": "0,1,2,3", 8330ecd94f1bSKan Liang "EventName": "OCR.ALL_PF_RFO.L3_MISS.HIT_OTHER_CORE_FWD", 8331ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 8332ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8333ecd94f1bSKan Liang "SampleAfterValue": "100003", 8334ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 8335ecd94f1bSKan Liang }, 8336ecd94f1bSKan Liang { 8337ecd94f1bSKan Liang "Offcore": "1", 8338ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 8339ecd94f1bSKan Liang "UMask": "0x1", 8340ecd94f1bSKan Liang "BriefDescription": "TBD TBD TBD", 8341ecd94f1bSKan Liang "MSRValue": "0x103C000120", 8342ecd94f1bSKan Liang "Counter": "0,1,2,3", 8343ecd94f1bSKan Liang "EventName": "OCR.ALL_PF_RFO.L3_MISS.HITM_OTHER_CORE", 8344ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 8345ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8346ecd94f1bSKan Liang "SampleAfterValue": "100003", 8347ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 8348ecd94f1bSKan Liang }, 8349ecd94f1bSKan Liang { 8350ecd94f1bSKan Liang "Offcore": "1", 8351ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 8352ecd94f1bSKan Liang "UMask": "0x1", 8353ecd94f1bSKan Liang "BriefDescription": "TBD TBD TBD", 8354ecd94f1bSKan Liang "MSRValue": "0x3FBC000120", 8355ecd94f1bSKan Liang "Counter": "0,1,2,3", 8356ecd94f1bSKan Liang "EventName": "OCR.ALL_PF_RFO.L3_MISS.ANY_SNOOP", 8357ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 8358ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8359ecd94f1bSKan Liang "SampleAfterValue": "100003", 8360ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 8361ecd94f1bSKan Liang }, 8362ecd94f1bSKan Liang { 8363ecd94f1bSKan Liang "Offcore": "1", 8364ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 8365ecd94f1bSKan Liang "UMask": "0x1", 8366ecd94f1bSKan Liang "BriefDescription": "TBD", 8367ecd94f1bSKan Liang "MSRValue": "0x0084000491", 8368ecd94f1bSKan Liang "Counter": "0,1,2,3", 8369ecd94f1bSKan Liang "EventName": "OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NONE", 8370ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 8371ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8372ecd94f1bSKan Liang "SampleAfterValue": "100003", 8373ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 8374ecd94f1bSKan Liang }, 8375ecd94f1bSKan Liang { 8376ecd94f1bSKan Liang "Offcore": "1", 8377ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 8378ecd94f1bSKan Liang "UMask": "0x1", 8379ecd94f1bSKan Liang "BriefDescription": "TBD TBD", 8380ecd94f1bSKan Liang "MSRValue": "0x0104000491", 8381ecd94f1bSKan Liang "Counter": "0,1,2,3", 8382ecd94f1bSKan Liang "EventName": "OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED", 8383ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 8384ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8385ecd94f1bSKan Liang "SampleAfterValue": "100003", 8386ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 8387ecd94f1bSKan Liang }, 8388ecd94f1bSKan Liang { 8389ecd94f1bSKan Liang "Offcore": "1", 8390ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 8391ecd94f1bSKan Liang "UMask": "0x1", 8392ecd94f1bSKan Liang "BriefDescription": "TBD", 8393ecd94f1bSKan Liang "MSRValue": "0x0204000491", 8394ecd94f1bSKan Liang "Counter": "0,1,2,3", 8395ecd94f1bSKan Liang "EventName": "OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS", 8396ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 8397ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8398ecd94f1bSKan Liang "SampleAfterValue": "100003", 8399ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 8400ecd94f1bSKan Liang }, 8401ecd94f1bSKan Liang { 8402ecd94f1bSKan Liang "Offcore": "1", 8403ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 8404ecd94f1bSKan Liang "UMask": "0x1", 8405ecd94f1bSKan Liang "BriefDescription": "TBD TBD", 8406ecd94f1bSKan Liang "MSRValue": "0x0404000491", 8407ecd94f1bSKan Liang "Counter": "0,1,2,3", 8408ecd94f1bSKan Liang "EventName": "OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD", 8409ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 8410ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8411ecd94f1bSKan Liang "SampleAfterValue": "100003", 8412ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 8413ecd94f1bSKan Liang }, 8414ecd94f1bSKan Liang { 8415ecd94f1bSKan Liang "Offcore": "1", 8416ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 8417ecd94f1bSKan Liang "UMask": "0x1", 8418ecd94f1bSKan Liang "BriefDescription": "TBD TBD", 8419ecd94f1bSKan Liang "MSRValue": "0x0804000491", 8420ecd94f1bSKan Liang "Counter": "0,1,2,3", 8421ecd94f1bSKan Liang "EventName": "OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD", 8422ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 8423ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8424ecd94f1bSKan Liang "SampleAfterValue": "100003", 8425ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 8426ecd94f1bSKan Liang }, 8427ecd94f1bSKan Liang { 8428ecd94f1bSKan Liang "Offcore": "1", 8429ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 8430ecd94f1bSKan Liang "UMask": "0x1", 8431ecd94f1bSKan Liang "BriefDescription": "TBD TBD", 8432ecd94f1bSKan Liang "MSRValue": "0x1004000491", 8433ecd94f1bSKan Liang "Counter": "0,1,2,3", 8434ecd94f1bSKan Liang "EventName": "OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE", 8435ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 8436ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8437ecd94f1bSKan Liang "SampleAfterValue": "100003", 8438ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 8439ecd94f1bSKan Liang }, 8440ecd94f1bSKan Liang { 8441ecd94f1bSKan Liang "Offcore": "1", 8442ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 8443ecd94f1bSKan Liang "UMask": "0x1", 8444ecd94f1bSKan Liang "BriefDescription": "TBD TBD", 8445ecd94f1bSKan Liang "MSRValue": "0x3F84000491", 8446ecd94f1bSKan Liang "Counter": "0,1,2,3", 8447ecd94f1bSKan Liang "EventName": "OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP", 8448ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 8449ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8450ecd94f1bSKan Liang "SampleAfterValue": "100003", 8451ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 8452ecd94f1bSKan Liang }, 8453ecd94f1bSKan Liang { 8454ecd94f1bSKan Liang "Offcore": "1", 8455ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 8456ecd94f1bSKan Liang "UMask": "0x1", 8457ecd94f1bSKan Liang "BriefDescription": "TBD", 8458ecd94f1bSKan Liang "MSRValue": "0x0090000491", 8459ecd94f1bSKan Liang "Counter": "0,1,2,3", 8460ecd94f1bSKan Liang "EventName": "OCR.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE", 8461ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 8462ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8463ecd94f1bSKan Liang "SampleAfterValue": "100003", 8464ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 8465ecd94f1bSKan Liang }, 8466ecd94f1bSKan Liang { 8467ecd94f1bSKan Liang "Offcore": "1", 8468ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 8469ecd94f1bSKan Liang "UMask": "0x1", 8470ecd94f1bSKan Liang "BriefDescription": "TBD TBD", 8471ecd94f1bSKan Liang "MSRValue": "0x0110000491", 8472ecd94f1bSKan Liang "Counter": "0,1,2,3", 8473ecd94f1bSKan Liang "EventName": "OCR.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED", 8474ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 8475ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8476ecd94f1bSKan Liang "SampleAfterValue": "100003", 8477ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 8478ecd94f1bSKan Liang }, 8479ecd94f1bSKan Liang { 8480ecd94f1bSKan Liang "Offcore": "1", 8481ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 8482ecd94f1bSKan Liang "UMask": "0x1", 8483ecd94f1bSKan Liang "BriefDescription": "TBD", 8484ecd94f1bSKan Liang "MSRValue": "0x0210000491", 8485ecd94f1bSKan Liang "Counter": "0,1,2,3", 8486ecd94f1bSKan Liang "EventName": "OCR.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS", 8487ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 8488ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8489ecd94f1bSKan Liang "SampleAfterValue": "100003", 8490ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 8491ecd94f1bSKan Liang }, 8492ecd94f1bSKan Liang { 8493ecd94f1bSKan Liang "Offcore": "1", 8494ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 8495ecd94f1bSKan Liang "UMask": "0x1", 8496ecd94f1bSKan Liang "BriefDescription": "TBD TBD", 8497ecd94f1bSKan Liang "MSRValue": "0x0410000491", 8498ecd94f1bSKan Liang "Counter": "0,1,2,3", 8499ecd94f1bSKan Liang "EventName": "OCR.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD", 8500ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 8501ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8502ecd94f1bSKan Liang "SampleAfterValue": "100003", 8503ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 8504ecd94f1bSKan Liang }, 8505ecd94f1bSKan Liang { 8506ecd94f1bSKan Liang "Offcore": "1", 8507ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 8508ecd94f1bSKan Liang "UMask": "0x1", 8509ecd94f1bSKan Liang "BriefDescription": "TBD TBD", 8510ecd94f1bSKan Liang "MSRValue": "0x0810000491", 8511ecd94f1bSKan Liang "Counter": "0,1,2,3", 8512ecd94f1bSKan Liang "EventName": "OCR.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD", 8513ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 8514ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8515ecd94f1bSKan Liang "SampleAfterValue": "100003", 8516ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 8517ecd94f1bSKan Liang }, 8518ecd94f1bSKan Liang { 8519ecd94f1bSKan Liang "Offcore": "1", 8520ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 8521ecd94f1bSKan Liang "UMask": "0x1", 8522ecd94f1bSKan Liang "BriefDescription": "TBD TBD", 8523ecd94f1bSKan Liang "MSRValue": "0x1010000491", 8524ecd94f1bSKan Liang "Counter": "0,1,2,3", 8525ecd94f1bSKan Liang "EventName": "OCR.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE", 8526ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 8527ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8528ecd94f1bSKan Liang "SampleAfterValue": "100003", 8529ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 8530ecd94f1bSKan Liang }, 8531ecd94f1bSKan Liang { 8532ecd94f1bSKan Liang "Offcore": "1", 8533ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 8534ecd94f1bSKan Liang "UMask": "0x1", 8535ecd94f1bSKan Liang "BriefDescription": "TBD TBD", 8536ecd94f1bSKan Liang "MSRValue": "0x3F90000491", 8537ecd94f1bSKan Liang "Counter": "0,1,2,3", 8538ecd94f1bSKan Liang "EventName": "OCR.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP", 8539ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 8540ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8541ecd94f1bSKan Liang "SampleAfterValue": "100003", 8542ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 8543ecd94f1bSKan Liang }, 8544ecd94f1bSKan Liang { 8545ecd94f1bSKan Liang "Offcore": "1", 8546ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 8547ecd94f1bSKan Liang "UMask": "0x1", 8548ecd94f1bSKan Liang "BriefDescription": "TBD TBD", 8549ecd94f1bSKan Liang "MSRValue": "0x00BC000491", 8550ecd94f1bSKan Liang "Counter": "0,1,2,3", 8551ecd94f1bSKan Liang "EventName": "OCR.ALL_DATA_RD.L3_MISS.SNOOP_NONE", 8552ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 8553ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8554ecd94f1bSKan Liang "SampleAfterValue": "100003", 8555ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 8556ecd94f1bSKan Liang }, 8557ecd94f1bSKan Liang { 8558ecd94f1bSKan Liang "Offcore": "1", 8559ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 8560ecd94f1bSKan Liang "UMask": "0x1", 8561ecd94f1bSKan Liang "BriefDescription": "TBD TBD TBD", 8562ecd94f1bSKan Liang "MSRValue": "0x013C000491", 8563ecd94f1bSKan Liang "Counter": "0,1,2,3", 8564ecd94f1bSKan Liang "EventName": "OCR.ALL_DATA_RD.L3_MISS.NO_SNOOP_NEEDED", 8565ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 8566ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8567ecd94f1bSKan Liang "SampleAfterValue": "100003", 8568ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 8569ecd94f1bSKan Liang }, 8570ecd94f1bSKan Liang { 8571ecd94f1bSKan Liang "Offcore": "1", 8572ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 8573ecd94f1bSKan Liang "UMask": "0x1", 8574ecd94f1bSKan Liang "BriefDescription": "TBD TBD", 8575ecd94f1bSKan Liang "MSRValue": "0x023C000491", 8576ecd94f1bSKan Liang "Counter": "0,1,2,3", 8577ecd94f1bSKan Liang "EventName": "OCR.ALL_DATA_RD.L3_MISS.SNOOP_MISS", 8578ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 8579ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8580ecd94f1bSKan Liang "SampleAfterValue": "100003", 8581ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 8582ecd94f1bSKan Liang }, 8583ecd94f1bSKan Liang { 8584ecd94f1bSKan Liang "Offcore": "1", 8585ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 8586ecd94f1bSKan Liang "UMask": "0x1", 8587ecd94f1bSKan Liang "BriefDescription": "TBD TBD TBD", 8588ecd94f1bSKan Liang "MSRValue": "0x043C000491", 8589ecd94f1bSKan Liang "Counter": "0,1,2,3", 8590ecd94f1bSKan Liang "EventName": "OCR.ALL_DATA_RD.L3_MISS.HIT_OTHER_CORE_NO_FWD", 8591ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 8592ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8593ecd94f1bSKan Liang "SampleAfterValue": "100003", 8594ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 8595ecd94f1bSKan Liang }, 8596ecd94f1bSKan Liang { 8597ecd94f1bSKan Liang "Offcore": "1", 8598ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 8599ecd94f1bSKan Liang "UMask": "0x1", 8600ecd94f1bSKan Liang "BriefDescription": "TBD TBD TBD", 8601ecd94f1bSKan Liang "MSRValue": "0x083C000491", 8602ecd94f1bSKan Liang "Counter": "0,1,2,3", 8603ecd94f1bSKan Liang "EventName": "OCR.ALL_DATA_RD.L3_MISS.HIT_OTHER_CORE_FWD", 8604ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 8605ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8606ecd94f1bSKan Liang "SampleAfterValue": "100003", 8607ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 8608ecd94f1bSKan Liang }, 8609ecd94f1bSKan Liang { 8610ecd94f1bSKan Liang "Offcore": "1", 8611ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 8612ecd94f1bSKan Liang "UMask": "0x1", 8613ecd94f1bSKan Liang "BriefDescription": "TBD TBD TBD", 8614ecd94f1bSKan Liang "MSRValue": "0x103C000491", 8615ecd94f1bSKan Liang "Counter": "0,1,2,3", 8616ecd94f1bSKan Liang "EventName": "OCR.ALL_DATA_RD.L3_MISS.HITM_OTHER_CORE", 8617ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 8618ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8619ecd94f1bSKan Liang "SampleAfterValue": "100003", 8620ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 8621ecd94f1bSKan Liang }, 8622ecd94f1bSKan Liang { 8623ecd94f1bSKan Liang "Offcore": "1", 8624ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 8625ecd94f1bSKan Liang "UMask": "0x1", 8626ecd94f1bSKan Liang "BriefDescription": "TBD TBD TBD", 8627ecd94f1bSKan Liang "MSRValue": "0x3FBC000491", 8628ecd94f1bSKan Liang "Counter": "0,1,2,3", 8629ecd94f1bSKan Liang "EventName": "OCR.ALL_DATA_RD.L3_MISS.ANY_SNOOP", 8630ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 8631ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8632ecd94f1bSKan Liang "SampleAfterValue": "100003", 8633ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 8634ecd94f1bSKan Liang }, 8635ecd94f1bSKan Liang { 8636ecd94f1bSKan Liang "Offcore": "1", 8637ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 8638ecd94f1bSKan Liang "UMask": "0x1", 8639ecd94f1bSKan Liang "BriefDescription": "TBD", 8640ecd94f1bSKan Liang "MSRValue": "0x0084000122", 8641ecd94f1bSKan Liang "Counter": "0,1,2,3", 8642ecd94f1bSKan Liang "EventName": "OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NONE", 8643ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 8644ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8645ecd94f1bSKan Liang "SampleAfterValue": "100003", 8646ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 8647ecd94f1bSKan Liang }, 8648ecd94f1bSKan Liang { 8649ecd94f1bSKan Liang "Offcore": "1", 8650ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 8651ecd94f1bSKan Liang "UMask": "0x1", 8652ecd94f1bSKan Liang "BriefDescription": "TBD TBD", 8653ecd94f1bSKan Liang "MSRValue": "0x0104000122", 8654ecd94f1bSKan Liang "Counter": "0,1,2,3", 8655ecd94f1bSKan Liang "EventName": "OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED", 8656ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 8657ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8658ecd94f1bSKan Liang "SampleAfterValue": "100003", 8659ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 8660ecd94f1bSKan Liang }, 8661ecd94f1bSKan Liang { 8662ecd94f1bSKan Liang "Offcore": "1", 8663ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 8664ecd94f1bSKan Liang "UMask": "0x1", 8665ecd94f1bSKan Liang "BriefDescription": "TBD", 8666ecd94f1bSKan Liang "MSRValue": "0x0204000122", 8667ecd94f1bSKan Liang "Counter": "0,1,2,3", 8668ecd94f1bSKan Liang "EventName": "OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS", 8669ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 8670ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8671ecd94f1bSKan Liang "SampleAfterValue": "100003", 8672ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 8673ecd94f1bSKan Liang }, 8674ecd94f1bSKan Liang { 8675ecd94f1bSKan Liang "Offcore": "1", 8676ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 8677ecd94f1bSKan Liang "UMask": "0x1", 8678ecd94f1bSKan Liang "BriefDescription": "TBD TBD", 8679ecd94f1bSKan Liang "MSRValue": "0x0404000122", 8680ecd94f1bSKan Liang "Counter": "0,1,2,3", 8681ecd94f1bSKan Liang "EventName": "OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD", 8682ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 8683ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8684ecd94f1bSKan Liang "SampleAfterValue": "100003", 8685ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 8686ecd94f1bSKan Liang }, 8687ecd94f1bSKan Liang { 8688ecd94f1bSKan Liang "Offcore": "1", 8689ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 8690ecd94f1bSKan Liang "UMask": "0x1", 8691ecd94f1bSKan Liang "BriefDescription": "TBD TBD", 8692ecd94f1bSKan Liang "MSRValue": "0x0804000122", 8693ecd94f1bSKan Liang "Counter": "0,1,2,3", 8694ecd94f1bSKan Liang "EventName": "OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD", 8695ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 8696ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8697ecd94f1bSKan Liang "SampleAfterValue": "100003", 8698ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 8699ecd94f1bSKan Liang }, 8700ecd94f1bSKan Liang { 8701ecd94f1bSKan Liang "Offcore": "1", 8702ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 8703ecd94f1bSKan Liang "UMask": "0x1", 8704ecd94f1bSKan Liang "BriefDescription": "TBD TBD", 8705ecd94f1bSKan Liang "MSRValue": "0x1004000122", 8706ecd94f1bSKan Liang "Counter": "0,1,2,3", 8707ecd94f1bSKan Liang "EventName": "OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE", 8708ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 8709ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8710ecd94f1bSKan Liang "SampleAfterValue": "100003", 8711ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 8712ecd94f1bSKan Liang }, 8713ecd94f1bSKan Liang { 8714ecd94f1bSKan Liang "Offcore": "1", 8715ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 8716ecd94f1bSKan Liang "UMask": "0x1", 8717ecd94f1bSKan Liang "BriefDescription": "TBD TBD", 8718ecd94f1bSKan Liang "MSRValue": "0x3F84000122", 8719ecd94f1bSKan Liang "Counter": "0,1,2,3", 8720ecd94f1bSKan Liang "EventName": "OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.ANY_SNOOP", 8721ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 8722ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8723ecd94f1bSKan Liang "SampleAfterValue": "100003", 8724ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 8725ecd94f1bSKan Liang }, 8726ecd94f1bSKan Liang { 8727ecd94f1bSKan Liang "Offcore": "1", 8728ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 8729ecd94f1bSKan Liang "UMask": "0x1", 8730ecd94f1bSKan Liang "BriefDescription": "TBD", 8731ecd94f1bSKan Liang "MSRValue": "0x0090000122", 8732ecd94f1bSKan Liang "Counter": "0,1,2,3", 8733ecd94f1bSKan Liang "EventName": "OCR.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE", 8734ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 8735ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8736ecd94f1bSKan Liang "SampleAfterValue": "100003", 8737ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 8738ecd94f1bSKan Liang }, 8739ecd94f1bSKan Liang { 8740ecd94f1bSKan Liang "Offcore": "1", 8741ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 8742ecd94f1bSKan Liang "UMask": "0x1", 8743ecd94f1bSKan Liang "BriefDescription": "TBD TBD", 8744ecd94f1bSKan Liang "MSRValue": "0x0110000122", 8745ecd94f1bSKan Liang "Counter": "0,1,2,3", 8746ecd94f1bSKan Liang "EventName": "OCR.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED", 8747ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 8748ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8749ecd94f1bSKan Liang "SampleAfterValue": "100003", 8750ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 8751ecd94f1bSKan Liang }, 8752ecd94f1bSKan Liang { 8753ecd94f1bSKan Liang "Offcore": "1", 8754ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 8755ecd94f1bSKan Liang "UMask": "0x1", 8756ecd94f1bSKan Liang "BriefDescription": "TBD", 8757ecd94f1bSKan Liang "MSRValue": "0x0210000122", 8758ecd94f1bSKan Liang "Counter": "0,1,2,3", 8759ecd94f1bSKan Liang "EventName": "OCR.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS", 8760ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 8761ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8762ecd94f1bSKan Liang "SampleAfterValue": "100003", 8763ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 8764ecd94f1bSKan Liang }, 8765ecd94f1bSKan Liang { 8766ecd94f1bSKan Liang "Offcore": "1", 8767ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 8768ecd94f1bSKan Liang "UMask": "0x1", 8769ecd94f1bSKan Liang "BriefDescription": "TBD TBD", 8770ecd94f1bSKan Liang "MSRValue": "0x0410000122", 8771ecd94f1bSKan Liang "Counter": "0,1,2,3", 8772ecd94f1bSKan Liang "EventName": "OCR.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD", 8773ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 8774ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8775ecd94f1bSKan Liang "SampleAfterValue": "100003", 8776ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 8777ecd94f1bSKan Liang }, 8778ecd94f1bSKan Liang { 8779ecd94f1bSKan Liang "Offcore": "1", 8780ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 8781ecd94f1bSKan Liang "UMask": "0x1", 8782ecd94f1bSKan Liang "BriefDescription": "TBD TBD", 8783ecd94f1bSKan Liang "MSRValue": "0x0810000122", 8784ecd94f1bSKan Liang "Counter": "0,1,2,3", 8785ecd94f1bSKan Liang "EventName": "OCR.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD", 8786ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 8787ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8788ecd94f1bSKan Liang "SampleAfterValue": "100003", 8789ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 8790ecd94f1bSKan Liang }, 8791ecd94f1bSKan Liang { 8792ecd94f1bSKan Liang "Offcore": "1", 8793ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 8794ecd94f1bSKan Liang "UMask": "0x1", 8795ecd94f1bSKan Liang "BriefDescription": "TBD TBD", 8796ecd94f1bSKan Liang "MSRValue": "0x1010000122", 8797ecd94f1bSKan Liang "Counter": "0,1,2,3", 8798ecd94f1bSKan Liang "EventName": "OCR.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE", 8799ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 8800ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8801ecd94f1bSKan Liang "SampleAfterValue": "100003", 8802ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 8803ecd94f1bSKan Liang }, 8804ecd94f1bSKan Liang { 8805ecd94f1bSKan Liang "Offcore": "1", 8806ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 8807ecd94f1bSKan Liang "UMask": "0x1", 8808ecd94f1bSKan Liang "BriefDescription": "TBD TBD", 8809ecd94f1bSKan Liang "MSRValue": "0x3F90000122", 8810ecd94f1bSKan Liang "Counter": "0,1,2,3", 8811ecd94f1bSKan Liang "EventName": "OCR.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP", 8812ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 8813ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8814ecd94f1bSKan Liang "SampleAfterValue": "100003", 8815ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 8816ecd94f1bSKan Liang }, 8817ecd94f1bSKan Liang { 8818ecd94f1bSKan Liang "Offcore": "1", 8819ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 8820ecd94f1bSKan Liang "UMask": "0x1", 8821ecd94f1bSKan Liang "BriefDescription": "TBD TBD", 8822ecd94f1bSKan Liang "MSRValue": "0x00BC000122", 8823ecd94f1bSKan Liang "Counter": "0,1,2,3", 8824ecd94f1bSKan Liang "EventName": "OCR.ALL_RFO.L3_MISS.SNOOP_NONE", 8825ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 8826ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8827ecd94f1bSKan Liang "SampleAfterValue": "100003", 8828ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 8829ecd94f1bSKan Liang }, 8830ecd94f1bSKan Liang { 8831ecd94f1bSKan Liang "Offcore": "1", 8832ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 8833ecd94f1bSKan Liang "UMask": "0x1", 8834ecd94f1bSKan Liang "BriefDescription": "TBD TBD TBD", 8835ecd94f1bSKan Liang "MSRValue": "0x013C000122", 8836ecd94f1bSKan Liang "Counter": "0,1,2,3", 8837ecd94f1bSKan Liang "EventName": "OCR.ALL_RFO.L3_MISS.NO_SNOOP_NEEDED", 8838ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 8839ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8840ecd94f1bSKan Liang "SampleAfterValue": "100003", 8841ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 8842ecd94f1bSKan Liang }, 8843ecd94f1bSKan Liang { 8844ecd94f1bSKan Liang "Offcore": "1", 8845ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 8846ecd94f1bSKan Liang "UMask": "0x1", 8847ecd94f1bSKan Liang "BriefDescription": "TBD TBD", 8848ecd94f1bSKan Liang "MSRValue": "0x023C000122", 8849ecd94f1bSKan Liang "Counter": "0,1,2,3", 8850ecd94f1bSKan Liang "EventName": "OCR.ALL_RFO.L3_MISS.SNOOP_MISS", 8851ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 8852ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8853ecd94f1bSKan Liang "SampleAfterValue": "100003", 8854ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 8855ecd94f1bSKan Liang }, 8856ecd94f1bSKan Liang { 8857ecd94f1bSKan Liang "Offcore": "1", 8858ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 8859ecd94f1bSKan Liang "UMask": "0x1", 8860ecd94f1bSKan Liang "BriefDescription": "TBD TBD TBD", 8861ecd94f1bSKan Liang "MSRValue": "0x043C000122", 8862ecd94f1bSKan Liang "Counter": "0,1,2,3", 8863ecd94f1bSKan Liang "EventName": "OCR.ALL_RFO.L3_MISS.HIT_OTHER_CORE_NO_FWD", 8864ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 8865ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8866ecd94f1bSKan Liang "SampleAfterValue": "100003", 8867ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 8868ecd94f1bSKan Liang }, 8869ecd94f1bSKan Liang { 8870ecd94f1bSKan Liang "Offcore": "1", 8871ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 8872ecd94f1bSKan Liang "UMask": "0x1", 8873ecd94f1bSKan Liang "BriefDescription": "TBD TBD TBD", 8874ecd94f1bSKan Liang "MSRValue": "0x083C000122", 8875ecd94f1bSKan Liang "Counter": "0,1,2,3", 8876ecd94f1bSKan Liang "EventName": "OCR.ALL_RFO.L3_MISS.HIT_OTHER_CORE_FWD", 8877ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 8878ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8879ecd94f1bSKan Liang "SampleAfterValue": "100003", 8880ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 8881ecd94f1bSKan Liang }, 8882ecd94f1bSKan Liang { 8883ecd94f1bSKan Liang "Offcore": "1", 8884ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 8885ecd94f1bSKan Liang "UMask": "0x1", 8886ecd94f1bSKan Liang "BriefDescription": "TBD TBD TBD", 8887ecd94f1bSKan Liang "MSRValue": "0x103C000122", 8888ecd94f1bSKan Liang "Counter": "0,1,2,3", 8889ecd94f1bSKan Liang "EventName": "OCR.ALL_RFO.L3_MISS.HITM_OTHER_CORE", 8890ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 8891ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8892ecd94f1bSKan Liang "SampleAfterValue": "100003", 8893ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 8894ecd94f1bSKan Liang }, 8895ecd94f1bSKan Liang { 8896ecd94f1bSKan Liang "Offcore": "1", 8897ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 8898ecd94f1bSKan Liang "UMask": "0x1", 8899ecd94f1bSKan Liang "BriefDescription": "TBD TBD TBD", 8900ecd94f1bSKan Liang "MSRValue": "0x3FBC000122", 8901ecd94f1bSKan Liang "Counter": "0,1,2,3", 8902ecd94f1bSKan Liang "EventName": "OCR.ALL_RFO.L3_MISS.ANY_SNOOP", 8903ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 8904ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8905ecd94f1bSKan Liang "SampleAfterValue": "100003", 8906ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 8907ecd94f1bSKan Liang }, 8908ecd94f1bSKan Liang { 8909ecd94f1bSKan Liang "Offcore": "1", 8910ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 8911ecd94f1bSKan Liang "UMask": "0x1", 8912ecd94f1bSKan Liang "BriefDescription": "TBD", 8913ecd94f1bSKan Liang "MSRValue": "0x00840007F7", 8914ecd94f1bSKan Liang "Counter": "0,1,2,3", 8915ecd94f1bSKan Liang "EventName": "OCR.ALL_READS.L3_MISS_LOCAL_DRAM.SNOOP_NONE", 8916ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 8917ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8918ecd94f1bSKan Liang "SampleAfterValue": "100003", 8919ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 8920ecd94f1bSKan Liang }, 8921ecd94f1bSKan Liang { 8922ecd94f1bSKan Liang "Offcore": "1", 8923ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 8924ecd94f1bSKan Liang "UMask": "0x1", 8925ecd94f1bSKan Liang "BriefDescription": "TBD TBD", 8926ecd94f1bSKan Liang "MSRValue": "0x01040007F7", 8927ecd94f1bSKan Liang "Counter": "0,1,2,3", 8928ecd94f1bSKan Liang "EventName": "OCR.ALL_READS.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED", 8929ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 8930ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8931ecd94f1bSKan Liang "SampleAfterValue": "100003", 8932ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 8933ecd94f1bSKan Liang }, 8934ecd94f1bSKan Liang { 8935ecd94f1bSKan Liang "Offcore": "1", 8936ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 8937ecd94f1bSKan Liang "UMask": "0x1", 8938ecd94f1bSKan Liang "BriefDescription": "TBD", 8939ecd94f1bSKan Liang "MSRValue": "0x02040007F7", 8940ecd94f1bSKan Liang "Counter": "0,1,2,3", 8941ecd94f1bSKan Liang "EventName": "OCR.ALL_READS.L3_MISS_LOCAL_DRAM.SNOOP_MISS", 8942ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 8943ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8944ecd94f1bSKan Liang "SampleAfterValue": "100003", 8945ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 8946ecd94f1bSKan Liang }, 8947ecd94f1bSKan Liang { 8948ecd94f1bSKan Liang "Offcore": "1", 8949ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 8950ecd94f1bSKan Liang "UMask": "0x1", 8951ecd94f1bSKan Liang "BriefDescription": "TBD TBD", 8952ecd94f1bSKan Liang "MSRValue": "0x04040007F7", 8953ecd94f1bSKan Liang "Counter": "0,1,2,3", 8954ecd94f1bSKan Liang "EventName": "OCR.ALL_READS.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD", 8955ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 8956ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8957ecd94f1bSKan Liang "SampleAfterValue": "100003", 8958ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 8959ecd94f1bSKan Liang }, 8960ecd94f1bSKan Liang { 8961ecd94f1bSKan Liang "Offcore": "1", 8962ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 8963ecd94f1bSKan Liang "UMask": "0x1", 8964ecd94f1bSKan Liang "BriefDescription": "TBD TBD", 8965ecd94f1bSKan Liang "MSRValue": "0x08040007F7", 8966ecd94f1bSKan Liang "Counter": "0,1,2,3", 8967ecd94f1bSKan Liang "EventName": "OCR.ALL_READS.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD", 8968ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 8969ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8970ecd94f1bSKan Liang "SampleAfterValue": "100003", 8971ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 8972ecd94f1bSKan Liang }, 8973ecd94f1bSKan Liang { 8974ecd94f1bSKan Liang "Offcore": "1", 8975ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 8976ecd94f1bSKan Liang "UMask": "0x1", 8977ecd94f1bSKan Liang "BriefDescription": "TBD TBD", 8978ecd94f1bSKan Liang "MSRValue": "0x10040007F7", 8979ecd94f1bSKan Liang "Counter": "0,1,2,3", 8980ecd94f1bSKan Liang "EventName": "OCR.ALL_READS.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE", 8981ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 8982ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8983ecd94f1bSKan Liang "SampleAfterValue": "100003", 8984ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 8985ecd94f1bSKan Liang }, 8986ecd94f1bSKan Liang { 8987ecd94f1bSKan Liang "Offcore": "1", 8988ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 8989ecd94f1bSKan Liang "UMask": "0x1", 8990ecd94f1bSKan Liang "BriefDescription": "TBD TBD", 8991ecd94f1bSKan Liang "MSRValue": "0x3F840007F7", 8992ecd94f1bSKan Liang "Counter": "0,1,2,3", 8993ecd94f1bSKan Liang "EventName": "OCR.ALL_READS.L3_MISS_LOCAL_DRAM.ANY_SNOOP", 8994ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 8995ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8996ecd94f1bSKan Liang "SampleAfterValue": "100003", 8997ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 8998ecd94f1bSKan Liang }, 8999ecd94f1bSKan Liang { 9000ecd94f1bSKan Liang "Offcore": "1", 9001ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 9002ecd94f1bSKan Liang "UMask": "0x1", 9003ecd94f1bSKan Liang "BriefDescription": "TBD", 9004ecd94f1bSKan Liang "MSRValue": "0x00900007F7", 9005ecd94f1bSKan Liang "Counter": "0,1,2,3", 9006ecd94f1bSKan Liang "EventName": "OCR.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE", 9007ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 9008ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 9009ecd94f1bSKan Liang "SampleAfterValue": "100003", 9010ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 9011ecd94f1bSKan Liang }, 9012ecd94f1bSKan Liang { 9013ecd94f1bSKan Liang "Offcore": "1", 9014ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 9015ecd94f1bSKan Liang "UMask": "0x1", 9016ecd94f1bSKan Liang "BriefDescription": "TBD TBD", 9017ecd94f1bSKan Liang "MSRValue": "0x01100007F7", 9018ecd94f1bSKan Liang "Counter": "0,1,2,3", 9019ecd94f1bSKan Liang "EventName": "OCR.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED", 9020ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 9021ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 9022ecd94f1bSKan Liang "SampleAfterValue": "100003", 9023ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 9024ecd94f1bSKan Liang }, 9025ecd94f1bSKan Liang { 9026ecd94f1bSKan Liang "Offcore": "1", 9027ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 9028ecd94f1bSKan Liang "UMask": "0x1", 9029ecd94f1bSKan Liang "BriefDescription": "TBD", 9030ecd94f1bSKan Liang "MSRValue": "0x02100007F7", 9031ecd94f1bSKan Liang "Counter": "0,1,2,3", 9032ecd94f1bSKan Liang "EventName": "OCR.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS", 9033ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 9034ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 9035ecd94f1bSKan Liang "SampleAfterValue": "100003", 9036ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 9037ecd94f1bSKan Liang }, 9038ecd94f1bSKan Liang { 9039ecd94f1bSKan Liang "Offcore": "1", 9040ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 9041ecd94f1bSKan Liang "UMask": "0x1", 9042ecd94f1bSKan Liang "BriefDescription": "TBD TBD", 9043ecd94f1bSKan Liang "MSRValue": "0x04100007F7", 9044ecd94f1bSKan Liang "Counter": "0,1,2,3", 9045ecd94f1bSKan Liang "EventName": "OCR.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD", 9046ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 9047ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 9048ecd94f1bSKan Liang "SampleAfterValue": "100003", 9049ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 9050ecd94f1bSKan Liang }, 9051ecd94f1bSKan Liang { 9052ecd94f1bSKan Liang "Offcore": "1", 9053ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 9054ecd94f1bSKan Liang "UMask": "0x1", 9055ecd94f1bSKan Liang "BriefDescription": "TBD TBD", 9056ecd94f1bSKan Liang "MSRValue": "0x08100007F7", 9057ecd94f1bSKan Liang "Counter": "0,1,2,3", 9058ecd94f1bSKan Liang "EventName": "OCR.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD", 9059ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 9060ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 9061ecd94f1bSKan Liang "SampleAfterValue": "100003", 9062ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 9063ecd94f1bSKan Liang }, 9064ecd94f1bSKan Liang { 9065ecd94f1bSKan Liang "Offcore": "1", 9066ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 9067ecd94f1bSKan Liang "UMask": "0x1", 9068ecd94f1bSKan Liang "BriefDescription": "TBD TBD", 9069ecd94f1bSKan Liang "MSRValue": "0x10100007F7", 9070ecd94f1bSKan Liang "Counter": "0,1,2,3", 9071ecd94f1bSKan Liang "EventName": "OCR.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE", 9072ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 9073ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 9074ecd94f1bSKan Liang "SampleAfterValue": "100003", 9075ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 9076ecd94f1bSKan Liang }, 9077ecd94f1bSKan Liang { 9078ecd94f1bSKan Liang "Offcore": "1", 9079ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 9080ecd94f1bSKan Liang "UMask": "0x1", 9081ecd94f1bSKan Liang "BriefDescription": "TBD TBD", 9082ecd94f1bSKan Liang "MSRValue": "0x3F900007F7", 9083ecd94f1bSKan Liang "Counter": "0,1,2,3", 9084ecd94f1bSKan Liang "EventName": "OCR.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP", 9085ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 9086ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 9087ecd94f1bSKan Liang "SampleAfterValue": "100003", 9088ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 9089ecd94f1bSKan Liang }, 9090ecd94f1bSKan Liang { 9091ecd94f1bSKan Liang "Offcore": "1", 9092ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 9093ecd94f1bSKan Liang "UMask": "0x1", 9094ecd94f1bSKan Liang "BriefDescription": "TBD TBD", 9095ecd94f1bSKan Liang "MSRValue": "0x00BC0007F7", 9096ecd94f1bSKan Liang "Counter": "0,1,2,3", 9097ecd94f1bSKan Liang "EventName": "OCR.ALL_READS.L3_MISS.SNOOP_NONE", 9098ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 9099ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 9100ecd94f1bSKan Liang "SampleAfterValue": "100003", 9101ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 9102ecd94f1bSKan Liang }, 9103ecd94f1bSKan Liang { 9104ecd94f1bSKan Liang "Offcore": "1", 9105ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 9106ecd94f1bSKan Liang "UMask": "0x1", 9107ecd94f1bSKan Liang "BriefDescription": "TBD TBD TBD", 9108ecd94f1bSKan Liang "MSRValue": "0x013C0007F7", 9109ecd94f1bSKan Liang "Counter": "0,1,2,3", 9110ecd94f1bSKan Liang "EventName": "OCR.ALL_READS.L3_MISS.NO_SNOOP_NEEDED", 9111ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 9112ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 9113ecd94f1bSKan Liang "SampleAfterValue": "100003", 9114ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 9115ecd94f1bSKan Liang }, 9116ecd94f1bSKan Liang { 9117ecd94f1bSKan Liang "Offcore": "1", 9118ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 9119ecd94f1bSKan Liang "UMask": "0x1", 9120ecd94f1bSKan Liang "BriefDescription": "TBD TBD", 9121ecd94f1bSKan Liang "MSRValue": "0x023C0007F7", 9122ecd94f1bSKan Liang "Counter": "0,1,2,3", 9123ecd94f1bSKan Liang "EventName": "OCR.ALL_READS.L3_MISS.SNOOP_MISS", 9124ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 9125ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 9126ecd94f1bSKan Liang "SampleAfterValue": "100003", 9127ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 9128ecd94f1bSKan Liang }, 9129ecd94f1bSKan Liang { 9130ecd94f1bSKan Liang "Offcore": "1", 9131ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 9132ecd94f1bSKan Liang "UMask": "0x1", 9133ecd94f1bSKan Liang "BriefDescription": "TBD TBD TBD", 9134ecd94f1bSKan Liang "MSRValue": "0x043C0007F7", 9135ecd94f1bSKan Liang "Counter": "0,1,2,3", 9136ecd94f1bSKan Liang "EventName": "OCR.ALL_READS.L3_MISS.HIT_OTHER_CORE_NO_FWD", 9137ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 9138ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 9139ecd94f1bSKan Liang "SampleAfterValue": "100003", 9140ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 9141ecd94f1bSKan Liang }, 9142ecd94f1bSKan Liang { 9143ecd94f1bSKan Liang "Offcore": "1", 9144ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 9145ecd94f1bSKan Liang "UMask": "0x1", 9146ecd94f1bSKan Liang "BriefDescription": "TBD TBD TBD", 9147ecd94f1bSKan Liang "MSRValue": "0x083C0007F7", 9148ecd94f1bSKan Liang "Counter": "0,1,2,3", 9149ecd94f1bSKan Liang "EventName": "OCR.ALL_READS.L3_MISS.HIT_OTHER_CORE_FWD", 9150ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 9151ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 9152ecd94f1bSKan Liang "SampleAfterValue": "100003", 9153ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 9154ecd94f1bSKan Liang }, 9155ecd94f1bSKan Liang { 9156ecd94f1bSKan Liang "Offcore": "1", 9157ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 9158ecd94f1bSKan Liang "UMask": "0x1", 9159ecd94f1bSKan Liang "BriefDescription": "TBD TBD TBD", 9160ecd94f1bSKan Liang "MSRValue": "0x103C0007F7", 9161ecd94f1bSKan Liang "Counter": "0,1,2,3", 9162ecd94f1bSKan Liang "EventName": "OCR.ALL_READS.L3_MISS.HITM_OTHER_CORE", 9163ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 9164ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 9165ecd94f1bSKan Liang "SampleAfterValue": "100003", 9166ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 9167ecd94f1bSKan Liang }, 9168ecd94f1bSKan Liang { 9169ecd94f1bSKan Liang "Offcore": "1", 9170ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 9171ecd94f1bSKan Liang "UMask": "0x1", 9172ecd94f1bSKan Liang "BriefDescription": "TBD TBD TBD", 9173ecd94f1bSKan Liang "MSRValue": "0x3FBC0007F7", 9174ecd94f1bSKan Liang "Counter": "0,1,2,3", 9175ecd94f1bSKan Liang "EventName": "OCR.ALL_READS.L3_MISS.ANY_SNOOP", 9176ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 9177ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 9178ecd94f1bSKan Liang "SampleAfterValue": "100003", 9179ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 9180ecd94f1bSKan Liang }, 9181ecd94f1bSKan Liang { 9182ecd94f1bSKan Liang "Offcore": "1", 9183ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 9184ecd94f1bSKan Liang "UMask": "0x1", 9185ecd94f1bSKan Liang "BriefDescription": "Counts demand data reads TBD", 9186ecd94f1bSKan Liang "MSRValue": "0x063B800001", 9187ecd94f1bSKan Liang "Counter": "0,1,2,3", 9188ecd94f1bSKan Liang "EventName": "OCR.DEMAND_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", 9189ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 9190ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 9191ecd94f1bSKan Liang "SampleAfterValue": "100003", 9192ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 9193ecd94f1bSKan Liang }, 9194ecd94f1bSKan Liang { 9195ecd94f1bSKan Liang "Offcore": "1", 9196ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 9197ecd94f1bSKan Liang "UMask": "0x1", 9198ecd94f1bSKan Liang "BriefDescription": "Counts demand data reads TBD", 9199ecd94f1bSKan Liang "MSRValue": "0x0604000001", 9200ecd94f1bSKan Liang "Counter": "0,1,2,3", 9201ecd94f1bSKan Liang "EventName": "OCR.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", 9202ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 9203ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 9204ecd94f1bSKan Liang "SampleAfterValue": "100003", 9205ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 9206ecd94f1bSKan Liang }, 9207ecd94f1bSKan Liang { 9208ecd94f1bSKan Liang "Offcore": "1", 9209ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 9210ecd94f1bSKan Liang "UMask": "0x1", 9211ecd94f1bSKan Liang "BriefDescription": "Counts all demand data writes (RFOs) TBD", 9212ecd94f1bSKan Liang "MSRValue": "0x063B800002", 9213ecd94f1bSKan Liang "Counter": "0,1,2,3", 9214ecd94f1bSKan Liang "EventName": "OCR.DEMAND_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", 9215ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 9216ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 9217ecd94f1bSKan Liang "SampleAfterValue": "100003", 9218ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 9219ecd94f1bSKan Liang }, 9220ecd94f1bSKan Liang { 9221ecd94f1bSKan Liang "Offcore": "1", 9222ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 9223ecd94f1bSKan Liang "UMask": "0x1", 9224ecd94f1bSKan Liang "BriefDescription": "Counts all demand data writes (RFOs) TBD", 9225ecd94f1bSKan Liang "MSRValue": "0x0604000002", 9226ecd94f1bSKan Liang "Counter": "0,1,2,3", 9227ecd94f1bSKan Liang "EventName": "OCR.DEMAND_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", 9228ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 9229ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 9230ecd94f1bSKan Liang "SampleAfterValue": "100003", 9231ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 9232ecd94f1bSKan Liang }, 9233ecd94f1bSKan Liang { 9234ecd94f1bSKan Liang "Offcore": "1", 9235ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 9236ecd94f1bSKan Liang "UMask": "0x1", 9237ecd94f1bSKan Liang "BriefDescription": "Counts all demand code reads TBD", 9238ecd94f1bSKan Liang "MSRValue": "0x063B800004", 9239ecd94f1bSKan Liang "Counter": "0,1,2,3", 9240ecd94f1bSKan Liang "EventName": "OCR.DEMAND_CODE_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", 9241ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 9242ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 9243ecd94f1bSKan Liang "SampleAfterValue": "100003", 9244ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 9245ecd94f1bSKan Liang }, 9246ecd94f1bSKan Liang { 9247ecd94f1bSKan Liang "Offcore": "1", 9248ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 9249ecd94f1bSKan Liang "UMask": "0x1", 9250ecd94f1bSKan Liang "BriefDescription": "Counts all demand code reads TBD", 9251ecd94f1bSKan Liang "MSRValue": "0x0604000004", 9252ecd94f1bSKan Liang "Counter": "0,1,2,3", 9253ecd94f1bSKan Liang "EventName": "OCR.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", 9254ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 9255ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 9256ecd94f1bSKan Liang "SampleAfterValue": "100003", 9257ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 9258ecd94f1bSKan Liang }, 9259ecd94f1bSKan Liang { 9260ecd94f1bSKan Liang "Offcore": "1", 9261ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 9262ecd94f1bSKan Liang "UMask": "0x1", 9263ecd94f1bSKan Liang "BriefDescription": "Counts prefetch (that bring data to L2) data reads TBD", 9264ecd94f1bSKan Liang "MSRValue": "0x063B800010", 9265ecd94f1bSKan Liang "Counter": "0,1,2,3", 9266ecd94f1bSKan Liang "EventName": "OCR.PF_L2_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", 9267ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 9268ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 9269ecd94f1bSKan Liang "SampleAfterValue": "100003", 9270ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 9271ecd94f1bSKan Liang }, 9272ecd94f1bSKan Liang { 9273ecd94f1bSKan Liang "Offcore": "1", 9274ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 9275ecd94f1bSKan Liang "UMask": "0x1", 9276ecd94f1bSKan Liang "BriefDescription": "Counts prefetch (that bring data to L2) data reads TBD", 9277ecd94f1bSKan Liang "MSRValue": "0x0604000010", 9278ecd94f1bSKan Liang "Counter": "0,1,2,3", 9279ecd94f1bSKan Liang "EventName": "OCR.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", 9280ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 9281ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 9282ecd94f1bSKan Liang "SampleAfterValue": "100003", 9283ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 9284ecd94f1bSKan Liang }, 9285ecd94f1bSKan Liang { 9286ecd94f1bSKan Liang "Offcore": "1", 9287ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 9288ecd94f1bSKan Liang "UMask": "0x1", 9289ecd94f1bSKan Liang "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs TBD", 9290ecd94f1bSKan Liang "MSRValue": "0x063B800020", 9291ecd94f1bSKan Liang "Counter": "0,1,2,3", 9292ecd94f1bSKan Liang "EventName": "OCR.PF_L2_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", 9293ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 9294ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 9295ecd94f1bSKan Liang "SampleAfterValue": "100003", 9296ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 9297ecd94f1bSKan Liang }, 9298ecd94f1bSKan Liang { 9299ecd94f1bSKan Liang "Offcore": "1", 9300ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 9301ecd94f1bSKan Liang "UMask": "0x1", 9302ecd94f1bSKan Liang "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs TBD", 9303ecd94f1bSKan Liang "MSRValue": "0x0604000020", 9304ecd94f1bSKan Liang "Counter": "0,1,2,3", 9305ecd94f1bSKan Liang "EventName": "OCR.PF_L2_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", 9306ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 9307ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 9308ecd94f1bSKan Liang "SampleAfterValue": "100003", 9309ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 9310ecd94f1bSKan Liang }, 9311ecd94f1bSKan Liang { 9312ecd94f1bSKan Liang "Offcore": "1", 9313ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 9314ecd94f1bSKan Liang "UMask": "0x1", 9315ecd94f1bSKan Liang "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads TBD", 9316ecd94f1bSKan Liang "MSRValue": "0x063B800080", 9317ecd94f1bSKan Liang "Counter": "0,1,2,3", 9318ecd94f1bSKan Liang "EventName": "OCR.PF_L3_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", 9319ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 9320ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 9321ecd94f1bSKan Liang "SampleAfterValue": "100003", 9322ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 9323ecd94f1bSKan Liang }, 9324ecd94f1bSKan Liang { 9325ecd94f1bSKan Liang "Offcore": "1", 9326ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 9327ecd94f1bSKan Liang "UMask": "0x1", 9328ecd94f1bSKan Liang "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads TBD", 9329ecd94f1bSKan Liang "MSRValue": "0x0604000080", 9330ecd94f1bSKan Liang "Counter": "0,1,2,3", 9331ecd94f1bSKan Liang "EventName": "OCR.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", 9332ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 9333ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 9334ecd94f1bSKan Liang "SampleAfterValue": "100003", 9335ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 9336ecd94f1bSKan Liang }, 9337ecd94f1bSKan Liang { 9338ecd94f1bSKan Liang "Offcore": "1", 9339ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 9340ecd94f1bSKan Liang "UMask": "0x1", 9341ecd94f1bSKan Liang "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs TBD", 9342ecd94f1bSKan Liang "MSRValue": "0x063B800100", 9343ecd94f1bSKan Liang "Counter": "0,1,2,3", 9344ecd94f1bSKan Liang "EventName": "OCR.PF_L3_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", 9345ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 9346ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 9347ecd94f1bSKan Liang "SampleAfterValue": "100003", 9348ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 9349ecd94f1bSKan Liang }, 9350ecd94f1bSKan Liang { 9351ecd94f1bSKan Liang "Offcore": "1", 9352ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 9353ecd94f1bSKan Liang "UMask": "0x1", 9354ecd94f1bSKan Liang "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs TBD", 9355ecd94f1bSKan Liang "MSRValue": "0x0604000100", 9356ecd94f1bSKan Liang "Counter": "0,1,2,3", 9357ecd94f1bSKan Liang "EventName": "OCR.PF_L3_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", 9358ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 9359ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 9360ecd94f1bSKan Liang "SampleAfterValue": "100003", 9361ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 9362ecd94f1bSKan Liang }, 9363ecd94f1bSKan Liang { 9364ecd94f1bSKan Liang "Offcore": "1", 9365ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 9366ecd94f1bSKan Liang "UMask": "0x1", 9367ecd94f1bSKan Liang "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests TBD", 9368ecd94f1bSKan Liang "MSRValue": "0x063B800400", 9369ecd94f1bSKan Liang "Counter": "0,1,2,3", 9370ecd94f1bSKan Liang "EventName": "OCR.PF_L1D_AND_SW.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", 9371ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 9372ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 9373ecd94f1bSKan Liang "SampleAfterValue": "100003", 9374ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 9375ecd94f1bSKan Liang }, 9376ecd94f1bSKan Liang { 9377ecd94f1bSKan Liang "Offcore": "1", 9378ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 9379ecd94f1bSKan Liang "UMask": "0x1", 9380ecd94f1bSKan Liang "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests TBD", 9381ecd94f1bSKan Liang "MSRValue": "0x0604000400", 9382ecd94f1bSKan Liang "Counter": "0,1,2,3", 9383ecd94f1bSKan Liang "EventName": "OCR.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", 9384ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 9385ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 9386ecd94f1bSKan Liang "SampleAfterValue": "100003", 9387ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 9388ecd94f1bSKan Liang }, 9389ecd94f1bSKan Liang { 9390ecd94f1bSKan Liang "Offcore": "1", 9391ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 9392ecd94f1bSKan Liang "UMask": "0x1", 9393ecd94f1bSKan Liang "BriefDescription": "Counts any other requests TBD", 9394ecd94f1bSKan Liang "MSRValue": "0x063B808000", 9395ecd94f1bSKan Liang "Counter": "0,1,2,3", 9396ecd94f1bSKan Liang "EventName": "OCR.OTHER.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", 9397ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 9398ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 9399ecd94f1bSKan Liang "SampleAfterValue": "100003", 9400ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 9401ecd94f1bSKan Liang }, 9402ecd94f1bSKan Liang { 9403ecd94f1bSKan Liang "Offcore": "1", 9404ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 9405ecd94f1bSKan Liang "UMask": "0x1", 9406ecd94f1bSKan Liang "BriefDescription": "Counts any other requests TBD", 9407ecd94f1bSKan Liang "MSRValue": "0x0604008000", 9408ecd94f1bSKan Liang "Counter": "0,1,2,3", 9409ecd94f1bSKan Liang "EventName": "OCR.OTHER.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", 9410ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 9411ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 9412ecd94f1bSKan Liang "SampleAfterValue": "100003", 9413ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 9414ecd94f1bSKan Liang }, 9415ecd94f1bSKan Liang { 9416ecd94f1bSKan Liang "Offcore": "1", 9417ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 9418ecd94f1bSKan Liang "UMask": "0x1", 9419ecd94f1bSKan Liang "BriefDescription": "TBD TBD", 9420ecd94f1bSKan Liang "MSRValue": "0x063B800490", 9421ecd94f1bSKan Liang "Counter": "0,1,2,3", 9422ecd94f1bSKan Liang "EventName": "OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", 9423ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 9424ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 9425ecd94f1bSKan Liang "SampleAfterValue": "100003", 9426ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 9427ecd94f1bSKan Liang }, 9428ecd94f1bSKan Liang { 9429ecd94f1bSKan Liang "Offcore": "1", 9430ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 9431ecd94f1bSKan Liang "UMask": "0x1", 9432ecd94f1bSKan Liang "BriefDescription": "TBD TBD", 9433ecd94f1bSKan Liang "MSRValue": "0x0604000490", 9434ecd94f1bSKan Liang "Counter": "0,1,2,3", 9435ecd94f1bSKan Liang "EventName": "OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", 9436ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 9437ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 9438ecd94f1bSKan Liang "SampleAfterValue": "100003", 9439ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 9440ecd94f1bSKan Liang }, 9441ecd94f1bSKan Liang { 9442ecd94f1bSKan Liang "Offcore": "1", 9443ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 9444ecd94f1bSKan Liang "UMask": "0x1", 9445ecd94f1bSKan Liang "BriefDescription": "TBD TBD", 9446ecd94f1bSKan Liang "MSRValue": "0x063B800120", 9447ecd94f1bSKan Liang "Counter": "0,1,2,3", 9448ecd94f1bSKan Liang "EventName": "OCR.ALL_PF_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", 9449ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 9450ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 9451ecd94f1bSKan Liang "SampleAfterValue": "100003", 9452ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 9453ecd94f1bSKan Liang }, 9454ecd94f1bSKan Liang { 9455ecd94f1bSKan Liang "Offcore": "1", 9456ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 9457ecd94f1bSKan Liang "UMask": "0x1", 9458ecd94f1bSKan Liang "BriefDescription": "TBD TBD", 9459ecd94f1bSKan Liang "MSRValue": "0x0604000120", 9460ecd94f1bSKan Liang "Counter": "0,1,2,3", 9461ecd94f1bSKan Liang "EventName": "OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", 9462ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 9463ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 9464ecd94f1bSKan Liang "SampleAfterValue": "100003", 9465ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 9466ecd94f1bSKan Liang }, 9467ecd94f1bSKan Liang { 9468ecd94f1bSKan Liang "Offcore": "1", 9469ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 9470ecd94f1bSKan Liang "UMask": "0x1", 9471ecd94f1bSKan Liang "BriefDescription": "TBD TBD", 9472ecd94f1bSKan Liang "MSRValue": "0x063B800491", 9473ecd94f1bSKan Liang "Counter": "0,1,2,3", 9474ecd94f1bSKan Liang "EventName": "OCR.ALL_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", 9475ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 9476ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 9477ecd94f1bSKan Liang "SampleAfterValue": "100003", 9478ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 9479ecd94f1bSKan Liang }, 9480ecd94f1bSKan Liang { 9481ecd94f1bSKan Liang "Offcore": "1", 9482ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 9483ecd94f1bSKan Liang "UMask": "0x1", 9484ecd94f1bSKan Liang "BriefDescription": "TBD TBD", 9485ecd94f1bSKan Liang "MSRValue": "0x0604000491", 9486ecd94f1bSKan Liang "Counter": "0,1,2,3", 9487ecd94f1bSKan Liang "EventName": "OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", 9488ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 9489ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 9490ecd94f1bSKan Liang "SampleAfterValue": "100003", 9491ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 9492ecd94f1bSKan Liang }, 9493ecd94f1bSKan Liang { 9494ecd94f1bSKan Liang "Offcore": "1", 9495ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 9496ecd94f1bSKan Liang "UMask": "0x1", 9497ecd94f1bSKan Liang "BriefDescription": "TBD TBD", 9498ecd94f1bSKan Liang "MSRValue": "0x063B800122", 9499ecd94f1bSKan Liang "Counter": "0,1,2,3", 9500ecd94f1bSKan Liang "EventName": "OCR.ALL_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", 9501ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 9502ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 9503ecd94f1bSKan Liang "SampleAfterValue": "100003", 9504ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 9505ecd94f1bSKan Liang }, 9506ecd94f1bSKan Liang { 9507ecd94f1bSKan Liang "Offcore": "1", 9508ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 9509ecd94f1bSKan Liang "UMask": "0x1", 9510ecd94f1bSKan Liang "BriefDescription": "TBD TBD", 9511ecd94f1bSKan Liang "MSRValue": "0x0604000122", 9512ecd94f1bSKan Liang "Counter": "0,1,2,3", 9513ecd94f1bSKan Liang "EventName": "OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", 9514ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 9515ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 9516ecd94f1bSKan Liang "SampleAfterValue": "100003", 9517ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 9518ecd94f1bSKan Liang }, 9519ecd94f1bSKan Liang { 9520ecd94f1bSKan Liang "Offcore": "1", 9521ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 9522ecd94f1bSKan Liang "UMask": "0x1", 9523ecd94f1bSKan Liang "BriefDescription": "TBD TBD", 9524ecd94f1bSKan Liang "MSRValue": "0x063B8007F7", 9525ecd94f1bSKan Liang "Counter": "0,1,2,3", 9526ecd94f1bSKan Liang "EventName": "OCR.ALL_READS.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", 9527ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 9528ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 9529ecd94f1bSKan Liang "SampleAfterValue": "100003", 9530ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 9531ecd94f1bSKan Liang }, 9532ecd94f1bSKan Liang { 9533ecd94f1bSKan Liang "Offcore": "1", 9534ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 9535ecd94f1bSKan Liang "UMask": "0x1", 9536ecd94f1bSKan Liang "BriefDescription": "TBD TBD", 9537ecd94f1bSKan Liang "MSRValue": "0x06040007F7", 9538ecd94f1bSKan Liang "Counter": "0,1,2,3", 9539ecd94f1bSKan Liang "EventName": "OCR.ALL_READS.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", 9540ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 9541ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 9542ecd94f1bSKan Liang "SampleAfterValue": "100003", 9543ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 9544ecd94f1bSKan Liang }, 9545ecd94f1bSKan Liang { 9546ecd94f1bSKan Liang "Offcore": "1", 9547ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 9548ecd94f1bSKan Liang "UMask": "0x1", 9549ecd94f1bSKan Liang "BriefDescription": "Counts demand data reads TBD", 9550ecd94f1bSKan Liang "MSRValue": "0x103FC00001", 9551ecd94f1bSKan Liang "Counter": "0,1,2,3", 9552ecd94f1bSKan Liang "EventName": "OCR.DEMAND_DATA_RD.L3_MISS.REMOTE_HITM", 9553ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 9554ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 9555ecd94f1bSKan Liang "SampleAfterValue": "100003", 9556ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 9557ecd94f1bSKan Liang }, 9558ecd94f1bSKan Liang { 9559ecd94f1bSKan Liang "Offcore": "1", 9560ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 9561ecd94f1bSKan Liang "UMask": "0x1", 9562ecd94f1bSKan Liang "BriefDescription": "Counts all demand data writes (RFOs) TBD", 9563ecd94f1bSKan Liang "MSRValue": "0x103FC00002", 9564ecd94f1bSKan Liang "Counter": "0,1,2,3", 9565ecd94f1bSKan Liang "EventName": "OCR.DEMAND_RFO.L3_MISS.REMOTE_HITM", 9566ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 9567ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 9568ecd94f1bSKan Liang "SampleAfterValue": "100003", 9569ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 9570ecd94f1bSKan Liang }, 9571ecd94f1bSKan Liang { 9572ecd94f1bSKan Liang "Offcore": "1", 9573ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 9574ecd94f1bSKan Liang "UMask": "0x1", 9575ecd94f1bSKan Liang "BriefDescription": "Counts all demand code reads TBD", 9576ecd94f1bSKan Liang "MSRValue": "0x103FC00004", 9577ecd94f1bSKan Liang "Counter": "0,1,2,3", 9578ecd94f1bSKan Liang "EventName": "OCR.DEMAND_CODE_RD.L3_MISS.REMOTE_HITM", 9579ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 9580ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 9581ecd94f1bSKan Liang "SampleAfterValue": "100003", 9582ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 9583ecd94f1bSKan Liang }, 9584ecd94f1bSKan Liang { 9585ecd94f1bSKan Liang "Offcore": "1", 9586ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 9587ecd94f1bSKan Liang "UMask": "0x1", 9588ecd94f1bSKan Liang "BriefDescription": "Counts prefetch (that bring data to L2) data reads TBD", 9589ecd94f1bSKan Liang "MSRValue": "0x103FC00010", 9590ecd94f1bSKan Liang "Counter": "0,1,2,3", 9591ecd94f1bSKan Liang "EventName": "OCR.PF_L2_DATA_RD.L3_MISS.REMOTE_HITM", 9592ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 9593ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 9594ecd94f1bSKan Liang "SampleAfterValue": "100003", 9595ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 9596ecd94f1bSKan Liang }, 9597ecd94f1bSKan Liang { 9598ecd94f1bSKan Liang "Offcore": "1", 9599ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 9600ecd94f1bSKan Liang "UMask": "0x1", 9601ecd94f1bSKan Liang "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs TBD", 9602ecd94f1bSKan Liang "MSRValue": "0x103FC00020", 9603ecd94f1bSKan Liang "Counter": "0,1,2,3", 9604ecd94f1bSKan Liang "EventName": "OCR.PF_L2_RFO.L3_MISS.REMOTE_HITM", 9605ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 9606ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 9607ecd94f1bSKan Liang "SampleAfterValue": "100003", 9608ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 9609ecd94f1bSKan Liang }, 9610ecd94f1bSKan Liang { 9611ecd94f1bSKan Liang "Offcore": "1", 9612ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 9613ecd94f1bSKan Liang "UMask": "0x1", 9614ecd94f1bSKan Liang "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads TBD", 9615ecd94f1bSKan Liang "MSRValue": "0x103FC00080", 9616ecd94f1bSKan Liang "Counter": "0,1,2,3", 9617ecd94f1bSKan Liang "EventName": "OCR.PF_L3_DATA_RD.L3_MISS.REMOTE_HITM", 9618ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 9619ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 9620ecd94f1bSKan Liang "SampleAfterValue": "100003", 9621ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 9622ecd94f1bSKan Liang }, 9623ecd94f1bSKan Liang { 9624ecd94f1bSKan Liang "Offcore": "1", 9625ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 9626ecd94f1bSKan Liang "UMask": "0x1", 9627ecd94f1bSKan Liang "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs TBD", 9628ecd94f1bSKan Liang "MSRValue": "0x103FC00100", 9629ecd94f1bSKan Liang "Counter": "0,1,2,3", 9630ecd94f1bSKan Liang "EventName": "OCR.PF_L3_RFO.L3_MISS.REMOTE_HITM", 9631ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 9632ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 9633ecd94f1bSKan Liang "SampleAfterValue": "100003", 9634ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 9635ecd94f1bSKan Liang }, 9636ecd94f1bSKan Liang { 9637ecd94f1bSKan Liang "Offcore": "1", 9638ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 9639ecd94f1bSKan Liang "UMask": "0x1", 9640ecd94f1bSKan Liang "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests TBD", 9641ecd94f1bSKan Liang "MSRValue": "0x103FC00400", 9642ecd94f1bSKan Liang "Counter": "0,1,2,3", 9643ecd94f1bSKan Liang "EventName": "OCR.PF_L1D_AND_SW.L3_MISS.REMOTE_HITM", 9644ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 9645ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 9646ecd94f1bSKan Liang "SampleAfterValue": "100003", 9647ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 9648ecd94f1bSKan Liang }, 9649ecd94f1bSKan Liang { 9650ecd94f1bSKan Liang "Offcore": "1", 9651ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 9652ecd94f1bSKan Liang "UMask": "0x1", 9653ecd94f1bSKan Liang "BriefDescription": "Counts any other requests TBD", 9654ecd94f1bSKan Liang "MSRValue": "0x103FC08000", 9655ecd94f1bSKan Liang "Counter": "0,1,2,3", 9656ecd94f1bSKan Liang "EventName": "OCR.OTHER.L3_MISS.REMOTE_HITM", 9657ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 9658ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 9659ecd94f1bSKan Liang "SampleAfterValue": "100003", 9660ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 9661ecd94f1bSKan Liang }, 9662ecd94f1bSKan Liang { 9663ecd94f1bSKan Liang "Offcore": "1", 9664ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 9665ecd94f1bSKan Liang "UMask": "0x1", 9666ecd94f1bSKan Liang "BriefDescription": "TBD TBD", 9667ecd94f1bSKan Liang "MSRValue": "0x103FC00490", 9668ecd94f1bSKan Liang "Counter": "0,1,2,3", 9669ecd94f1bSKan Liang "EventName": "OCR.ALL_PF_DATA_RD.L3_MISS.REMOTE_HITM", 9670ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 9671ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 9672ecd94f1bSKan Liang "SampleAfterValue": "100003", 9673ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 9674ecd94f1bSKan Liang }, 9675ecd94f1bSKan Liang { 9676ecd94f1bSKan Liang "Offcore": "1", 9677ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 9678ecd94f1bSKan Liang "UMask": "0x1", 9679ecd94f1bSKan Liang "BriefDescription": "TBD TBD", 9680ecd94f1bSKan Liang "MSRValue": "0x103FC00120", 9681ecd94f1bSKan Liang "Counter": "0,1,2,3", 9682ecd94f1bSKan Liang "EventName": "OCR.ALL_PF_RFO.L3_MISS.REMOTE_HITM", 9683ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 9684ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 9685ecd94f1bSKan Liang "SampleAfterValue": "100003", 9686ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 9687ecd94f1bSKan Liang }, 9688ecd94f1bSKan Liang { 9689ecd94f1bSKan Liang "Offcore": "1", 9690ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 9691ecd94f1bSKan Liang "UMask": "0x1", 9692ecd94f1bSKan Liang "BriefDescription": "TBD TBD", 9693ecd94f1bSKan Liang "MSRValue": "0x103FC00491", 9694ecd94f1bSKan Liang "Counter": "0,1,2,3", 9695ecd94f1bSKan Liang "EventName": "OCR.ALL_DATA_RD.L3_MISS.REMOTE_HITM", 9696ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 9697ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 9698ecd94f1bSKan Liang "SampleAfterValue": "100003", 9699ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 9700ecd94f1bSKan Liang }, 9701ecd94f1bSKan Liang { 9702ecd94f1bSKan Liang "Offcore": "1", 9703ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 9704ecd94f1bSKan Liang "UMask": "0x1", 9705ecd94f1bSKan Liang "BriefDescription": "TBD TBD", 9706ecd94f1bSKan Liang "MSRValue": "0x103FC00122", 9707ecd94f1bSKan Liang "Counter": "0,1,2,3", 9708ecd94f1bSKan Liang "EventName": "OCR.ALL_RFO.L3_MISS.REMOTE_HITM", 9709ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 9710ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 9711ecd94f1bSKan Liang "SampleAfterValue": "100003", 9712ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 9713ecd94f1bSKan Liang }, 9714ecd94f1bSKan Liang { 9715ecd94f1bSKan Liang "Offcore": "1", 9716ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 9717ecd94f1bSKan Liang "UMask": "0x1", 9718ecd94f1bSKan Liang "BriefDescription": "TBD TBD", 9719ecd94f1bSKan Liang "MSRValue": "0x103FC007F7", 9720ecd94f1bSKan Liang "Counter": "0,1,2,3", 9721ecd94f1bSKan Liang "EventName": "OCR.ALL_READS.L3_MISS.REMOTE_HITM", 9722ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 9723ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 9724ecd94f1bSKan Liang "SampleAfterValue": "100003", 9725ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 9726ecd94f1bSKan Liang }, 9727ecd94f1bSKan Liang { 9728ecd94f1bSKan Liang "Offcore": "1", 9729ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 9730ecd94f1bSKan Liang "UMask": "0x1", 9731ecd94f1bSKan Liang "BriefDescription": "Counts demand data reads TBD", 9732ecd94f1bSKan Liang "MSRValue": "0x083FC00001", 9733ecd94f1bSKan Liang "Counter": "0,1,2,3", 9734ecd94f1bSKan Liang "EventName": "OCR.DEMAND_DATA_RD.L3_MISS.REMOTE_HIT_FORWARD", 9735ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 9736ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 9737ecd94f1bSKan Liang "SampleAfterValue": "100003", 9738ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 9739ecd94f1bSKan Liang }, 9740ecd94f1bSKan Liang { 9741ecd94f1bSKan Liang "Offcore": "1", 9742ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 9743ecd94f1bSKan Liang "UMask": "0x1", 9744ecd94f1bSKan Liang "BriefDescription": "Counts all demand data writes (RFOs) TBD", 9745ecd94f1bSKan Liang "MSRValue": "0x083FC00002", 9746ecd94f1bSKan Liang "Counter": "0,1,2,3", 9747ecd94f1bSKan Liang "EventName": "OCR.DEMAND_RFO.L3_MISS.REMOTE_HIT_FORWARD", 9748ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 9749ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 9750ecd94f1bSKan Liang "SampleAfterValue": "100003", 9751ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 9752ecd94f1bSKan Liang }, 9753ecd94f1bSKan Liang { 9754ecd94f1bSKan Liang "Offcore": "1", 9755ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 9756ecd94f1bSKan Liang "UMask": "0x1", 9757ecd94f1bSKan Liang "BriefDescription": "Counts all demand code reads TBD", 9758ecd94f1bSKan Liang "MSRValue": "0x083FC00004", 9759ecd94f1bSKan Liang "Counter": "0,1,2,3", 9760ecd94f1bSKan Liang "EventName": "OCR.DEMAND_CODE_RD.L3_MISS.REMOTE_HIT_FORWARD", 9761ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 9762ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 9763ecd94f1bSKan Liang "SampleAfterValue": "100003", 9764ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 9765ecd94f1bSKan Liang }, 9766ecd94f1bSKan Liang { 9767ecd94f1bSKan Liang "Offcore": "1", 9768ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 9769ecd94f1bSKan Liang "UMask": "0x1", 9770ecd94f1bSKan Liang "BriefDescription": "Counts prefetch (that bring data to L2) data reads TBD", 9771ecd94f1bSKan Liang "MSRValue": "0x083FC00010", 9772ecd94f1bSKan Liang "Counter": "0,1,2,3", 9773ecd94f1bSKan Liang "EventName": "OCR.PF_L2_DATA_RD.L3_MISS.REMOTE_HIT_FORWARD", 9774ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 9775ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 9776ecd94f1bSKan Liang "SampleAfterValue": "100003", 9777ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 9778ecd94f1bSKan Liang }, 9779ecd94f1bSKan Liang { 9780ecd94f1bSKan Liang "Offcore": "1", 9781ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 9782ecd94f1bSKan Liang "UMask": "0x1", 9783ecd94f1bSKan Liang "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs TBD", 9784ecd94f1bSKan Liang "MSRValue": "0x083FC00020", 9785ecd94f1bSKan Liang "Counter": "0,1,2,3", 9786ecd94f1bSKan Liang "EventName": "OCR.PF_L2_RFO.L3_MISS.REMOTE_HIT_FORWARD", 9787ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 9788ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 9789ecd94f1bSKan Liang "SampleAfterValue": "100003", 9790ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 9791ecd94f1bSKan Liang }, 9792ecd94f1bSKan Liang { 9793ecd94f1bSKan Liang "Offcore": "1", 9794ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 9795ecd94f1bSKan Liang "UMask": "0x1", 9796ecd94f1bSKan Liang "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads TBD", 9797ecd94f1bSKan Liang "MSRValue": "0x083FC00080", 9798ecd94f1bSKan Liang "Counter": "0,1,2,3", 9799ecd94f1bSKan Liang "EventName": "OCR.PF_L3_DATA_RD.L3_MISS.REMOTE_HIT_FORWARD", 9800ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 9801ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 9802ecd94f1bSKan Liang "SampleAfterValue": "100003", 9803ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 9804ecd94f1bSKan Liang }, 9805ecd94f1bSKan Liang { 9806ecd94f1bSKan Liang "Offcore": "1", 9807ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 9808ecd94f1bSKan Liang "UMask": "0x1", 9809ecd94f1bSKan Liang "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs TBD", 9810ecd94f1bSKan Liang "MSRValue": "0x083FC00100", 9811ecd94f1bSKan Liang "Counter": "0,1,2,3", 9812ecd94f1bSKan Liang "EventName": "OCR.PF_L3_RFO.L3_MISS.REMOTE_HIT_FORWARD", 9813ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 9814ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 9815ecd94f1bSKan Liang "SampleAfterValue": "100003", 9816ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 9817ecd94f1bSKan Liang }, 9818ecd94f1bSKan Liang { 9819ecd94f1bSKan Liang "Offcore": "1", 9820ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 9821ecd94f1bSKan Liang "UMask": "0x1", 9822ecd94f1bSKan Liang "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests TBD", 9823ecd94f1bSKan Liang "MSRValue": "0x083FC00400", 9824ecd94f1bSKan Liang "Counter": "0,1,2,3", 9825ecd94f1bSKan Liang "EventName": "OCR.PF_L1D_AND_SW.L3_MISS.REMOTE_HIT_FORWARD", 9826ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 9827ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 9828ecd94f1bSKan Liang "SampleAfterValue": "100003", 9829ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 9830ecd94f1bSKan Liang }, 9831ecd94f1bSKan Liang { 9832ecd94f1bSKan Liang "Offcore": "1", 9833ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 9834ecd94f1bSKan Liang "UMask": "0x1", 9835ecd94f1bSKan Liang "BriefDescription": "Counts any other requests TBD", 9836ecd94f1bSKan Liang "MSRValue": "0x083FC08000", 9837ecd94f1bSKan Liang "Counter": "0,1,2,3", 9838ecd94f1bSKan Liang "EventName": "OCR.OTHER.L3_MISS.REMOTE_HIT_FORWARD", 9839ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 9840ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 9841ecd94f1bSKan Liang "SampleAfterValue": "100003", 9842ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 9843ecd94f1bSKan Liang }, 9844ecd94f1bSKan Liang { 9845ecd94f1bSKan Liang "Offcore": "1", 9846ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 9847ecd94f1bSKan Liang "UMask": "0x1", 9848ecd94f1bSKan Liang "BriefDescription": "TBD TBD", 9849ecd94f1bSKan Liang "MSRValue": "0x083FC00490", 9850ecd94f1bSKan Liang "Counter": "0,1,2,3", 9851ecd94f1bSKan Liang "EventName": "OCR.ALL_PF_DATA_RD.L3_MISS.REMOTE_HIT_FORWARD", 9852ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 9853ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 9854ecd94f1bSKan Liang "SampleAfterValue": "100003", 9855ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 9856ecd94f1bSKan Liang }, 9857ecd94f1bSKan Liang { 9858ecd94f1bSKan Liang "Offcore": "1", 9859ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 9860ecd94f1bSKan Liang "UMask": "0x1", 9861ecd94f1bSKan Liang "BriefDescription": "TBD TBD", 9862ecd94f1bSKan Liang "MSRValue": "0x083FC00120", 9863ecd94f1bSKan Liang "Counter": "0,1,2,3", 9864ecd94f1bSKan Liang "EventName": "OCR.ALL_PF_RFO.L3_MISS.REMOTE_HIT_FORWARD", 9865ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 9866ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 9867ecd94f1bSKan Liang "SampleAfterValue": "100003", 9868ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 9869ecd94f1bSKan Liang }, 9870ecd94f1bSKan Liang { 9871ecd94f1bSKan Liang "Offcore": "1", 9872ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 9873ecd94f1bSKan Liang "UMask": "0x1", 9874ecd94f1bSKan Liang "BriefDescription": "TBD TBD", 9875ecd94f1bSKan Liang "MSRValue": "0x083FC00491", 9876ecd94f1bSKan Liang "Counter": "0,1,2,3", 9877ecd94f1bSKan Liang "EventName": "OCR.ALL_DATA_RD.L3_MISS.REMOTE_HIT_FORWARD", 9878ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 9879ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 9880ecd94f1bSKan Liang "SampleAfterValue": "100003", 9881ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 9882ecd94f1bSKan Liang }, 9883ecd94f1bSKan Liang { 9884ecd94f1bSKan Liang "Offcore": "1", 9885ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 9886ecd94f1bSKan Liang "UMask": "0x1", 9887ecd94f1bSKan Liang "BriefDescription": "TBD TBD", 9888ecd94f1bSKan Liang "MSRValue": "0x083FC00122", 9889ecd94f1bSKan Liang "Counter": "0,1,2,3", 9890ecd94f1bSKan Liang "EventName": "OCR.ALL_RFO.L3_MISS.REMOTE_HIT_FORWARD", 9891ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 9892ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 9893ecd94f1bSKan Liang "SampleAfterValue": "100003", 9894ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 9895ecd94f1bSKan Liang }, 9896ecd94f1bSKan Liang { 9897ecd94f1bSKan Liang "Offcore": "1", 9898ecd94f1bSKan Liang "EventCode": "0xB7, 0xBB", 9899ecd94f1bSKan Liang "UMask": "0x1", 9900ecd94f1bSKan Liang "BriefDescription": "TBD TBD", 9901ecd94f1bSKan Liang "MSRValue": "0x083FC007F7", 9902ecd94f1bSKan Liang "Counter": "0,1,2,3", 9903ecd94f1bSKan Liang "EventName": "OCR.ALL_READS.L3_MISS.REMOTE_HIT_FORWARD", 9904ecd94f1bSKan Liang "MSRIndex": "0x1a6,0x1a7", 9905ecd94f1bSKan Liang "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 9906ecd94f1bSKan Liang "SampleAfterValue": "100003", 9907ecd94f1bSKan Liang "CounterHTOff": "0,1,2,3" 9908ecd94f1bSKan Liang } 9909ecd94f1bSKan Liang]