1[ 2 { 3 "BriefDescription": "DRAM Activate Count; Activate due to Read", 4 "Counter": "0,1,2,3", 5 "EventCode": "0x1", 6 "EventName": "UNC_M_ACT_COUNT.RD", 7 "PerPkg": "1", 8 "UMask": "0x1", 9 "Unit": "iMC" 10 }, 11 { 12 "BriefDescription": "DRAM Activate Count; Activate due to Write", 13 "Counter": "0,1,2,3", 14 "EventCode": "0x1", 15 "EventName": "UNC_M_ACT_COUNT.WR", 16 "PerPkg": "1", 17 "UMask": "0x2", 18 "Unit": "iMC" 19 }, 20 { 21 "BriefDescription": "DRAM Activate Count; Activate due to Write", 22 "Counter": "0,1,2,3", 23 "EventCode": "0x1", 24 "EventName": "UNC_M_ACT_COUNT.BYP", 25 "PerPkg": "1", 26 "UMask": "0x8", 27 "Unit": "iMC" 28 }, 29 { 30 "BriefDescription": "ACT command issued by 2 cycle bypass", 31 "Counter": "0,1,2,3", 32 "EventCode": "0xA1", 33 "EventName": "UNC_M_BYP_CMDS.ACT", 34 "PerPkg": "1", 35 "UMask": "0x1", 36 "Unit": "iMC" 37 }, 38 { 39 "BriefDescription": "CAS command issued by 2 cycle bypass", 40 "Counter": "0,1,2,3", 41 "EventCode": "0xA1", 42 "EventName": "UNC_M_BYP_CMDS.CAS", 43 "PerPkg": "1", 44 "UMask": "0x2", 45 "Unit": "iMC" 46 }, 47 { 48 "BriefDescription": "PRE command issued by 2 cycle bypass", 49 "Counter": "0,1,2,3", 50 "EventCode": "0xA1", 51 "EventName": "UNC_M_BYP_CMDS.PRE", 52 "PerPkg": "1", 53 "UMask": "0x4", 54 "Unit": "iMC" 55 }, 56 { 57 "BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; All DRAM RD_CAS (w/ and w/out auto-pre)", 58 "Counter": "0,1,2,3", 59 "EventCode": "0x4", 60 "EventName": "UNC_M_CAS_COUNT.RD_REG", 61 "PerPkg": "1", 62 "UMask": "0x1", 63 "Unit": "iMC" 64 }, 65 { 66 "BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; Underfill Read Issued", 67 "Counter": "0,1,2,3", 68 "EventCode": "0x4", 69 "EventName": "UNC_M_CAS_COUNT.RD_UNDERFILL", 70 "PerPkg": "1", 71 "UMask": "0x2", 72 "Unit": "iMC" 73 }, 74 { 75 "BriefDescription": "read requests to memory controller. Derived from unc_m_cas_count.rd", 76 "Counter": "0,1,2,3", 77 "EventCode": "0x4", 78 "EventName": "LLC_MISSES.MEM_READ", 79 "PerPkg": "1", 80 "ScaleUnit": "64Bytes", 81 "UMask": "0x3", 82 "Unit": "iMC" 83 }, 84 { 85 "BriefDescription": "read requests to memory controller", 86 "Counter": "0,1,2,3", 87 "EventCode": "0x4", 88 "EventName": "UNC_M_CAS_COUNT.RD", 89 "PerPkg": "1", 90 "ScaleUnit": "64Bytes", 91 "UMask": "0x3", 92 "Unit": "iMC" 93 }, 94 { 95 "BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; DRAM WR_CAS (w/ and w/out auto-pre) in Write Major Mode", 96 "Counter": "0,1,2,3", 97 "EventCode": "0x4", 98 "EventName": "UNC_M_CAS_COUNT.WR_WMM", 99 "PerPkg": "1", 100 "UMask": "0x4", 101 "Unit": "iMC" 102 }, 103 { 104 "BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; DRAM WR_CAS (w/ and w/out auto-pre) in Read Major Mode", 105 "Counter": "0,1,2,3", 106 "EventCode": "0x4", 107 "EventName": "UNC_M_CAS_COUNT.WR_RMM", 108 "PerPkg": "1", 109 "UMask": "0x8", 110 "Unit": "iMC" 111 }, 112 { 113 "BriefDescription": "write requests to memory controller. Derived from unc_m_cas_count.wr", 114 "Counter": "0,1,2,3", 115 "EventCode": "0x4", 116 "EventName": "LLC_MISSES.MEM_WRITE", 117 "PerPkg": "1", 118 "ScaleUnit": "64Bytes", 119 "UMask": "0xC", 120 "Unit": "iMC" 121 }, 122 { 123 "BriefDescription": "write requests to memory controller", 124 "Counter": "0,1,2,3", 125 "EventCode": "0x4", 126 "EventName": "UNC_M_CAS_COUNT.WR", 127 "PerPkg": "1", 128 "ScaleUnit": "64Bytes", 129 "UMask": "0xC", 130 "Unit": "iMC" 131 }, 132 { 133 "BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; All DRAM WR_CAS (w/ and w/out auto-pre)", 134 "Counter": "0,1,2,3", 135 "EventCode": "0x4", 136 "EventName": "UNC_M_CAS_COUNT.ALL", 137 "PerPkg": "1", 138 "UMask": "0xF", 139 "Unit": "iMC" 140 }, 141 { 142 "BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; Read CAS issued in WMM", 143 "Counter": "0,1,2,3", 144 "EventCode": "0x4", 145 "EventName": "UNC_M_CAS_COUNT.RD_WMM", 146 "PerPkg": "1", 147 "UMask": "0x10", 148 "Unit": "iMC" 149 }, 150 { 151 "BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; Read CAS issued in RMM", 152 "Counter": "0,1,2,3", 153 "EventCode": "0x4", 154 "EventName": "UNC_M_CAS_COUNT.RD_RMM", 155 "PerPkg": "1", 156 "UMask": "0x20", 157 "Unit": "iMC" 158 }, 159 { 160 "BriefDescription": "This event is deprecated. Refer to new event UNC_M_CLOCKTICKS_P", 161 "Counter": "0,1,2,3", 162 "EventName": "UNC_M_DCLOCKTICKS", 163 "PerPkg": "1", 164 "Unit": "iMC" 165 }, 166 { 167 "BriefDescription": "DRAM Precharge All Commands", 168 "Counter": "0,1,2,3", 169 "EventCode": "0x6", 170 "EventName": "UNC_M_DRAM_PRE_ALL", 171 "PerPkg": "1", 172 "Unit": "iMC" 173 }, 174 { 175 "BriefDescription": "Number of DRAM Refreshes Issued", 176 "Counter": "0,1,2,3", 177 "EventCode": "0x5", 178 "EventName": "UNC_M_DRAM_REFRESH.PANIC", 179 "PerPkg": "1", 180 "UMask": "0x2", 181 "Unit": "iMC" 182 }, 183 { 184 "BriefDescription": "Number of DRAM Refreshes Issued", 185 "Counter": "0,1,2,3", 186 "EventCode": "0x5", 187 "EventName": "UNC_M_DRAM_REFRESH.HIGH", 188 "PerPkg": "1", 189 "UMask": "0x4", 190 "Unit": "iMC" 191 }, 192 { 193 "BriefDescription": "ECC Correctable Errors", 194 "Counter": "0,1,2,3", 195 "EventCode": "0x9", 196 "EventName": "UNC_M_ECC_CORRECTABLE_ERRORS", 197 "PerPkg": "1", 198 "Unit": "iMC" 199 }, 200 { 201 "BriefDescription": "Cycles in a Major Mode; Read Major Mode", 202 "Counter": "0,1,2,3", 203 "EventCode": "0x7", 204 "EventName": "UNC_M_MAJOR_MODES.READ", 205 "PerPkg": "1", 206 "UMask": "0x1", 207 "Unit": "iMC" 208 }, 209 { 210 "BriefDescription": "Cycles in a Major Mode; Write Major Mode", 211 "Counter": "0,1,2,3", 212 "EventCode": "0x7", 213 "EventName": "UNC_M_MAJOR_MODES.WRITE", 214 "PerPkg": "1", 215 "UMask": "0x2", 216 "Unit": "iMC" 217 }, 218 { 219 "BriefDescription": "Cycles in a Major Mode; Partial Major Mode", 220 "Counter": "0,1,2,3", 221 "EventCode": "0x7", 222 "EventName": "UNC_M_MAJOR_MODES.PARTIAL", 223 "PerPkg": "1", 224 "UMask": "0x4", 225 "Unit": "iMC" 226 }, 227 { 228 "BriefDescription": "Cycles in a Major Mode; Isoch Major Mode", 229 "Counter": "0,1,2,3", 230 "EventCode": "0x7", 231 "EventName": "UNC_M_MAJOR_MODES.ISOCH", 232 "PerPkg": "1", 233 "UMask": "0x8", 234 "Unit": "iMC" 235 }, 236 { 237 "BriefDescription": "Channel DLLOFF Cycles", 238 "Counter": "0,1,2,3", 239 "EventCode": "0x84", 240 "EventName": "UNC_M_POWER_CHANNEL_DLLOFF", 241 "PerPkg": "1", 242 "Unit": "iMC" 243 }, 244 { 245 "BriefDescription": "Channel PPD Cycles", 246 "Counter": "0,1,2,3", 247 "EventCode": "0x85", 248 "EventName": "UNC_M_POWER_CHANNEL_PPD", 249 "PerPkg": "1", 250 "Unit": "iMC" 251 }, 252 { 253 "BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID", 254 "Counter": "0,1,2,3", 255 "EventCode": "0x83", 256 "EventName": "UNC_M_POWER_CKE_CYCLES.RANK0", 257 "PerPkg": "1", 258 "UMask": "0x1", 259 "Unit": "iMC" 260 }, 261 { 262 "BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID", 263 "Counter": "0,1,2,3", 264 "EventCode": "0x83", 265 "EventName": "UNC_M_POWER_CKE_CYCLES.RANK1", 266 "PerPkg": "1", 267 "UMask": "0x2", 268 "Unit": "iMC" 269 }, 270 { 271 "BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID", 272 "Counter": "0,1,2,3", 273 "EventCode": "0x83", 274 "EventName": "UNC_M_POWER_CKE_CYCLES.RANK2", 275 "PerPkg": "1", 276 "UMask": "0x4", 277 "Unit": "iMC" 278 }, 279 { 280 "BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID", 281 "Counter": "0,1,2,3", 282 "EventCode": "0x83", 283 "EventName": "UNC_M_POWER_CKE_CYCLES.RANK3", 284 "PerPkg": "1", 285 "UMask": "0x8", 286 "Unit": "iMC" 287 }, 288 { 289 "BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID", 290 "Counter": "0,1,2,3", 291 "EventCode": "0x83", 292 "EventName": "UNC_M_POWER_CKE_CYCLES.RANK4", 293 "PerPkg": "1", 294 "UMask": "0x10", 295 "Unit": "iMC" 296 }, 297 { 298 "BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID", 299 "Counter": "0,1,2,3", 300 "EventCode": "0x83", 301 "EventName": "UNC_M_POWER_CKE_CYCLES.RANK5", 302 "PerPkg": "1", 303 "UMask": "0x20", 304 "Unit": "iMC" 305 }, 306 { 307 "BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID", 308 "Counter": "0,1,2,3", 309 "EventCode": "0x83", 310 "EventName": "UNC_M_POWER_CKE_CYCLES.RANK6", 311 "PerPkg": "1", 312 "UMask": "0x40", 313 "Unit": "iMC" 314 }, 315 { 316 "BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID", 317 "Counter": "0,1,2,3", 318 "EventCode": "0x83", 319 "EventName": "UNC_M_POWER_CKE_CYCLES.RANK7", 320 "PerPkg": "1", 321 "UMask": "0x80", 322 "Unit": "iMC" 323 }, 324 { 325 "BriefDescription": "Critical Throttle Cycles", 326 "Counter": "0,1,2,3", 327 "EventCode": "0x86", 328 "EventName": "UNC_M_POWER_CRITICAL_THROTTLE_CYCLES", 329 "PerPkg": "1", 330 "Unit": "iMC" 331 }, 332 { 333 "BriefDescription": "UNC_M_POWER_PCU_THROTTLING", 334 "Counter": "0,1,2,3", 335 "EventCode": "0x42", 336 "EventName": "UNC_M_POWER_PCU_THROTTLING", 337 "PerPkg": "1", 338 "Unit": "iMC" 339 }, 340 { 341 "BriefDescription": "Clock-Enabled Self-Refresh", 342 "Counter": "0,1,2,3", 343 "EventCode": "0x43", 344 "EventName": "UNC_M_POWER_SELF_REFRESH", 345 "PerPkg": "1", 346 "Unit": "iMC" 347 }, 348 { 349 "BriefDescription": "Throttle Cycles for Rank 0; DIMM ID", 350 "Counter": "0,1,2,3", 351 "EventCode": "0x41", 352 "EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK0", 353 "PerPkg": "1", 354 "UMask": "0x1", 355 "Unit": "iMC" 356 }, 357 { 358 "BriefDescription": "Throttle Cycles for Rank 0; DIMM ID", 359 "Counter": "0,1,2,3", 360 "EventCode": "0x41", 361 "EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK1", 362 "PerPkg": "1", 363 "UMask": "0x2", 364 "Unit": "iMC" 365 }, 366 { 367 "BriefDescription": "Throttle Cycles for Rank 0; DIMM ID", 368 "Counter": "0,1,2,3", 369 "EventCode": "0x41", 370 "EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK2", 371 "PerPkg": "1", 372 "UMask": "0x4", 373 "Unit": "iMC" 374 }, 375 { 376 "BriefDescription": "Throttle Cycles for Rank 0; DIMM ID", 377 "Counter": "0,1,2,3", 378 "EventCode": "0x41", 379 "EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK3", 380 "PerPkg": "1", 381 "UMask": "0x8", 382 "Unit": "iMC" 383 }, 384 { 385 "BriefDescription": "Throttle Cycles for Rank 0; DIMM ID", 386 "Counter": "0,1,2,3", 387 "EventCode": "0x41", 388 "EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK4", 389 "PerPkg": "1", 390 "UMask": "0x10", 391 "Unit": "iMC" 392 }, 393 { 394 "BriefDescription": "Throttle Cycles for Rank 0; DIMM ID", 395 "Counter": "0,1,2,3", 396 "EventCode": "0x41", 397 "EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK5", 398 "PerPkg": "1", 399 "UMask": "0x20", 400 "Unit": "iMC" 401 }, 402 { 403 "BriefDescription": "Throttle Cycles for Rank 0; DIMM ID", 404 "Counter": "0,1,2,3", 405 "EventCode": "0x41", 406 "EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK6", 407 "PerPkg": "1", 408 "UMask": "0x40", 409 "Unit": "iMC" 410 }, 411 { 412 "BriefDescription": "Throttle Cycles for Rank 0; DIMM ID", 413 "Counter": "0,1,2,3", 414 "EventCode": "0x41", 415 "EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK7", 416 "PerPkg": "1", 417 "UMask": "0x80", 418 "Unit": "iMC" 419 }, 420 { 421 "BriefDescription": "Read Preemption Count; Read over Read Preemption", 422 "Counter": "0,1,2,3", 423 "EventCode": "0x8", 424 "EventName": "UNC_M_PREEMPTION.RD_PREEMPT_RD", 425 "PerPkg": "1", 426 "UMask": "0x1", 427 "Unit": "iMC" 428 }, 429 { 430 "BriefDescription": "Read Preemption Count; Read over Write Preemption", 431 "Counter": "0,1,2,3", 432 "EventCode": "0x8", 433 "EventName": "UNC_M_PREEMPTION.RD_PREEMPT_WR", 434 "PerPkg": "1", 435 "UMask": "0x2", 436 "Unit": "iMC" 437 }, 438 { 439 "BriefDescription": "DRAM Precharge commands.; Precharges due to page miss", 440 "Counter": "0,1,2,3", 441 "EventCode": "0x2", 442 "EventName": "UNC_M_PRE_COUNT.PAGE_MISS", 443 "PerPkg": "1", 444 "UMask": "0x1", 445 "Unit": "iMC" 446 }, 447 { 448 "BriefDescription": "DRAM Precharge commands.; Precharge due to timer expiration", 449 "Counter": "0,1,2,3", 450 "EventCode": "0x2", 451 "EventName": "UNC_M_PRE_COUNT.PAGE_CLOSE", 452 "PerPkg": "1", 453 "UMask": "0x2", 454 "Unit": "iMC" 455 }, 456 { 457 "BriefDescription": "DRAM Precharge commands.; Precharge due to read", 458 "Counter": "0,1,2,3", 459 "EventCode": "0x2", 460 "EventName": "UNC_M_PRE_COUNT.RD", 461 "PerPkg": "1", 462 "UMask": "0x4", 463 "Unit": "iMC" 464 }, 465 { 466 "BriefDescription": "DRAM Precharge commands.; Precharge due to write", 467 "Counter": "0,1,2,3", 468 "EventCode": "0x2", 469 "EventName": "UNC_M_PRE_COUNT.WR", 470 "PerPkg": "1", 471 "UMask": "0x8", 472 "Unit": "iMC" 473 }, 474 { 475 "BriefDescription": "DRAM Precharge commands.; Precharge due to bypass", 476 "Counter": "0,1,2,3", 477 "EventCode": "0x2", 478 "EventName": "UNC_M_PRE_COUNT.BYP", 479 "PerPkg": "1", 480 "UMask": "0x10", 481 "Unit": "iMC" 482 }, 483 { 484 "BriefDescription": "Read CAS issued with LOW priority", 485 "Counter": "0,1,2,3", 486 "EventCode": "0xA0", 487 "EventName": "UNC_M_RD_CAS_PRIO.LOW", 488 "PerPkg": "1", 489 "UMask": "0x1", 490 "Unit": "iMC" 491 }, 492 { 493 "BriefDescription": "Read CAS issued with MEDIUM priority", 494 "Counter": "0,1,2,3", 495 "EventCode": "0xA0", 496 "EventName": "UNC_M_RD_CAS_PRIO.MED", 497 "PerPkg": "1", 498 "UMask": "0x2", 499 "Unit": "iMC" 500 }, 501 { 502 "BriefDescription": "Read CAS issued with HIGH priority", 503 "Counter": "0,1,2,3", 504 "EventCode": "0xA0", 505 "EventName": "UNC_M_RD_CAS_PRIO.HIGH", 506 "PerPkg": "1", 507 "UMask": "0x4", 508 "Unit": "iMC" 509 }, 510 { 511 "BriefDescription": "Read CAS issued with PANIC NON ISOCH priority (starved)", 512 "Counter": "0,1,2,3", 513 "EventCode": "0xA0", 514 "EventName": "UNC_M_RD_CAS_PRIO.PANIC", 515 "PerPkg": "1", 516 "UMask": "0x8", 517 "Unit": "iMC" 518 }, 519 { 520 "BriefDescription": "RD_CAS Access to Rank 0; Bank 1", 521 "Counter": "0,1,2,3", 522 "EventCode": "0xB0", 523 "EventName": "UNC_M_RD_CAS_RANK0.BANK1", 524 "PerPkg": "1", 525 "UMask": "0x1", 526 "Unit": "iMC" 527 }, 528 { 529 "BriefDescription": "RD_CAS Access to Rank 0; Bank 2", 530 "Counter": "0,1,2,3", 531 "EventCode": "0xB0", 532 "EventName": "UNC_M_RD_CAS_RANK0.BANK2", 533 "PerPkg": "1", 534 "UMask": "0x2", 535 "Unit": "iMC" 536 }, 537 { 538 "BriefDescription": "RD_CAS Access to Rank 0; Bank 4", 539 "Counter": "0,1,2,3", 540 "EventCode": "0xB0", 541 "EventName": "UNC_M_RD_CAS_RANK0.BANK4", 542 "PerPkg": "1", 543 "UMask": "0x4", 544 "Unit": "iMC" 545 }, 546 { 547 "BriefDescription": "RD_CAS Access to Rank 0; Bank 8", 548 "Counter": "0,1,2,3", 549 "EventCode": "0xB0", 550 "EventName": "UNC_M_RD_CAS_RANK0.BANK8", 551 "PerPkg": "1", 552 "UMask": "0x8", 553 "Unit": "iMC" 554 }, 555 { 556 "BriefDescription": "RD_CAS Access to Rank 0; All Banks", 557 "Counter": "0,1,2,3", 558 "EventCode": "0xB0", 559 "EventName": "UNC_M_RD_CAS_RANK0.ALLBANKS", 560 "PerPkg": "1", 561 "UMask": "0x10", 562 "Unit": "iMC" 563 }, 564 { 565 "BriefDescription": "RD_CAS Access to Rank 0; Bank 0", 566 "Counter": "0,1,2,3", 567 "EventCode": "0xB0", 568 "EventName": "UNC_M_RD_CAS_RANK0.BANK0", 569 "PerPkg": "1", 570 "Unit": "iMC" 571 }, 572 { 573 "BriefDescription": "RD_CAS Access to Rank 0; Bank 3", 574 "Counter": "0,1,2,3", 575 "EventCode": "0xB0", 576 "EventName": "UNC_M_RD_CAS_RANK0.BANK3", 577 "PerPkg": "1", 578 "UMask": "0x3", 579 "Unit": "iMC" 580 }, 581 { 582 "BriefDescription": "RD_CAS Access to Rank 0; Bank 5", 583 "Counter": "0,1,2,3", 584 "EventCode": "0xB0", 585 "EventName": "UNC_M_RD_CAS_RANK0.BANK5", 586 "PerPkg": "1", 587 "UMask": "0x5", 588 "Unit": "iMC" 589 }, 590 { 591 "BriefDescription": "RD_CAS Access to Rank 0; Bank 6", 592 "Counter": "0,1,2,3", 593 "EventCode": "0xB0", 594 "EventName": "UNC_M_RD_CAS_RANK0.BANK6", 595 "PerPkg": "1", 596 "UMask": "0x6", 597 "Unit": "iMC" 598 }, 599 { 600 "BriefDescription": "RD_CAS Access to Rank 0; Bank 7", 601 "Counter": "0,1,2,3", 602 "EventCode": "0xB0", 603 "EventName": "UNC_M_RD_CAS_RANK0.BANK7", 604 "PerPkg": "1", 605 "UMask": "0x7", 606 "Unit": "iMC" 607 }, 608 { 609 "BriefDescription": "RD_CAS Access to Rank 0; Bank 9", 610 "Counter": "0,1,2,3", 611 "EventCode": "0xB0", 612 "EventName": "UNC_M_RD_CAS_RANK0.BANK9", 613 "PerPkg": "1", 614 "UMask": "0x9", 615 "Unit": "iMC" 616 }, 617 { 618 "BriefDescription": "RD_CAS Access to Rank 0; Bank 10", 619 "Counter": "0,1,2,3", 620 "EventCode": "0xB0", 621 "EventName": "UNC_M_RD_CAS_RANK0.BANK10", 622 "PerPkg": "1", 623 "UMask": "0xA", 624 "Unit": "iMC" 625 }, 626 { 627 "BriefDescription": "RD_CAS Access to Rank 0; Bank 11", 628 "Counter": "0,1,2,3", 629 "EventCode": "0xB0", 630 "EventName": "UNC_M_RD_CAS_RANK0.BANK11", 631 "PerPkg": "1", 632 "UMask": "0xB", 633 "Unit": "iMC" 634 }, 635 { 636 "BriefDescription": "RD_CAS Access to Rank 0; Bank 12", 637 "Counter": "0,1,2,3", 638 "EventCode": "0xB0", 639 "EventName": "UNC_M_RD_CAS_RANK0.BANK12", 640 "PerPkg": "1", 641 "UMask": "0xC", 642 "Unit": "iMC" 643 }, 644 { 645 "BriefDescription": "RD_CAS Access to Rank 0; Bank 13", 646 "Counter": "0,1,2,3", 647 "EventCode": "0xB0", 648 "EventName": "UNC_M_RD_CAS_RANK0.BANK13", 649 "PerPkg": "1", 650 "UMask": "0xD", 651 "Unit": "iMC" 652 }, 653 { 654 "BriefDescription": "RD_CAS Access to Rank 0; Bank 14", 655 "Counter": "0,1,2,3", 656 "EventCode": "0xB0", 657 "EventName": "UNC_M_RD_CAS_RANK0.BANK14", 658 "PerPkg": "1", 659 "UMask": "0xE", 660 "Unit": "iMC" 661 }, 662 { 663 "BriefDescription": "RD_CAS Access to Rank 0; Bank 15", 664 "Counter": "0,1,2,3", 665 "EventCode": "0xB0", 666 "EventName": "UNC_M_RD_CAS_RANK0.BANK15", 667 "PerPkg": "1", 668 "UMask": "0xF", 669 "Unit": "iMC" 670 }, 671 { 672 "BriefDescription": "RD_CAS Access to Rank 0; Bank Group 0 (Banks 0-3)", 673 "Counter": "0,1,2,3", 674 "EventCode": "0xB0", 675 "EventName": "UNC_M_RD_CAS_RANK0.BANKG0", 676 "PerPkg": "1", 677 "UMask": "0x11", 678 "Unit": "iMC" 679 }, 680 { 681 "BriefDescription": "RD_CAS Access to Rank 0; Bank Group 1 (Banks 4-7)", 682 "Counter": "0,1,2,3", 683 "EventCode": "0xB0", 684 "EventName": "UNC_M_RD_CAS_RANK0.BANKG1", 685 "PerPkg": "1", 686 "UMask": "0x12", 687 "Unit": "iMC" 688 }, 689 { 690 "BriefDescription": "RD_CAS Access to Rank 0; Bank Group 2 (Banks 8-11)", 691 "Counter": "0,1,2,3", 692 "EventCode": "0xB0", 693 "EventName": "UNC_M_RD_CAS_RANK0.BANKG2", 694 "PerPkg": "1", 695 "UMask": "0x13", 696 "Unit": "iMC" 697 }, 698 { 699 "BriefDescription": "RD_CAS Access to Rank 0; Bank Group 3 (Banks 12-15)", 700 "Counter": "0,1,2,3", 701 "EventCode": "0xB0", 702 "EventName": "UNC_M_RD_CAS_RANK0.BANKG3", 703 "PerPkg": "1", 704 "UMask": "0x14", 705 "Unit": "iMC" 706 }, 707 { 708 "BriefDescription": "RD_CAS Access to Rank 1; Bank 1", 709 "Counter": "0,1,2,3", 710 "EventCode": "0xB1", 711 "EventName": "UNC_M_RD_CAS_RANK1.BANK1", 712 "PerPkg": "1", 713 "UMask": "0x1", 714 "Unit": "iMC" 715 }, 716 { 717 "BriefDescription": "RD_CAS Access to Rank 1; Bank 2", 718 "Counter": "0,1,2,3", 719 "EventCode": "0xB1", 720 "EventName": "UNC_M_RD_CAS_RANK1.BANK2", 721 "PerPkg": "1", 722 "UMask": "0x2", 723 "Unit": "iMC" 724 }, 725 { 726 "BriefDescription": "RD_CAS Access to Rank 1; Bank 4", 727 "Counter": "0,1,2,3", 728 "EventCode": "0xB1", 729 "EventName": "UNC_M_RD_CAS_RANK1.BANK4", 730 "PerPkg": "1", 731 "UMask": "0x4", 732 "Unit": "iMC" 733 }, 734 { 735 "BriefDescription": "RD_CAS Access to Rank 1; Bank 8", 736 "Counter": "0,1,2,3", 737 "EventCode": "0xB1", 738 "EventName": "UNC_M_RD_CAS_RANK1.BANK8", 739 "PerPkg": "1", 740 "UMask": "0x8", 741 "Unit": "iMC" 742 }, 743 { 744 "BriefDescription": "RD_CAS Access to Rank 1; All Banks", 745 "Counter": "0,1,2,3", 746 "EventCode": "0xB1", 747 "EventName": "UNC_M_RD_CAS_RANK1.ALLBANKS", 748 "PerPkg": "1", 749 "UMask": "0x10", 750 "Unit": "iMC" 751 }, 752 { 753 "BriefDescription": "RD_CAS Access to Rank 1; Bank 0", 754 "Counter": "0,1,2,3", 755 "EventCode": "0xB1", 756 "EventName": "UNC_M_RD_CAS_RANK1.BANK0", 757 "PerPkg": "1", 758 "Unit": "iMC" 759 }, 760 { 761 "BriefDescription": "RD_CAS Access to Rank 1; Bank 3", 762 "Counter": "0,1,2,3", 763 "EventCode": "0xB1", 764 "EventName": "UNC_M_RD_CAS_RANK1.BANK3", 765 "PerPkg": "1", 766 "UMask": "0x3", 767 "Unit": "iMC" 768 }, 769 { 770 "BriefDescription": "RD_CAS Access to Rank 1; Bank 5", 771 "Counter": "0,1,2,3", 772 "EventCode": "0xB1", 773 "EventName": "UNC_M_RD_CAS_RANK1.BANK5", 774 "PerPkg": "1", 775 "UMask": "0x5", 776 "Unit": "iMC" 777 }, 778 { 779 "BriefDescription": "RD_CAS Access to Rank 1; Bank 6", 780 "Counter": "0,1,2,3", 781 "EventCode": "0xB1", 782 "EventName": "UNC_M_RD_CAS_RANK1.BANK6", 783 "PerPkg": "1", 784 "UMask": "0x6", 785 "Unit": "iMC" 786 }, 787 { 788 "BriefDescription": "RD_CAS Access to Rank 1; Bank 7", 789 "Counter": "0,1,2,3", 790 "EventCode": "0xB1", 791 "EventName": "UNC_M_RD_CAS_RANK1.BANK7", 792 "PerPkg": "1", 793 "UMask": "0x7", 794 "Unit": "iMC" 795 }, 796 { 797 "BriefDescription": "RD_CAS Access to Rank 1; Bank 9", 798 "Counter": "0,1,2,3", 799 "EventCode": "0xB1", 800 "EventName": "UNC_M_RD_CAS_RANK1.BANK9", 801 "PerPkg": "1", 802 "UMask": "0x9", 803 "Unit": "iMC" 804 }, 805 { 806 "BriefDescription": "RD_CAS Access to Rank 1; Bank 10", 807 "Counter": "0,1,2,3", 808 "EventCode": "0xB1", 809 "EventName": "UNC_M_RD_CAS_RANK1.BANK10", 810 "PerPkg": "1", 811 "UMask": "0xA", 812 "Unit": "iMC" 813 }, 814 { 815 "BriefDescription": "RD_CAS Access to Rank 1; Bank 11", 816 "Counter": "0,1,2,3", 817 "EventCode": "0xB1", 818 "EventName": "UNC_M_RD_CAS_RANK1.BANK11", 819 "PerPkg": "1", 820 "UMask": "0xB", 821 "Unit": "iMC" 822 }, 823 { 824 "BriefDescription": "RD_CAS Access to Rank 1; Bank 12", 825 "Counter": "0,1,2,3", 826 "EventCode": "0xB1", 827 "EventName": "UNC_M_RD_CAS_RANK1.BANK12", 828 "PerPkg": "1", 829 "UMask": "0xC", 830 "Unit": "iMC" 831 }, 832 { 833 "BriefDescription": "RD_CAS Access to Rank 1; Bank 13", 834 "Counter": "0,1,2,3", 835 "EventCode": "0xB1", 836 "EventName": "UNC_M_RD_CAS_RANK1.BANK13", 837 "PerPkg": "1", 838 "UMask": "0xD", 839 "Unit": "iMC" 840 }, 841 { 842 "BriefDescription": "RD_CAS Access to Rank 1; Bank 14", 843 "Counter": "0,1,2,3", 844 "EventCode": "0xB1", 845 "EventName": "UNC_M_RD_CAS_RANK1.BANK14", 846 "PerPkg": "1", 847 "UMask": "0xE", 848 "Unit": "iMC" 849 }, 850 { 851 "BriefDescription": "RD_CAS Access to Rank 1; Bank 15", 852 "Counter": "0,1,2,3", 853 "EventCode": "0xB1", 854 "EventName": "UNC_M_RD_CAS_RANK1.BANK15", 855 "PerPkg": "1", 856 "UMask": "0xF", 857 "Unit": "iMC" 858 }, 859 { 860 "BriefDescription": "RD_CAS Access to Rank 1; Bank Group 0 (Banks 0-3)", 861 "Counter": "0,1,2,3", 862 "EventCode": "0xB1", 863 "EventName": "UNC_M_RD_CAS_RANK1.BANKG0", 864 "PerPkg": "1", 865 "UMask": "0x11", 866 "Unit": "iMC" 867 }, 868 { 869 "BriefDescription": "RD_CAS Access to Rank 1; Bank Group 1 (Banks 4-7)", 870 "Counter": "0,1,2,3", 871 "EventCode": "0xB1", 872 "EventName": "UNC_M_RD_CAS_RANK1.BANKG1", 873 "PerPkg": "1", 874 "UMask": "0x12", 875 "Unit": "iMC" 876 }, 877 { 878 "BriefDescription": "RD_CAS Access to Rank 1; Bank Group 2 (Banks 8-11)", 879 "Counter": "0,1,2,3", 880 "EventCode": "0xB1", 881 "EventName": "UNC_M_RD_CAS_RANK1.BANKG2", 882 "PerPkg": "1", 883 "UMask": "0x13", 884 "Unit": "iMC" 885 }, 886 { 887 "BriefDescription": "RD_CAS Access to Rank 1; Bank Group 3 (Banks 12-15)", 888 "Counter": "0,1,2,3", 889 "EventCode": "0xB1", 890 "EventName": "UNC_M_RD_CAS_RANK1.BANKG3", 891 "PerPkg": "1", 892 "UMask": "0x14", 893 "Unit": "iMC" 894 }, 895 { 896 "BriefDescription": "RD_CAS Access to Rank 2; Bank 0", 897 "Counter": "0,1,2,3", 898 "EventCode": "0xB2", 899 "EventName": "UNC_M_RD_CAS_RANK2.BANK0", 900 "PerPkg": "1", 901 "Unit": "iMC" 902 }, 903 { 904 "BriefDescription": "RD_CAS Access to Rank 4; Bank 1", 905 "Counter": "0,1,2,3", 906 "EventCode": "0xB4", 907 "EventName": "UNC_M_RD_CAS_RANK4.BANK1", 908 "PerPkg": "1", 909 "UMask": "0x1", 910 "Unit": "iMC" 911 }, 912 { 913 "BriefDescription": "RD_CAS Access to Rank 4; Bank 2", 914 "Counter": "0,1,2,3", 915 "EventCode": "0xB4", 916 "EventName": "UNC_M_RD_CAS_RANK4.BANK2", 917 "PerPkg": "1", 918 "UMask": "0x2", 919 "Unit": "iMC" 920 }, 921 { 922 "BriefDescription": "RD_CAS Access to Rank 4; Bank 4", 923 "Counter": "0,1,2,3", 924 "EventCode": "0xB4", 925 "EventName": "UNC_M_RD_CAS_RANK4.BANK4", 926 "PerPkg": "1", 927 "UMask": "0x4", 928 "Unit": "iMC" 929 }, 930 { 931 "BriefDescription": "RD_CAS Access to Rank 4; Bank 8", 932 "Counter": "0,1,2,3", 933 "EventCode": "0xB4", 934 "EventName": "UNC_M_RD_CAS_RANK4.BANK8", 935 "PerPkg": "1", 936 "UMask": "0x8", 937 "Unit": "iMC" 938 }, 939 { 940 "BriefDescription": "RD_CAS Access to Rank 4; All Banks", 941 "Counter": "0,1,2,3", 942 "EventCode": "0xB4", 943 "EventName": "UNC_M_RD_CAS_RANK4.ALLBANKS", 944 "PerPkg": "1", 945 "UMask": "0x10", 946 "Unit": "iMC" 947 }, 948 { 949 "BriefDescription": "RD_CAS Access to Rank 4; Bank 0", 950 "Counter": "0,1,2,3", 951 "EventCode": "0xB4", 952 "EventName": "UNC_M_RD_CAS_RANK4.BANK0", 953 "PerPkg": "1", 954 "Unit": "iMC" 955 }, 956 { 957 "BriefDescription": "RD_CAS Access to Rank 4; Bank 3", 958 "Counter": "0,1,2,3", 959 "EventCode": "0xB4", 960 "EventName": "UNC_M_RD_CAS_RANK4.BANK3", 961 "PerPkg": "1", 962 "UMask": "0x3", 963 "Unit": "iMC" 964 }, 965 { 966 "BriefDescription": "RD_CAS Access to Rank 4; Bank 5", 967 "Counter": "0,1,2,3", 968 "EventCode": "0xB4", 969 "EventName": "UNC_M_RD_CAS_RANK4.BANK5", 970 "PerPkg": "1", 971 "UMask": "0x5", 972 "Unit": "iMC" 973 }, 974 { 975 "BriefDescription": "RD_CAS Access to Rank 4; Bank 6", 976 "Counter": "0,1,2,3", 977 "EventCode": "0xB4", 978 "EventName": "UNC_M_RD_CAS_RANK4.BANK6", 979 "PerPkg": "1", 980 "UMask": "0x6", 981 "Unit": "iMC" 982 }, 983 { 984 "BriefDescription": "RD_CAS Access to Rank 4; Bank 7", 985 "Counter": "0,1,2,3", 986 "EventCode": "0xB4", 987 "EventName": "UNC_M_RD_CAS_RANK4.BANK7", 988 "PerPkg": "1", 989 "UMask": "0x7", 990 "Unit": "iMC" 991 }, 992 { 993 "BriefDescription": "RD_CAS Access to Rank 4; Bank 9", 994 "Counter": "0,1,2,3", 995 "EventCode": "0xB4", 996 "EventName": "UNC_M_RD_CAS_RANK4.BANK9", 997 "PerPkg": "1", 998 "UMask": "0x9", 999 "Unit": "iMC" 1000 }, 1001 { 1002 "BriefDescription": "RD_CAS Access to Rank 4; Bank 10", 1003 "Counter": "0,1,2,3", 1004 "EventCode": "0xB4", 1005 "EventName": "UNC_M_RD_CAS_RANK4.BANK10", 1006 "PerPkg": "1", 1007 "UMask": "0xA", 1008 "Unit": "iMC" 1009 }, 1010 { 1011 "BriefDescription": "RD_CAS Access to Rank 4; Bank 11", 1012 "Counter": "0,1,2,3", 1013 "EventCode": "0xB4", 1014 "EventName": "UNC_M_RD_CAS_RANK4.BANK11", 1015 "PerPkg": "1", 1016 "UMask": "0xB", 1017 "Unit": "iMC" 1018 }, 1019 { 1020 "BriefDescription": "RD_CAS Access to Rank 4; Bank 12", 1021 "Counter": "0,1,2,3", 1022 "EventCode": "0xB4", 1023 "EventName": "UNC_M_RD_CAS_RANK4.BANK12", 1024 "PerPkg": "1", 1025 "UMask": "0xC", 1026 "Unit": "iMC" 1027 }, 1028 { 1029 "BriefDescription": "RD_CAS Access to Rank 4; Bank 13", 1030 "Counter": "0,1,2,3", 1031 "EventCode": "0xB4", 1032 "EventName": "UNC_M_RD_CAS_RANK4.BANK13", 1033 "PerPkg": "1", 1034 "UMask": "0xD", 1035 "Unit": "iMC" 1036 }, 1037 { 1038 "BriefDescription": "RD_CAS Access to Rank 4; Bank 14", 1039 "Counter": "0,1,2,3", 1040 "EventCode": "0xB4", 1041 "EventName": "UNC_M_RD_CAS_RANK4.BANK14", 1042 "PerPkg": "1", 1043 "UMask": "0xE", 1044 "Unit": "iMC" 1045 }, 1046 { 1047 "BriefDescription": "RD_CAS Access to Rank 4; Bank 15", 1048 "Counter": "0,1,2,3", 1049 "EventCode": "0xB4", 1050 "EventName": "UNC_M_RD_CAS_RANK4.BANK15", 1051 "PerPkg": "1", 1052 "UMask": "0xF", 1053 "Unit": "iMC" 1054 }, 1055 { 1056 "BriefDescription": "RD_CAS Access to Rank 4; Bank Group 0 (Banks 0-3)", 1057 "Counter": "0,1,2,3", 1058 "EventCode": "0xB4", 1059 "EventName": "UNC_M_RD_CAS_RANK4.BANKG0", 1060 "PerPkg": "1", 1061 "UMask": "0x11", 1062 "Unit": "iMC" 1063 }, 1064 { 1065 "BriefDescription": "RD_CAS Access to Rank 4; Bank Group 1 (Banks 4-7)", 1066 "Counter": "0,1,2,3", 1067 "EventCode": "0xB4", 1068 "EventName": "UNC_M_RD_CAS_RANK4.BANKG1", 1069 "PerPkg": "1", 1070 "UMask": "0x12", 1071 "Unit": "iMC" 1072 }, 1073 { 1074 "BriefDescription": "RD_CAS Access to Rank 4; Bank Group 2 (Banks 8-11)", 1075 "Counter": "0,1,2,3", 1076 "EventCode": "0xB4", 1077 "EventName": "UNC_M_RD_CAS_RANK4.BANKG2", 1078 "PerPkg": "1", 1079 "UMask": "0x13", 1080 "Unit": "iMC" 1081 }, 1082 { 1083 "BriefDescription": "RD_CAS Access to Rank 4; Bank Group 3 (Banks 12-15)", 1084 "Counter": "0,1,2,3", 1085 "EventCode": "0xB4", 1086 "EventName": "UNC_M_RD_CAS_RANK4.BANKG3", 1087 "PerPkg": "1", 1088 "UMask": "0x14", 1089 "Unit": "iMC" 1090 }, 1091 { 1092 "BriefDescription": "RD_CAS Access to Rank 5; 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Bank 0", 1138 "Counter": "0,1,2,3", 1139 "EventCode": "0xB5", 1140 "EventName": "UNC_M_RD_CAS_RANK5.BANK0", 1141 "PerPkg": "1", 1142 "Unit": "iMC" 1143 }, 1144 { 1145 "BriefDescription": "RD_CAS Access to Rank 5; Bank 3", 1146 "Counter": "0,1,2,3", 1147 "EventCode": "0xB5", 1148 "EventName": "UNC_M_RD_CAS_RANK5.BANK3", 1149 "PerPkg": "1", 1150 "UMask": "0x3", 1151 "Unit": "iMC" 1152 }, 1153 { 1154 "BriefDescription": "RD_CAS Access to Rank 5; Bank 5", 1155 "Counter": "0,1,2,3", 1156 "EventCode": "0xB5", 1157 "EventName": "UNC_M_RD_CAS_RANK5.BANK5", 1158 "PerPkg": "1", 1159 "UMask": "0x5", 1160 "Unit": "iMC" 1161 }, 1162 { 1163 "BriefDescription": "RD_CAS Access to Rank 5; Bank 6", 1164 "Counter": "0,1,2,3", 1165 "EventCode": "0xB5", 1166 "EventName": "UNC_M_RD_CAS_RANK5.BANK6", 1167 "PerPkg": "1", 1168 "UMask": "0x6", 1169 "Unit": "iMC" 1170 }, 1171 { 1172 "BriefDescription": "RD_CAS Access to Rank 5; Bank 7", 1173 "Counter": "0,1,2,3", 1174 "EventCode": "0xB5", 1175 "EventName": "UNC_M_RD_CAS_RANK5.BANK7", 1176 "PerPkg": "1", 1177 "UMask": "0x7", 1178 "Unit": "iMC" 1179 }, 1180 { 1181 "BriefDescription": "RD_CAS Access to Rank 5; Bank 9", 1182 "Counter": "0,1,2,3", 1183 "EventCode": "0xB5", 1184 "EventName": "UNC_M_RD_CAS_RANK5.BANK9", 1185 "PerPkg": "1", 1186 "UMask": "0x9", 1187 "Unit": "iMC" 1188 }, 1189 { 1190 "BriefDescription": "RD_CAS Access to Rank 5; Bank 10", 1191 "Counter": "0,1,2,3", 1192 "EventCode": "0xB5", 1193 "EventName": "UNC_M_RD_CAS_RANK5.BANK10", 1194 "PerPkg": "1", 1195 "UMask": "0xA", 1196 "Unit": "iMC" 1197 }, 1198 { 1199 "BriefDescription": "RD_CAS Access to Rank 5; Bank 11", 1200 "Counter": "0,1,2,3", 1201 "EventCode": "0xB5", 1202 "EventName": "UNC_M_RD_CAS_RANK5.BANK11", 1203 "PerPkg": "1", 1204 "UMask": "0xB", 1205 "Unit": "iMC" 1206 }, 1207 { 1208 "BriefDescription": "RD_CAS Access to Rank 5; Bank 12", 1209 "Counter": "0,1,2,3", 1210 "EventCode": "0xB5", 1211 "EventName": "UNC_M_RD_CAS_RANK5.BANK12", 1212 "PerPkg": "1", 1213 "UMask": "0xC", 1214 "Unit": "iMC" 1215 }, 1216 { 1217 "BriefDescription": "RD_CAS Access to Rank 5; Bank 13", 1218 "Counter": "0,1,2,3", 1219 "EventCode": "0xB5", 1220 "EventName": "UNC_M_RD_CAS_RANK5.BANK13", 1221 "PerPkg": "1", 1222 "UMask": "0xD", 1223 "Unit": "iMC" 1224 }, 1225 { 1226 "BriefDescription": "RD_CAS Access to Rank 5; Bank 14", 1227 "Counter": "0,1,2,3", 1228 "EventCode": "0xB5", 1229 "EventName": "UNC_M_RD_CAS_RANK5.BANK14", 1230 "PerPkg": "1", 1231 "UMask": "0xE", 1232 "Unit": "iMC" 1233 }, 1234 { 1235 "BriefDescription": "RD_CAS Access to Rank 5; Bank 15", 1236 "Counter": "0,1,2,3", 1237 "EventCode": "0xB5", 1238 "EventName": "UNC_M_RD_CAS_RANK5.BANK15", 1239 "PerPkg": "1", 1240 "UMask": "0xF", 1241 "Unit": "iMC" 1242 }, 1243 { 1244 "BriefDescription": "RD_CAS Access to Rank 5; Bank Group 0 (Banks 0-3)", 1245 "Counter": "0,1,2,3", 1246 "EventCode": "0xB5", 1247 "EventName": "UNC_M_RD_CAS_RANK5.BANKG0", 1248 "PerPkg": "1", 1249 "UMask": "0x11", 1250 "Unit": "iMC" 1251 }, 1252 { 1253 "BriefDescription": "RD_CAS Access to Rank 5; Bank Group 1 (Banks 4-7)", 1254 "Counter": "0,1,2,3", 1255 "EventCode": "0xB5", 1256 "EventName": "UNC_M_RD_CAS_RANK5.BANKG1", 1257 "PerPkg": "1", 1258 "UMask": "0x12", 1259 "Unit": "iMC" 1260 }, 1261 { 1262 "BriefDescription": "RD_CAS Access to Rank 5; Bank Group 2 (Banks 8-11)", 1263 "Counter": "0,1,2,3", 1264 "EventCode": "0xB5", 1265 "EventName": "UNC_M_RD_CAS_RANK5.BANKG2", 1266 "PerPkg": "1", 1267 "UMask": "0x13", 1268 "Unit": "iMC" 1269 }, 1270 { 1271 "BriefDescription": "RD_CAS Access to Rank 5; Bank Group 3 (Banks 12-15)", 1272 "Counter": "0,1,2,3", 1273 "EventCode": "0xB5", 1274 "EventName": "UNC_M_RD_CAS_RANK5.BANKG3", 1275 "PerPkg": "1", 1276 "UMask": "0x14", 1277 "Unit": "iMC" 1278 }, 1279 { 1280 "BriefDescription": "RD_CAS Access to Rank 6; Bank 1", 1281 "Counter": "0,1,2,3", 1282 "EventCode": "0xB6", 1283 "EventName": "UNC_M_RD_CAS_RANK6.BANK1", 1284 "PerPkg": "1", 1285 "UMask": "0x1", 1286 "Unit": "iMC" 1287 }, 1288 { 1289 "BriefDescription": "RD_CAS Access to Rank 6; Bank 2", 1290 "Counter": "0,1,2,3", 1291 "EventCode": "0xB6", 1292 "EventName": "UNC_M_RD_CAS_RANK6.BANK2", 1293 "PerPkg": "1", 1294 "UMask": "0x2", 1295 "Unit": "iMC" 1296 }, 1297 { 1298 "BriefDescription": "RD_CAS Access to Rank 6; Bank 4", 1299 "Counter": "0,1,2,3", 1300 "EventCode": "0xB6", 1301 "EventName": "UNC_M_RD_CAS_RANK6.BANK4", 1302 "PerPkg": "1", 1303 "UMask": "0x4", 1304 "Unit": "iMC" 1305 }, 1306 { 1307 "BriefDescription": "RD_CAS Access to Rank 6; Bank 8", 1308 "Counter": "0,1,2,3", 1309 "EventCode": "0xB6", 1310 "EventName": "UNC_M_RD_CAS_RANK6.BANK8", 1311 "PerPkg": "1", 1312 "UMask": "0x8", 1313 "Unit": "iMC" 1314 }, 1315 { 1316 "BriefDescription": "RD_CAS Access to Rank 6; All Banks", 1317 "Counter": "0,1,2,3", 1318 "EventCode": "0xB6", 1319 "EventName": "UNC_M_RD_CAS_RANK6.ALLBANKS", 1320 "PerPkg": "1", 1321 "UMask": "0x10", 1322 "Unit": "iMC" 1323 }, 1324 { 1325 "BriefDescription": "RD_CAS Access to Rank 6; Bank 0", 1326 "Counter": "0,1,2,3", 1327 "EventCode": "0xB6", 1328 "EventName": "UNC_M_RD_CAS_RANK6.BANK0", 1329 "PerPkg": "1", 1330 "Unit": "iMC" 1331 }, 1332 { 1333 "BriefDescription": "RD_CAS Access to Rank 6; Bank 3", 1334 "Counter": "0,1,2,3", 1335 "EventCode": "0xB6", 1336 "EventName": "UNC_M_RD_CAS_RANK6.BANK3", 1337 "PerPkg": "1", 1338 "UMask": "0x3", 1339 "Unit": "iMC" 1340 }, 1341 { 1342 "BriefDescription": "RD_CAS Access to Rank 6; Bank 5", 1343 "Counter": "0,1,2,3", 1344 "EventCode": "0xB6", 1345 "EventName": "UNC_M_RD_CAS_RANK6.BANK5", 1346 "PerPkg": "1", 1347 "UMask": "0x5", 1348 "Unit": "iMC" 1349 }, 1350 { 1351 "BriefDescription": "RD_CAS Access to Rank 6; Bank 6", 1352 "Counter": "0,1,2,3", 1353 "EventCode": "0xB6", 1354 "EventName": "UNC_M_RD_CAS_RANK6.BANK6", 1355 "PerPkg": "1", 1356 "UMask": "0x6", 1357 "Unit": "iMC" 1358 }, 1359 { 1360 "BriefDescription": "RD_CAS Access to Rank 6; Bank 7", 1361 "Counter": "0,1,2,3", 1362 "EventCode": "0xB6", 1363 "EventName": "UNC_M_RD_CAS_RANK6.BANK7", 1364 "PerPkg": "1", 1365 "UMask": "0x7", 1366 "Unit": "iMC" 1367 }, 1368 { 1369 "BriefDescription": "RD_CAS Access to Rank 6; Bank 9", 1370 "Counter": "0,1,2,3", 1371 "EventCode": "0xB6", 1372 "EventName": "UNC_M_RD_CAS_RANK6.BANK9", 1373 "PerPkg": "1", 1374 "UMask": "0x9", 1375 "Unit": "iMC" 1376 }, 1377 { 1378 "BriefDescription": "RD_CAS Access to Rank 6; Bank 10", 1379 "Counter": "0,1,2,3", 1380 "EventCode": "0xB6", 1381 "EventName": "UNC_M_RD_CAS_RANK6.BANK10", 1382 "PerPkg": "1", 1383 "UMask": "0xA", 1384 "Unit": "iMC" 1385 }, 1386 { 1387 "BriefDescription": "RD_CAS Access to Rank 6; Bank 11", 1388 "Counter": "0,1,2,3", 1389 "EventCode": "0xB6", 1390 "EventName": "UNC_M_RD_CAS_RANK6.BANK11", 1391 "PerPkg": "1", 1392 "UMask": "0xB", 1393 "Unit": "iMC" 1394 }, 1395 { 1396 "BriefDescription": "RD_CAS Access to Rank 6; Bank 12", 1397 "Counter": "0,1,2,3", 1398 "EventCode": "0xB6", 1399 "EventName": "UNC_M_RD_CAS_RANK6.BANK12", 1400 "PerPkg": "1", 1401 "UMask": "0xC", 1402 "Unit": "iMC" 1403 }, 1404 { 1405 "BriefDescription": "RD_CAS Access to Rank 6; Bank 13", 1406 "Counter": "0,1,2,3", 1407 "EventCode": "0xB6", 1408 "EventName": "UNC_M_RD_CAS_RANK6.BANK13", 1409 "PerPkg": "1", 1410 "UMask": "0xD", 1411 "Unit": "iMC" 1412 }, 1413 { 1414 "BriefDescription": "RD_CAS Access to Rank 6; Bank 14", 1415 "Counter": "0,1,2,3", 1416 "EventCode": "0xB6", 1417 "EventName": "UNC_M_RD_CAS_RANK6.BANK14", 1418 "PerPkg": "1", 1419 "UMask": "0xE", 1420 "Unit": "iMC" 1421 }, 1422 { 1423 "BriefDescription": "RD_CAS Access to Rank 6; Bank 15", 1424 "Counter": "0,1,2,3", 1425 "EventCode": "0xB6", 1426 "EventName": "UNC_M_RD_CAS_RANK6.BANK15", 1427 "PerPkg": "1", 1428 "UMask": "0xF", 1429 "Unit": "iMC" 1430 }, 1431 { 1432 "BriefDescription": "RD_CAS Access to Rank 6; Bank Group 0 (Banks 0-3)", 1433 "Counter": "0,1,2,3", 1434 "EventCode": "0xB6", 1435 "EventName": "UNC_M_RD_CAS_RANK6.BANKG0", 1436 "PerPkg": "1", 1437 "UMask": "0x11", 1438 "Unit": "iMC" 1439 }, 1440 { 1441 "BriefDescription": "RD_CAS Access to Rank 6; Bank Group 1 (Banks 4-7)", 1442 "Counter": "0,1,2,3", 1443 "EventCode": "0xB6", 1444 "EventName": "UNC_M_RD_CAS_RANK6.BANKG1", 1445 "PerPkg": "1", 1446 "UMask": "0x12", 1447 "Unit": "iMC" 1448 }, 1449 { 1450 "BriefDescription": "RD_CAS Access to Rank 6; Bank Group 2 (Banks 8-11)", 1451 "Counter": "0,1,2,3", 1452 "EventCode": "0xB6", 1453 "EventName": "UNC_M_RD_CAS_RANK6.BANKG2", 1454 "PerPkg": "1", 1455 "UMask": "0x13", 1456 "Unit": "iMC" 1457 }, 1458 { 1459 "BriefDescription": "RD_CAS Access to Rank 6; Bank Group 3 (Banks 12-15)", 1460 "Counter": "0,1,2,3", 1461 "EventCode": "0xB6", 1462 "EventName": "UNC_M_RD_CAS_RANK6.BANKG3", 1463 "PerPkg": "1", 1464 "UMask": "0x14", 1465 "Unit": "iMC" 1466 }, 1467 { 1468 "BriefDescription": "RD_CAS Access to Rank 7; Bank 1", 1469 "Counter": "0,1,2,3", 1470 "EventCode": "0xB7", 1471 "EventName": "UNC_M_RD_CAS_RANK7.BANK1", 1472 "PerPkg": "1", 1473 "UMask": "0x1", 1474 "Unit": "iMC" 1475 }, 1476 { 1477 "BriefDescription": "RD_CAS Access to Rank 7; Bank 2", 1478 "Counter": "0,1,2,3", 1479 "EventCode": "0xB7", 1480 "EventName": "UNC_M_RD_CAS_RANK7.BANK2", 1481 "PerPkg": "1", 1482 "UMask": "0x2", 1483 "Unit": "iMC" 1484 }, 1485 { 1486 "BriefDescription": "RD_CAS Access to Rank 7; Bank 4", 1487 "Counter": "0,1,2,3", 1488 "EventCode": "0xB7", 1489 "EventName": "UNC_M_RD_CAS_RANK7.BANK4", 1490 "PerPkg": "1", 1491 "UMask": "0x4", 1492 "Unit": "iMC" 1493 }, 1494 { 1495 "BriefDescription": "RD_CAS Access to Rank 7; Bank 8", 1496 "Counter": "0,1,2,3", 1497 "EventCode": "0xB7", 1498 "EventName": "UNC_M_RD_CAS_RANK7.BANK8", 1499 "PerPkg": "1", 1500 "UMask": "0x8", 1501 "Unit": "iMC" 1502 }, 1503 { 1504 "BriefDescription": "RD_CAS Access to Rank 7; All Banks", 1505 "Counter": "0,1,2,3", 1506 "EventCode": "0xB7", 1507 "EventName": "UNC_M_RD_CAS_RANK7.ALLBANKS", 1508 "PerPkg": "1", 1509 "UMask": "0x10", 1510 "Unit": "iMC" 1511 }, 1512 { 1513 "BriefDescription": "RD_CAS Access to Rank 7; Bank 0", 1514 "Counter": "0,1,2,3", 1515 "EventCode": "0xB7", 1516 "EventName": "UNC_M_RD_CAS_RANK7.BANK0", 1517 "PerPkg": "1", 1518 "Unit": "iMC" 1519 }, 1520 { 1521 "BriefDescription": "RD_CAS Access to Rank 7; Bank 3", 1522 "Counter": "0,1,2,3", 1523 "EventCode": "0xB7", 1524 "EventName": "UNC_M_RD_CAS_RANK7.BANK3", 1525 "PerPkg": "1", 1526 "UMask": "0x3", 1527 "Unit": "iMC" 1528 }, 1529 { 1530 "BriefDescription": "RD_CAS Access to Rank 7; Bank 5", 1531 "Counter": "0,1,2,3", 1532 "EventCode": "0xB7", 1533 "EventName": "UNC_M_RD_CAS_RANK7.BANK5", 1534 "PerPkg": "1", 1535 "UMask": "0x5", 1536 "Unit": "iMC" 1537 }, 1538 { 1539 "BriefDescription": "RD_CAS Access to Rank 7; Bank 6", 1540 "Counter": "0,1,2,3", 1541 "EventCode": "0xB7", 1542 "EventName": "UNC_M_RD_CAS_RANK7.BANK6", 1543 "PerPkg": "1", 1544 "UMask": "0x6", 1545 "Unit": "iMC" 1546 }, 1547 { 1548 "BriefDescription": "RD_CAS Access to Rank 7; Bank 7", 1549 "Counter": "0,1,2,3", 1550 "EventCode": "0xB7", 1551 "EventName": "UNC_M_RD_CAS_RANK7.BANK7", 1552 "PerPkg": "1", 1553 "UMask": "0x7", 1554 "Unit": "iMC" 1555 }, 1556 { 1557 "BriefDescription": "RD_CAS Access to Rank 7; Bank 9", 1558 "Counter": "0,1,2,3", 1559 "EventCode": "0xB7", 1560 "EventName": "UNC_M_RD_CAS_RANK7.BANK9", 1561 "PerPkg": "1", 1562 "UMask": "0x9", 1563 "Unit": "iMC" 1564 }, 1565 { 1566 "BriefDescription": "RD_CAS Access to Rank 7; Bank 10", 1567 "Counter": "0,1,2,3", 1568 "EventCode": "0xB7", 1569 "EventName": "UNC_M_RD_CAS_RANK7.BANK10", 1570 "PerPkg": "1", 1571 "UMask": "0xA", 1572 "Unit": "iMC" 1573 }, 1574 { 1575 "BriefDescription": "RD_CAS Access to Rank 7; Bank 11", 1576 "Counter": "0,1,2,3", 1577 "EventCode": "0xB7", 1578 "EventName": "UNC_M_RD_CAS_RANK7.BANK11", 1579 "PerPkg": "1", 1580 "UMask": "0xB", 1581 "Unit": "iMC" 1582 }, 1583 { 1584 "BriefDescription": "RD_CAS Access to Rank 7; Bank 12", 1585 "Counter": "0,1,2,3", 1586 "EventCode": "0xB7", 1587 "EventName": "UNC_M_RD_CAS_RANK7.BANK12", 1588 "PerPkg": "1", 1589 "UMask": "0xC", 1590 "Unit": "iMC" 1591 }, 1592 { 1593 "BriefDescription": "RD_CAS Access to Rank 7; Bank 13", 1594 "Counter": "0,1,2,3", 1595 "EventCode": "0xB7", 1596 "EventName": "UNC_M_RD_CAS_RANK7.BANK13", 1597 "PerPkg": "1", 1598 "UMask": "0xD", 1599 "Unit": "iMC" 1600 }, 1601 { 1602 "BriefDescription": "RD_CAS Access to Rank 7; Bank 14", 1603 "Counter": "0,1,2,3", 1604 "EventCode": "0xB7", 1605 "EventName": "UNC_M_RD_CAS_RANK7.BANK14", 1606 "PerPkg": "1", 1607 "UMask": "0xE", 1608 "Unit": "iMC" 1609 }, 1610 { 1611 "BriefDescription": "RD_CAS Access to Rank 7; Bank 15", 1612 "Counter": "0,1,2,3", 1613 "EventCode": "0xB7", 1614 "EventName": "UNC_M_RD_CAS_RANK7.BANK15", 1615 "PerPkg": "1", 1616 "UMask": "0xF", 1617 "Unit": "iMC" 1618 }, 1619 { 1620 "BriefDescription": "RD_CAS Access to Rank 7; Bank Group 0 (Banks 0-3)", 1621 "Counter": "0,1,2,3", 1622 "EventCode": "0xB7", 1623 "EventName": "UNC_M_RD_CAS_RANK7.BANKG0", 1624 "PerPkg": "1", 1625 "UMask": "0x11", 1626 "Unit": "iMC" 1627 }, 1628 { 1629 "BriefDescription": "RD_CAS Access to Rank 7; Bank Group 1 (Banks 4-7)", 1630 "Counter": "0,1,2,3", 1631 "EventCode": "0xB7", 1632 "EventName": "UNC_M_RD_CAS_RANK7.BANKG1", 1633 "PerPkg": "1", 1634 "UMask": "0x12", 1635 "Unit": "iMC" 1636 }, 1637 { 1638 "BriefDescription": "RD_CAS Access to Rank 7; Bank Group 2 (Banks 8-11)", 1639 "Counter": "0,1,2,3", 1640 "EventCode": "0xB7", 1641 "EventName": "UNC_M_RD_CAS_RANK7.BANKG2", 1642 "PerPkg": "1", 1643 "UMask": "0x13", 1644 "Unit": "iMC" 1645 }, 1646 { 1647 "BriefDescription": "RD_CAS Access to Rank 7; Bank Group 3 (Banks 12-15)", 1648 "Counter": "0,1,2,3", 1649 "EventCode": "0xB7", 1650 "EventName": "UNC_M_RD_CAS_RANK7.BANKG3", 1651 "PerPkg": "1", 1652 "UMask": "0x14", 1653 "Unit": "iMC" 1654 }, 1655 { 1656 "BriefDescription": "Read Pending Queue Not Empty", 1657 "Counter": "0,1,2,3", 1658 "EventCode": "0x11", 1659 "EventName": "UNC_M_RPQ_CYCLES_NE", 1660 "PerPkg": "1", 1661 "Unit": "iMC" 1662 }, 1663 { 1664 "BriefDescription": "Read Pending Queue Allocations", 1665 "Counter": "0,1,2,3", 1666 "EventCode": "0x10", 1667 "EventName": "UNC_M_RPQ_INSERTS", 1668 "PerPkg": "1", 1669 "Unit": "iMC" 1670 }, 1671 { 1672 "BriefDescription": "VMSE MXB write buffer occupancy", 1673 "Counter": "0,1,2,3", 1674 "EventCode": "0x91", 1675 "EventName": "UNC_M_VMSE_MXB_WR_OCCUPANCY", 1676 "PerPkg": "1", 1677 "Unit": "iMC" 1678 }, 1679 { 1680 "BriefDescription": "VMSE WR PUSH issued; VMSE write PUSH issued in WMM", 1681 "Counter": "0,1,2,3", 1682 "EventCode": "0x90", 1683 "EventName": "UNC_M_VMSE_WR_PUSH.WMM", 1684 "PerPkg": "1", 1685 "UMask": "0x1", 1686 "Unit": "iMC" 1687 }, 1688 { 1689 "BriefDescription": "VMSE WR PUSH issued; VMSE write PUSH issued in RMM", 1690 "Counter": "0,1,2,3", 1691 "EventCode": "0x90", 1692 "EventName": "UNC_M_VMSE_WR_PUSH.RMM", 1693 "PerPkg": "1", 1694 "UMask": "0x2", 1695 "Unit": "iMC" 1696 }, 1697 { 1698 "BriefDescription": "Transition from WMM to RMM because of low threshold; Transition from WMM to RMM because of starve counter", 1699 "Counter": "0,1,2,3", 1700 "EventCode": "0xC0", 1701 "EventName": "UNC_M_WMM_TO_RMM.LOW_THRESH", 1702 "PerPkg": "1", 1703 "UMask": "0x1", 1704 "Unit": "iMC" 1705 }, 1706 { 1707 "BriefDescription": "Transition from WMM to RMM because of low threshold", 1708 "Counter": "0,1,2,3", 1709 "EventCode": "0xC0", 1710 "EventName": "UNC_M_WMM_TO_RMM.STARVE", 1711 "PerPkg": "1", 1712 "UMask": "0x2", 1713 "Unit": "iMC" 1714 }, 1715 { 1716 "BriefDescription": "Transition from WMM to RMM because of low threshold", 1717 "Counter": "0,1,2,3", 1718 "EventCode": "0xC0", 1719 "EventName": "UNC_M_WMM_TO_RMM.VMSE_RETRY", 1720 "PerPkg": "1", 1721 "UMask": "0x4", 1722 "Unit": "iMC" 1723 }, 1724 { 1725 "BriefDescription": "Write Pending Queue Full Cycles", 1726 "Counter": "0,1,2,3", 1727 "EventCode": "0x22", 1728 "EventName": "UNC_M_WPQ_CYCLES_FULL", 1729 "PerPkg": "1", 1730 "Unit": "iMC" 1731 }, 1732 { 1733 "BriefDescription": "Write Pending Queue Not Empty", 1734 "Counter": "0,1,2,3", 1735 "EventCode": "0x21", 1736 "EventName": "UNC_M_WPQ_CYCLES_NE", 1737 "PerPkg": "1", 1738 "Unit": "iMC" 1739 }, 1740 { 1741 "BriefDescription": "Write Pending Queue CAM Match", 1742 "Counter": "0,1,2,3", 1743 "EventCode": "0x23", 1744 "EventName": "UNC_M_WPQ_READ_HIT", 1745 "PerPkg": "1", 1746 "Unit": "iMC" 1747 }, 1748 { 1749 "BriefDescription": "Write Pending Queue CAM Match", 1750 "Counter": "0,1,2,3", 1751 "EventCode": "0x24", 1752 "EventName": "UNC_M_WPQ_WRITE_HIT", 1753 "PerPkg": "1", 1754 "Unit": "iMC" 1755 }, 1756 { 1757 "BriefDescription": "Not getting the requested Major Mode", 1758 "Counter": "0,1,2,3", 1759 "EventCode": "0xC1", 1760 "EventName": "UNC_M_WRONG_MM", 1761 "PerPkg": "1", 1762 "Unit": "iMC" 1763 }, 1764 { 1765 "BriefDescription": "WR_CAS Access to Rank 0; Bank 1", 1766 "Counter": "0,1,2,3", 1767 "EventCode": "0xB8", 1768 "EventName": "UNC_M_WR_CAS_RANK0.BANK1", 1769 "PerPkg": "1", 1770 "UMask": "0x1", 1771 "Unit": "iMC" 1772 }, 1773 { 1774 "BriefDescription": "WR_CAS Access to Rank 0; Bank 2", 1775 "Counter": "0,1,2,3", 1776 "EventCode": "0xB8", 1777 "EventName": "UNC_M_WR_CAS_RANK0.BANK2", 1778 "PerPkg": "1", 1779 "UMask": "0x2", 1780 "Unit": "iMC" 1781 }, 1782 { 1783 "BriefDescription": "WR_CAS Access to Rank 0; Bank 4", 1784 "Counter": "0,1,2,3", 1785 "EventCode": "0xB8", 1786 "EventName": "UNC_M_WR_CAS_RANK0.BANK4", 1787 "PerPkg": "1", 1788 "UMask": "0x4", 1789 "Unit": "iMC" 1790 }, 1791 { 1792 "BriefDescription": "WR_CAS Access to Rank 0; Bank 8", 1793 "Counter": "0,1,2,3", 1794 "EventCode": "0xB8", 1795 "EventName": "UNC_M_WR_CAS_RANK0.BANK8", 1796 "PerPkg": "1", 1797 "UMask": "0x8", 1798 "Unit": "iMC" 1799 }, 1800 { 1801 "BriefDescription": "WR_CAS Access to Rank 0; All Banks", 1802 "Counter": "0,1,2,3", 1803 "EventCode": "0xB8", 1804 "EventName": "UNC_M_WR_CAS_RANK0.ALLBANKS", 1805 "PerPkg": "1", 1806 "UMask": "0x10", 1807 "Unit": "iMC" 1808 }, 1809 { 1810 "BriefDescription": "WR_CAS Access to Rank 0; Bank 0", 1811 "Counter": "0,1,2,3", 1812 "EventCode": "0xB8", 1813 "EventName": "UNC_M_WR_CAS_RANK0.BANK0", 1814 "PerPkg": "1", 1815 "Unit": "iMC" 1816 }, 1817 { 1818 "BriefDescription": "WR_CAS Access to Rank 0; Bank 3", 1819 "Counter": "0,1,2,3", 1820 "EventCode": "0xB8", 1821 "EventName": "UNC_M_WR_CAS_RANK0.BANK3", 1822 "PerPkg": "1", 1823 "UMask": "0x3", 1824 "Unit": "iMC" 1825 }, 1826 { 1827 "BriefDescription": "WR_CAS Access to Rank 0; Bank 5", 1828 "Counter": "0,1,2,3", 1829 "EventCode": "0xB8", 1830 "EventName": "UNC_M_WR_CAS_RANK0.BANK5", 1831 "PerPkg": "1", 1832 "UMask": "0x5", 1833 "Unit": "iMC" 1834 }, 1835 { 1836 "BriefDescription": "WR_CAS Access to Rank 0; Bank 6", 1837 "Counter": "0,1,2,3", 1838 "EventCode": "0xB8", 1839 "EventName": "UNC_M_WR_CAS_RANK0.BANK6", 1840 "PerPkg": "1", 1841 "UMask": "0x6", 1842 "Unit": "iMC" 1843 }, 1844 { 1845 "BriefDescription": "WR_CAS Access to Rank 0; Bank 7", 1846 "Counter": "0,1,2,3", 1847 "EventCode": "0xB8", 1848 "EventName": "UNC_M_WR_CAS_RANK0.BANK7", 1849 "PerPkg": "1", 1850 "UMask": "0x7", 1851 "Unit": "iMC" 1852 }, 1853 { 1854 "BriefDescription": "WR_CAS Access to Rank 0; Bank 9", 1855 "Counter": "0,1,2,3", 1856 "EventCode": "0xB8", 1857 "EventName": "UNC_M_WR_CAS_RANK0.BANK9", 1858 "PerPkg": "1", 1859 "UMask": "0x9", 1860 "Unit": "iMC" 1861 }, 1862 { 1863 "BriefDescription": "WR_CAS Access to Rank 0; Bank 10", 1864 "Counter": "0,1,2,3", 1865 "EventCode": "0xB8", 1866 "EventName": "UNC_M_WR_CAS_RANK0.BANK10", 1867 "PerPkg": "1", 1868 "UMask": "0xA", 1869 "Unit": "iMC" 1870 }, 1871 { 1872 "BriefDescription": "WR_CAS Access to Rank 0; Bank 11", 1873 "Counter": "0,1,2,3", 1874 "EventCode": "0xB8", 1875 "EventName": "UNC_M_WR_CAS_RANK0.BANK11", 1876 "PerPkg": "1", 1877 "UMask": "0xB", 1878 "Unit": "iMC" 1879 }, 1880 { 1881 "BriefDescription": "WR_CAS Access to Rank 0; Bank 12", 1882 "Counter": "0,1,2,3", 1883 "EventCode": "0xB8", 1884 "EventName": "UNC_M_WR_CAS_RANK0.BANK12", 1885 "PerPkg": "1", 1886 "UMask": "0xC", 1887 "Unit": "iMC" 1888 }, 1889 { 1890 "BriefDescription": "WR_CAS Access to Rank 0; Bank 13", 1891 "Counter": "0,1,2,3", 1892 "EventCode": "0xB8", 1893 "EventName": "UNC_M_WR_CAS_RANK0.BANK13", 1894 "PerPkg": "1", 1895 "UMask": "0xD", 1896 "Unit": "iMC" 1897 }, 1898 { 1899 "BriefDescription": "WR_CAS Access to Rank 0; Bank 14", 1900 "Counter": "0,1,2,3", 1901 "EventCode": "0xB8", 1902 "EventName": "UNC_M_WR_CAS_RANK0.BANK14", 1903 "PerPkg": "1", 1904 "UMask": "0xE", 1905 "Unit": "iMC" 1906 }, 1907 { 1908 "BriefDescription": "WR_CAS Access to Rank 0; Bank 15", 1909 "Counter": "0,1,2,3", 1910 "EventCode": "0xB8", 1911 "EventName": "UNC_M_WR_CAS_RANK0.BANK15", 1912 "PerPkg": "1", 1913 "UMask": "0xF", 1914 "Unit": "iMC" 1915 }, 1916 { 1917 "BriefDescription": "WR_CAS Access to Rank 0; Bank Group 0 (Banks 0-3)", 1918 "Counter": "0,1,2,3", 1919 "EventCode": "0xB8", 1920 "EventName": "UNC_M_WR_CAS_RANK0.BANKG0", 1921 "PerPkg": "1", 1922 "UMask": "0x11", 1923 "Unit": "iMC" 1924 }, 1925 { 1926 "BriefDescription": "WR_CAS Access to Rank 0; Bank Group 1 (Banks 4-7)", 1927 "Counter": "0,1,2,3", 1928 "EventCode": "0xB8", 1929 "EventName": "UNC_M_WR_CAS_RANK0.BANKG1", 1930 "PerPkg": "1", 1931 "UMask": "0x12", 1932 "Unit": "iMC" 1933 }, 1934 { 1935 "BriefDescription": "WR_CAS Access to Rank 0; Bank Group 2 (Banks 8-11)", 1936 "Counter": "0,1,2,3", 1937 "EventCode": "0xB8", 1938 "EventName": "UNC_M_WR_CAS_RANK0.BANKG2", 1939 "PerPkg": "1", 1940 "UMask": "0x13", 1941 "Unit": "iMC" 1942 }, 1943 { 1944 "BriefDescription": "WR_CAS Access to Rank 0; Bank Group 3 (Banks 12-15)", 1945 "Counter": "0,1,2,3", 1946 "EventCode": "0xB8", 1947 "EventName": "UNC_M_WR_CAS_RANK0.BANKG3", 1948 "PerPkg": "1", 1949 "UMask": "0x14", 1950 "Unit": "iMC" 1951 }, 1952 { 1953 "BriefDescription": "WR_CAS Access to Rank 1; Bank 1", 1954 "Counter": "0,1,2,3", 1955 "EventCode": "0xB9", 1956 "EventName": "UNC_M_WR_CAS_RANK1.BANK1", 1957 "PerPkg": "1", 1958 "UMask": "0x1", 1959 "Unit": "iMC" 1960 }, 1961 { 1962 "BriefDescription": "WR_CAS Access to Rank 1; Bank 2", 1963 "Counter": "0,1,2,3", 1964 "EventCode": "0xB9", 1965 "EventName": "UNC_M_WR_CAS_RANK1.BANK2", 1966 "PerPkg": "1", 1967 "UMask": "0x2", 1968 "Unit": "iMC" 1969 }, 1970 { 1971 "BriefDescription": "WR_CAS Access to Rank 1; Bank 4", 1972 "Counter": "0,1,2,3", 1973 "EventCode": "0xB9", 1974 "EventName": "UNC_M_WR_CAS_RANK1.BANK4", 1975 "PerPkg": "1", 1976 "UMask": "0x4", 1977 "Unit": "iMC" 1978 }, 1979 { 1980 "BriefDescription": "WR_CAS Access to Rank 1; Bank 8", 1981 "Counter": "0,1,2,3", 1982 "EventCode": "0xB9", 1983 "EventName": "UNC_M_WR_CAS_RANK1.BANK8", 1984 "PerPkg": "1", 1985 "UMask": "0x8", 1986 "Unit": "iMC" 1987 }, 1988 { 1989 "BriefDescription": "WR_CAS Access to Rank 1; All Banks", 1990 "Counter": "0,1,2,3", 1991 "EventCode": "0xB9", 1992 "EventName": "UNC_M_WR_CAS_RANK1.ALLBANKS", 1993 "PerPkg": "1", 1994 "UMask": "0x10", 1995 "Unit": "iMC" 1996 }, 1997 { 1998 "BriefDescription": "WR_CAS Access to Rank 1; Bank 0", 1999 "Counter": "0,1,2,3", 2000 "EventCode": "0xB9", 2001 "EventName": "UNC_M_WR_CAS_RANK1.BANK0", 2002 "PerPkg": "1", 2003 "Unit": "iMC" 2004 }, 2005 { 2006 "BriefDescription": "WR_CAS Access to Rank 1; Bank 3", 2007 "Counter": "0,1,2,3", 2008 "EventCode": "0xB9", 2009 "EventName": "UNC_M_WR_CAS_RANK1.BANK3", 2010 "PerPkg": "1", 2011 "UMask": "0x3", 2012 "Unit": "iMC" 2013 }, 2014 { 2015 "BriefDescription": "WR_CAS Access to Rank 1; Bank 5", 2016 "Counter": "0,1,2,3", 2017 "EventCode": "0xB9", 2018 "EventName": "UNC_M_WR_CAS_RANK1.BANK5", 2019 "PerPkg": "1", 2020 "UMask": "0x5", 2021 "Unit": "iMC" 2022 }, 2023 { 2024 "BriefDescription": "WR_CAS Access to Rank 1; Bank 6", 2025 "Counter": "0,1,2,3", 2026 "EventCode": "0xB9", 2027 "EventName": "UNC_M_WR_CAS_RANK1.BANK6", 2028 "PerPkg": "1", 2029 "UMask": "0x6", 2030 "Unit": "iMC" 2031 }, 2032 { 2033 "BriefDescription": "WR_CAS Access to Rank 1; Bank 7", 2034 "Counter": "0,1,2,3", 2035 "EventCode": "0xB9", 2036 "EventName": "UNC_M_WR_CAS_RANK1.BANK7", 2037 "PerPkg": "1", 2038 "UMask": "0x7", 2039 "Unit": "iMC" 2040 }, 2041 { 2042 "BriefDescription": "WR_CAS Access to Rank 1; Bank 9", 2043 "Counter": "0,1,2,3", 2044 "EventCode": "0xB9", 2045 "EventName": "UNC_M_WR_CAS_RANK1.BANK9", 2046 "PerPkg": "1", 2047 "UMask": "0x9", 2048 "Unit": "iMC" 2049 }, 2050 { 2051 "BriefDescription": "WR_CAS Access to Rank 1; Bank 10", 2052 "Counter": "0,1,2,3", 2053 "EventCode": "0xB9", 2054 "EventName": "UNC_M_WR_CAS_RANK1.BANK10", 2055 "PerPkg": "1", 2056 "UMask": "0xA", 2057 "Unit": "iMC" 2058 }, 2059 { 2060 "BriefDescription": "WR_CAS Access to Rank 1; Bank 11", 2061 "Counter": "0,1,2,3", 2062 "EventCode": "0xB9", 2063 "EventName": "UNC_M_WR_CAS_RANK1.BANK11", 2064 "PerPkg": "1", 2065 "UMask": "0xB", 2066 "Unit": "iMC" 2067 }, 2068 { 2069 "BriefDescription": "WR_CAS Access to Rank 1; Bank 12", 2070 "Counter": "0,1,2,3", 2071 "EventCode": "0xB9", 2072 "EventName": "UNC_M_WR_CAS_RANK1.BANK12", 2073 "PerPkg": "1", 2074 "UMask": "0xC", 2075 "Unit": "iMC" 2076 }, 2077 { 2078 "BriefDescription": "WR_CAS Access to Rank 1; Bank 13", 2079 "Counter": "0,1,2,3", 2080 "EventCode": "0xB9", 2081 "EventName": "UNC_M_WR_CAS_RANK1.BANK13", 2082 "PerPkg": "1", 2083 "UMask": "0xD", 2084 "Unit": "iMC" 2085 }, 2086 { 2087 "BriefDescription": "WR_CAS Access to Rank 1; Bank 14", 2088 "Counter": "0,1,2,3", 2089 "EventCode": "0xB9", 2090 "EventName": "UNC_M_WR_CAS_RANK1.BANK14", 2091 "PerPkg": "1", 2092 "UMask": "0xE", 2093 "Unit": "iMC" 2094 }, 2095 { 2096 "BriefDescription": "WR_CAS Access to Rank 1; Bank 15", 2097 "Counter": "0,1,2,3", 2098 "EventCode": "0xB9", 2099 "EventName": "UNC_M_WR_CAS_RANK1.BANK15", 2100 "PerPkg": "1", 2101 "UMask": "0xF", 2102 "Unit": "iMC" 2103 }, 2104 { 2105 "BriefDescription": "WR_CAS Access to Rank 1; Bank Group 0 (Banks 0-3)", 2106 "Counter": "0,1,2,3", 2107 "EventCode": "0xB9", 2108 "EventName": "UNC_M_WR_CAS_RANK1.BANKG0", 2109 "PerPkg": "1", 2110 "UMask": "0x11", 2111 "Unit": "iMC" 2112 }, 2113 { 2114 "BriefDescription": "WR_CAS Access to Rank 1; Bank Group 1 (Banks 4-7)", 2115 "Counter": "0,1,2,3", 2116 "EventCode": "0xB9", 2117 "EventName": "UNC_M_WR_CAS_RANK1.BANKG1", 2118 "PerPkg": "1", 2119 "UMask": "0x12", 2120 "Unit": "iMC" 2121 }, 2122 { 2123 "BriefDescription": "WR_CAS Access to Rank 1; Bank Group 2 (Banks 8-11)", 2124 "Counter": "0,1,2,3", 2125 "EventCode": "0xB9", 2126 "EventName": "UNC_M_WR_CAS_RANK1.BANKG2", 2127 "PerPkg": "1", 2128 "UMask": "0x13", 2129 "Unit": "iMC" 2130 }, 2131 { 2132 "BriefDescription": "WR_CAS Access to Rank 1; Bank Group 3 (Banks 12-15)", 2133 "Counter": "0,1,2,3", 2134 "EventCode": "0xB9", 2135 "EventName": "UNC_M_WR_CAS_RANK1.BANKG3", 2136 "PerPkg": "1", 2137 "UMask": "0x14", 2138 "Unit": "iMC" 2139 }, 2140 { 2141 "BriefDescription": "WR_CAS Access to Rank 4; Bank 1", 2142 "Counter": "0,1,2,3", 2143 "EventCode": "0xBC", 2144 "EventName": "UNC_M_WR_CAS_RANK4.BANK1", 2145 "PerPkg": "1", 2146 "UMask": "0x1", 2147 "Unit": "iMC" 2148 }, 2149 { 2150 "BriefDescription": "WR_CAS Access to Rank 4; Bank 2", 2151 "Counter": "0,1,2,3", 2152 "EventCode": "0xBC", 2153 "EventName": "UNC_M_WR_CAS_RANK4.BANK2", 2154 "PerPkg": "1", 2155 "UMask": "0x2", 2156 "Unit": "iMC" 2157 }, 2158 { 2159 "BriefDescription": "WR_CAS Access to Rank 4; Bank 4", 2160 "Counter": "0,1,2,3", 2161 "EventCode": "0xBC", 2162 "EventName": "UNC_M_WR_CAS_RANK4.BANK4", 2163 "PerPkg": "1", 2164 "UMask": "0x4", 2165 "Unit": "iMC" 2166 }, 2167 { 2168 "BriefDescription": "WR_CAS Access to Rank 4; Bank 8", 2169 "Counter": "0,1,2,3", 2170 "EventCode": "0xBC", 2171 "EventName": "UNC_M_WR_CAS_RANK4.BANK8", 2172 "PerPkg": "1", 2173 "UMask": "0x8", 2174 "Unit": "iMC" 2175 }, 2176 { 2177 "BriefDescription": "WR_CAS Access to Rank 4; All Banks", 2178 "Counter": "0,1,2,3", 2179 "EventCode": "0xBC", 2180 "EventName": "UNC_M_WR_CAS_RANK4.ALLBANKS", 2181 "PerPkg": "1", 2182 "UMask": "0x10", 2183 "Unit": "iMC" 2184 }, 2185 { 2186 "BriefDescription": "WR_CAS Access to Rank 4; Bank 0", 2187 "Counter": "0,1,2,3", 2188 "EventCode": "0xBC", 2189 "EventName": "UNC_M_WR_CAS_RANK4.BANK0", 2190 "PerPkg": "1", 2191 "Unit": "iMC" 2192 }, 2193 { 2194 "BriefDescription": "WR_CAS Access to Rank 4; Bank 3", 2195 "Counter": "0,1,2,3", 2196 "EventCode": "0xBC", 2197 "EventName": "UNC_M_WR_CAS_RANK4.BANK3", 2198 "PerPkg": "1", 2199 "UMask": "0x3", 2200 "Unit": "iMC" 2201 }, 2202 { 2203 "BriefDescription": "WR_CAS Access to Rank 4; Bank 5", 2204 "Counter": "0,1,2,3", 2205 "EventCode": "0xBC", 2206 "EventName": "UNC_M_WR_CAS_RANK4.BANK5", 2207 "PerPkg": "1", 2208 "UMask": "0x5", 2209 "Unit": "iMC" 2210 }, 2211 { 2212 "BriefDescription": "WR_CAS Access to Rank 4; Bank 6", 2213 "Counter": "0,1,2,3", 2214 "EventCode": "0xBC", 2215 "EventName": "UNC_M_WR_CAS_RANK4.BANK6", 2216 "PerPkg": "1", 2217 "UMask": "0x6", 2218 "Unit": "iMC" 2219 }, 2220 { 2221 "BriefDescription": "WR_CAS Access to Rank 4; Bank 7", 2222 "Counter": "0,1,2,3", 2223 "EventCode": "0xBC", 2224 "EventName": "UNC_M_WR_CAS_RANK4.BANK7", 2225 "PerPkg": "1", 2226 "UMask": "0x7", 2227 "Unit": "iMC" 2228 }, 2229 { 2230 "BriefDescription": "WR_CAS Access to Rank 4; Bank 9", 2231 "Counter": "0,1,2,3", 2232 "EventCode": "0xBC", 2233 "EventName": "UNC_M_WR_CAS_RANK4.BANK9", 2234 "PerPkg": "1", 2235 "UMask": "0x9", 2236 "Unit": "iMC" 2237 }, 2238 { 2239 "BriefDescription": "WR_CAS Access to Rank 4; Bank 10", 2240 "Counter": "0,1,2,3", 2241 "EventCode": "0xBC", 2242 "EventName": "UNC_M_WR_CAS_RANK4.BANK10", 2243 "PerPkg": "1", 2244 "UMask": "0xA", 2245 "Unit": "iMC" 2246 }, 2247 { 2248 "BriefDescription": "WR_CAS Access to Rank 4; Bank 11", 2249 "Counter": "0,1,2,3", 2250 "EventCode": "0xBC", 2251 "EventName": "UNC_M_WR_CAS_RANK4.BANK11", 2252 "PerPkg": "1", 2253 "UMask": "0xB", 2254 "Unit": "iMC" 2255 }, 2256 { 2257 "BriefDescription": "WR_CAS Access to Rank 4; Bank 12", 2258 "Counter": "0,1,2,3", 2259 "EventCode": "0xBC", 2260 "EventName": "UNC_M_WR_CAS_RANK4.BANK12", 2261 "PerPkg": "1", 2262 "UMask": "0xC", 2263 "Unit": "iMC" 2264 }, 2265 { 2266 "BriefDescription": "WR_CAS Access to Rank 4; Bank 13", 2267 "Counter": "0,1,2,3", 2268 "EventCode": "0xBC", 2269 "EventName": "UNC_M_WR_CAS_RANK4.BANK13", 2270 "PerPkg": "1", 2271 "UMask": "0xD", 2272 "Unit": "iMC" 2273 }, 2274 { 2275 "BriefDescription": "WR_CAS Access to Rank 4; Bank 14", 2276 "Counter": "0,1,2,3", 2277 "EventCode": "0xBC", 2278 "EventName": "UNC_M_WR_CAS_RANK4.BANK14", 2279 "PerPkg": "1", 2280 "UMask": "0xE", 2281 "Unit": "iMC" 2282 }, 2283 { 2284 "BriefDescription": "WR_CAS Access to Rank 4; Bank 15", 2285 "Counter": "0,1,2,3", 2286 "EventCode": "0xBC", 2287 "EventName": "UNC_M_WR_CAS_RANK4.BANK15", 2288 "PerPkg": "1", 2289 "UMask": "0xF", 2290 "Unit": "iMC" 2291 }, 2292 { 2293 "BriefDescription": "WR_CAS Access to Rank 4; Bank Group 0 (Banks 0-3)", 2294 "Counter": "0,1,2,3", 2295 "EventCode": "0xBC", 2296 "EventName": "UNC_M_WR_CAS_RANK4.BANKG0", 2297 "PerPkg": "1", 2298 "UMask": "0x11", 2299 "Unit": "iMC" 2300 }, 2301 { 2302 "BriefDescription": "WR_CAS Access to Rank 4; Bank Group 1 (Banks 4-7)", 2303 "Counter": "0,1,2,3", 2304 "EventCode": "0xBC", 2305 "EventName": "UNC_M_WR_CAS_RANK4.BANKG1", 2306 "PerPkg": "1", 2307 "UMask": "0x12", 2308 "Unit": "iMC" 2309 }, 2310 { 2311 "BriefDescription": "WR_CAS Access to Rank 4; Bank Group 2 (Banks 8-11)", 2312 "Counter": "0,1,2,3", 2313 "EventCode": "0xBC", 2314 "EventName": "UNC_M_WR_CAS_RANK4.BANKG2", 2315 "PerPkg": "1", 2316 "UMask": "0x13", 2317 "Unit": "iMC" 2318 }, 2319 { 2320 "BriefDescription": "WR_CAS Access to Rank 4; Bank Group 3 (Banks 12-15)", 2321 "Counter": "0,1,2,3", 2322 "EventCode": "0xBC", 2323 "EventName": "UNC_M_WR_CAS_RANK4.BANKG3", 2324 "PerPkg": "1", 2325 "UMask": "0x14", 2326 "Unit": "iMC" 2327 }, 2328 { 2329 "BriefDescription": "WR_CAS Access to Rank 5; Bank 1", 2330 "Counter": "0,1,2,3", 2331 "EventCode": "0xBD", 2332 "EventName": "UNC_M_WR_CAS_RANK5.BANK1", 2333 "PerPkg": "1", 2334 "UMask": "0x1", 2335 "Unit": "iMC" 2336 }, 2337 { 2338 "BriefDescription": "WR_CAS Access to Rank 5; Bank 2", 2339 "Counter": "0,1,2,3", 2340 "EventCode": "0xBD", 2341 "EventName": "UNC_M_WR_CAS_RANK5.BANK2", 2342 "PerPkg": "1", 2343 "UMask": "0x2", 2344 "Unit": "iMC" 2345 }, 2346 { 2347 "BriefDescription": "WR_CAS Access to Rank 5; Bank 4", 2348 "Counter": "0,1,2,3", 2349 "EventCode": "0xBD", 2350 "EventName": "UNC_M_WR_CAS_RANK5.BANK4", 2351 "PerPkg": "1", 2352 "UMask": "0x4", 2353 "Unit": "iMC" 2354 }, 2355 { 2356 "BriefDescription": "WR_CAS Access to Rank 5; Bank 8", 2357 "Counter": "0,1,2,3", 2358 "EventCode": "0xBD", 2359 "EventName": "UNC_M_WR_CAS_RANK5.BANK8", 2360 "PerPkg": "1", 2361 "UMask": "0x8", 2362 "Unit": "iMC" 2363 }, 2364 { 2365 "BriefDescription": "WR_CAS Access to Rank 5; All Banks", 2366 "Counter": "0,1,2,3", 2367 "EventCode": "0xBD", 2368 "EventName": "UNC_M_WR_CAS_RANK5.ALLBANKS", 2369 "PerPkg": "1", 2370 "UMask": "0x10", 2371 "Unit": "iMC" 2372 }, 2373 { 2374 "BriefDescription": "WR_CAS Access to Rank 5; Bank 0", 2375 "Counter": "0,1,2,3", 2376 "EventCode": "0xBD", 2377 "EventName": "UNC_M_WR_CAS_RANK5.BANK0", 2378 "PerPkg": "1", 2379 "Unit": "iMC" 2380 }, 2381 { 2382 "BriefDescription": "WR_CAS Access to Rank 5; Bank 3", 2383 "Counter": "0,1,2,3", 2384 "EventCode": "0xBD", 2385 "EventName": "UNC_M_WR_CAS_RANK5.BANK3", 2386 "PerPkg": "1", 2387 "UMask": "0x3", 2388 "Unit": "iMC" 2389 }, 2390 { 2391 "BriefDescription": "WR_CAS Access to Rank 5; Bank 5", 2392 "Counter": "0,1,2,3", 2393 "EventCode": "0xBD", 2394 "EventName": "UNC_M_WR_CAS_RANK5.BANK5", 2395 "PerPkg": "1", 2396 "UMask": "0x5", 2397 "Unit": "iMC" 2398 }, 2399 { 2400 "BriefDescription": "WR_CAS Access to Rank 5; Bank 6", 2401 "Counter": "0,1,2,3", 2402 "EventCode": "0xBD", 2403 "EventName": "UNC_M_WR_CAS_RANK5.BANK6", 2404 "PerPkg": "1", 2405 "UMask": "0x6", 2406 "Unit": "iMC" 2407 }, 2408 { 2409 "BriefDescription": "WR_CAS Access to Rank 5; Bank 7", 2410 "Counter": "0,1,2,3", 2411 "EventCode": "0xBD", 2412 "EventName": "UNC_M_WR_CAS_RANK5.BANK7", 2413 "PerPkg": "1", 2414 "UMask": "0x7", 2415 "Unit": "iMC" 2416 }, 2417 { 2418 "BriefDescription": "WR_CAS Access to Rank 5; Bank 9", 2419 "Counter": "0,1,2,3", 2420 "EventCode": "0xBD", 2421 "EventName": "UNC_M_WR_CAS_RANK5.BANK9", 2422 "PerPkg": "1", 2423 "UMask": "0x9", 2424 "Unit": "iMC" 2425 }, 2426 { 2427 "BriefDescription": "WR_CAS Access to Rank 5; Bank 10", 2428 "Counter": "0,1,2,3", 2429 "EventCode": "0xBD", 2430 "EventName": "UNC_M_WR_CAS_RANK5.BANK10", 2431 "PerPkg": "1", 2432 "UMask": "0xA", 2433 "Unit": "iMC" 2434 }, 2435 { 2436 "BriefDescription": "WR_CAS Access to Rank 5; Bank 11", 2437 "Counter": "0,1,2,3", 2438 "EventCode": "0xBD", 2439 "EventName": "UNC_M_WR_CAS_RANK5.BANK11", 2440 "PerPkg": "1", 2441 "UMask": "0xB", 2442 "Unit": "iMC" 2443 }, 2444 { 2445 "BriefDescription": "WR_CAS Access to Rank 5; Bank 12", 2446 "Counter": "0,1,2,3", 2447 "EventCode": "0xBD", 2448 "EventName": "UNC_M_WR_CAS_RANK5.BANK12", 2449 "PerPkg": "1", 2450 "UMask": "0xC", 2451 "Unit": "iMC" 2452 }, 2453 { 2454 "BriefDescription": "WR_CAS Access to Rank 5; Bank 13", 2455 "Counter": "0,1,2,3", 2456 "EventCode": "0xBD", 2457 "EventName": "UNC_M_WR_CAS_RANK5.BANK13", 2458 "PerPkg": "1", 2459 "UMask": "0xD", 2460 "Unit": "iMC" 2461 }, 2462 { 2463 "BriefDescription": "WR_CAS Access to Rank 5; Bank 14", 2464 "Counter": "0,1,2,3", 2465 "EventCode": "0xBD", 2466 "EventName": "UNC_M_WR_CAS_RANK5.BANK14", 2467 "PerPkg": "1", 2468 "UMask": "0xE", 2469 "Unit": "iMC" 2470 }, 2471 { 2472 "BriefDescription": "WR_CAS Access to Rank 5; Bank 15", 2473 "Counter": "0,1,2,3", 2474 "EventCode": "0xBD", 2475 "EventName": "UNC_M_WR_CAS_RANK5.BANK15", 2476 "PerPkg": "1", 2477 "UMask": "0xF", 2478 "Unit": "iMC" 2479 }, 2480 { 2481 "BriefDescription": "WR_CAS Access to Rank 5; Bank Group 0 (Banks 0-3)", 2482 "Counter": "0,1,2,3", 2483 "EventCode": "0xBD", 2484 "EventName": "UNC_M_WR_CAS_RANK5.BANKG0", 2485 "PerPkg": "1", 2486 "UMask": "0x11", 2487 "Unit": "iMC" 2488 }, 2489 { 2490 "BriefDescription": "WR_CAS Access to Rank 5; Bank Group 1 (Banks 4-7)", 2491 "Counter": "0,1,2,3", 2492 "EventCode": "0xBD", 2493 "EventName": "UNC_M_WR_CAS_RANK5.BANKG1", 2494 "PerPkg": "1", 2495 "UMask": "0x12", 2496 "Unit": "iMC" 2497 }, 2498 { 2499 "BriefDescription": "WR_CAS Access to Rank 5; Bank Group 2 (Banks 8-11)", 2500 "Counter": "0,1,2,3", 2501 "EventCode": "0xBD", 2502 "EventName": "UNC_M_WR_CAS_RANK5.BANKG2", 2503 "PerPkg": "1", 2504 "UMask": "0x13", 2505 "Unit": "iMC" 2506 }, 2507 { 2508 "BriefDescription": "WR_CAS Access to Rank 5; Bank Group 3 (Banks 12-15)", 2509 "Counter": "0,1,2,3", 2510 "EventCode": "0xBD", 2511 "EventName": "UNC_M_WR_CAS_RANK5.BANKG3", 2512 "PerPkg": "1", 2513 "UMask": "0x14", 2514 "Unit": "iMC" 2515 }, 2516 { 2517 "BriefDescription": "WR_CAS Access to Rank 6; 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