1[ 2 { 3 "BriefDescription": "Number of times HLE abort was triggered (PEBS)", 4 "Counter": "0,1,2,3", 5 "CounterHTOff": "0,1,2,3,4,5,6,7", 6 "EventCode": "0xc8", 7 "EventName": "HLE_RETIRED.ABORTED", 8 "PEBS": "1", 9 "PublicDescription": "Number of times HLE abort was triggered (PEBS).", 10 "SampleAfterValue": "2000003", 11 "UMask": "0x4" 12 }, 13 { 14 "BriefDescription": "Number of times an HLE execution aborted due to various memory events (e.g., read/write capacity and conflicts).", 15 "Counter": "0,1,2,3", 16 "CounterHTOff": "0,1,2,3,4,5,6,7", 17 "EventCode": "0xc8", 18 "EventName": "HLE_RETIRED.ABORTED_MISC1", 19 "PublicDescription": "Number of times an HLE abort was attributed to a Memory condition (See TSX_Memory event for additional details).", 20 "SampleAfterValue": "2000003", 21 "UMask": "0x8" 22 }, 23 { 24 "BriefDescription": "Number of times an HLE execution aborted due to uncommon conditions", 25 "Counter": "0,1,2,3", 26 "CounterHTOff": "0,1,2,3,4,5,6,7", 27 "EventCode": "0xc8", 28 "EventName": "HLE_RETIRED.ABORTED_MISC2", 29 "PublicDescription": "Number of times the TSX watchdog signaled an HLE abort.", 30 "SampleAfterValue": "2000003", 31 "UMask": "0x10" 32 }, 33 { 34 "BriefDescription": "Number of times an HLE execution aborted due to HLE-unfriendly instructions", 35 "Counter": "0,1,2,3", 36 "CounterHTOff": "0,1,2,3,4,5,6,7", 37 "EventCode": "0xc8", 38 "EventName": "HLE_RETIRED.ABORTED_MISC3", 39 "PublicDescription": "Number of times a disallowed operation caused an HLE abort.", 40 "SampleAfterValue": "2000003", 41 "UMask": "0x20" 42 }, 43 { 44 "BriefDescription": "Number of times an HLE execution aborted due to incompatible memory type", 45 "Counter": "0,1,2,3", 46 "CounterHTOff": "0,1,2,3,4,5,6,7", 47 "EventCode": "0xc8", 48 "EventName": "HLE_RETIRED.ABORTED_MISC4", 49 "PublicDescription": "Number of times HLE caused a fault.", 50 "SampleAfterValue": "2000003", 51 "UMask": "0x40" 52 }, 53 { 54 "BriefDescription": "Number of times an HLE execution aborted due to none of the previous 4 categories (e.g. interrupts)", 55 "Counter": "0,1,2,3", 56 "CounterHTOff": "0,1,2,3,4,5,6,7", 57 "EventCode": "0xc8", 58 "EventName": "HLE_RETIRED.ABORTED_MISC5", 59 "PublicDescription": "Number of times HLE aborted and was not due to the abort conditions in subevents 3-6.", 60 "SampleAfterValue": "2000003", 61 "UMask": "0x80" 62 }, 63 { 64 "BriefDescription": "Number of times HLE commit succeeded", 65 "Counter": "0,1,2,3", 66 "CounterHTOff": "0,1,2,3,4,5,6,7", 67 "EventCode": "0xc8", 68 "EventName": "HLE_RETIRED.COMMIT", 69 "PublicDescription": "Number of times HLE commit succeeded.", 70 "SampleAfterValue": "2000003", 71 "UMask": "0x2" 72 }, 73 { 74 "BriefDescription": "Number of times we entered an HLE region; does not count nested transactions", 75 "Counter": "0,1,2,3", 76 "CounterHTOff": "0,1,2,3,4,5,6,7", 77 "EventCode": "0xc8", 78 "EventName": "HLE_RETIRED.START", 79 "PublicDescription": "Number of times we entered an HLE region\n does not count nested transactions.", 80 "SampleAfterValue": "2000003", 81 "UMask": "0x1" 82 }, 83 { 84 "BriefDescription": "Counts the number of machine clears due to memory order conflicts.", 85 "Counter": "0,1,2,3", 86 "CounterHTOff": "0,1,2,3,4,5,6,7", 87 "EventCode": "0xC3", 88 "EventName": "MACHINE_CLEARS.MEMORY_ORDERING", 89 "PublicDescription": "This event counts the number of memory ordering Machine Clears detected. Memory Ordering Machine Clears can result from one of the following:\n1. memory disambiguation,\n2. external snoop, or\n3. cross SMT-HW-thread snoop (stores) hitting load buffer.", 90 "SampleAfterValue": "100003", 91 "UMask": "0x2" 92 }, 93 { 94 "BriefDescription": "Loads with latency value being above 128", 95 "Counter": "3", 96 "CounterHTOff": "3", 97 "Errata": "BDM100, BDM35", 98 "EventCode": "0xCD", 99 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_128", 100 "MSRIndex": "0x3F6", 101 "MSRValue": "0x80", 102 "PEBS": "2", 103 "PublicDescription": "This event counts loads with latency value being above 128.", 104 "SampleAfterValue": "1009", 105 "TakenAlone": "1", 106 "UMask": "0x1" 107 }, 108 { 109 "BriefDescription": "Loads with latency value being above 16", 110 "Counter": "3", 111 "CounterHTOff": "3", 112 "Errata": "BDM100, BDM35", 113 "EventCode": "0xCD", 114 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_16", 115 "MSRIndex": "0x3F6", 116 "MSRValue": "0x10", 117 "PEBS": "2", 118 "PublicDescription": "This event counts loads with latency value being above 16.", 119 "SampleAfterValue": "20011", 120 "TakenAlone": "1", 121 "UMask": "0x1" 122 }, 123 { 124 "BriefDescription": "Loads with latency value being above 256", 125 "Counter": "3", 126 "CounterHTOff": "3", 127 "Errata": "BDM100, BDM35", 128 "EventCode": "0xCD", 129 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_256", 130 "MSRIndex": "0x3F6", 131 "MSRValue": "0x100", 132 "PEBS": "2", 133 "PublicDescription": "This event counts loads with latency value being above 256.", 134 "SampleAfterValue": "503", 135 "TakenAlone": "1", 136 "UMask": "0x1" 137 }, 138 { 139 "BriefDescription": "Loads with latency value being above 32", 140 "Counter": "3", 141 "CounterHTOff": "3", 142 "Errata": "BDM100, BDM35", 143 "EventCode": "0xCD", 144 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_32", 145 "MSRIndex": "0x3F6", 146 "MSRValue": "0x20", 147 "PEBS": "2", 148 "PublicDescription": "This event counts loads with latency value being above 32.", 149 "SampleAfterValue": "100007", 150 "TakenAlone": "1", 151 "UMask": "0x1" 152 }, 153 { 154 "BriefDescription": "Loads with latency value being above 4", 155 "Counter": "3", 156 "CounterHTOff": "3", 157 "Errata": "BDM100, BDM35", 158 "EventCode": "0xCD", 159 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_4", 160 "MSRIndex": "0x3F6", 161 "MSRValue": "0x4", 162 "PEBS": "2", 163 "PublicDescription": "This event counts loads with latency value being above four.", 164 "SampleAfterValue": "100003", 165 "TakenAlone": "1", 166 "UMask": "0x1" 167 }, 168 { 169 "BriefDescription": "Loads with latency value being above 512", 170 "Counter": "3", 171 "CounterHTOff": "3", 172 "Errata": "BDM100, BDM35", 173 "EventCode": "0xCD", 174 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_512", 175 "MSRIndex": "0x3F6", 176 "MSRValue": "0x200", 177 "PEBS": "2", 178 "PublicDescription": "This event counts loads with latency value being above 512.", 179 "SampleAfterValue": "101", 180 "TakenAlone": "1", 181 "UMask": "0x1" 182 }, 183 { 184 "BriefDescription": "Loads with latency value being above 64", 185 "Counter": "3", 186 "CounterHTOff": "3", 187 "Errata": "BDM100, BDM35", 188 "EventCode": "0xCD", 189 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_64", 190 "MSRIndex": "0x3F6", 191 "MSRValue": "0x40", 192 "PEBS": "2", 193 "PublicDescription": "This event counts loads with latency value being above 64.", 194 "SampleAfterValue": "2003", 195 "TakenAlone": "1", 196 "UMask": "0x1" 197 }, 198 { 199 "BriefDescription": "Loads with latency value being above 8", 200 "Counter": "3", 201 "CounterHTOff": "3", 202 "Errata": "BDM100, BDM35", 203 "EventCode": "0xCD", 204 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_8", 205 "MSRIndex": "0x3F6", 206 "MSRValue": "0x8", 207 "PEBS": "2", 208 "PublicDescription": "This event counts loads with latency value being above eight.", 209 "SampleAfterValue": "50021", 210 "TakenAlone": "1", 211 "UMask": "0x1" 212 }, 213 { 214 "BriefDescription": "Speculative cache line split load uops dispatched to L1 cache", 215 "Counter": "0,1,2,3", 216 "CounterHTOff": "0,1,2,3,4,5,6,7", 217 "EventCode": "0x05", 218 "EventName": "MISALIGN_MEM_REF.LOADS", 219 "PublicDescription": "This event counts speculative cache-line split load uops dispatched to the L1 cache.", 220 "SampleAfterValue": "2000003", 221 "UMask": "0x1" 222 }, 223 { 224 "BriefDescription": "Speculative cache line split STA uops dispatched to L1 cache", 225 "Counter": "0,1,2,3", 226 "CounterHTOff": "0,1,2,3,4,5,6,7", 227 "EventCode": "0x05", 228 "EventName": "MISALIGN_MEM_REF.STORES", 229 "PublicDescription": "This event counts speculative cache line split store-address (STA) uops dispatched to the L1 cache.", 230 "SampleAfterValue": "2000003", 231 "UMask": "0x2" 232 }, 233 { 234 "BriefDescription": "Number of times RTM abort was triggered (PEBS)", 235 "Counter": "0,1,2,3", 236 "CounterHTOff": "0,1,2,3", 237 "EventCode": "0xc9", 238 "EventName": "RTM_RETIRED.ABORTED", 239 "PEBS": "1", 240 "PublicDescription": "Number of times RTM abort was triggered (PEBS).", 241 "SampleAfterValue": "2000003", 242 "UMask": "0x4" 243 }, 244 { 245 "BriefDescription": "Number of times an RTM execution aborted due to various memory events (e.g. read/write capacity and conflicts)", 246 "Counter": "0,1,2,3", 247 "CounterHTOff": "0,1,2,3", 248 "EventCode": "0xc9", 249 "EventName": "RTM_RETIRED.ABORTED_MISC1", 250 "PublicDescription": "Number of times an RTM abort was attributed to a Memory condition (See TSX_Memory event for additional details).", 251 "SampleAfterValue": "2000003", 252 "UMask": "0x8" 253 }, 254 { 255 "BriefDescription": "Number of times an RTM execution aborted due to various memory events (e.g., read/write capacity and conflicts).", 256 "Counter": "0,1,2,3", 257 "CounterHTOff": "0,1,2,3", 258 "EventCode": "0xc9", 259 "EventName": "RTM_RETIRED.ABORTED_MISC2", 260 "PublicDescription": "Number of times the TSX watchdog signaled an RTM abort.", 261 "SampleAfterValue": "2000003", 262 "UMask": "0x10" 263 }, 264 { 265 "BriefDescription": "Number of times an RTM execution aborted due to HLE-unfriendly instructions", 266 "Counter": "0,1,2,3", 267 "CounterHTOff": "0,1,2,3", 268 "EventCode": "0xc9", 269 "EventName": "RTM_RETIRED.ABORTED_MISC3", 270 "PublicDescription": "Number of times a disallowed operation caused an RTM abort.", 271 "SampleAfterValue": "2000003", 272 "UMask": "0x20" 273 }, 274 { 275 "BriefDescription": "Number of times an RTM execution aborted due to incompatible memory type", 276 "Counter": "0,1,2,3", 277 "CounterHTOff": "0,1,2,3", 278 "EventCode": "0xc9", 279 "EventName": "RTM_RETIRED.ABORTED_MISC4", 280 "PublicDescription": "Number of times a RTM caused a fault.", 281 "SampleAfterValue": "2000003", 282 "UMask": "0x40" 283 }, 284 { 285 "BriefDescription": "Number of times an RTM execution aborted due to none of the previous 4 categories (e.g. interrupt)", 286 "Counter": "0,1,2,3", 287 "CounterHTOff": "0,1,2,3", 288 "EventCode": "0xc9", 289 "EventName": "RTM_RETIRED.ABORTED_MISC5", 290 "PublicDescription": "Number of times RTM aborted and was not due to the abort conditions in subevents 3-6.", 291 "SampleAfterValue": "2000003", 292 "UMask": "0x80" 293 }, 294 { 295 "BriefDescription": "Number of times RTM commit succeeded", 296 "Counter": "0,1,2,3", 297 "CounterHTOff": "0,1,2,3", 298 "EventCode": "0xc9", 299 "EventName": "RTM_RETIRED.COMMIT", 300 "PublicDescription": "Number of times RTM commit succeeded.", 301 "SampleAfterValue": "2000003", 302 "UMask": "0x2" 303 }, 304 { 305 "BriefDescription": "Number of times we entered an RTM region; does not count nested transactions", 306 "Counter": "0,1,2,3", 307 "CounterHTOff": "0,1,2,3", 308 "EventCode": "0xc9", 309 "EventName": "RTM_RETIRED.START", 310 "PublicDescription": "Number of times we entered an RTM region\n does not count nested transactions.", 311 "SampleAfterValue": "2000003", 312 "UMask": "0x1" 313 }, 314 { 315 "BriefDescription": "Counts the number of times a class of instructions that may cause a transactional abort was executed. Since this is the count of execution, it may not always cause a transactional abort.", 316 "Counter": "0,1,2,3", 317 "CounterHTOff": "0,1,2,3,4,5,6,7", 318 "EventCode": "0x5d", 319 "EventName": "TX_EXEC.MISC1", 320 "SampleAfterValue": "2000003", 321 "UMask": "0x1" 322 }, 323 { 324 "BriefDescription": "Counts the number of times a class of instructions (e.g., vzeroupper) that may cause a transactional abort was executed inside a transactional region", 325 "Counter": "0,1,2,3", 326 "CounterHTOff": "0,1,2,3,4,5,6,7", 327 "EventCode": "0x5d", 328 "EventName": "TX_EXEC.MISC2", 329 "PublicDescription": "Unfriendly TSX abort triggered by a vzeroupper instruction.", 330 "SampleAfterValue": "2000003", 331 "UMask": "0x2" 332 }, 333 { 334 "BriefDescription": "Counts the number of times an instruction execution caused the transactional nest count supported to be exceeded", 335 "Counter": "0,1,2,3", 336 "CounterHTOff": "0,1,2,3,4,5,6,7", 337 "EventCode": "0x5d", 338 "EventName": "TX_EXEC.MISC3", 339 "PublicDescription": "Unfriendly TSX abort triggered by a nest count that is too deep.", 340 "SampleAfterValue": "2000003", 341 "UMask": "0x4" 342 }, 343 { 344 "BriefDescription": "Counts the number of times a XBEGIN instruction was executed inside an HLE transactional region.", 345 "Counter": "0,1,2,3", 346 "CounterHTOff": "0,1,2,3,4,5,6,7", 347 "EventCode": "0x5d", 348 "EventName": "TX_EXEC.MISC4", 349 "PublicDescription": "RTM region detected inside HLE.", 350 "SampleAfterValue": "2000003", 351 "UMask": "0x8" 352 }, 353 { 354 "BriefDescription": "Counts the number of times an HLE XACQUIRE instruction was executed inside an RTM transactional region.", 355 "Counter": "0,1,2,3", 356 "CounterHTOff": "0,1,2,3,4,5,6,7", 357 "EventCode": "0x5d", 358 "EventName": "TX_EXEC.MISC5", 359 "SampleAfterValue": "2000003", 360 "UMask": "0x10" 361 }, 362 { 363 "BriefDescription": "Number of times a TSX Abort was triggered due to an evicted line caused by a transaction overflow", 364 "Counter": "0,1,2,3", 365 "CounterHTOff": "0,1,2,3,4,5,6,7", 366 "EventCode": "0x54", 367 "EventName": "TX_MEM.ABORT_CAPACITY_WRITE", 368 "PublicDescription": "Number of times a TSX Abort was triggered due to an evicted line caused by a transaction overflow.", 369 "SampleAfterValue": "2000003", 370 "UMask": "0x2" 371 }, 372 { 373 "BriefDescription": "Number of times a TSX line had a cache conflict", 374 "Counter": "0,1,2,3", 375 "CounterHTOff": "0,1,2,3,4,5,6,7", 376 "EventCode": "0x54", 377 "EventName": "TX_MEM.ABORT_CONFLICT", 378 "PublicDescription": "Number of times a TSX line had a cache conflict.", 379 "SampleAfterValue": "2000003", 380 "UMask": "0x1" 381 }, 382 { 383 "BriefDescription": "Number of times a TSX Abort was triggered due to release/commit but data and address mismatch", 384 "Counter": "0,1,2,3", 385 "CounterHTOff": "0,1,2,3,4,5,6,7", 386 "EventCode": "0x54", 387 "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_MISMATCH", 388 "PublicDescription": "Number of times a TSX Abort was triggered due to release/commit but data and address mismatch.", 389 "SampleAfterValue": "2000003", 390 "UMask": "0x10" 391 }, 392 { 393 "BriefDescription": "Number of times a TSX Abort was triggered due to commit but Lock Buffer not empty", 394 "Counter": "0,1,2,3", 395 "CounterHTOff": "0,1,2,3,4,5,6,7", 396 "EventCode": "0x54", 397 "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_NOT_EMPTY", 398 "PublicDescription": "Number of times a TSX Abort was triggered due to commit but Lock Buffer not empty.", 399 "SampleAfterValue": "2000003", 400 "UMask": "0x8" 401 }, 402 { 403 "BriefDescription": "Number of times a TSX Abort was triggered due to attempting an unsupported alignment from Lock Buffer", 404 "Counter": "0,1,2,3", 405 "CounterHTOff": "0,1,2,3,4,5,6,7", 406 "EventCode": "0x54", 407 "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_UNSUPPORTED_ALIGNMENT", 408 "PublicDescription": "Number of times a TSX Abort was triggered due to attempting an unsupported alignment from Lock Buffer.", 409 "SampleAfterValue": "2000003", 410 "UMask": "0x20" 411 }, 412 { 413 "BriefDescription": "Number of times a TSX Abort was triggered due to a non-release/commit store to lock", 414 "Counter": "0,1,2,3", 415 "CounterHTOff": "0,1,2,3,4,5,6,7", 416 "EventCode": "0x54", 417 "EventName": "TX_MEM.ABORT_HLE_STORE_TO_ELIDED_LOCK", 418 "PublicDescription": "Number of times a TSX Abort was triggered due to a non-release/commit store to lock.", 419 "SampleAfterValue": "2000003", 420 "UMask": "0x4" 421 }, 422 { 423 "BriefDescription": "Number of times we could not allocate Lock Buffer", 424 "Counter": "0,1,2,3", 425 "CounterHTOff": "0,1,2,3,4,5,6,7", 426 "EventCode": "0x54", 427 "EventName": "TX_MEM.HLE_ELISION_BUFFER_FULL", 428 "PublicDescription": "Number of times we could not allocate Lock Buffer.", 429 "SampleAfterValue": "2000003", 430 "UMask": "0x40" 431 } 432] 433