1[
2    {
3        "BriefDescription": "Number of times HLE abort was triggered (PEBS)",
4        "EventCode": "0xc8",
5        "EventName": "HLE_RETIRED.ABORTED",
6        "PEBS": "1",
7        "PublicDescription": "Number of times HLE abort was triggered (PEBS).",
8        "SampleAfterValue": "2000003",
9        "UMask": "0x4"
10    },
11    {
12        "BriefDescription": "Number of times an HLE execution aborted due to various memory events (e.g., read/write capacity and conflicts).",
13        "EventCode": "0xc8",
14        "EventName": "HLE_RETIRED.ABORTED_MISC1",
15        "PublicDescription": "Number of times an HLE abort was attributed to a Memory condition (See TSX_Memory event for additional details).",
16        "SampleAfterValue": "2000003",
17        "UMask": "0x8"
18    },
19    {
20        "BriefDescription": "Number of times an HLE execution aborted due to uncommon conditions",
21        "EventCode": "0xc8",
22        "EventName": "HLE_RETIRED.ABORTED_MISC2",
23        "PublicDescription": "Number of times the TSX watchdog signaled an HLE abort.",
24        "SampleAfterValue": "2000003",
25        "UMask": "0x10"
26    },
27    {
28        "BriefDescription": "Number of times an HLE execution aborted due to HLE-unfriendly instructions",
29        "EventCode": "0xc8",
30        "EventName": "HLE_RETIRED.ABORTED_MISC3",
31        "PublicDescription": "Number of times a disallowed operation caused an HLE abort.",
32        "SampleAfterValue": "2000003",
33        "UMask": "0x20"
34    },
35    {
36        "BriefDescription": "Number of times an HLE execution aborted due to incompatible memory type",
37        "EventCode": "0xc8",
38        "EventName": "HLE_RETIRED.ABORTED_MISC4",
39        "PublicDescription": "Number of times HLE caused a fault.",
40        "SampleAfterValue": "2000003",
41        "UMask": "0x40"
42    },
43    {
44        "BriefDescription": "Number of times an HLE execution aborted due to none of the previous 4 categories (e.g. interrupts)",
45        "EventCode": "0xc8",
46        "EventName": "HLE_RETIRED.ABORTED_MISC5",
47        "PublicDescription": "Number of times HLE aborted and was not due to the abort conditions in subevents 3-6.",
48        "SampleAfterValue": "2000003",
49        "UMask": "0x80"
50    },
51    {
52        "BriefDescription": "Number of times HLE commit succeeded",
53        "EventCode": "0xc8",
54        "EventName": "HLE_RETIRED.COMMIT",
55        "PublicDescription": "Number of times HLE commit succeeded.",
56        "SampleAfterValue": "2000003",
57        "UMask": "0x2"
58    },
59    {
60        "BriefDescription": "Number of times we entered an HLE region; does not count nested transactions",
61        "EventCode": "0xc8",
62        "EventName": "HLE_RETIRED.START",
63        "PublicDescription": "Number of times we entered an HLE region\n does not count nested transactions.",
64        "SampleAfterValue": "2000003",
65        "UMask": "0x1"
66    },
67    {
68        "BriefDescription": "Counts the number of machine clears due to memory order conflicts.",
69        "EventCode": "0xC3",
70        "EventName": "MACHINE_CLEARS.MEMORY_ORDERING",
71        "PublicDescription": "This event counts the number of memory ordering Machine Clears detected. Memory Ordering Machine Clears can result from one of the following:\n1. memory disambiguation,\n2. external snoop, or\n3. cross SMT-HW-thread snoop (stores) hitting load buffer.",
72        "SampleAfterValue": "100003",
73        "UMask": "0x2"
74    },
75    {
76        "BriefDescription": "Loads with latency value being above 128",
77        "Errata": "BDM100, BDM35",
78        "EventCode": "0xCD",
79        "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_128",
80        "MSRIndex": "0x3F6",
81        "MSRValue": "0x80",
82        "PEBS": "2",
83        "PublicDescription": "This event counts loads with latency value being above 128.",
84        "SampleAfterValue": "1009",
85        "UMask": "0x1"
86    },
87    {
88        "BriefDescription": "Loads with latency value being above 16",
89        "Errata": "BDM100, BDM35",
90        "EventCode": "0xCD",
91        "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_16",
92        "MSRIndex": "0x3F6",
93        "MSRValue": "0x10",
94        "PEBS": "2",
95        "PublicDescription": "This event counts loads with latency value being above 16.",
96        "SampleAfterValue": "20011",
97        "UMask": "0x1"
98    },
99    {
100        "BriefDescription": "Loads with latency value being above 256",
101        "Errata": "BDM100, BDM35",
102        "EventCode": "0xCD",
103        "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_256",
104        "MSRIndex": "0x3F6",
105        "MSRValue": "0x100",
106        "PEBS": "2",
107        "PublicDescription": "This event counts loads with latency value being above 256.",
108        "SampleAfterValue": "503",
109        "UMask": "0x1"
110    },
111    {
112        "BriefDescription": "Loads with latency value being above 32",
113        "Errata": "BDM100, BDM35",
114        "EventCode": "0xCD",
115        "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_32",
116        "MSRIndex": "0x3F6",
117        "MSRValue": "0x20",
118        "PEBS": "2",
119        "PublicDescription": "This event counts loads with latency value being above 32.",
120        "SampleAfterValue": "100007",
121        "UMask": "0x1"
122    },
123    {
124        "BriefDescription": "Loads with latency value being above 4",
125        "Errata": "BDM100, BDM35",
126        "EventCode": "0xCD",
127        "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_4",
128        "MSRIndex": "0x3F6",
129        "MSRValue": "0x4",
130        "PEBS": "2",
131        "PublicDescription": "This event counts loads with latency value being above four.",
132        "SampleAfterValue": "100003",
133        "UMask": "0x1"
134    },
135    {
136        "BriefDescription": "Loads with latency value being above 512",
137        "Errata": "BDM100, BDM35",
138        "EventCode": "0xCD",
139        "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_512",
140        "MSRIndex": "0x3F6",
141        "MSRValue": "0x200",
142        "PEBS": "2",
143        "PublicDescription": "This event counts loads with latency value being above 512.",
144        "SampleAfterValue": "101",
145        "UMask": "0x1"
146    },
147    {
148        "BriefDescription": "Loads with latency value being above 64",
149        "Errata": "BDM100, BDM35",
150        "EventCode": "0xCD",
151        "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_64",
152        "MSRIndex": "0x3F6",
153        "MSRValue": "0x40",
154        "PEBS": "2",
155        "PublicDescription": "This event counts loads with latency value being above 64.",
156        "SampleAfterValue": "2003",
157        "UMask": "0x1"
158    },
159    {
160        "BriefDescription": "Loads with latency value being above 8",
161        "Errata": "BDM100, BDM35",
162        "EventCode": "0xCD",
163        "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_8",
164        "MSRIndex": "0x3F6",
165        "MSRValue": "0x8",
166        "PEBS": "2",
167        "PublicDescription": "This event counts loads with latency value being above eight.",
168        "SampleAfterValue": "50021",
169        "UMask": "0x1"
170    },
171    {
172        "BriefDescription": "Speculative cache line split load uops dispatched to L1 cache",
173        "EventCode": "0x05",
174        "EventName": "MISALIGN_MEM_REF.LOADS",
175        "PublicDescription": "This event counts speculative cache-line split load uops dispatched to the L1 cache.",
176        "SampleAfterValue": "2000003",
177        "UMask": "0x1"
178    },
179    {
180        "BriefDescription": "Speculative cache line split STA uops dispatched to L1 cache",
181        "EventCode": "0x05",
182        "EventName": "MISALIGN_MEM_REF.STORES",
183        "PublicDescription": "This event counts speculative cache line split store-address (STA) uops dispatched to the L1 cache.",
184        "SampleAfterValue": "2000003",
185        "UMask": "0x2"
186    },
187    {
188        "BriefDescription": "Number of times RTM abort was triggered (PEBS)",
189        "EventCode": "0xc9",
190        "EventName": "RTM_RETIRED.ABORTED",
191        "PEBS": "1",
192        "PublicDescription": "Number of times RTM abort was triggered (PEBS).",
193        "SampleAfterValue": "2000003",
194        "UMask": "0x4"
195    },
196    {
197        "BriefDescription": "Number of times an RTM execution aborted due to various memory events (e.g. read/write capacity and conflicts)",
198        "EventCode": "0xc9",
199        "EventName": "RTM_RETIRED.ABORTED_MISC1",
200        "PublicDescription": "Number of times an RTM abort was attributed to a Memory condition (See TSX_Memory event for additional details).",
201        "SampleAfterValue": "2000003",
202        "UMask": "0x8"
203    },
204    {
205        "BriefDescription": "Number of times an RTM execution aborted due to various memory events (e.g., read/write capacity and conflicts).",
206        "EventCode": "0xc9",
207        "EventName": "RTM_RETIRED.ABORTED_MISC2",
208        "PublicDescription": "Number of times the TSX watchdog signaled an RTM abort.",
209        "SampleAfterValue": "2000003",
210        "UMask": "0x10"
211    },
212    {
213        "BriefDescription": "Number of times an RTM execution aborted due to HLE-unfriendly instructions",
214        "EventCode": "0xc9",
215        "EventName": "RTM_RETIRED.ABORTED_MISC3",
216        "PublicDescription": "Number of times a disallowed operation caused an RTM abort.",
217        "SampleAfterValue": "2000003",
218        "UMask": "0x20"
219    },
220    {
221        "BriefDescription": "Number of times an RTM execution aborted due to incompatible memory type",
222        "EventCode": "0xc9",
223        "EventName": "RTM_RETIRED.ABORTED_MISC4",
224        "PublicDescription": "Number of times a RTM caused a fault.",
225        "SampleAfterValue": "2000003",
226        "UMask": "0x40"
227    },
228    {
229        "BriefDescription": "Number of times an RTM execution aborted due to none of the previous 4 categories (e.g. interrupt)",
230        "EventCode": "0xc9",
231        "EventName": "RTM_RETIRED.ABORTED_MISC5",
232        "PublicDescription": "Number of times RTM aborted and was not due to the abort conditions in subevents 3-6.",
233        "SampleAfterValue": "2000003",
234        "UMask": "0x80"
235    },
236    {
237        "BriefDescription": "Number of times RTM commit succeeded",
238        "EventCode": "0xc9",
239        "EventName": "RTM_RETIRED.COMMIT",
240        "PublicDescription": "Number of times RTM commit succeeded.",
241        "SampleAfterValue": "2000003",
242        "UMask": "0x2"
243    },
244    {
245        "BriefDescription": "Number of times we entered an RTM region; does not count nested transactions",
246        "EventCode": "0xc9",
247        "EventName": "RTM_RETIRED.START",
248        "PublicDescription": "Number of times we entered an RTM region\n does not count nested transactions.",
249        "SampleAfterValue": "2000003",
250        "UMask": "0x1"
251    },
252    {
253        "BriefDescription": "Counts the number of times a class of instructions that may cause a transactional abort was executed. Since this is the count of execution, it may not always cause a transactional abort.",
254        "EventCode": "0x5d",
255        "EventName": "TX_EXEC.MISC1",
256        "SampleAfterValue": "2000003",
257        "UMask": "0x1"
258    },
259    {
260        "BriefDescription": "Counts the number of times a class of instructions (e.g., vzeroupper) that may cause a transactional abort was executed inside a transactional region",
261        "EventCode": "0x5d",
262        "EventName": "TX_EXEC.MISC2",
263        "PublicDescription": "Unfriendly TSX abort triggered by  a vzeroupper instruction.",
264        "SampleAfterValue": "2000003",
265        "UMask": "0x2"
266    },
267    {
268        "BriefDescription": "Counts the number of times an instruction execution caused the transactional nest count supported to be exceeded",
269        "EventCode": "0x5d",
270        "EventName": "TX_EXEC.MISC3",
271        "PublicDescription": "Unfriendly TSX abort triggered by a nest count that is too deep.",
272        "SampleAfterValue": "2000003",
273        "UMask": "0x4"
274    },
275    {
276        "BriefDescription": "Counts the number of times a XBEGIN instruction was executed inside an HLE transactional region.",
277        "EventCode": "0x5d",
278        "EventName": "TX_EXEC.MISC4",
279        "PublicDescription": "RTM region detected inside HLE.",
280        "SampleAfterValue": "2000003",
281        "UMask": "0x8"
282    },
283    {
284        "BriefDescription": "Counts the number of times an HLE XACQUIRE instruction was executed inside an RTM transactional region.",
285        "EventCode": "0x5d",
286        "EventName": "TX_EXEC.MISC5",
287        "SampleAfterValue": "2000003",
288        "UMask": "0x10"
289    },
290    {
291        "BriefDescription": "Number of times a TSX Abort was triggered due to an evicted line caused by a transaction overflow",
292        "EventCode": "0x54",
293        "EventName": "TX_MEM.ABORT_CAPACITY_WRITE",
294        "PublicDescription": "Number of times a TSX Abort was triggered due to an evicted line caused by a transaction overflow.",
295        "SampleAfterValue": "2000003",
296        "UMask": "0x2"
297    },
298    {
299        "BriefDescription": "Number of times a TSX line had a cache conflict",
300        "EventCode": "0x54",
301        "EventName": "TX_MEM.ABORT_CONFLICT",
302        "PublicDescription": "Number of times a TSX line had a cache conflict.",
303        "SampleAfterValue": "2000003",
304        "UMask": "0x1"
305    },
306    {
307        "BriefDescription": "Number of times a TSX Abort was triggered due to release/commit but data and address mismatch",
308        "EventCode": "0x54",
309        "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_MISMATCH",
310        "PublicDescription": "Number of times a TSX Abort was triggered due to release/commit but data and address mismatch.",
311        "SampleAfterValue": "2000003",
312        "UMask": "0x10"
313    },
314    {
315        "BriefDescription": "Number of times a TSX Abort was triggered due to commit but Lock Buffer not empty",
316        "EventCode": "0x54",
317        "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_NOT_EMPTY",
318        "PublicDescription": "Number of times a TSX Abort was triggered due to commit but Lock Buffer not empty.",
319        "SampleAfterValue": "2000003",
320        "UMask": "0x8"
321    },
322    {
323        "BriefDescription": "Number of times a TSX Abort was triggered due to attempting an unsupported alignment from Lock Buffer",
324        "EventCode": "0x54",
325        "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_UNSUPPORTED_ALIGNMENT",
326        "PublicDescription": "Number of times a TSX Abort was triggered due to attempting an unsupported alignment from Lock Buffer.",
327        "SampleAfterValue": "2000003",
328        "UMask": "0x20"
329    },
330    {
331        "BriefDescription": "Number of times a TSX Abort was triggered due to a non-release/commit store to lock",
332        "EventCode": "0x54",
333        "EventName": "TX_MEM.ABORT_HLE_STORE_TO_ELIDED_LOCK",
334        "PublicDescription": "Number of times a TSX Abort was triggered due to a non-release/commit store to lock.",
335        "SampleAfterValue": "2000003",
336        "UMask": "0x4"
337    },
338    {
339        "BriefDescription": "Number of times we could not allocate Lock Buffer",
340        "EventCode": "0x54",
341        "EventName": "TX_MEM.HLE_ELISION_BUFFER_FULL",
342        "PublicDescription": "Number of times we could not allocate Lock Buffer.",
343        "SampleAfterValue": "2000003",
344        "UMask": "0x40"
345    }
346]
347