1[
2    {
3        "EventCode": "0x8",
4        "Counter": "0,1",
5        "UMask": "0x7",
6        "EventName": "DATA_TLB_MISSES.DTLB_MISS",
7        "SampleAfterValue": "200000",
8        "BriefDescription": "Memory accesses that missed the DTLB."
9    },
10    {
11        "EventCode": "0x8",
12        "Counter": "0,1",
13        "UMask": "0x5",
14        "EventName": "DATA_TLB_MISSES.DTLB_MISS_LD",
15        "SampleAfterValue": "200000",
16        "BriefDescription": "DTLB misses due to load operations."
17    },
18    {
19        "EventCode": "0x8",
20        "Counter": "0,1",
21        "UMask": "0x9",
22        "EventName": "DATA_TLB_MISSES.L0_DTLB_MISS_LD",
23        "SampleAfterValue": "200000",
24        "BriefDescription": "L0 DTLB misses due to load operations."
25    },
26    {
27        "EventCode": "0x8",
28        "Counter": "0,1",
29        "UMask": "0x6",
30        "EventName": "DATA_TLB_MISSES.DTLB_MISS_ST",
31        "SampleAfterValue": "200000",
32        "BriefDescription": "DTLB misses due to store operations."
33    },
34    {
35        "EventCode": "0x8",
36        "Counter": "0,1",
37        "UMask": "0xa",
38        "EventName": "DATA_TLB_MISSES.L0_DTLB_MISS_ST",
39        "SampleAfterValue": "200000",
40        "BriefDescription": "L0 DTLB misses due to store operations"
41    },
42    {
43        "EventCode": "0xC",
44        "Counter": "0,1",
45        "UMask": "0x3",
46        "EventName": "PAGE_WALKS.WALKS",
47        "SampleAfterValue": "200000",
48        "BriefDescription": "Number of page-walks executed."
49    },
50    {
51        "EventCode": "0xC",
52        "Counter": "0,1",
53        "UMask": "0x3",
54        "EventName": "PAGE_WALKS.CYCLES",
55        "SampleAfterValue": "2000000",
56        "BriefDescription": "Duration of page-walks in core cycles"
57    },
58    {
59        "EventCode": "0xC",
60        "Counter": "0,1",
61        "UMask": "0x1",
62        "EventName": "PAGE_WALKS.D_SIDE_WALKS",
63        "SampleAfterValue": "200000",
64        "BriefDescription": "Number of D-side only page walks"
65    },
66    {
67        "EventCode": "0xC",
68        "Counter": "0,1",
69        "UMask": "0x1",
70        "EventName": "PAGE_WALKS.D_SIDE_CYCLES",
71        "SampleAfterValue": "2000000",
72        "BriefDescription": "Duration of D-side only page walks"
73    },
74    {
75        "EventCode": "0xC",
76        "Counter": "0,1",
77        "UMask": "0x2",
78        "EventName": "PAGE_WALKS.I_SIDE_WALKS",
79        "SampleAfterValue": "200000",
80        "BriefDescription": "Number of I-Side page walks"
81    },
82    {
83        "EventCode": "0xC",
84        "Counter": "0,1",
85        "UMask": "0x2",
86        "EventName": "PAGE_WALKS.I_SIDE_CYCLES",
87        "SampleAfterValue": "2000000",
88        "BriefDescription": "Duration of I-Side page walks"
89    },
90    {
91        "EventCode": "0x82",
92        "Counter": "0,1",
93        "UMask": "0x1",
94        "EventName": "ITLB.HIT",
95        "SampleAfterValue": "200000",
96        "BriefDescription": "ITLB hits."
97    },
98    {
99        "EventCode": "0x82",
100        "Counter": "0,1",
101        "UMask": "0x4",
102        "EventName": "ITLB.FLUSH",
103        "SampleAfterValue": "200000",
104        "BriefDescription": "ITLB flushes."
105    },
106    {
107        "PEBS": "2",
108        "EventCode": "0x82",
109        "Counter": "0,1",
110        "UMask": "0x2",
111        "EventName": "ITLB.MISSES",
112        "SampleAfterValue": "200000",
113        "BriefDescription": "ITLB misses."
114    },
115    {
116        "PEBS": "1",
117        "EventCode": "0xCB",
118        "Counter": "0,1",
119        "UMask": "0x4",
120        "EventName": "MEM_LOAD_RETIRED.DTLB_MISS",
121        "SampleAfterValue": "200000",
122        "BriefDescription": "Retired loads that miss the DTLB (precise event)."
123    }
124]