1052aa3ccSAndi Kleen[ 2052aa3ccSAndi Kleen { 3*c42bee96SIan Rogers "BriefDescription": "Bogus branches", 4052aa3ccSAndi Kleen "Counter": "0,1", 5052aa3ccSAndi Kleen "EventCode": "0xE4", 6052aa3ccSAndi Kleen "EventName": "BOGUS_BR", 7052aa3ccSAndi Kleen "SampleAfterValue": "2000000", 8*c42bee96SIan Rogers "UMask": "0x1" 9052aa3ccSAndi Kleen }, 10052aa3ccSAndi Kleen { 11*c42bee96SIan Rogers "BriefDescription": "Branch instructions decoded", 12052aa3ccSAndi Kleen "Counter": "0,1", 13*c42bee96SIan Rogers "EventCode": "0xE0", 14*c42bee96SIan Rogers "EventName": "BR_INST_DECODED", 15052aa3ccSAndi Kleen "SampleAfterValue": "2000000", 16*c42bee96SIan Rogers "UMask": "0x1" 17052aa3ccSAndi Kleen }, 18052aa3ccSAndi Kleen { 19*c42bee96SIan Rogers "BriefDescription": "Retired branch instructions.", 20052aa3ccSAndi Kleen "Counter": "0,1", 21*c42bee96SIan Rogers "EventCode": "0xC4", 22*c42bee96SIan Rogers "EventName": "BR_INST_RETIRED.ANY", 23*c42bee96SIan Rogers "SampleAfterValue": "2000000", 24*c42bee96SIan Rogers "UMask": "0x0" 25*c42bee96SIan Rogers }, 26*c42bee96SIan Rogers { 27*c42bee96SIan Rogers "BriefDescription": "Retired branch instructions.", 28*c42bee96SIan Rogers "Counter": "0,1", 29*c42bee96SIan Rogers "EventCode": "0xC4", 30*c42bee96SIan Rogers "EventName": "BR_INST_RETIRED.ANY1", 31*c42bee96SIan Rogers "SampleAfterValue": "2000000", 32*c42bee96SIan Rogers "UMask": "0xf" 33*c42bee96SIan Rogers }, 34*c42bee96SIan Rogers { 35*c42bee96SIan Rogers "BriefDescription": "Retired mispredicted branch instructions (precise event).", 36*c42bee96SIan Rogers "Counter": "0,1", 37*c42bee96SIan Rogers "EventCode": "0xC5", 38*c42bee96SIan Rogers "EventName": "BR_INST_RETIRED.MISPRED", 39*c42bee96SIan Rogers "PEBS": "1", 40*c42bee96SIan Rogers "SampleAfterValue": "200000", 41*c42bee96SIan Rogers "UMask": "0x0" 42*c42bee96SIan Rogers }, 43*c42bee96SIan Rogers { 44*c42bee96SIan Rogers "BriefDescription": "Retired branch instructions that were mispredicted not-taken.", 45*c42bee96SIan Rogers "Counter": "0,1", 46*c42bee96SIan Rogers "EventCode": "0xC4", 47*c42bee96SIan Rogers "EventName": "BR_INST_RETIRED.MISPRED_NOT_TAKEN", 48*c42bee96SIan Rogers "SampleAfterValue": "200000", 49*c42bee96SIan Rogers "UMask": "0x2" 50*c42bee96SIan Rogers }, 51*c42bee96SIan Rogers { 52*c42bee96SIan Rogers "BriefDescription": "Retired branch instructions that were mispredicted taken.", 53*c42bee96SIan Rogers "Counter": "0,1", 54*c42bee96SIan Rogers "EventCode": "0xC4", 55*c42bee96SIan Rogers "EventName": "BR_INST_RETIRED.MISPRED_TAKEN", 56*c42bee96SIan Rogers "SampleAfterValue": "200000", 57*c42bee96SIan Rogers "UMask": "0x8" 58*c42bee96SIan Rogers }, 59*c42bee96SIan Rogers { 60*c42bee96SIan Rogers "BriefDescription": "Retired branch instructions that were predicted not-taken.", 61*c42bee96SIan Rogers "Counter": "0,1", 62*c42bee96SIan Rogers "EventCode": "0xC4", 63*c42bee96SIan Rogers "EventName": "BR_INST_RETIRED.PRED_NOT_TAKEN", 64*c42bee96SIan Rogers "SampleAfterValue": "2000000", 65*c42bee96SIan Rogers "UMask": "0x1" 66*c42bee96SIan Rogers }, 67*c42bee96SIan Rogers { 68*c42bee96SIan Rogers "BriefDescription": "Retired branch instructions that were predicted taken.", 69*c42bee96SIan Rogers "Counter": "0,1", 70*c42bee96SIan Rogers "EventCode": "0xC4", 71*c42bee96SIan Rogers "EventName": "BR_INST_RETIRED.PRED_TAKEN", 72*c42bee96SIan Rogers "SampleAfterValue": "2000000", 73*c42bee96SIan Rogers "UMask": "0x4" 74*c42bee96SIan Rogers }, 75*c42bee96SIan Rogers { 76*c42bee96SIan Rogers "BriefDescription": "Retired taken branch instructions.", 77*c42bee96SIan Rogers "Counter": "0,1", 78*c42bee96SIan Rogers "EventCode": "0xC4", 79*c42bee96SIan Rogers "EventName": "BR_INST_RETIRED.TAKEN", 80*c42bee96SIan Rogers "SampleAfterValue": "2000000", 81*c42bee96SIan Rogers "UMask": "0xc" 82*c42bee96SIan Rogers }, 83*c42bee96SIan Rogers { 84*c42bee96SIan Rogers "BriefDescription": "All macro conditional branch instructions.", 85*c42bee96SIan Rogers "Counter": "0,1", 86*c42bee96SIan Rogers "EventCode": "0x88", 87*c42bee96SIan Rogers "EventName": "BR_INST_TYPE_RETIRED.COND", 88*c42bee96SIan Rogers "SampleAfterValue": "2000000", 89*c42bee96SIan Rogers "UMask": "0x1" 90*c42bee96SIan Rogers }, 91*c42bee96SIan Rogers { 92*c42bee96SIan Rogers "BriefDescription": "Only taken macro conditional branch instructions", 93*c42bee96SIan Rogers "Counter": "0,1", 94*c42bee96SIan Rogers "EventCode": "0x88", 95*c42bee96SIan Rogers "EventName": "BR_INST_TYPE_RETIRED.COND_TAKEN", 96*c42bee96SIan Rogers "SampleAfterValue": "2000000", 97*c42bee96SIan Rogers "UMask": "0x41" 98*c42bee96SIan Rogers }, 99*c42bee96SIan Rogers { 100*c42bee96SIan Rogers "BriefDescription": "All non-indirect calls", 101*c42bee96SIan Rogers "Counter": "0,1", 102*c42bee96SIan Rogers "EventCode": "0x88", 103*c42bee96SIan Rogers "EventName": "BR_INST_TYPE_RETIRED.DIR_CALL", 104*c42bee96SIan Rogers "SampleAfterValue": "2000000", 105*c42bee96SIan Rogers "UMask": "0x10" 106*c42bee96SIan Rogers }, 107*c42bee96SIan Rogers { 108*c42bee96SIan Rogers "BriefDescription": "All indirect branches that are not calls.", 109*c42bee96SIan Rogers "Counter": "0,1", 110*c42bee96SIan Rogers "EventCode": "0x88", 111*c42bee96SIan Rogers "EventName": "BR_INST_TYPE_RETIRED.IND", 112*c42bee96SIan Rogers "SampleAfterValue": "2000000", 113*c42bee96SIan Rogers "UMask": "0x4" 114*c42bee96SIan Rogers }, 115*c42bee96SIan Rogers { 116*c42bee96SIan Rogers "BriefDescription": "All indirect calls, including both register and memory indirect.", 117*c42bee96SIan Rogers "Counter": "0,1", 118*c42bee96SIan Rogers "EventCode": "0x88", 119*c42bee96SIan Rogers "EventName": "BR_INST_TYPE_RETIRED.IND_CALL", 120*c42bee96SIan Rogers "SampleAfterValue": "2000000", 121*c42bee96SIan Rogers "UMask": "0x20" 122*c42bee96SIan Rogers }, 123*c42bee96SIan Rogers { 124*c42bee96SIan Rogers "BriefDescription": "All indirect branches that have a return mnemonic", 125*c42bee96SIan Rogers "Counter": "0,1", 126*c42bee96SIan Rogers "EventCode": "0x88", 127*c42bee96SIan Rogers "EventName": "BR_INST_TYPE_RETIRED.RET", 128*c42bee96SIan Rogers "SampleAfterValue": "2000000", 129*c42bee96SIan Rogers "UMask": "0x8" 130*c42bee96SIan Rogers }, 131*c42bee96SIan Rogers { 132*c42bee96SIan Rogers "BriefDescription": "All macro unconditional branch instructions, excluding calls and indirects", 133*c42bee96SIan Rogers "Counter": "0,1", 134*c42bee96SIan Rogers "EventCode": "0x88", 135*c42bee96SIan Rogers "EventName": "BR_INST_TYPE_RETIRED.UNCOND", 136*c42bee96SIan Rogers "SampleAfterValue": "2000000", 137*c42bee96SIan Rogers "UMask": "0x2" 138*c42bee96SIan Rogers }, 139*c42bee96SIan Rogers { 140*c42bee96SIan Rogers "BriefDescription": "Mispredicted cond branch instructions retired", 141*c42bee96SIan Rogers "Counter": "0,1", 142*c42bee96SIan Rogers "EventCode": "0x89", 143*c42bee96SIan Rogers "EventName": "BR_MISSP_TYPE_RETIRED.COND", 144*c42bee96SIan Rogers "SampleAfterValue": "200000", 145*c42bee96SIan Rogers "UMask": "0x1" 146*c42bee96SIan Rogers }, 147*c42bee96SIan Rogers { 148*c42bee96SIan Rogers "BriefDescription": "Mispredicted and taken cond branch instructions retired", 149*c42bee96SIan Rogers "Counter": "0,1", 150*c42bee96SIan Rogers "EventCode": "0x89", 151*c42bee96SIan Rogers "EventName": "BR_MISSP_TYPE_RETIRED.COND_TAKEN", 152*c42bee96SIan Rogers "SampleAfterValue": "200000", 153*c42bee96SIan Rogers "UMask": "0x11" 154*c42bee96SIan Rogers }, 155*c42bee96SIan Rogers { 156*c42bee96SIan Rogers "BriefDescription": "Mispredicted ind branches that are not calls", 157*c42bee96SIan Rogers "Counter": "0,1", 158*c42bee96SIan Rogers "EventCode": "0x89", 159*c42bee96SIan Rogers "EventName": "BR_MISSP_TYPE_RETIRED.IND", 160*c42bee96SIan Rogers "SampleAfterValue": "200000", 161*c42bee96SIan Rogers "UMask": "0x2" 162*c42bee96SIan Rogers }, 163*c42bee96SIan Rogers { 164*c42bee96SIan Rogers "BriefDescription": "Mispredicted indirect calls, including both register and memory indirect.", 165*c42bee96SIan Rogers "Counter": "0,1", 166*c42bee96SIan Rogers "EventCode": "0x89", 167*c42bee96SIan Rogers "EventName": "BR_MISSP_TYPE_RETIRED.IND_CALL", 168*c42bee96SIan Rogers "SampleAfterValue": "200000", 169*c42bee96SIan Rogers "UMask": "0x8" 170*c42bee96SIan Rogers }, 171*c42bee96SIan Rogers { 172*c42bee96SIan Rogers "BriefDescription": "Mispredicted return branches", 173*c42bee96SIan Rogers "Counter": "0,1", 174*c42bee96SIan Rogers "EventCode": "0x89", 175*c42bee96SIan Rogers "EventName": "BR_MISSP_TYPE_RETIRED.RETURN", 176*c42bee96SIan Rogers "SampleAfterValue": "200000", 177*c42bee96SIan Rogers "UMask": "0x4" 178*c42bee96SIan Rogers }, 179*c42bee96SIan Rogers { 180*c42bee96SIan Rogers "BriefDescription": "Bus cycles when core is not halted", 181*c42bee96SIan Rogers "Counter": "0,1", 182*c42bee96SIan Rogers "EventCode": "0x3C", 183*c42bee96SIan Rogers "EventName": "CPU_CLK_UNHALTED.BUS", 184*c42bee96SIan Rogers "SampleAfterValue": "200000", 185*c42bee96SIan Rogers "UMask": "0x1" 186*c42bee96SIan Rogers }, 187*c42bee96SIan Rogers { 188*c42bee96SIan Rogers "BriefDescription": "Core cycles when core is not halted", 189*c42bee96SIan Rogers "Counter": "Fixed counter 2", 190*c42bee96SIan Rogers "EventCode": "0xA", 191*c42bee96SIan Rogers "EventName": "CPU_CLK_UNHALTED.CORE", 192*c42bee96SIan Rogers "SampleAfterValue": "2000000", 193*c42bee96SIan Rogers "UMask": "0x0" 194*c42bee96SIan Rogers }, 195*c42bee96SIan Rogers { 196*c42bee96SIan Rogers "BriefDescription": "Core cycles when core is not halted", 197*c42bee96SIan Rogers "Counter": "0,1", 198*c42bee96SIan Rogers "EventCode": "0x3C", 199*c42bee96SIan Rogers "EventName": "CPU_CLK_UNHALTED.CORE_P", 200*c42bee96SIan Rogers "SampleAfterValue": "2000000", 201*c42bee96SIan Rogers "UMask": "0x0" 202*c42bee96SIan Rogers }, 203*c42bee96SIan Rogers { 204*c42bee96SIan Rogers "BriefDescription": "Reference cycles when core is not halted.", 205*c42bee96SIan Rogers "Counter": "Fixed counter 3", 206*c42bee96SIan Rogers "EventCode": "0xA", 207*c42bee96SIan Rogers "EventName": "CPU_CLK_UNHALTED.REF", 208*c42bee96SIan Rogers "SampleAfterValue": "2000000", 209*c42bee96SIan Rogers "UMask": "0x0" 210*c42bee96SIan Rogers }, 211*c42bee96SIan Rogers { 212*c42bee96SIan Rogers "BriefDescription": "Cycles the divider is busy.", 213*c42bee96SIan Rogers "Counter": "0,1", 214*c42bee96SIan Rogers "EventCode": "0x14", 215*c42bee96SIan Rogers "EventName": "CYCLES_DIV_BUSY", 216*c42bee96SIan Rogers "SampleAfterValue": "2000000", 217*c42bee96SIan Rogers "UMask": "0x1" 218*c42bee96SIan Rogers }, 219*c42bee96SIan Rogers { 220*c42bee96SIan Rogers "BriefDescription": "Divide operations retired", 221*c42bee96SIan Rogers "Counter": "0,1", 222*c42bee96SIan Rogers "EventCode": "0x13", 223*c42bee96SIan Rogers "EventName": "DIV.AR", 224*c42bee96SIan Rogers "SampleAfterValue": "2000000", 225*c42bee96SIan Rogers "UMask": "0x81" 226*c42bee96SIan Rogers }, 227*c42bee96SIan Rogers { 228*c42bee96SIan Rogers "BriefDescription": "Divide operations executed.", 229*c42bee96SIan Rogers "Counter": "0,1", 230*c42bee96SIan Rogers "EventCode": "0x13", 231*c42bee96SIan Rogers "EventName": "DIV.S", 232*c42bee96SIan Rogers "SampleAfterValue": "2000000", 233*c42bee96SIan Rogers "UMask": "0x1" 234*c42bee96SIan Rogers }, 235*c42bee96SIan Rogers { 236*c42bee96SIan Rogers "BriefDescription": "Instructions retired.", 237*c42bee96SIan Rogers "Counter": "Fixed counter 1", 238*c42bee96SIan Rogers "EventCode": "0xA", 239*c42bee96SIan Rogers "EventName": "INST_RETIRED.ANY", 240*c42bee96SIan Rogers "SampleAfterValue": "2000000", 241*c42bee96SIan Rogers "UMask": "0x0" 242*c42bee96SIan Rogers }, 243*c42bee96SIan Rogers { 244*c42bee96SIan Rogers "BriefDescription": "Instructions retired (precise event).", 245*c42bee96SIan Rogers "Counter": "0,1", 246*c42bee96SIan Rogers "EventCode": "0xC0", 247*c42bee96SIan Rogers "EventName": "INST_RETIRED.ANY_P", 248*c42bee96SIan Rogers "PEBS": "2", 249*c42bee96SIan Rogers "SampleAfterValue": "2000000", 250*c42bee96SIan Rogers "UMask": "0x0" 251*c42bee96SIan Rogers }, 252*c42bee96SIan Rogers { 253*c42bee96SIan Rogers "BriefDescription": "Self-Modifying Code detected.", 254*c42bee96SIan Rogers "Counter": "0,1", 255*c42bee96SIan Rogers "EventCode": "0xC3", 256*c42bee96SIan Rogers "EventName": "MACHINE_CLEARS.SMC", 257*c42bee96SIan Rogers "SampleAfterValue": "200000", 258*c42bee96SIan Rogers "UMask": "0x1" 259*c42bee96SIan Rogers }, 260*c42bee96SIan Rogers { 261*c42bee96SIan Rogers "BriefDescription": "Multiply operations retired", 262*c42bee96SIan Rogers "Counter": "0,1", 263*c42bee96SIan Rogers "EventCode": "0x12", 264*c42bee96SIan Rogers "EventName": "MUL.AR", 265*c42bee96SIan Rogers "SampleAfterValue": "2000000", 266*c42bee96SIan Rogers "UMask": "0x81" 267*c42bee96SIan Rogers }, 268*c42bee96SIan Rogers { 269*c42bee96SIan Rogers "BriefDescription": "Multiply operations executed.", 270*c42bee96SIan Rogers "Counter": "0,1", 271*c42bee96SIan Rogers "EventCode": "0x12", 272*c42bee96SIan Rogers "EventName": "MUL.S", 273*c42bee96SIan Rogers "SampleAfterValue": "2000000", 274*c42bee96SIan Rogers "UMask": "0x1" 275*c42bee96SIan Rogers }, 276*c42bee96SIan Rogers { 277*c42bee96SIan Rogers "BriefDescription": "Micro-op reissues for any cause", 278*c42bee96SIan Rogers "Counter": "0,1", 279*c42bee96SIan Rogers "EventCode": "0x3", 280*c42bee96SIan Rogers "EventName": "REISSUE.ANY", 281*c42bee96SIan Rogers "SampleAfterValue": "200000", 282*c42bee96SIan Rogers "UMask": "0x7f" 283*c42bee96SIan Rogers }, 284*c42bee96SIan Rogers { 285*c42bee96SIan Rogers "BriefDescription": "Micro-op reissues for any cause (At Retirement)", 286*c42bee96SIan Rogers "Counter": "0,1", 287*c42bee96SIan Rogers "EventCode": "0x3", 288*c42bee96SIan Rogers "EventName": "REISSUE.ANY.AR", 289*c42bee96SIan Rogers "SampleAfterValue": "200000", 290*c42bee96SIan Rogers "UMask": "0xff" 291*c42bee96SIan Rogers }, 292*c42bee96SIan Rogers { 293*c42bee96SIan Rogers "BriefDescription": "Micro-op reissues on a store-load collision", 294*c42bee96SIan Rogers "Counter": "0,1", 295*c42bee96SIan Rogers "EventCode": "0x3", 296052aa3ccSAndi Kleen "EventName": "REISSUE.OVERLAP_STORE", 297052aa3ccSAndi Kleen "SampleAfterValue": "200000", 298*c42bee96SIan Rogers "UMask": "0x1" 299052aa3ccSAndi Kleen }, 300052aa3ccSAndi Kleen { 301*c42bee96SIan Rogers "BriefDescription": "Micro-op reissues on a store-load collision (At Retirement)", 302052aa3ccSAndi Kleen "Counter": "0,1", 303*c42bee96SIan Rogers "EventCode": "0x3", 304052aa3ccSAndi Kleen "EventName": "REISSUE.OVERLAP_STORE.AR", 305052aa3ccSAndi Kleen "SampleAfterValue": "200000", 306*c42bee96SIan Rogers "UMask": "0x81" 307*c42bee96SIan Rogers }, 308*c42bee96SIan Rogers { 309*c42bee96SIan Rogers "BriefDescription": "Cycles issue is stalled due to div busy.", 310*c42bee96SIan Rogers "Counter": "0,1", 311*c42bee96SIan Rogers "EventCode": "0xDC", 312*c42bee96SIan Rogers "EventName": "RESOURCE_STALLS.DIV_BUSY", 313*c42bee96SIan Rogers "SampleAfterValue": "2000000", 314*c42bee96SIan Rogers "UMask": "0x2" 315*c42bee96SIan Rogers }, 316*c42bee96SIan Rogers { 317*c42bee96SIan Rogers "BriefDescription": "All store forwards", 318*c42bee96SIan Rogers "Counter": "0,1", 319*c42bee96SIan Rogers "EventCode": "0x2", 320*c42bee96SIan Rogers "EventName": "STORE_FORWARDS.ANY", 321*c42bee96SIan Rogers "SampleAfterValue": "200000", 322*c42bee96SIan Rogers "UMask": "0x83" 323*c42bee96SIan Rogers }, 324*c42bee96SIan Rogers { 325*c42bee96SIan Rogers "BriefDescription": "Good store forwards", 326*c42bee96SIan Rogers "Counter": "0,1", 327*c42bee96SIan Rogers "EventCode": "0x2", 328*c42bee96SIan Rogers "EventName": "STORE_FORWARDS.GOOD", 329*c42bee96SIan Rogers "SampleAfterValue": "200000", 330*c42bee96SIan Rogers "UMask": "0x81" 331*c42bee96SIan Rogers }, 332*c42bee96SIan Rogers { 333*c42bee96SIan Rogers "BriefDescription": "Micro-ops retired.", 334*c42bee96SIan Rogers "Counter": "0,1", 335*c42bee96SIan Rogers "EventCode": "0xC2", 336*c42bee96SIan Rogers "EventName": "UOPS_RETIRED.ANY", 337*c42bee96SIan Rogers "SampleAfterValue": "2000000", 338*c42bee96SIan Rogers "UMask": "0x10" 339*c42bee96SIan Rogers }, 340*c42bee96SIan Rogers { 341*c42bee96SIan Rogers "BriefDescription": "Cycles no micro-ops retired.", 342*c42bee96SIan Rogers "Counter": "0,1", 343*c42bee96SIan Rogers "EventCode": "0xC2", 344*c42bee96SIan Rogers "EventName": "UOPS_RETIRED.STALLED_CYCLES", 345*c42bee96SIan Rogers "SampleAfterValue": "2000000", 346*c42bee96SIan Rogers "UMask": "0x10" 347*c42bee96SIan Rogers }, 348*c42bee96SIan Rogers { 349*c42bee96SIan Rogers "BriefDescription": "Periods no micro-ops retired.", 350*c42bee96SIan Rogers "Counter": "0,1", 351*c42bee96SIan Rogers "EventCode": "0xC2", 352*c42bee96SIan Rogers "EventName": "UOPS_RETIRED.STALLS", 353*c42bee96SIan Rogers "SampleAfterValue": "2000000", 354*c42bee96SIan Rogers "UMask": "0x10" 355052aa3ccSAndi Kleen } 356052aa3ccSAndi Kleen]