1*da666586SSmita Koralahalli[
2*da666586SSmita Koralahalli  {
3*da666586SSmita Koralahalli    "MetricName": "branch_misprediction_ratio",
4*da666586SSmita Koralahalli    "BriefDescription": "Execution-Time Branch Misprediction Ratio (Non-Speculative)",
5*da666586SSmita Koralahalli    "MetricExpr": "d_ratio(ex_ret_brn_misp, ex_ret_brn)",
6*da666586SSmita Koralahalli    "MetricGroup": "branch_prediction",
7*da666586SSmita Koralahalli    "ScaleUnit": "100%"
8*da666586SSmita Koralahalli  },
9*da666586SSmita Koralahalli  {
10*da666586SSmita Koralahalli    "EventName": "all_data_cache_accesses",
11*da666586SSmita Koralahalli    "EventCode": "0x29",
12*da666586SSmita Koralahalli    "BriefDescription": "All L1 Data Cache Accesses",
13*da666586SSmita Koralahalli    "UMask": "0x07"
14*da666586SSmita Koralahalli  },
15*da666586SSmita Koralahalli  {
16*da666586SSmita Koralahalli    "MetricName": "all_l2_cache_accesses",
17*da666586SSmita Koralahalli    "BriefDescription": "All L2 Cache Accesses",
18*da666586SSmita Koralahalli    "MetricExpr": "l2_request_g1.all_no_prefetch + l2_pf_hit_l2 + l2_pf_miss_l2_hit_l3 + l2_pf_miss_l2_l3",
19*da666586SSmita Koralahalli    "MetricGroup": "l2_cache"
20*da666586SSmita Koralahalli  },
21*da666586SSmita Koralahalli  {
22*da666586SSmita Koralahalli    "EventName": "l2_cache_accesses_from_ic_misses",
23*da666586SSmita Koralahalli    "EventCode": "0x60",
24*da666586SSmita Koralahalli    "BriefDescription": "L2 Cache Accesses from L1 Instruction Cache Misses (including prefetch)",
25*da666586SSmita Koralahalli    "UMask": "0x10"
26*da666586SSmita Koralahalli  },
27*da666586SSmita Koralahalli  {
28*da666586SSmita Koralahalli    "EventName": "l2_cache_accesses_from_dc_misses",
29*da666586SSmita Koralahalli    "EventCode": "0x60",
30*da666586SSmita Koralahalli    "BriefDescription": "L2 Cache Accesses from L1 Data Cache Misses (including prefetch)",
31*da666586SSmita Koralahalli    "UMask": "0xe8"
32*da666586SSmita Koralahalli  },
33*da666586SSmita Koralahalli  {
34*da666586SSmita Koralahalli    "MetricName": "l2_cache_accesses_from_l2_hwpf",
35*da666586SSmita Koralahalli    "BriefDescription": "L2 Cache Accesses from L2 HWPF",
36*da666586SSmita Koralahalli    "MetricExpr": "l2_pf_hit_l2 + l2_pf_miss_l2_hit_l3 + l2_pf_miss_l2_l3",
37*da666586SSmita Koralahalli    "MetricGroup": "l2_cache"
38*da666586SSmita Koralahalli  },
39*da666586SSmita Koralahalli  {
40*da666586SSmita Koralahalli    "MetricName": "all_l2_cache_misses",
41*da666586SSmita Koralahalli    "BriefDescription": "All L2 Cache Misses",
42*da666586SSmita Koralahalli    "MetricExpr": "l2_cache_req_stat.ic_dc_miss_in_l2 + l2_pf_miss_l2_hit_l3 + l2_pf_miss_l2_l3",
43*da666586SSmita Koralahalli    "MetricGroup": "l2_cache"
44*da666586SSmita Koralahalli  },
45*da666586SSmita Koralahalli  {
46*da666586SSmita Koralahalli    "EventName": "l2_cache_misses_from_ic_miss",
47*da666586SSmita Koralahalli    "EventCode": "0x64",
48*da666586SSmita Koralahalli    "BriefDescription": "L2 Cache Misses from L1 Instruction Cache Misses",
49*da666586SSmita Koralahalli    "UMask": "0x01"
50*da666586SSmita Koralahalli  },
51*da666586SSmita Koralahalli  {
52*da666586SSmita Koralahalli    "EventName": "l2_cache_misses_from_dc_misses",
53*da666586SSmita Koralahalli    "EventCode": "0x64",
54*da666586SSmita Koralahalli    "BriefDescription": "L2 Cache Misses from L1 Data Cache Misses",
55*da666586SSmita Koralahalli    "UMask": "0x08"
56*da666586SSmita Koralahalli  },
57*da666586SSmita Koralahalli  {
58*da666586SSmita Koralahalli    "MetricName": "l2_cache_misses_from_l2_hwpf",
59*da666586SSmita Koralahalli    "BriefDescription": "L2 Cache Misses from L2 Cache HWPF",
60*da666586SSmita Koralahalli    "MetricExpr": "l2_pf_miss_l2_hit_l3 + l2_pf_miss_l2_l3",
61*da666586SSmita Koralahalli    "MetricGroup": "l2_cache"
62*da666586SSmita Koralahalli  },
63*da666586SSmita Koralahalli  {
64*da666586SSmita Koralahalli    "MetricName": "all_l2_cache_hits",
65*da666586SSmita Koralahalli    "BriefDescription": "All L2 Cache Hits",
66*da666586SSmita Koralahalli    "MetricExpr": "l2_cache_req_stat.ic_dc_hit_in_l2 + l2_pf_hit_l2",
67*da666586SSmita Koralahalli    "MetricGroup": "l2_cache"
68*da666586SSmita Koralahalli  },
69*da666586SSmita Koralahalli  {
70*da666586SSmita Koralahalli    "EventName": "l2_cache_hits_from_ic_misses",
71*da666586SSmita Koralahalli    "EventCode": "0x64",
72*da666586SSmita Koralahalli    "BriefDescription": "L2 Cache Hits from L1 Instruction Cache Misses",
73*da666586SSmita Koralahalli    "UMask": "0x06"
74*da666586SSmita Koralahalli  },
75*da666586SSmita Koralahalli  {
76*da666586SSmita Koralahalli    "EventName": "l2_cache_hits_from_dc_misses",
77*da666586SSmita Koralahalli    "EventCode": "0x64",
78*da666586SSmita Koralahalli    "BriefDescription": "L2 Cache Hits from L1 Data Cache Misses",
79*da666586SSmita Koralahalli    "UMask": "0xf0"
80*da666586SSmita Koralahalli  },
81*da666586SSmita Koralahalli  {
82*da666586SSmita Koralahalli    "EventName": "l2_cache_hits_from_l2_hwpf",
83*da666586SSmita Koralahalli    "EventCode": "0x70",
84*da666586SSmita Koralahalli    "BriefDescription": "L2 Cache Hits from L2 Cache HWPF",
85*da666586SSmita Koralahalli    "UMask": "0xff"
86*da666586SSmita Koralahalli  },
87*da666586SSmita Koralahalli  {
88*da666586SSmita Koralahalli    "EventName": "l3_cache_accesses",
89*da666586SSmita Koralahalli    "EventCode": "0x04",
90*da666586SSmita Koralahalli    "BriefDescription": "L3 Cache Accesses",
91*da666586SSmita Koralahalli    "UMask": "0xff",
92*da666586SSmita Koralahalli    "Unit": "L3PMC"
93*da666586SSmita Koralahalli  },
94*da666586SSmita Koralahalli  {
95*da666586SSmita Koralahalli    "EventName": "l3_misses",
96*da666586SSmita Koralahalli    "EventCode": "0x04",
97*da666586SSmita Koralahalli    "BriefDescription": "L3 Misses (includes cacheline state change requests)",
98*da666586SSmita Koralahalli    "UMask": "0x01",
99*da666586SSmita Koralahalli    "Unit": "L3PMC"
100*da666586SSmita Koralahalli  },
101*da666586SSmita Koralahalli  {
102*da666586SSmita Koralahalli    "MetricName": "l3_read_miss_latency",
103*da666586SSmita Koralahalli    "BriefDescription": "Average L3 Read Miss Latency (in core clocks)",
104*da666586SSmita Koralahalli    "MetricExpr": "(xi_sys_fill_latency * 16) / xi_ccx_sdp_req1",
105*da666586SSmita Koralahalli    "MetricGroup": "l3_cache",
106*da666586SSmita Koralahalli    "ScaleUnit": "1core clocks"
107*da666586SSmita Koralahalli  },
108*da666586SSmita Koralahalli  {
109*da666586SSmita Koralahalli    "MetricName": "op_cache_fetch_miss_ratio",
110*da666586SSmita Koralahalli    "BriefDescription": "Op Cache (64B) Fetch Miss Ratio",
111*da666586SSmita Koralahalli    "MetricExpr": "d_ratio(op_cache_hit_miss.op_cache_miss, op_cache_hit_miss.all_op_cache_accesses)",
112*da666586SSmita Koralahalli    "MetricGroup": "l2_cache"
113*da666586SSmita Koralahalli  },
114*da666586SSmita Koralahalli  {
115*da666586SSmita Koralahalli    "MetricName": "ic_fetch_miss_ratio",
116*da666586SSmita Koralahalli    "BriefDescription": "Instruction Cache (32B) Fetch Miss Ratio",
117*da666586SSmita Koralahalli    "MetricExpr": "d_ratio(ic_tag_hit_miss.instruction_cache_miss, ic_tag_hit_miss.all_instruction_cache_accesses)",
118*da666586SSmita Koralahalli    "MetricGroup": "l2_cache",
119*da666586SSmita Koralahalli    "ScaleUnit": "100%"
120*da666586SSmita Koralahalli  },
121*da666586SSmita Koralahalli  {
122*da666586SSmita Koralahalli    "EventName": "l1_data_cache_fills_from_memory",
123*da666586SSmita Koralahalli    "EventCode": "0x44",
124*da666586SSmita Koralahalli    "BriefDescription": "L1 Data Cache Fills: From Memory",
125*da666586SSmita Koralahalli    "UMask": "0x48"
126*da666586SSmita Koralahalli  },
127*da666586SSmita Koralahalli  {
128*da666586SSmita Koralahalli    "EventName": "l1_data_cache_fills_from_remote_node",
129*da666586SSmita Koralahalli    "EventCode": "0x44",
130*da666586SSmita Koralahalli    "BriefDescription": "L1 Data Cache Fills: From Remote Node",
131*da666586SSmita Koralahalli    "UMask": "0x50"
132*da666586SSmita Koralahalli  },
133*da666586SSmita Koralahalli  {
134*da666586SSmita Koralahalli    "EventName": "l1_data_cache_fills_from_within_same_ccx",
135*da666586SSmita Koralahalli    "EventCode": "0x44",
136*da666586SSmita Koralahalli    "BriefDescription": "L1 Data Cache Fills: From within same CCX",
137*da666586SSmita Koralahalli    "UMask": "0x03"
138*da666586SSmita Koralahalli  },
139*da666586SSmita Koralahalli  {
140*da666586SSmita Koralahalli    "EventName": "l1_data_cache_fills_from_external_ccx_cache",
141*da666586SSmita Koralahalli    "EventCode": "0x44",
142*da666586SSmita Koralahalli    "BriefDescription": "L1 Data Cache Fills: From External CCX Cache",
143*da666586SSmita Koralahalli    "UMask": "0x14"
144*da666586SSmita Koralahalli  },
145*da666586SSmita Koralahalli  {
146*da666586SSmita Koralahalli    "EventName": "l1_data_cache_fills_all",
147*da666586SSmita Koralahalli    "EventCode": "0x44",
148*da666586SSmita Koralahalli    "BriefDescription": "L1 Data Cache Fills: All",
149*da666586SSmita Koralahalli    "UMask": "0xff"
150*da666586SSmita Koralahalli  },
151*da666586SSmita Koralahalli  {
152*da666586SSmita Koralahalli    "MetricName": "l1_itlb_misses",
153*da666586SSmita Koralahalli    "BriefDescription": "L1 ITLB Misses",
154*da666586SSmita Koralahalli    "MetricExpr": "bp_l1_tlb_miss_l2_tlb_hit + bp_l1_tlb_miss_l2_tlb_miss",
155*da666586SSmita Koralahalli    "MetricGroup": "tlb"
156*da666586SSmita Koralahalli  },
157*da666586SSmita Koralahalli  {
158*da666586SSmita Koralahalli    "EventName": "l2_itlb_misses",
159*da666586SSmita Koralahalli    "EventCode": "0x85",
160*da666586SSmita Koralahalli    "BriefDescription": "L2 ITLB Misses & Instruction page walks",
161*da666586SSmita Koralahalli    "UMask": "0x07"
162*da666586SSmita Koralahalli  },
163*da666586SSmita Koralahalli  {
164*da666586SSmita Koralahalli    "EventName": "l1_dtlb_misses",
165*da666586SSmita Koralahalli    "EventCode": "0x45",
166*da666586SSmita Koralahalli    "BriefDescription": "L1 DTLB Misses",
167*da666586SSmita Koralahalli    "UMask": "0xff"
168*da666586SSmita Koralahalli  },
169*da666586SSmita Koralahalli  {
170*da666586SSmita Koralahalli    "EventName": "l2_dtlb_misses",
171*da666586SSmita Koralahalli    "EventCode": "0x45",
172*da666586SSmita Koralahalli    "BriefDescription": "L2 DTLB Misses & Data page walks",
173*da666586SSmita Koralahalli    "UMask": "0xf0"
174*da666586SSmita Koralahalli  },
175*da666586SSmita Koralahalli  {
176*da666586SSmita Koralahalli    "EventName": "all_tlbs_flushed",
177*da666586SSmita Koralahalli    "EventCode": "0x78",
178*da666586SSmita Koralahalli    "BriefDescription": "All TLBs Flushed",
179*da666586SSmita Koralahalli    "UMask": "0xff"
180*da666586SSmita Koralahalli  },
181*da666586SSmita Koralahalli  {
182*da666586SSmita Koralahalli    "MetricName": "macro_ops_dispatched",
183*da666586SSmita Koralahalli    "BriefDescription": "Macro-ops Dispatched",
184*da666586SSmita Koralahalli    "MetricExpr": "de_dis_cops_from_decoder.disp_op_type.any_integer_dispatch + de_dis_cops_from_decoder.disp_op_type.any_fp_dispatch",
185*da666586SSmita Koralahalli    "MetricGroup": "decoder"
186*da666586SSmita Koralahalli  },
187*da666586SSmita Koralahalli  {
188*da666586SSmita Koralahalli    "EventName": "sse_avx_stalls",
189*da666586SSmita Koralahalli    "EventCode": "0x0e",
190*da666586SSmita Koralahalli    "BriefDescription": "Mixed SSE/AVX Stalls",
191*da666586SSmita Koralahalli    "UMask": "0x0e"
192*da666586SSmita Koralahalli  },
193*da666586SSmita Koralahalli  {
194*da666586SSmita Koralahalli    "EventName": "macro_ops_retired",
195*da666586SSmita Koralahalli    "EventCode": "0xc1",
196*da666586SSmita Koralahalli    "BriefDescription": "Macro-ops Retired"
197*da666586SSmita Koralahalli  },
198*da666586SSmita Koralahalli  {
199*da666586SSmita Koralahalli    "MetricName": "all_remote_links_outbound",
200*da666586SSmita Koralahalli    "BriefDescription": "Approximate: Outbound data bytes for all Remote Links for a node (die)",
201*da666586SSmita Koralahalli    "MetricExpr": "remote_outbound_data_controller_0 + remote_outbound_data_controller_1 + remote_outbound_data_controller_2 + remote_outbound_data_controller_3",
202*da666586SSmita Koralahalli    "MetricGroup": "data_fabric",
203*da666586SSmita Koralahalli    "PerPkg": "1",
204*da666586SSmita Koralahalli    "ScaleUnit": "3e-5MiB"
205*da666586SSmita Koralahalli  },
206*da666586SSmita Koralahalli  {
207*da666586SSmita Koralahalli    "MetricName": "nps1_die_to_dram",
208*da666586SSmita Koralahalli    "BriefDescription": "Approximate: Combined DRAM B/bytes of all channels on a NPS1 node (die) (may need --metric-no-group)",
209*da666586SSmita Koralahalli    "MetricExpr": "dram_channel_data_controller_0 + dram_channel_data_controller_1 + dram_channel_data_controller_2 + dram_channel_data_controller_3 + dram_channel_data_controller_4 + dram_channel_data_controller_5 + dram_channel_data_controller_6 + dram_channel_data_controller_7",
210*da666586SSmita Koralahalli    "MetricGroup": "data_fabric",
211*da666586SSmita Koralahalli    "PerPkg": "1",
212*da666586SSmita Koralahalli    "ScaleUnit": "6.1e-5MiB"
213*da666586SSmita Koralahalli  }
214*da666586SSmita Koralahalli]
215