12079f7aaSVijay Thakkar[ 22079f7aaSVijay Thakkar { 32079f7aaSVijay Thakkar "EventName": "ls_bad_status2.stli_other", 42079f7aaSVijay Thakkar "EventCode": "0x24", 52079f7aaSVijay Thakkar "BriefDescription": "Non-forwardable conflict; used to reduce STLI's via software. All reasons. Store To Load Interlock (STLI) are loads that were unable to complete because of a possible match with an older store, and the older store could not do STLF for some reason.", 62079f7aaSVijay Thakkar "PublicDescription" : "Store-to-load conflicts: A load was unable to complete due to a non-forwardable conflict with an older store. Most commonly, a load's address range partially but not completely overlaps with an uncompleted older store. Software can avoid this problem by using same-size and same-alignment loads and stores when accessing the same data. Vector/SIMD code is particularly susceptible to this problem; software should construct wide vector stores by manipulating vector elements in registers using shuffle/blend/swap instructions prior to storing to memory, instead of using narrow element-by-element stores.", 72079f7aaSVijay Thakkar "UMask": "0x2" 82079f7aaSVijay Thakkar }, 92079f7aaSVijay Thakkar { 102079f7aaSVijay Thakkar "EventName": "ls_locks.spec_lock_hi_spec", 112079f7aaSVijay Thakkar "EventCode": "0x25", 122079f7aaSVijay Thakkar "BriefDescription": "Retired lock instructions. High speculative cacheable lock speculation succeeded.", 132079f7aaSVijay Thakkar "UMask": "0x8" 142079f7aaSVijay Thakkar }, 152079f7aaSVijay Thakkar { 162079f7aaSVijay Thakkar "EventName": "ls_locks.spec_lock_lo_spec", 172079f7aaSVijay Thakkar "EventCode": "0x25", 182079f7aaSVijay Thakkar "BriefDescription": "Retired lock instructions. Low speculative cacheable lock speculation succeeded.", 192079f7aaSVijay Thakkar "UMask": "0x4" 202079f7aaSVijay Thakkar }, 212079f7aaSVijay Thakkar { 222079f7aaSVijay Thakkar "EventName": "ls_locks.non_spec_lock", 232079f7aaSVijay Thakkar "EventCode": "0x25", 242079f7aaSVijay Thakkar "BriefDescription": "Retired lock instructions. Non-speculative lock succeeded.", 252079f7aaSVijay Thakkar "UMask": "0x2" 262079f7aaSVijay Thakkar }, 272079f7aaSVijay Thakkar { 282079f7aaSVijay Thakkar "EventName": "ls_locks.bus_lock", 292079f7aaSVijay Thakkar "EventCode": "0x25", 302079f7aaSVijay Thakkar "BriefDescription": "Retired lock instructions. Bus lock when a locked operations crosses a cache boundary or is done on an uncacheable memory type. Comparable to legacy bus lock.", 312079f7aaSVijay Thakkar "UMask": "0x1" 322079f7aaSVijay Thakkar }, 332079f7aaSVijay Thakkar { 342079f7aaSVijay Thakkar "EventName": "ls_ret_cl_flush", 352079f7aaSVijay Thakkar "EventCode": "0x26", 362079f7aaSVijay Thakkar "BriefDescription": "Number of retired CLFLUSH instructions." 372079f7aaSVijay Thakkar }, 382079f7aaSVijay Thakkar { 392079f7aaSVijay Thakkar "EventName": "ls_ret_cpuid", 402079f7aaSVijay Thakkar "EventCode": "0x27", 412079f7aaSVijay Thakkar "BriefDescription": "Number of retired CPUID instructions." 422079f7aaSVijay Thakkar }, 432079f7aaSVijay Thakkar { 442079f7aaSVijay Thakkar "EventName": "ls_dispatch.ld_st_dispatch", 452079f7aaSVijay Thakkar "EventCode": "0x29", 462079f7aaSVijay Thakkar "BriefDescription": "Dispatch of a single op that performs a load from and store to the same memory address. Number of single ops that do load/store to an address.", 472079f7aaSVijay Thakkar "UMask": "0x4" 482079f7aaSVijay Thakkar }, 492079f7aaSVijay Thakkar { 502079f7aaSVijay Thakkar "EventName": "ls_dispatch.store_dispatch", 512079f7aaSVijay Thakkar "EventCode": "0x29", 522079f7aaSVijay Thakkar "BriefDescription": "Number of stores dispatched. Counts the number of operations dispatched to the LS unit. Unit Masks ADDed.", 532079f7aaSVijay Thakkar "UMask": "0x2" 542079f7aaSVijay Thakkar }, 552079f7aaSVijay Thakkar { 562079f7aaSVijay Thakkar "EventName": "ls_dispatch.ld_dispatch", 572079f7aaSVijay Thakkar "EventCode": "0x29", 582079f7aaSVijay Thakkar "BriefDescription": "Number of loads dispatched. Counts the number of operations dispatched to the LS unit. Unit Masks ADDed.", 592079f7aaSVijay Thakkar "UMask": "0x1" 602079f7aaSVijay Thakkar }, 612079f7aaSVijay Thakkar { 622079f7aaSVijay Thakkar "EventName": "ls_smi_rx", 63*ff64c981SSmita Koralahalli "EventCode": "0x2b", 642079f7aaSVijay Thakkar "BriefDescription": "Number of SMIs received." 652079f7aaSVijay Thakkar }, 662079f7aaSVijay Thakkar { 672079f7aaSVijay Thakkar "EventName": "ls_int_taken", 68*ff64c981SSmita Koralahalli "EventCode": "0x2c", 692079f7aaSVijay Thakkar "BriefDescription": "Number of interrupts taken." 702079f7aaSVijay Thakkar }, 712079f7aaSVijay Thakkar { 722079f7aaSVijay Thakkar "EventName": "ls_rdtsc", 73*ff64c981SSmita Koralahalli "EventCode": "0x2d", 742079f7aaSVijay Thakkar "BriefDescription": "Number of reads of the TSC (RDTSC instructions). The count is speculative." 752079f7aaSVijay Thakkar }, 762079f7aaSVijay Thakkar { 772079f7aaSVijay Thakkar "EventName": "ls_stlf", 782079f7aaSVijay Thakkar "EventCode": "0x35", 792079f7aaSVijay Thakkar "BriefDescription": "Number of STLF hits." 802079f7aaSVijay Thakkar }, 812079f7aaSVijay Thakkar { 822079f7aaSVijay Thakkar "EventName": "ls_st_commit_cancel2.st_commit_cancel_wcb_full", 832079f7aaSVijay Thakkar "EventCode": "0x37", 842079f7aaSVijay Thakkar "BriefDescription": "A non-cacheable store and the non-cacheable commit buffer is full." 852079f7aaSVijay Thakkar }, 862079f7aaSVijay Thakkar { 872079f7aaSVijay Thakkar "EventName": "ls_dc_accesses", 882079f7aaSVijay Thakkar "EventCode": "0x40", 892079f7aaSVijay Thakkar "BriefDescription": "Number of accesses to the dcache for load/store references.", 902079f7aaSVijay Thakkar "PublicDescription": "The number of accesses to the data cache for load and store references. This may include certain microcode scratchpad accesses, although these are generally rare. Each increment represents an eight-byte access, although the instruction may only be accessing a portion of that. This event is a speculative event." 912079f7aaSVijay Thakkar }, 922079f7aaSVijay Thakkar { 932079f7aaSVijay Thakkar "EventName": "ls_mab_alloc.dc_prefetcher", 942079f7aaSVijay Thakkar "EventCode": "0x41", 952079f7aaSVijay Thakkar "BriefDescription": "LS MAB Allocates by Type. DC prefetcher.", 962079f7aaSVijay Thakkar "UMask": "0x8" 972079f7aaSVijay Thakkar }, 982079f7aaSVijay Thakkar { 992079f7aaSVijay Thakkar "EventName": "ls_mab_alloc.stores", 1002079f7aaSVijay Thakkar "EventCode": "0x41", 1012079f7aaSVijay Thakkar "BriefDescription": "LS MAB Allocates by Type. Stores.", 1022079f7aaSVijay Thakkar "UMask": "0x2" 1032079f7aaSVijay Thakkar }, 1042079f7aaSVijay Thakkar { 1052079f7aaSVijay Thakkar "EventName": "ls_mab_alloc.loads", 1062079f7aaSVijay Thakkar "EventCode": "0x41", 1072079f7aaSVijay Thakkar "BriefDescription": "LS MAB Allocates by Type. Loads.", 1082079f7aaSVijay Thakkar "UMask": "0x1" 1092079f7aaSVijay Thakkar }, 1102079f7aaSVijay Thakkar { 1112079f7aaSVijay Thakkar "EventName": "ls_refills_from_sys.ls_mabresp_rmt_dram", 1122079f7aaSVijay Thakkar "EventCode": "0x43", 1132079f7aaSVijay Thakkar "BriefDescription": "Demand Data Cache Fills by Data Source. DRAM or IO from different die.", 1142079f7aaSVijay Thakkar "UMask": "0x40" 1152079f7aaSVijay Thakkar }, 1162079f7aaSVijay Thakkar { 1172079f7aaSVijay Thakkar "EventName": "ls_refills_from_sys.ls_mabresp_rmt_cache", 1182079f7aaSVijay Thakkar "EventCode": "0x43", 1192079f7aaSVijay Thakkar "BriefDescription": "Demand Data Cache Fills by Data Source. Hit in cache; Remote CCX and the address's Home Node is on a different die.", 1202079f7aaSVijay Thakkar "UMask": "0x10" 1212079f7aaSVijay Thakkar }, 1222079f7aaSVijay Thakkar { 1232079f7aaSVijay Thakkar "EventName": "ls_refills_from_sys.ls_mabresp_lcl_dram", 1242079f7aaSVijay Thakkar "EventCode": "0x43", 1252079f7aaSVijay Thakkar "BriefDescription": "Demand Data Cache Fills by Data Source. DRAM or IO from this thread's die.", 1262079f7aaSVijay Thakkar "UMask": "0x8" 1272079f7aaSVijay Thakkar }, 1282079f7aaSVijay Thakkar { 1292079f7aaSVijay Thakkar "EventName": "ls_refills_from_sys.ls_mabresp_lcl_cache", 1302079f7aaSVijay Thakkar "EventCode": "0x43", 1312079f7aaSVijay Thakkar "BriefDescription": "Demand Data Cache Fills by Data Source. Hit in cache; local CCX (not Local L2), or Remote CCX and the address's Home Node is on this thread's die.", 1322079f7aaSVijay Thakkar "UMask": "0x2" 1332079f7aaSVijay Thakkar }, 1342079f7aaSVijay Thakkar { 1352079f7aaSVijay Thakkar "EventName": "ls_refills_from_sys.ls_mabresp_lcl_l2", 1362079f7aaSVijay Thakkar "EventCode": "0x43", 1372079f7aaSVijay Thakkar "BriefDescription": "Demand Data Cache Fills by Data Source. Local L2 hit.", 1382079f7aaSVijay Thakkar "UMask": "0x1" 1392079f7aaSVijay Thakkar }, 1402079f7aaSVijay Thakkar { 1412079f7aaSVijay Thakkar "EventName": "ls_l1_d_tlb_miss.all", 1422079f7aaSVijay Thakkar "EventCode": "0x45", 1432079f7aaSVijay Thakkar "BriefDescription": "All L1 DTLB Misses or Reloads.", 1442079f7aaSVijay Thakkar "UMask": "0xff" 1452079f7aaSVijay Thakkar }, 1462079f7aaSVijay Thakkar { 1472079f7aaSVijay Thakkar "EventName": "ls_l1_d_tlb_miss.tlb_reload_1g_l2_miss", 1482079f7aaSVijay Thakkar "EventCode": "0x45", 1492079f7aaSVijay Thakkar "BriefDescription": "L1 DTLB Miss. DTLB reload to a 1G page that miss in the L2 TLB.", 1502079f7aaSVijay Thakkar "UMask": "0x80" 1512079f7aaSVijay Thakkar }, 1522079f7aaSVijay Thakkar { 1532079f7aaSVijay Thakkar "EventName": "ls_l1_d_tlb_miss.tlb_reload_2m_l2_miss", 1542079f7aaSVijay Thakkar "EventCode": "0x45", 1552079f7aaSVijay Thakkar "BriefDescription": "L1 DTLB Miss. DTLB reload to a 2M page that miss in the L2 TLB.", 1562079f7aaSVijay Thakkar "UMask": "0x40" 1572079f7aaSVijay Thakkar }, 1582079f7aaSVijay Thakkar { 1592079f7aaSVijay Thakkar "EventName": "ls_l1_d_tlb_miss.tlb_reload_coalesced_page_miss", 1602079f7aaSVijay Thakkar "EventCode": "0x45", 1612079f7aaSVijay Thakkar "BriefDescription": "L1 DTLB Miss. DTLB reload coalesced page miss.", 1622079f7aaSVijay Thakkar "UMask": "0x20" 1632079f7aaSVijay Thakkar }, 1642079f7aaSVijay Thakkar { 1652079f7aaSVijay Thakkar "EventName": "ls_l1_d_tlb_miss.tlb_reload_4k_l2_miss", 1662079f7aaSVijay Thakkar "EventCode": "0x45", 1672079f7aaSVijay Thakkar "BriefDescription": "L1 DTLB Miss. DTLB reload to a 4K page that miss the L2 TLB.", 1682079f7aaSVijay Thakkar "UMask": "0x10" 1692079f7aaSVijay Thakkar }, 1702079f7aaSVijay Thakkar { 1712079f7aaSVijay Thakkar "EventName": "ls_l1_d_tlb_miss.tlb_reload_1g_l2_hit", 1722079f7aaSVijay Thakkar "EventCode": "0x45", 1732079f7aaSVijay Thakkar "BriefDescription": "L1 DTLB Miss. DTLB reload to a 1G page that hit in the L2 TLB.", 1742079f7aaSVijay Thakkar "UMask": "0x8" 1752079f7aaSVijay Thakkar }, 1762079f7aaSVijay Thakkar { 1772079f7aaSVijay Thakkar "EventName": "ls_l1_d_tlb_miss.tlb_reload_2m_l2_hit", 1782079f7aaSVijay Thakkar "EventCode": "0x45", 1792079f7aaSVijay Thakkar "BriefDescription": "L1 DTLB Miss. DTLB reload to a 2M page that hit in the L2 TLB.", 1802079f7aaSVijay Thakkar "UMask": "0x4" 1812079f7aaSVijay Thakkar }, 1822079f7aaSVijay Thakkar { 1832079f7aaSVijay Thakkar "EventName": "ls_l1_d_tlb_miss.tlb_reload_coalesced_page_hit", 1842079f7aaSVijay Thakkar "EventCode": "0x45", 1852079f7aaSVijay Thakkar "BriefDescription": "L1 DTLB Miss. DTLB reload hit a coalesced page.", 1862079f7aaSVijay Thakkar "UMask": "0x2" 1872079f7aaSVijay Thakkar }, 1882079f7aaSVijay Thakkar { 1892079f7aaSVijay Thakkar "EventName": "ls_l1_d_tlb_miss.tlb_reload_4k_l2_hit", 1902079f7aaSVijay Thakkar "EventCode": "0x45", 1912079f7aaSVijay Thakkar "BriefDescription": "L1 DTLB Miss. DTLB reload to a 4K page that hit in the L2 TLB.", 1922079f7aaSVijay Thakkar "UMask": "0x1" 1932079f7aaSVijay Thakkar }, 1942079f7aaSVijay Thakkar { 1952079f7aaSVijay Thakkar "EventName": "ls_tablewalker.iside", 1962079f7aaSVijay Thakkar "EventCode": "0x46", 1972079f7aaSVijay Thakkar "BriefDescription": "Total Page Table Walks on I-side.", 1982079f7aaSVijay Thakkar "UMask": "0xc" 1992079f7aaSVijay Thakkar }, 2002079f7aaSVijay Thakkar { 2012079f7aaSVijay Thakkar "EventName": "ls_tablewalker.ic_type1", 2022079f7aaSVijay Thakkar "EventCode": "0x46", 2032079f7aaSVijay Thakkar "BriefDescription": "Total Page Table Walks IC Type 1.", 2042079f7aaSVijay Thakkar "UMask": "0x8" 2052079f7aaSVijay Thakkar }, 2062079f7aaSVijay Thakkar { 2072079f7aaSVijay Thakkar "EventName": "ls_tablewalker.ic_type0", 2082079f7aaSVijay Thakkar "EventCode": "0x46", 2092079f7aaSVijay Thakkar "BriefDescription": "Total Page Table Walks IC Type 0.", 2102079f7aaSVijay Thakkar "UMask": "0x4" 2112079f7aaSVijay Thakkar }, 2122079f7aaSVijay Thakkar { 2132079f7aaSVijay Thakkar "EventName": "ls_tablewalker.dside", 2142079f7aaSVijay Thakkar "EventCode": "0x46", 2152079f7aaSVijay Thakkar "BriefDescription": "Total Page Table Walks on D-side.", 2162079f7aaSVijay Thakkar "UMask": "0x3" 2172079f7aaSVijay Thakkar }, 2182079f7aaSVijay Thakkar { 2192079f7aaSVijay Thakkar "EventName": "ls_tablewalker.dc_type1", 2202079f7aaSVijay Thakkar "EventCode": "0x46", 2212079f7aaSVijay Thakkar "BriefDescription": "Total Page Table Walks DC Type 1.", 2222079f7aaSVijay Thakkar "UMask": "0x2" 2232079f7aaSVijay Thakkar }, 2242079f7aaSVijay Thakkar { 2252079f7aaSVijay Thakkar "EventName": "ls_tablewalker.dc_type0", 2262079f7aaSVijay Thakkar "EventCode": "0x46", 2272079f7aaSVijay Thakkar "BriefDescription": "Total Page Table Walks DC Type 0.", 2282079f7aaSVijay Thakkar "UMask": "0x1" 2292079f7aaSVijay Thakkar }, 2302079f7aaSVijay Thakkar { 2312079f7aaSVijay Thakkar "EventName": "ls_misal_accesses", 2322079f7aaSVijay Thakkar "EventCode": "0x47", 2332079f7aaSVijay Thakkar "BriefDescription": "Misaligned loads." 2342079f7aaSVijay Thakkar }, 2352079f7aaSVijay Thakkar { 2362079f7aaSVijay Thakkar "EventName": "ls_pref_instr_disp", 2372079f7aaSVijay Thakkar "EventCode": "0x4b", 2382079f7aaSVijay Thakkar "BriefDescription": "Software Prefetch Instructions Dispatched (Speculative).", 2392079f7aaSVijay Thakkar "UMask": "0xff" 2402079f7aaSVijay Thakkar }, 2412079f7aaSVijay Thakkar { 2422079f7aaSVijay Thakkar "EventName": "ls_pref_instr_disp.prefetch_nta", 2432079f7aaSVijay Thakkar "EventCode": "0x4b", 2442079f7aaSVijay Thakkar "BriefDescription": "Software Prefetch Instructions Dispatched (Speculative). PrefetchNTA instruction. See docAPM3 PREFETCHlevel.", 2452079f7aaSVijay Thakkar "UMask": "0x4" 2462079f7aaSVijay Thakkar }, 2472079f7aaSVijay Thakkar { 2482079f7aaSVijay Thakkar "EventName": "ls_pref_instr_disp.prefetch_w", 2492079f7aaSVijay Thakkar "EventCode": "0x4b", 2502079f7aaSVijay Thakkar "BriefDescription": "Software Prefetch Instructions Dispatched (Speculative). See docAPM3 PREFETCHW.", 2512079f7aaSVijay Thakkar "UMask": "0x2" 2522079f7aaSVijay Thakkar }, 2532079f7aaSVijay Thakkar { 2542079f7aaSVijay Thakkar "EventName": "ls_pref_instr_disp.prefetch", 2552079f7aaSVijay Thakkar "EventCode": "0x4b", 2562079f7aaSVijay Thakkar "BriefDescription": "Software Prefetch Instructions Dispatched (Speculative). Prefetch_T0_T1_T2. PrefetchT0, T1 and T2 instructions. See docAPM3 PREFETCHlevel.", 2572079f7aaSVijay Thakkar "UMask": "0x1" 2582079f7aaSVijay Thakkar }, 2592079f7aaSVijay Thakkar { 2602079f7aaSVijay Thakkar "EventName": "ls_inef_sw_pref.mab_mch_cnt", 2612079f7aaSVijay Thakkar "EventCode": "0x52", 2622079f7aaSVijay Thakkar "BriefDescription": "The number of software prefetches that did not fetch data outside of the processor core. Software PREFETCH instruction saw a match on an already-allocated miss request buffer.", 2632079f7aaSVijay Thakkar "UMask": "0x2" 2642079f7aaSVijay Thakkar }, 2652079f7aaSVijay Thakkar { 2662079f7aaSVijay Thakkar "EventName": "ls_inef_sw_pref.data_pipe_sw_pf_dc_hit", 2672079f7aaSVijay Thakkar "EventCode": "0x52", 2682079f7aaSVijay Thakkar "BriefDescription": "The number of software prefetches that did not fetch data outside of the processor core. Software PREFETCH instruction saw a DC hit.", 2692079f7aaSVijay Thakkar "UMask": "0x1" 2702079f7aaSVijay Thakkar }, 2712079f7aaSVijay Thakkar { 2722079f7aaSVijay Thakkar "EventName": "ls_sw_pf_dc_fill.ls_mabresp_rmt_dram", 2732079f7aaSVijay Thakkar "EventCode": "0x59", 2742079f7aaSVijay Thakkar "BriefDescription": "Software Prefetch Data Cache Fills by Data Source. From DRAM (home node remote).", 2752079f7aaSVijay Thakkar "UMask": "0x40" 2762079f7aaSVijay Thakkar }, 2772079f7aaSVijay Thakkar { 2782079f7aaSVijay Thakkar "EventName": "ls_sw_pf_dc_fill.ls_mabresp_rmt_cache", 2792079f7aaSVijay Thakkar "EventCode": "0x59", 2802079f7aaSVijay Thakkar "BriefDescription": "Software Prefetch Data Cache Fills by Data Source. From another cache (home node remote).", 2812079f7aaSVijay Thakkar "UMask": "0x10" 2822079f7aaSVijay Thakkar }, 2832079f7aaSVijay Thakkar { 2842079f7aaSVijay Thakkar "EventName": "ls_sw_pf_dc_fill.ls_mabresp_lcl_dram", 2852079f7aaSVijay Thakkar "EventCode": "0x59", 2862079f7aaSVijay Thakkar "BriefDescription": "Software Prefetch Data Cache Fills by Data Source. DRAM or IO from this thread's die. From DRAM (home node local).", 2872079f7aaSVijay Thakkar "UMask": "0x8" 2882079f7aaSVijay Thakkar }, 2892079f7aaSVijay Thakkar { 2902079f7aaSVijay Thakkar "EventName": "ls_sw_pf_dc_fill.ls_mabresp_lcl_cache", 2912079f7aaSVijay Thakkar "EventCode": "0x59", 2922079f7aaSVijay Thakkar "BriefDescription": "Software Prefetch Data Cache Fills by Data Source. From another cache (home node local).", 2932079f7aaSVijay Thakkar "UMask": "0x2" 2942079f7aaSVijay Thakkar }, 2952079f7aaSVijay Thakkar { 2962079f7aaSVijay Thakkar "EventName": "ls_sw_pf_dc_fill.ls_mabresp_lcl_l2", 2972079f7aaSVijay Thakkar "EventCode": "0x59", 2982079f7aaSVijay Thakkar "BriefDescription": "Software Prefetch Data Cache Fills by Data Source. Local L2 hit.", 2992079f7aaSVijay Thakkar "UMask": "0x1" 3002079f7aaSVijay Thakkar }, 3012079f7aaSVijay Thakkar { 3022079f7aaSVijay Thakkar "EventName": "ls_hw_pf_dc_fill.ls_mabresp_rmt_dram", 303*ff64c981SSmita Koralahalli "EventCode": "0x5a", 3042079f7aaSVijay Thakkar "BriefDescription": "Hardware Prefetch Data Cache Fills by Data Source. From DRAM (home node remote).", 3052079f7aaSVijay Thakkar "UMask": "0x40" 3062079f7aaSVijay Thakkar }, 3072079f7aaSVijay Thakkar { 3082079f7aaSVijay Thakkar "EventName": "ls_hw_pf_dc_fill.ls_mabresp_rmt_cache", 309*ff64c981SSmita Koralahalli "EventCode": "0x5a", 3102079f7aaSVijay Thakkar "BriefDescription": "Hardware Prefetch Data Cache Fills by Data Source. From another cache (home node remote).", 3112079f7aaSVijay Thakkar "UMask": "0x10" 3122079f7aaSVijay Thakkar }, 3132079f7aaSVijay Thakkar { 3142079f7aaSVijay Thakkar "EventName": "ls_hw_pf_dc_fill.ls_mabresp_lcl_dram", 315*ff64c981SSmita Koralahalli "EventCode": "0x5a", 3162079f7aaSVijay Thakkar "BriefDescription": "Hardware Prefetch Data Cache Fills by Data Source. From DRAM (home node local).", 3172079f7aaSVijay Thakkar "UMask": "0x8" 3182079f7aaSVijay Thakkar }, 3192079f7aaSVijay Thakkar { 3202079f7aaSVijay Thakkar "EventName": "ls_hw_pf_dc_fill.ls_mabresp_lcl_cache", 321*ff64c981SSmita Koralahalli "EventCode": "0x5a", 3222079f7aaSVijay Thakkar "BriefDescription": "Hardware Prefetch Data Cache Fills by Data Source. From another cache (home node local).", 3232079f7aaSVijay Thakkar "UMask": "0x2" 3242079f7aaSVijay Thakkar }, 3252079f7aaSVijay Thakkar { 3262079f7aaSVijay Thakkar "EventName": "ls_hw_pf_dc_fill.ls_mabresp_lcl_l2", 327*ff64c981SSmita Koralahalli "EventCode": "0x5a", 3282079f7aaSVijay Thakkar "BriefDescription": "Hardware Prefetch Data Cache Fills by Data Source. Local L2 hit.", 3292079f7aaSVijay Thakkar "UMask": "0x1" 3302079f7aaSVijay Thakkar }, 3312079f7aaSVijay Thakkar { 3322079f7aaSVijay Thakkar "EventName": "ls_not_halted_cyc", 3332079f7aaSVijay Thakkar "EventCode": "0x76", 3342079f7aaSVijay Thakkar "BriefDescription": "Cycles not in Halt." 3352079f7aaSVijay Thakkar }, 3362079f7aaSVijay Thakkar { 3372079f7aaSVijay Thakkar "EventName": "ls_tlb_flush", 3382079f7aaSVijay Thakkar "EventCode": "0x78", 3392079f7aaSVijay Thakkar "BriefDescription": "All TLB Flushes" 3402079f7aaSVijay Thakkar } 3412079f7aaSVijay Thakkar] 342