1c5f18e9eSVijay Thakkar[ 2c5f18e9eSVijay Thakkar { 3c5f18e9eSVijay Thakkar "EventName": "ls_locks.bus_lock", 4c5f18e9eSVijay Thakkar "EventCode": "0x25", 5c5f18e9eSVijay Thakkar "BriefDescription": "Bus lock when a locked operations crosses a cache boundary or is done on an uncacheable memory type.", 6c5f18e9eSVijay Thakkar "PublicDescription": "Bus lock when a locked operations crosses a cache boundary or is done on an uncacheable memory type.", 7c5f18e9eSVijay Thakkar "UMask": "0x1" 8c5f18e9eSVijay Thakkar }, 9c5f18e9eSVijay Thakkar { 10c5f18e9eSVijay Thakkar "EventName": "ls_dispatch.ld_st_dispatch", 11c5f18e9eSVijay Thakkar "EventCode": "0x29", 12c5f18e9eSVijay Thakkar "BriefDescription": "Load-op-Stores.", 13c5f18e9eSVijay Thakkar "PublicDescription": "Counts the number of operations dispatched to the LS unit. Unit Masks ADDed. Load-op-Stores.", 14c5f18e9eSVijay Thakkar "UMask": "0x4" 15c5f18e9eSVijay Thakkar }, 16c5f18e9eSVijay Thakkar { 17c5f18e9eSVijay Thakkar "EventName": "ls_dispatch.store_dispatch", 18c5f18e9eSVijay Thakkar "EventCode": "0x29", 19c5f18e9eSVijay Thakkar "BriefDescription": "Counts the number of operations dispatched to the LS unit. Unit Masks ADDed.", 20c5f18e9eSVijay Thakkar "PublicDescription": "Counts the number of operations dispatched to the LS unit. Unit Masks ADDed.", 21c5f18e9eSVijay Thakkar "UMask": "0x2" 22c5f18e9eSVijay Thakkar }, 23c5f18e9eSVijay Thakkar { 24c5f18e9eSVijay Thakkar "EventName": "ls_dispatch.ld_dispatch", 25c5f18e9eSVijay Thakkar "EventCode": "0x29", 26c5f18e9eSVijay Thakkar "BriefDescription": "Counts the number of operations dispatched to the LS unit. Unit Masks ADDed.", 27c5f18e9eSVijay Thakkar "PublicDescription": "Counts the number of operations dispatched to the LS unit. Unit Masks ADDed.", 28c5f18e9eSVijay Thakkar "UMask": "0x1" 29c5f18e9eSVijay Thakkar }, 30c5f18e9eSVijay Thakkar { 31c5f18e9eSVijay Thakkar "EventName": "ls_stlf", 32c5f18e9eSVijay Thakkar "EventCode": "0x35", 33c5f18e9eSVijay Thakkar "BriefDescription": "Number of STLF hits." 34c5f18e9eSVijay Thakkar }, 35c5f18e9eSVijay Thakkar { 36c5f18e9eSVijay Thakkar "EventName": "ls_dc_accesses", 37c5f18e9eSVijay Thakkar "EventCode": "0x40", 38c5f18e9eSVijay Thakkar "BriefDescription": "The number of accesses to the data cache for load and store references. This may include certain microcode scratchpad accesses, although these are generally rare. Each increment represents an eight-byte access, although the instruction may only be accessing a portion of that. This event is a speculative event." 39c5f18e9eSVijay Thakkar }, 40c5f18e9eSVijay Thakkar { 41c5f18e9eSVijay Thakkar "EventName": "ls_l1_d_tlb_miss.all", 42c5f18e9eSVijay Thakkar "EventCode": "0x45", 43c5f18e9eSVijay Thakkar "BriefDescription": "L1 DTLB Miss or Reload off all sizes.", 44c5f18e9eSVijay Thakkar "PublicDescription": "L1 DTLB Miss or Reload off all sizes.", 45c5f18e9eSVijay Thakkar "UMask": "0xff" 46c5f18e9eSVijay Thakkar }, 47c5f18e9eSVijay Thakkar { 48c5f18e9eSVijay Thakkar "EventName": "ls_l1_d_tlb_miss.tlb_reload_1g_l2_miss", 49c5f18e9eSVijay Thakkar "EventCode": "0x45", 50c5f18e9eSVijay Thakkar "BriefDescription": "L1 DTLB Miss of a page of 1G size.", 51c5f18e9eSVijay Thakkar "PublicDescription": "L1 DTLB Miss of a page of 1G size.", 52c5f18e9eSVijay Thakkar "UMask": "0x80" 53c5f18e9eSVijay Thakkar }, 54c5f18e9eSVijay Thakkar { 55c5f18e9eSVijay Thakkar "EventName": "ls_l1_d_tlb_miss.tlb_reload_2m_l2_miss", 56c5f18e9eSVijay Thakkar "EventCode": "0x45", 57c5f18e9eSVijay Thakkar "BriefDescription": "L1 DTLB Miss of a page of 2M size.", 58c5f18e9eSVijay Thakkar "PublicDescription": "L1 DTLB Miss of a page of 2M size.", 59c5f18e9eSVijay Thakkar "UMask": "0x40" 60c5f18e9eSVijay Thakkar }, 61c5f18e9eSVijay Thakkar { 62c5f18e9eSVijay Thakkar "EventName": "ls_l1_d_tlb_miss.tlb_reload_32k_l2_miss", 63c5f18e9eSVijay Thakkar "EventCode": "0x45", 64c5f18e9eSVijay Thakkar "BriefDescription": "L1 DTLB Miss of a page of 32K size.", 65c5f18e9eSVijay Thakkar "PublicDescription": "L1 DTLB Miss of a page of 32K size.", 66c5f18e9eSVijay Thakkar "UMask": "0x20" 67c5f18e9eSVijay Thakkar }, 68c5f18e9eSVijay Thakkar { 69c5f18e9eSVijay Thakkar "EventName": "ls_l1_d_tlb_miss.tlb_reload_4k_l2_miss", 70c5f18e9eSVijay Thakkar "EventCode": "0x45", 71c5f18e9eSVijay Thakkar "BriefDescription": "L1 DTLB Miss of a page of 4K size.", 72c5f18e9eSVijay Thakkar "PublicDescription": "L1 DTLB Miss of a page of 4K size.", 73c5f18e9eSVijay Thakkar "UMask": "0x10" 74c5f18e9eSVijay Thakkar }, 75c5f18e9eSVijay Thakkar { 76c5f18e9eSVijay Thakkar "EventName": "ls_l1_d_tlb_miss.tlb_reload_1g_l2_hit", 77c5f18e9eSVijay Thakkar "EventCode": "0x45", 78c5f18e9eSVijay Thakkar "BriefDescription": "L1 DTLB Reload of a page of 1G size.", 79c5f18e9eSVijay Thakkar "PublicDescription": "L1 DTLB Reload of a page of 1G size.", 80c5f18e9eSVijay Thakkar "UMask": "0x8" 81c5f18e9eSVijay Thakkar }, 82c5f18e9eSVijay Thakkar { 83c5f18e9eSVijay Thakkar "EventName": "ls_l1_d_tlb_miss.tlb_reload_2m_l2_hit", 84c5f18e9eSVijay Thakkar "EventCode": "0x45", 85c5f18e9eSVijay Thakkar "BriefDescription": "L1 DTLB Reload of a page of 2M size.", 86c5f18e9eSVijay Thakkar "PublicDescription": "L1 DTLB Reload of a page of 2M size.", 87c5f18e9eSVijay Thakkar "UMask": "0x4" 88c5f18e9eSVijay Thakkar }, 89c5f18e9eSVijay Thakkar { 90c5f18e9eSVijay Thakkar "EventName": "ls_l1_d_tlb_miss.tlb_reload_32k_l2_hit", 91c5f18e9eSVijay Thakkar "EventCode": "0x45", 92c5f18e9eSVijay Thakkar "BriefDescription": "L1 DTLB Reload of a page of 32K size.", 93c5f18e9eSVijay Thakkar "PublicDescription": "L1 DTLB Reload of a page of 32K size.", 94c5f18e9eSVijay Thakkar "UMask": "0x2" 95c5f18e9eSVijay Thakkar }, 96c5f18e9eSVijay Thakkar { 97c5f18e9eSVijay Thakkar "EventName": "ls_l1_d_tlb_miss.tlb_reload_4k_l2_hit", 98c5f18e9eSVijay Thakkar "EventCode": "0x45", 99c5f18e9eSVijay Thakkar "BriefDescription": "L1 DTLB Reload of a page of 4K size.", 100c5f18e9eSVijay Thakkar "PublicDescription": "L1 DTLB Reload of a page of 4K size.", 101c5f18e9eSVijay Thakkar "UMask": "0x1" 102c5f18e9eSVijay Thakkar }, 103c5f18e9eSVijay Thakkar { 104c5f18e9eSVijay Thakkar "EventName": "ls_tablewalker.perf_mon_tablewalk_alloc_iside", 105c5f18e9eSVijay Thakkar "EventCode": "0x46", 106c5f18e9eSVijay Thakkar "BriefDescription": "Tablewalker allocation.", 107c5f18e9eSVijay Thakkar "PublicDescription": "Tablewalker allocation.", 108c5f18e9eSVijay Thakkar "UMask": "0xc" 109c5f18e9eSVijay Thakkar }, 110c5f18e9eSVijay Thakkar { 111c5f18e9eSVijay Thakkar "EventName": "ls_tablewalker.perf_mon_tablewalk_alloc_dside", 112c5f18e9eSVijay Thakkar "EventCode": "0x46", 113c5f18e9eSVijay Thakkar "BriefDescription": "Tablewalker allocation.", 114c5f18e9eSVijay Thakkar "PublicDescription": "Tablewalker allocation.", 115c5f18e9eSVijay Thakkar "UMask": "0x3" 116c5f18e9eSVijay Thakkar }, 117c5f18e9eSVijay Thakkar { 118c5f18e9eSVijay Thakkar "EventName": "ls_misal_accesses", 119c5f18e9eSVijay Thakkar "EventCode": "0x47", 120c5f18e9eSVijay Thakkar "BriefDescription": "Misaligned loads." 121c5f18e9eSVijay Thakkar }, 122c5f18e9eSVijay Thakkar { 123c5f18e9eSVijay Thakkar "EventName": "ls_pref_instr_disp.prefetch_nta", 124c5f18e9eSVijay Thakkar "EventCode": "0x4b", 125c5f18e9eSVijay Thakkar "BriefDescription": "Software Prefetch Instructions (PREFETCHNTA instruction) Dispatched.", 126c5f18e9eSVijay Thakkar "PublicDescription": "Software Prefetch Instructions (PREFETCHNTA instruction) Dispatched.", 127c5f18e9eSVijay Thakkar "UMask": "0x4" 128c5f18e9eSVijay Thakkar }, 129c5f18e9eSVijay Thakkar { 130c5f18e9eSVijay Thakkar "EventName": "ls_pref_instr_disp.store_prefetch_w", 131c5f18e9eSVijay Thakkar "EventCode": "0x4b", 132c5f18e9eSVijay Thakkar "BriefDescription": "Software Prefetch Instructions (3DNow PREFETCHW instruction) Dispatched.", 133c5f18e9eSVijay Thakkar "PublicDescription": "Software Prefetch Instructions (3DNow PREFETCHW instruction) Dispatched.", 134c5f18e9eSVijay Thakkar "UMask": "0x2" 135c5f18e9eSVijay Thakkar }, 136c5f18e9eSVijay Thakkar { 137c5f18e9eSVijay Thakkar "EventName": "ls_pref_instr_disp.load_prefetch_w", 138c5f18e9eSVijay Thakkar "EventCode": "0x4b", 139c5f18e9eSVijay Thakkar "BriefDescription": "Prefetch, Prefetch_T0_T1_T2.", 140c5f18e9eSVijay Thakkar "PublicDescription": "Software Prefetch Instructions Dispatched. Prefetch, Prefetch_T0_T1_T2.", 141c5f18e9eSVijay Thakkar "UMask": "0x1" 142c5f18e9eSVijay Thakkar }, 143c5f18e9eSVijay Thakkar { 144c5f18e9eSVijay Thakkar "EventName": "ls_inef_sw_pref.mab_mch_cnt", 145c5f18e9eSVijay Thakkar "EventCode": "0x52", 146c5f18e9eSVijay Thakkar "BriefDescription": "The number of software prefetches that did not fetch data outside of the processor core.", 147c5f18e9eSVijay Thakkar "PublicDescription": "The number of software prefetches that did not fetch data outside of the processor core.", 148c5f18e9eSVijay Thakkar "UMask": "0x2" 149c5f18e9eSVijay Thakkar }, 150c5f18e9eSVijay Thakkar { 151c5f18e9eSVijay Thakkar "EventName": "ls_inef_sw_pref.data_pipe_sw_pf_dc_hit", 152c5f18e9eSVijay Thakkar "EventCode": "0x52", 153c5f18e9eSVijay Thakkar "BriefDescription": "The number of software prefetches that did not fetch data outside of the processor core.", 154c5f18e9eSVijay Thakkar "PublicDescription": "The number of software prefetches that did not fetch data outside of the processor core.", 155c5f18e9eSVijay Thakkar "UMask": "0x1" 156c5f18e9eSVijay Thakkar }, 157c5f18e9eSVijay Thakkar { 158c5f18e9eSVijay Thakkar "EventName": "ls_not_halted_cyc", 159c5f18e9eSVijay Thakkar "EventCode": "0x76", 160c5f18e9eSVijay Thakkar "BriefDescription": "Cycles not in Halt." 161c5f18e9eSVijay Thakkar } 162c5f18e9eSVijay Thakkar] 163