1c5f18e9eSVijay Thakkar[ 2c5f18e9eSVijay Thakkar { 3c5f18e9eSVijay Thakkar "EventName": "ls_locks.bus_lock", 4c5f18e9eSVijay Thakkar "EventCode": "0x25", 5c5f18e9eSVijay Thakkar "BriefDescription": "Bus lock when a locked operations crosses a cache boundary or is done on an uncacheable memory type.", 6c5f18e9eSVijay Thakkar "UMask": "0x1" 7c5f18e9eSVijay Thakkar }, 8c5f18e9eSVijay Thakkar { 9c5f18e9eSVijay Thakkar "EventName": "ls_dispatch.ld_st_dispatch", 10c5f18e9eSVijay Thakkar "EventCode": "0x29", 11b5b8a7cfSVijay Thakkar "BriefDescription": "Counts the number of operations dispatched to the LS unit. Unit Masks ADDed. Load-op-Stores.", 12c5f18e9eSVijay Thakkar "UMask": "0x4" 13c5f18e9eSVijay Thakkar }, 14c5f18e9eSVijay Thakkar { 15c5f18e9eSVijay Thakkar "EventName": "ls_dispatch.store_dispatch", 16c5f18e9eSVijay Thakkar "EventCode": "0x29", 17b5b8a7cfSVijay Thakkar "BriefDescription": "Counts the number of stores dispatched to the LS unit. Unit Masks ADDed.", 18c5f18e9eSVijay Thakkar "UMask": "0x2" 19c5f18e9eSVijay Thakkar }, 20c5f18e9eSVijay Thakkar { 21c5f18e9eSVijay Thakkar "EventName": "ls_dispatch.ld_dispatch", 22c5f18e9eSVijay Thakkar "EventCode": "0x29", 23b5b8a7cfSVijay Thakkar "BriefDescription": "Counts the number of loads dispatched to the LS unit. Unit Masks ADDed.", 24c5f18e9eSVijay Thakkar "UMask": "0x1" 25c5f18e9eSVijay Thakkar }, 26c5f18e9eSVijay Thakkar { 27c5f18e9eSVijay Thakkar "EventName": "ls_stlf", 28c5f18e9eSVijay Thakkar "EventCode": "0x35", 29c5f18e9eSVijay Thakkar "BriefDescription": "Number of STLF hits." 30c5f18e9eSVijay Thakkar }, 31c5f18e9eSVijay Thakkar { 32c5f18e9eSVijay Thakkar "EventName": "ls_dc_accesses", 33c5f18e9eSVijay Thakkar "EventCode": "0x40", 34c5f18e9eSVijay Thakkar "BriefDescription": "The number of accesses to the data cache for load and store references. This may include certain microcode scratchpad accesses, although these are generally rare. Each increment represents an eight-byte access, although the instruction may only be accessing a portion of that. This event is a speculative event." 35c5f18e9eSVijay Thakkar }, 36c5f18e9eSVijay Thakkar { 37b5b8a7cfSVijay Thakkar "EventName": "ls_mab_alloc.dc_prefetcher", 38b5b8a7cfSVijay Thakkar "EventCode": "0x41", 39b5b8a7cfSVijay Thakkar "BriefDescription": "LS MAB allocates by type - DC prefetcher.", 40b5b8a7cfSVijay Thakkar "UMask": "0x8" 41b5b8a7cfSVijay Thakkar }, 42b5b8a7cfSVijay Thakkar { 43b5b8a7cfSVijay Thakkar "EventName": "ls_mab_alloc.stores", 44b5b8a7cfSVijay Thakkar "EventCode": "0x41", 45b5b8a7cfSVijay Thakkar "BriefDescription": "LS MAB allocates by type - stores.", 46b5b8a7cfSVijay Thakkar "UMask": "0x2" 47b5b8a7cfSVijay Thakkar }, 48b5b8a7cfSVijay Thakkar { 49b5b8a7cfSVijay Thakkar "EventName": "ls_mab_alloc.loads", 50b5b8a7cfSVijay Thakkar "EventCode": "0x41", 51b5b8a7cfSVijay Thakkar "BriefDescription": "LS MAB allocates by type - loads.", 52b5b8a7cfSVijay Thakkar "UMask": "0x01" 53b5b8a7cfSVijay Thakkar }, 54b5b8a7cfSVijay Thakkar { 55c5f18e9eSVijay Thakkar "EventName": "ls_l1_d_tlb_miss.all", 56c5f18e9eSVijay Thakkar "EventCode": "0x45", 57c5f18e9eSVijay Thakkar "BriefDescription": "L1 DTLB Miss or Reload off all sizes.", 58c5f18e9eSVijay Thakkar "UMask": "0xff" 59c5f18e9eSVijay Thakkar }, 60c5f18e9eSVijay Thakkar { 61c5f18e9eSVijay Thakkar "EventName": "ls_l1_d_tlb_miss.tlb_reload_1g_l2_miss", 62c5f18e9eSVijay Thakkar "EventCode": "0x45", 63c5f18e9eSVijay Thakkar "BriefDescription": "L1 DTLB Miss of a page of 1G size.", 64c5f18e9eSVijay Thakkar "UMask": "0x80" 65c5f18e9eSVijay Thakkar }, 66c5f18e9eSVijay Thakkar { 67c5f18e9eSVijay Thakkar "EventName": "ls_l1_d_tlb_miss.tlb_reload_2m_l2_miss", 68c5f18e9eSVijay Thakkar "EventCode": "0x45", 69c5f18e9eSVijay Thakkar "BriefDescription": "L1 DTLB Miss of a page of 2M size.", 70c5f18e9eSVijay Thakkar "UMask": "0x40" 71c5f18e9eSVijay Thakkar }, 72c5f18e9eSVijay Thakkar { 73c5f18e9eSVijay Thakkar "EventName": "ls_l1_d_tlb_miss.tlb_reload_32k_l2_miss", 74c5f18e9eSVijay Thakkar "EventCode": "0x45", 75c5f18e9eSVijay Thakkar "BriefDescription": "L1 DTLB Miss of a page of 32K size.", 76c5f18e9eSVijay Thakkar "UMask": "0x20" 77c5f18e9eSVijay Thakkar }, 78c5f18e9eSVijay Thakkar { 79c5f18e9eSVijay Thakkar "EventName": "ls_l1_d_tlb_miss.tlb_reload_4k_l2_miss", 80c5f18e9eSVijay Thakkar "EventCode": "0x45", 81c5f18e9eSVijay Thakkar "BriefDescription": "L1 DTLB Miss of a page of 4K size.", 82c5f18e9eSVijay Thakkar "UMask": "0x10" 83c5f18e9eSVijay Thakkar }, 84c5f18e9eSVijay Thakkar { 85c5f18e9eSVijay Thakkar "EventName": "ls_l1_d_tlb_miss.tlb_reload_1g_l2_hit", 86c5f18e9eSVijay Thakkar "EventCode": "0x45", 87c5f18e9eSVijay Thakkar "BriefDescription": "L1 DTLB Reload of a page of 1G size.", 88c5f18e9eSVijay Thakkar "UMask": "0x8" 89c5f18e9eSVijay Thakkar }, 90c5f18e9eSVijay Thakkar { 91c5f18e9eSVijay Thakkar "EventName": "ls_l1_d_tlb_miss.tlb_reload_2m_l2_hit", 92c5f18e9eSVijay Thakkar "EventCode": "0x45", 93c5f18e9eSVijay Thakkar "BriefDescription": "L1 DTLB Reload of a page of 2M size.", 94c5f18e9eSVijay Thakkar "UMask": "0x4" 95c5f18e9eSVijay Thakkar }, 96c5f18e9eSVijay Thakkar { 97c5f18e9eSVijay Thakkar "EventName": "ls_l1_d_tlb_miss.tlb_reload_32k_l2_hit", 98c5f18e9eSVijay Thakkar "EventCode": "0x45", 99c5f18e9eSVijay Thakkar "BriefDescription": "L1 DTLB Reload of a page of 32K size.", 100c5f18e9eSVijay Thakkar "UMask": "0x2" 101c5f18e9eSVijay Thakkar }, 102c5f18e9eSVijay Thakkar { 103c5f18e9eSVijay Thakkar "EventName": "ls_l1_d_tlb_miss.tlb_reload_4k_l2_hit", 104c5f18e9eSVijay Thakkar "EventCode": "0x45", 105c5f18e9eSVijay Thakkar "BriefDescription": "L1 DTLB Reload of a page of 4K size.", 106c5f18e9eSVijay Thakkar "UMask": "0x1" 107c5f18e9eSVijay Thakkar }, 108c5f18e9eSVijay Thakkar { 109b5b8a7cfSVijay Thakkar "EventName": "ls_tablewalker.iside", 110c5f18e9eSVijay Thakkar "EventCode": "0x46", 111b5b8a7cfSVijay Thakkar "BriefDescription": "Total Page Table Walks on I-side.", 112c5f18e9eSVijay Thakkar "UMask": "0xc" 113c5f18e9eSVijay Thakkar }, 114c5f18e9eSVijay Thakkar { 115b5b8a7cfSVijay Thakkar "EventName": "ls_tablewalker.ic_type1", 116c5f18e9eSVijay Thakkar "EventCode": "0x46", 117b5b8a7cfSVijay Thakkar "BriefDescription": "Total Page Table Walks IC Type 1.", 118b5b8a7cfSVijay Thakkar "UMask": "0x8" 119b5b8a7cfSVijay Thakkar }, 120b5b8a7cfSVijay Thakkar { 121b5b8a7cfSVijay Thakkar "EventName": "ls_tablewalker.ic_type0", 122b5b8a7cfSVijay Thakkar "EventCode": "0x46", 123b5b8a7cfSVijay Thakkar "BriefDescription": "Total Page Table Walks IC Type 0.", 124b5b8a7cfSVijay Thakkar "UMask": "0x4" 125b5b8a7cfSVijay Thakkar }, 126b5b8a7cfSVijay Thakkar { 127b5b8a7cfSVijay Thakkar "EventName": "ls_tablewalker.dside", 128b5b8a7cfSVijay Thakkar "EventCode": "0x46", 129b5b8a7cfSVijay Thakkar "BriefDescription": "Total Page Table Walks on D-side.", 130c5f18e9eSVijay Thakkar "UMask": "0x3" 131c5f18e9eSVijay Thakkar }, 132c5f18e9eSVijay Thakkar { 133b5b8a7cfSVijay Thakkar "EventName": "ls_tablewalker.dc_type1", 134b5b8a7cfSVijay Thakkar "EventCode": "0x46", 135b5b8a7cfSVijay Thakkar "BriefDescription": "Total Page Table Walks DC Type 1.", 136b5b8a7cfSVijay Thakkar "UMask": "0x2" 137b5b8a7cfSVijay Thakkar }, 138b5b8a7cfSVijay Thakkar { 139b5b8a7cfSVijay Thakkar "EventName": "ls_tablewalker.dc_type0", 140b5b8a7cfSVijay Thakkar "EventCode": "0x46", 141b5b8a7cfSVijay Thakkar "BriefDescription": "Total Page Table Walks DC Type 0.", 142b5b8a7cfSVijay Thakkar "UMask": "0x1" 143b5b8a7cfSVijay Thakkar }, 144b5b8a7cfSVijay Thakkar { 145c5f18e9eSVijay Thakkar "EventName": "ls_misal_accesses", 146c5f18e9eSVijay Thakkar "EventCode": "0x47", 147c5f18e9eSVijay Thakkar "BriefDescription": "Misaligned loads." 148c5f18e9eSVijay Thakkar }, 149c5f18e9eSVijay Thakkar { 150c5f18e9eSVijay Thakkar "EventName": "ls_pref_instr_disp.prefetch_nta", 151c5f18e9eSVijay Thakkar "EventCode": "0x4b", 152c5f18e9eSVijay Thakkar "BriefDescription": "Software Prefetch Instructions (PREFETCHNTA instruction) Dispatched.", 153c5f18e9eSVijay Thakkar "UMask": "0x4" 154c5f18e9eSVijay Thakkar }, 155c5f18e9eSVijay Thakkar { 156c5f18e9eSVijay Thakkar "EventName": "ls_pref_instr_disp.store_prefetch_w", 157c5f18e9eSVijay Thakkar "EventCode": "0x4b", 158c5f18e9eSVijay Thakkar "BriefDescription": "Software Prefetch Instructions (3DNow PREFETCHW instruction) Dispatched.", 159c5f18e9eSVijay Thakkar "UMask": "0x2" 160c5f18e9eSVijay Thakkar }, 161c5f18e9eSVijay Thakkar { 162c5f18e9eSVijay Thakkar "EventName": "ls_pref_instr_disp.load_prefetch_w", 163c5f18e9eSVijay Thakkar "EventCode": "0x4b", 164b5b8a7cfSVijay Thakkar "BriefDescription": "Software Prefetch Instructions Dispatched. Prefetch, Prefetch_T0_T1_T2.", 165c5f18e9eSVijay Thakkar "UMask": "0x1" 166c5f18e9eSVijay Thakkar }, 167c5f18e9eSVijay Thakkar { 168c5f18e9eSVijay Thakkar "EventName": "ls_inef_sw_pref.mab_mch_cnt", 169c5f18e9eSVijay Thakkar "EventCode": "0x52", 170b5b8a7cfSVijay Thakkar "BriefDescription": "The number of software prefetches that did not fetch data outside of the processor core. Software PREFETCH instruction saw a match on an already-allocated miss request buffer.", 171c5f18e9eSVijay Thakkar "UMask": "0x2" 172c5f18e9eSVijay Thakkar }, 173c5f18e9eSVijay Thakkar { 174c5f18e9eSVijay Thakkar "EventName": "ls_inef_sw_pref.data_pipe_sw_pf_dc_hit", 175c5f18e9eSVijay Thakkar "EventCode": "0x52", 176b5b8a7cfSVijay Thakkar "BriefDescription": "The number of software prefetches that did not fetch data outside of the processor core. Software PREFETCH instruction saw a DC hit.", 177c5f18e9eSVijay Thakkar "UMask": "0x1" 178c5f18e9eSVijay Thakkar }, 179c5f18e9eSVijay Thakkar { 180c5f18e9eSVijay Thakkar "EventName": "ls_not_halted_cyc", 181c5f18e9eSVijay Thakkar "EventCode": "0x76", 182c5f18e9eSVijay Thakkar "BriefDescription": "Cycles not in Halt." 183c5f18e9eSVijay Thakkar } 184c5f18e9eSVijay Thakkar] 185