1*eafcbb68SZhengjun Xing[
2*eafcbb68SZhengjun Xing    {
3*eafcbb68SZhengjun Xing        "BriefDescription": "Counts the number of cycles that the head (oldest load) of the load buffer is stalled due to any number of reasons, including an L1 miss, WCB full, pagewalk, store address block or store data block, on a load that retires.",
4*eafcbb68SZhengjun Xing        "EventCode": "0x05",
5*eafcbb68SZhengjun Xing        "EventName": "LD_HEAD.ANY_AT_RET",
6*eafcbb68SZhengjun Xing        "SampleAfterValue": "1000003",
7*eafcbb68SZhengjun Xing        "UMask": "0xff"
8*eafcbb68SZhengjun Xing    },
9*eafcbb68SZhengjun Xing    {
10*eafcbb68SZhengjun Xing        "BriefDescription": "Counts the number of cycles that the head (oldest load) of the load buffer is stalled due to a core bound stall including a store address match, a DTLB miss or a page walk that detains the load from retiring.",
11*eafcbb68SZhengjun Xing        "EventCode": "0x05",
12*eafcbb68SZhengjun Xing        "EventName": "LD_HEAD.L1_BOUND_AT_RET",
13*eafcbb68SZhengjun Xing        "SampleAfterValue": "1000003",
14*eafcbb68SZhengjun Xing        "UMask": "0xf4"
15*eafcbb68SZhengjun Xing    },
16*eafcbb68SZhengjun Xing    {
17*eafcbb68SZhengjun Xing        "BriefDescription": "Counts the number of cycles that the head (oldest load) of the load buffer and retirement are both stalled due to other block cases.",
18*eafcbb68SZhengjun Xing        "EventCode": "0x05",
19*eafcbb68SZhengjun Xing        "EventName": "LD_HEAD.OTHER_AT_RET",
20*eafcbb68SZhengjun Xing        "PublicDescription": "Counts the number of cycles that the head (oldest load) of the load buffer and retirement are both stalled due to other block cases such as pipeline conflicts, fences, etc.",
21*eafcbb68SZhengjun Xing        "SampleAfterValue": "1000003",
22*eafcbb68SZhengjun Xing        "UMask": "0xc0"
23*eafcbb68SZhengjun Xing    },
24*eafcbb68SZhengjun Xing    {
25*eafcbb68SZhengjun Xing        "BriefDescription": "Counts the number of cycles that the head (oldest load) of the load buffer and retirement are both stalled due to a pagewalk.",
26*eafcbb68SZhengjun Xing        "EventCode": "0x05",
27*eafcbb68SZhengjun Xing        "EventName": "LD_HEAD.PGWALK_AT_RET",
28*eafcbb68SZhengjun Xing        "SampleAfterValue": "1000003",
29*eafcbb68SZhengjun Xing        "UMask": "0xa0"
30*eafcbb68SZhengjun Xing    },
31*eafcbb68SZhengjun Xing    {
32*eafcbb68SZhengjun Xing        "BriefDescription": "Counts the number of cycles that the head (oldest load) of the load buffer and retirement are both stalled due to a store address match.",
33*eafcbb68SZhengjun Xing        "EventCode": "0x05",
34*eafcbb68SZhengjun Xing        "EventName": "LD_HEAD.ST_ADDR_AT_RET",
35*eafcbb68SZhengjun Xing        "SampleAfterValue": "1000003",
36*eafcbb68SZhengjun Xing        "UMask": "0x84"
37*eafcbb68SZhengjun Xing    },
38*eafcbb68SZhengjun Xing    {
39*eafcbb68SZhengjun Xing        "BriefDescription": "Counts the number of machine clears due to memory ordering caused by a snoop from an external agent. Does not count internally generated machine clears such as those due to memory disambiguation.",
40*eafcbb68SZhengjun Xing        "EventCode": "0xc3",
41*eafcbb68SZhengjun Xing        "EventName": "MACHINE_CLEARS.MEMORY_ORDERING",
42*eafcbb68SZhengjun Xing        "SampleAfterValue": "20003",
43*eafcbb68SZhengjun Xing        "UMask": "0x2"
44*eafcbb68SZhengjun Xing    },
45*eafcbb68SZhengjun Xing    {
46*eafcbb68SZhengjun Xing        "BriefDescription": "Counts demand data reads that were not supplied by the L3 cache.",
47*eafcbb68SZhengjun Xing        "EventCode": "0xB7",
48*eafcbb68SZhengjun Xing        "EventName": "OCR.DEMAND_DATA_RD.L3_MISS",
49*eafcbb68SZhengjun Xing        "MSRIndex": "0x1a6,0x1a7",
50*eafcbb68SZhengjun Xing        "MSRValue": "0x3F84400001",
51*eafcbb68SZhengjun Xing        "SampleAfterValue": "100003",
52*eafcbb68SZhengjun Xing        "UMask": "0x1"
53*eafcbb68SZhengjun Xing    },
54*eafcbb68SZhengjun Xing    {
55*eafcbb68SZhengjun Xing        "BriefDescription": "Counts demand data reads that were not supplied by the L3 cache.",
56*eafcbb68SZhengjun Xing        "EventCode": "0xB7",
57*eafcbb68SZhengjun Xing        "EventName": "OCR.DEMAND_DATA_RD.L3_MISS_LOCAL",
58*eafcbb68SZhengjun Xing        "MSRIndex": "0x1a6,0x1a7",
59*eafcbb68SZhengjun Xing        "MSRValue": "0x3F84400001",
60*eafcbb68SZhengjun Xing        "SampleAfterValue": "100003",
61*eafcbb68SZhengjun Xing        "UMask": "0x1"
62*eafcbb68SZhengjun Xing    },
63*eafcbb68SZhengjun Xing    {
64*eafcbb68SZhengjun Xing        "BriefDescription": "Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were not supplied by the L3 cache.",
65*eafcbb68SZhengjun Xing        "EventCode": "0xB7",
66*eafcbb68SZhengjun Xing        "EventName": "OCR.DEMAND_RFO.L3_MISS",
67*eafcbb68SZhengjun Xing        "MSRIndex": "0x1a6,0x1a7",
68*eafcbb68SZhengjun Xing        "MSRValue": "0x3F84400002",
69*eafcbb68SZhengjun Xing        "SampleAfterValue": "100003",
70*eafcbb68SZhengjun Xing        "UMask": "0x1"
71*eafcbb68SZhengjun Xing    },
72*eafcbb68SZhengjun Xing    {
73*eafcbb68SZhengjun Xing        "BriefDescription": "Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were not supplied by the L3 cache.",
74*eafcbb68SZhengjun Xing        "EventCode": "0xB7",
75*eafcbb68SZhengjun Xing        "EventName": "OCR.DEMAND_RFO.L3_MISS_LOCAL",
76*eafcbb68SZhengjun Xing        "MSRIndex": "0x1a6,0x1a7",
77*eafcbb68SZhengjun Xing        "MSRValue": "0x3F84400002",
78*eafcbb68SZhengjun Xing        "SampleAfterValue": "100003",
79*eafcbb68SZhengjun Xing        "UMask": "0x1"
80*eafcbb68SZhengjun Xing    }
81*eafcbb68SZhengjun Xing]
82