1[
2    {
3        "BriefDescription": "Counts the number of page walks completed due to load DTLB misses to any page size.",
4        "CollectPEBSRecord": "2",
5        "Counter": "0,1,2,3,4,5",
6        "EventCode": "0x08",
7        "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED",
8        "PEBScounters": "0,1,2,3,4,5",
9        "SampleAfterValue": "200003",
10        "Speculative": "1",
11        "UMask": "0xe",
12        "Unit": "cpu_atom"
13    },
14    {
15        "BriefDescription": "Counts the number of page walks completed due to store DTLB misses to any page size.",
16        "CollectPEBSRecord": "2",
17        "Counter": "0,1,2,3,4,5",
18        "EventCode": "0x49",
19        "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED",
20        "PEBScounters": "0,1,2,3,4,5",
21        "SampleAfterValue": "2000003",
22        "Speculative": "1",
23        "UMask": "0xe",
24        "Unit": "cpu_atom"
25    },
26    {
27        "BriefDescription": "Counts the number of page walks initiated by a instruction fetch that missed the first and second level TLBs.",
28        "CollectPEBSRecord": "2",
29        "Counter": "0,1,2,3,4,5",
30        "EventCode": "0x85",
31        "EventName": "ITLB_MISSES.MISS_CAUSED_WALK",
32        "PEBScounters": "0,1,2,3,4,5",
33        "SampleAfterValue": "1000003",
34        "Speculative": "1",
35        "UMask": "0x1",
36        "Unit": "cpu_atom"
37    },
38    {
39        "BriefDescription": "Counts the number of page walks due to an instruction fetch that miss the PDE (Page Directory Entry) cache.",
40        "CollectPEBSRecord": "2",
41        "Counter": "0,1,2,3,4,5",
42        "EventCode": "0x85",
43        "EventName": "ITLB_MISSES.PDE_CACHE_MISS",
44        "PEBScounters": "0,1,2,3,4,5",
45        "SampleAfterValue": "2000003",
46        "Speculative": "1",
47        "UMask": "0x80",
48        "Unit": "cpu_atom"
49    },
50    {
51        "BriefDescription": "Counts the number of page walks completed due to instruction fetch misses to any page size.",
52        "CollectPEBSRecord": "2",
53        "Counter": "0,1,2,3,4,5",
54        "EventCode": "0x85",
55        "EventName": "ITLB_MISSES.WALK_COMPLETED",
56        "PEBScounters": "0,1,2,3,4,5",
57        "SampleAfterValue": "200003",
58        "Speculative": "1",
59        "UMask": "0xe",
60        "Unit": "cpu_atom"
61    },
62    {
63        "BriefDescription": "Counts the number of cycles that the head (oldest load) of the load buffer and retirement are both stalled due to a DTLB miss.",
64        "CollectPEBSRecord": "2",
65        "Counter": "0,1,2,3,4,5",
66        "EventCode": "0x05",
67        "EventName": "LD_HEAD.DTLB_MISS_AT_RET",
68        "PEBScounters": "0,1,2,3,4,5",
69        "SampleAfterValue": "1000003",
70        "Speculative": "1",
71        "UMask": "0x90",
72        "Unit": "cpu_atom"
73    },
74    {
75        "BriefDescription": "Loads that miss the DTLB and hit the STLB.",
76        "CollectPEBSRecord": "2",
77        "Counter": "0,1,2,3",
78        "EventCode": "0x12",
79        "EventName": "DTLB_LOAD_MISSES.STLB_HIT",
80        "PEBScounters": "0,1,2,3",
81        "SampleAfterValue": "100003",
82        "Speculative": "1",
83        "UMask": "0x20",
84        "Unit": "cpu_core"
85    },
86    {
87        "BriefDescription": "Cycles when at least one PMH is busy with a page walk for a demand load.",
88        "CollectPEBSRecord": "2",
89        "Counter": "0,1,2,3",
90        "CounterMask": "1",
91        "EventCode": "0x12",
92        "EventName": "DTLB_LOAD_MISSES.WALK_ACTIVE",
93        "PEBScounters": "0,1,2,3",
94        "SampleAfterValue": "100003",
95        "Speculative": "1",
96        "UMask": "0x10",
97        "Unit": "cpu_core"
98    },
99    {
100        "BriefDescription": "Load miss in all TLB levels causes a page walk that completes. (All page sizes)",
101        "CollectPEBSRecord": "2",
102        "Counter": "0,1,2,3",
103        "EventCode": "0x12",
104        "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED",
105        "PEBScounters": "0,1,2,3",
106        "SampleAfterValue": "100003",
107        "Speculative": "1",
108        "UMask": "0xe",
109        "Unit": "cpu_core"
110    },
111    {
112        "BriefDescription": "Page walks completed due to a demand data load to a 1G page.",
113        "CollectPEBSRecord": "2",
114        "Counter": "0,1,2,3",
115        "EventCode": "0x12",
116        "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_1G",
117        "PEBScounters": "0,1,2,3",
118        "SampleAfterValue": "100003",
119        "Speculative": "1",
120        "UMask": "0x8",
121        "Unit": "cpu_core"
122    },
123    {
124        "BriefDescription": "Page walks completed due to a demand data load to a 2M/4M page.",
125        "CollectPEBSRecord": "2",
126        "Counter": "0,1,2,3",
127        "EventCode": "0x12",
128        "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M",
129        "PEBScounters": "0,1,2,3",
130        "SampleAfterValue": "100003",
131        "Speculative": "1",
132        "UMask": "0x4",
133        "Unit": "cpu_core"
134    },
135    {
136        "BriefDescription": "Page walks completed due to a demand data load to a 4K page.",
137        "CollectPEBSRecord": "2",
138        "Counter": "0,1,2,3",
139        "EventCode": "0x12",
140        "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_4K",
141        "PEBScounters": "0,1,2,3",
142        "SampleAfterValue": "100003",
143        "Speculative": "1",
144        "UMask": "0x2",
145        "Unit": "cpu_core"
146    },
147    {
148        "BriefDescription": "Number of page walks outstanding for a demand load in the PMH each cycle.",
149        "CollectPEBSRecord": "2",
150        "Counter": "0,1,2,3",
151        "EventCode": "0x12",
152        "EventName": "DTLB_LOAD_MISSES.WALK_PENDING",
153        "PEBScounters": "0,1,2,3",
154        "SampleAfterValue": "100003",
155        "Speculative": "1",
156        "UMask": "0x10",
157        "Unit": "cpu_core"
158    },
159    {
160        "BriefDescription": "Stores that miss the DTLB and hit the STLB.",
161        "CollectPEBSRecord": "2",
162        "Counter": "0,1,2,3",
163        "EventCode": "0x13",
164        "EventName": "DTLB_STORE_MISSES.STLB_HIT",
165        "PEBScounters": "0,1,2,3",
166        "SampleAfterValue": "100003",
167        "Speculative": "1",
168        "UMask": "0x20",
169        "Unit": "cpu_core"
170    },
171    {
172        "BriefDescription": "Cycles when at least one PMH is busy with a page walk for a store.",
173        "CollectPEBSRecord": "2",
174        "Counter": "0,1,2,3",
175        "CounterMask": "1",
176        "EventCode": "0x13",
177        "EventName": "DTLB_STORE_MISSES.WALK_ACTIVE",
178        "PEBScounters": "0,1,2,3",
179        "SampleAfterValue": "100003",
180        "Speculative": "1",
181        "UMask": "0x10",
182        "Unit": "cpu_core"
183    },
184    {
185        "BriefDescription": "Store misses in all TLB levels causes a page walk that completes. (All page sizes)",
186        "CollectPEBSRecord": "2",
187        "Counter": "0,1,2,3",
188        "EventCode": "0x13",
189        "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED",
190        "PEBScounters": "0,1,2,3",
191        "SampleAfterValue": "100003",
192        "Speculative": "1",
193        "UMask": "0xe",
194        "Unit": "cpu_core"
195    },
196    {
197        "BriefDescription": "Page walks completed due to a demand data store to a 1G page.",
198        "CollectPEBSRecord": "2",
199        "Counter": "0,1,2,3",
200        "EventCode": "0x13",
201        "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_1G",
202        "PEBScounters": "0,1,2,3",
203        "SampleAfterValue": "100003",
204        "Speculative": "1",
205        "UMask": "0x8",
206        "Unit": "cpu_core"
207    },
208    {
209        "BriefDescription": "Page walks completed due to a demand data store to a 2M/4M page.",
210        "CollectPEBSRecord": "2",
211        "Counter": "0,1,2,3",
212        "EventCode": "0x13",
213        "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_2M_4M",
214        "PEBScounters": "0,1,2,3",
215        "SampleAfterValue": "100003",
216        "Speculative": "1",
217        "UMask": "0x4",
218        "Unit": "cpu_core"
219    },
220    {
221        "BriefDescription": "Page walks completed due to a demand data store to a 4K page.",
222        "CollectPEBSRecord": "2",
223        "Counter": "0,1,2,3",
224        "EventCode": "0x13",
225        "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_4K",
226        "PEBScounters": "0,1,2,3",
227        "SampleAfterValue": "100003",
228        "Speculative": "1",
229        "UMask": "0x2",
230        "Unit": "cpu_core"
231    },
232    {
233        "BriefDescription": "Number of page walks outstanding for a store in the PMH each cycle.",
234        "CollectPEBSRecord": "2",
235        "Counter": "0,1,2,3",
236        "EventCode": "0x13",
237        "EventName": "DTLB_STORE_MISSES.WALK_PENDING",
238        "PEBScounters": "0,1,2,3",
239        "SampleAfterValue": "100003",
240        "Speculative": "1",
241        "UMask": "0x10",
242        "Unit": "cpu_core"
243    },
244    {
245        "BriefDescription": "Instruction fetch requests that miss the ITLB and hit the STLB.",
246        "CollectPEBSRecord": "2",
247        "Counter": "0,1,2,3",
248        "EventCode": "0x11",
249        "EventName": "ITLB_MISSES.STLB_HIT",
250        "PEBScounters": "0,1,2,3",
251        "SampleAfterValue": "100003",
252        "Speculative": "1",
253        "UMask": "0x20",
254        "Unit": "cpu_core"
255    },
256    {
257        "BriefDescription": "Cycles when at least one PMH is busy with a page walk for code (instruction fetch) request.",
258        "CollectPEBSRecord": "2",
259        "Counter": "0,1,2,3",
260        "CounterMask": "1",
261        "EventCode": "0x11",
262        "EventName": "ITLB_MISSES.WALK_ACTIVE",
263        "PEBScounters": "0,1,2,3",
264        "SampleAfterValue": "100003",
265        "Speculative": "1",
266        "UMask": "0x10",
267        "Unit": "cpu_core"
268    },
269    {
270        "BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (All page sizes)",
271        "CollectPEBSRecord": "2",
272        "Counter": "0,1,2,3",
273        "EventCode": "0x11",
274        "EventName": "ITLB_MISSES.WALK_COMPLETED",
275        "PEBScounters": "0,1,2,3",
276        "SampleAfterValue": "100003",
277        "Speculative": "1",
278        "UMask": "0xe",
279        "Unit": "cpu_core"
280    },
281    {
282        "BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (2M/4M)",
283        "CollectPEBSRecord": "2",
284        "Counter": "0,1,2,3",
285        "EventCode": "0x11",
286        "EventName": "ITLB_MISSES.WALK_COMPLETED_2M_4M",
287        "PEBScounters": "0,1,2,3",
288        "SampleAfterValue": "100003",
289        "Speculative": "1",
290        "UMask": "0x4",
291        "Unit": "cpu_core"
292    },
293    {
294        "BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (4K)",
295        "CollectPEBSRecord": "2",
296        "Counter": "0,1,2,3",
297        "EventCode": "0x11",
298        "EventName": "ITLB_MISSES.WALK_COMPLETED_4K",
299        "PEBScounters": "0,1,2,3",
300        "SampleAfterValue": "100003",
301        "Speculative": "1",
302        "UMask": "0x2",
303        "Unit": "cpu_core"
304    },
305    {
306        "BriefDescription": "Number of page walks outstanding for an outstanding code request in the PMH each cycle.",
307        "CollectPEBSRecord": "2",
308        "Counter": "0,1,2,3",
309        "EventCode": "0x11",
310        "EventName": "ITLB_MISSES.WALK_PENDING",
311        "PEBScounters": "0,1,2,3",
312        "SampleAfterValue": "100003",
313        "Speculative": "1",
314        "UMask": "0x10",
315        "Unit": "cpu_core"
316    }
317]
318