12c0fd42cSZhengjun Xing[ 22c0fd42cSZhengjun Xing { 34c12f41aSZhengjun Xing "BriefDescription": "Counts every 64B read request entering the Memory Controller 0 to DRAM (sum of all channels).", 4*2e4555b0SIan Rogers "EventCode": "0xff", 54c12f41aSZhengjun Xing "EventName": "UNC_MC0_RDCAS_COUNT_FREERUN", 64c12f41aSZhengjun Xing "PerPkg": "1", 74c12f41aSZhengjun Xing "PublicDescription": "Counts every 64B read request entering the Memory Controller 0 to DRAM (sum of all channels).", 8*2e4555b0SIan Rogers "UMask": "0x20", 9*2e4555b0SIan Rogers "Unit": "imc_free_running_0" 104c12f41aSZhengjun Xing }, 114c12f41aSZhengjun Xing { 124c12f41aSZhengjun Xing "BriefDescription": "Counts every 64B write request entering the Memory Controller 0 to DRAM (sum of all channels). Each write request counts as a new request incrementing this counter. However, same cache line write requests (both full and partial) are combined to a single 64 byte data transfer to DRAM.", 13*2e4555b0SIan Rogers "EventCode": "0xff", 144c12f41aSZhengjun Xing "EventName": "UNC_MC0_WRCAS_COUNT_FREERUN", 152c0fd42cSZhengjun Xing "PerPkg": "1", 16*2e4555b0SIan Rogers "UMask": "0x30", 17*2e4555b0SIan Rogers "Unit": "imc_free_running_0" 182c0fd42cSZhengjun Xing }, 192c0fd42cSZhengjun Xing { 204c12f41aSZhengjun Xing "BriefDescription": "Counts every 64B read request entering the Memory Controller 1 to DRAM (sum of all channels).", 21*2e4555b0SIan Rogers "EventCode": "0xff", 224c12f41aSZhengjun Xing "EventName": "UNC_MC1_RDCAS_COUNT_FREERUN", 234c12f41aSZhengjun Xing "PerPkg": "1", 244c12f41aSZhengjun Xing "PublicDescription": "Counts every 64B read entering the Memory Controller 1 to DRAM (sum of all channels).", 25*2e4555b0SIan Rogers "UMask": "0x20", 26*2e4555b0SIan Rogers "Unit": "imc_free_running_1" 274c12f41aSZhengjun Xing }, 284c12f41aSZhengjun Xing { 294c12f41aSZhengjun Xing "BriefDescription": "Counts every 64B write request entering the Memory Controller 1 to DRAM (sum of all channels). Each write request counts as a new request incrementing this counter. However, same cache line write requests (both full and partial) are combined to a single 64 byte data transfer to DRAM.", 30*2e4555b0SIan Rogers "EventCode": "0xff", 314c12f41aSZhengjun Xing "EventName": "UNC_MC1_WRCAS_COUNT_FREERUN", 322c0fd42cSZhengjun Xing "PerPkg": "1", 33*2e4555b0SIan Rogers "UMask": "0x30", 34*2e4555b0SIan Rogers "Unit": "imc_free_running_1" 352c0fd42cSZhengjun Xing }, 362c0fd42cSZhengjun Xing { 374c12f41aSZhengjun Xing "BriefDescription": "ACT command for a read request sent to DRAM", 384c12f41aSZhengjun Xing "EventCode": "0x24", 394c12f41aSZhengjun Xing "EventName": "UNC_M_ACT_COUNT_RD", 402c0fd42cSZhengjun Xing "PerPkg": "1", 412c0fd42cSZhengjun Xing "Unit": "iMC" 422c0fd42cSZhengjun Xing }, 432c0fd42cSZhengjun Xing { 444c12f41aSZhengjun Xing "BriefDescription": "ACT command sent to DRAM", 454c12f41aSZhengjun Xing "EventCode": "0x26", 464c12f41aSZhengjun Xing "EventName": "UNC_M_ACT_COUNT_TOTAL", 472c0fd42cSZhengjun Xing "PerPkg": "1", 482c0fd42cSZhengjun Xing "Unit": "iMC" 492c0fd42cSZhengjun Xing }, 502c0fd42cSZhengjun Xing { 514c12f41aSZhengjun Xing "BriefDescription": "ACT command for a write request sent to DRAM", 524c12f41aSZhengjun Xing "EventCode": "0x25", 534c12f41aSZhengjun Xing "EventName": "UNC_M_ACT_COUNT_WR", 542c0fd42cSZhengjun Xing "PerPkg": "1", 552c0fd42cSZhengjun Xing "Unit": "iMC" 562c0fd42cSZhengjun Xing }, 572c0fd42cSZhengjun Xing { 582c0fd42cSZhengjun Xing "BriefDescription": "Read CAS command sent to DRAM", 592c0fd42cSZhengjun Xing "EventCode": "0x22", 602c0fd42cSZhengjun Xing "EventName": "UNC_M_CAS_COUNT_RD", 612c0fd42cSZhengjun Xing "PerPkg": "1", 622c0fd42cSZhengjun Xing "Unit": "iMC" 632c0fd42cSZhengjun Xing }, 642c0fd42cSZhengjun Xing { 652c0fd42cSZhengjun Xing "BriefDescription": "Write CAS command sent to DRAM", 662c0fd42cSZhengjun Xing "EventCode": "0x23", 672c0fd42cSZhengjun Xing "EventName": "UNC_M_CAS_COUNT_WR", 682c0fd42cSZhengjun Xing "PerPkg": "1", 692c0fd42cSZhengjun Xing "Unit": "iMC" 702c0fd42cSZhengjun Xing }, 712c0fd42cSZhengjun Xing { 724c12f41aSZhengjun Xing "BriefDescription": "Number of clocks", 734c12f41aSZhengjun Xing "EventCode": "0x01", 744c12f41aSZhengjun Xing "EventName": "UNC_M_CLOCKTICKS", 752c0fd42cSZhengjun Xing "PerPkg": "1", 762c0fd42cSZhengjun Xing "Unit": "iMC" 772c0fd42cSZhengjun Xing }, 782c0fd42cSZhengjun Xing { 794c12f41aSZhengjun Xing "BriefDescription": "incoming read request page status is Page Empty", 804c12f41aSZhengjun Xing "EventCode": "0x1D", 814c12f41aSZhengjun Xing "EventName": "UNC_M_DRAM_PAGE_EMPTY_RD", 822c0fd42cSZhengjun Xing "PerPkg": "1", 832c0fd42cSZhengjun Xing "Unit": "iMC" 842c0fd42cSZhengjun Xing }, 852c0fd42cSZhengjun Xing { 864c12f41aSZhengjun Xing "BriefDescription": "incoming write request page status is Page Empty", 874c12f41aSZhengjun Xing "EventCode": "0x20", 884c12f41aSZhengjun Xing "EventName": "UNC_M_DRAM_PAGE_EMPTY_WR", 892c0fd42cSZhengjun Xing "PerPkg": "1", 902c0fd42cSZhengjun Xing "Unit": "iMC" 912c0fd42cSZhengjun Xing }, 922c0fd42cSZhengjun Xing { 934c12f41aSZhengjun Xing "BriefDescription": "incoming read request page status is Page Hit", 944c12f41aSZhengjun Xing "EventCode": "0x1C", 954c12f41aSZhengjun Xing "EventName": "UNC_M_DRAM_PAGE_HIT_RD", 964c12f41aSZhengjun Xing "PerPkg": "1", 974c12f41aSZhengjun Xing "Unit": "iMC" 984c12f41aSZhengjun Xing }, 994c12f41aSZhengjun Xing { 1004c12f41aSZhengjun Xing "BriefDescription": "incoming write request page status is Page Hit", 1014c12f41aSZhengjun Xing "EventCode": "0x1F", 1024c12f41aSZhengjun Xing "EventName": "UNC_M_DRAM_PAGE_HIT_WR", 1034c12f41aSZhengjun Xing "PerPkg": "1", 1044c12f41aSZhengjun Xing "Unit": "iMC" 1054c12f41aSZhengjun Xing }, 1064c12f41aSZhengjun Xing { 1074c12f41aSZhengjun Xing "BriefDescription": "incoming read request page status is Page Miss", 1084c12f41aSZhengjun Xing "EventCode": "0x1E", 1094c12f41aSZhengjun Xing "EventName": "UNC_M_DRAM_PAGE_MISS_RD", 1104c12f41aSZhengjun Xing "PerPkg": "1", 1114c12f41aSZhengjun Xing "Unit": "iMC" 1124c12f41aSZhengjun Xing }, 1134c12f41aSZhengjun Xing { 1144c12f41aSZhengjun Xing "BriefDescription": "incoming write request page status is Page Miss", 1154c12f41aSZhengjun Xing "EventCode": "0x21", 1164c12f41aSZhengjun Xing "EventName": "UNC_M_DRAM_PAGE_MISS_WR", 1174c12f41aSZhengjun Xing "PerPkg": "1", 1184c12f41aSZhengjun Xing "Unit": "iMC" 1194c12f41aSZhengjun Xing }, 1204c12f41aSZhengjun Xing { 1214c12f41aSZhengjun Xing "BriefDescription": "Any Rank at Hot state", 1224c12f41aSZhengjun Xing "EventCode": "0x19", 1234c12f41aSZhengjun Xing "EventName": "UNC_M_DRAM_THERMAL_HOT", 1244c12f41aSZhengjun Xing "PerPkg": "1", 1254c12f41aSZhengjun Xing "Unit": "iMC" 1264c12f41aSZhengjun Xing }, 1274c12f41aSZhengjun Xing { 1284c12f41aSZhengjun Xing "BriefDescription": "Any Rank at Warm state", 1294c12f41aSZhengjun Xing "EventCode": "0x1A", 1304c12f41aSZhengjun Xing "EventName": "UNC_M_DRAM_THERMAL_WARM", 1314c12f41aSZhengjun Xing "PerPkg": "1", 1324c12f41aSZhengjun Xing "Unit": "iMC" 1334c12f41aSZhengjun Xing }, 1344c12f41aSZhengjun Xing { 1354c12f41aSZhengjun Xing "BriefDescription": "Incoming read prefetch request from IA.", 1364c12f41aSZhengjun Xing "EventCode": "0x0A", 1374c12f41aSZhengjun Xing "EventName": "UNC_M_PREFETCH_RD", 1382c0fd42cSZhengjun Xing "PerPkg": "1", 1392c0fd42cSZhengjun Xing "Unit": "iMC" 1402c0fd42cSZhengjun Xing }, 1412c0fd42cSZhengjun Xing { 1422c0fd42cSZhengjun Xing "BriefDescription": "PRE command sent to DRAM due to page table idle timer expiration", 1432c0fd42cSZhengjun Xing "EventCode": "0x28", 1442c0fd42cSZhengjun Xing "EventName": "UNC_M_PRE_COUNT_IDLE", 1452c0fd42cSZhengjun Xing "PerPkg": "1", 1462c0fd42cSZhengjun Xing "Unit": "iMC" 1472c0fd42cSZhengjun Xing }, 1482c0fd42cSZhengjun Xing { 1494c12f41aSZhengjun Xing "BriefDescription": "PRE command sent to DRAM for a read/write request", 1504c12f41aSZhengjun Xing "EventCode": "0x27", 1514c12f41aSZhengjun Xing "EventName": "UNC_M_PRE_COUNT_PAGE_MISS", 1522c0fd42cSZhengjun Xing "PerPkg": "1", 1532c0fd42cSZhengjun Xing "Unit": "iMC" 1542c0fd42cSZhengjun Xing }, 1552c0fd42cSZhengjun Xing { 1564c12f41aSZhengjun Xing "BriefDescription": "Incoming VC0 read request", 1574c12f41aSZhengjun Xing "EventCode": "0x02", 1584c12f41aSZhengjun Xing "EventName": "UNC_M_VC0_REQUESTS_RD", 1592c0fd42cSZhengjun Xing "PerPkg": "1", 1602c0fd42cSZhengjun Xing "Unit": "iMC" 1612c0fd42cSZhengjun Xing }, 1622c0fd42cSZhengjun Xing { 1634c12f41aSZhengjun Xing "BriefDescription": "Incoming VC0 write request", 1644c12f41aSZhengjun Xing "EventCode": "0x03", 1654c12f41aSZhengjun Xing "EventName": "UNC_M_VC0_REQUESTS_WR", 1662c0fd42cSZhengjun Xing "PerPkg": "1", 1672c0fd42cSZhengjun Xing "Unit": "iMC" 1682c0fd42cSZhengjun Xing }, 1692c0fd42cSZhengjun Xing { 1704c12f41aSZhengjun Xing "BriefDescription": "Incoming VC1 read request", 1714c12f41aSZhengjun Xing "EventCode": "0x04", 1724c12f41aSZhengjun Xing "EventName": "UNC_M_VC1_REQUESTS_RD", 1734c12f41aSZhengjun Xing "PerPkg": "1", 1744c12f41aSZhengjun Xing "Unit": "iMC" 1754c12f41aSZhengjun Xing }, 1764c12f41aSZhengjun Xing { 1774c12f41aSZhengjun Xing "BriefDescription": "Incoming VC1 write request", 1784c12f41aSZhengjun Xing "EventCode": "0x05", 1794c12f41aSZhengjun Xing "EventName": "UNC_M_VC1_REQUESTS_WR", 1802c0fd42cSZhengjun Xing "PerPkg": "1", 1812c0fd42cSZhengjun Xing "Unit": "iMC" 1822c0fd42cSZhengjun Xing } 1832c0fd42cSZhengjun Xing] 184