1[ 2 { 3 "BriefDescription": "Counts demand data reads that have any type of response.", 4 "Counter": "0,1,2,3", 5 "EventCode": "0xB7", 6 "EventName": "OCR.DEMAND_DATA_RD.ANY_RESPONSE", 7 "MSRIndex": "0x1a6,0x1a7", 8 "MSRValue": "0x10001", 9 "SampleAfterValue": "100003", 10 "UMask": "0x1", 11 "Unit": "cpu_atom" 12 }, 13 { 14 "BriefDescription": "Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that have any type of response.", 15 "Counter": "0,1,2,3", 16 "EventCode": "0xB7", 17 "EventName": "OCR.DEMAND_RFO.ANY_RESPONSE", 18 "MSRIndex": "0x1a6,0x1a7", 19 "MSRValue": "0x10002", 20 "SampleAfterValue": "100003", 21 "UMask": "0x1", 22 "Unit": "cpu_atom" 23 }, 24 { 25 "BriefDescription": "Counts streaming stores that have any type of response.", 26 "Counter": "0,1,2,3", 27 "EventCode": "0xB7", 28 "EventName": "OCR.STREAMING_WR.ANY_RESPONSE", 29 "MSRIndex": "0x1a6,0x1a7", 30 "MSRValue": "0x10800", 31 "SampleAfterValue": "100003", 32 "UMask": "0x1", 33 "Unit": "cpu_atom" 34 }, 35 { 36 "BriefDescription": "Number of occurrences where a microcode assist is invoked by hardware.", 37 "CollectPEBSRecord": "2", 38 "Counter": "0,1,2,3,4,5,6,7", 39 "EventCode": "0xc1", 40 "EventName": "ASSISTS.ANY", 41 "PEBScounters": "0,1,2,3,4,5,6,7", 42 "SampleAfterValue": "100003", 43 "UMask": "0x1f", 44 "Unit": "cpu_core" 45 }, 46 { 47 "BriefDescription": "Count all other microcode assist beyond FP, AVX_TILE_MIX and A/D assists (counted by their own sub-events). This includes assists at uop writeback like AVX* load/store (non-FP) assists, Null Assist in SNC (due to lack of FP precision format convert with FMA3x3 uarch) or assists generated by ROB (like assists to due to Missprediction for FSW register - fixed in SNC)", 48 "CollectPEBSRecord": "2", 49 "Counter": "0,1,2,3,4,5,6,7", 50 "EventCode": "0xc1", 51 "EventName": "ASSISTS.HARDWARE", 52 "PEBScounters": "0,1,2,3,4,5,6,7", 53 "SampleAfterValue": "100003", 54 "UMask": "0x4", 55 "Unit": "cpu_core" 56 }, 57 { 58 "BriefDescription": "TBD", 59 "CollectPEBSRecord": "2", 60 "Counter": "0,1,2,3,4,5,6,7", 61 "EventCode": "0xc1", 62 "EventName": "ASSISTS.PAGE_FAULT", 63 "PEBScounters": "0,1,2,3,4,5,6,7", 64 "SampleAfterValue": "1000003", 65 "UMask": "0x8", 66 "Unit": "cpu_core" 67 }, 68 { 69 "BriefDescription": "TBD", 70 "CollectPEBSRecord": "2", 71 "Counter": "0,1,2,3", 72 "EventCode": "0x28", 73 "EventName": "CORE_POWER.LICENSE_1", 74 "PEBScounters": "0,1,2,3", 75 "SampleAfterValue": "200003", 76 "UMask": "0x2", 77 "Unit": "cpu_core" 78 }, 79 { 80 "BriefDescription": "TBD", 81 "CollectPEBSRecord": "2", 82 "Counter": "0,1,2,3", 83 "EventCode": "0x28", 84 "EventName": "CORE_POWER.LICENSE_2", 85 "PEBScounters": "0,1,2,3", 86 "SampleAfterValue": "200003", 87 "UMask": "0x4", 88 "Unit": "cpu_core" 89 }, 90 { 91 "BriefDescription": "TBD", 92 "CollectPEBSRecord": "2", 93 "Counter": "0,1,2,3", 94 "EventCode": "0x28", 95 "EventName": "CORE_POWER.LICENSE_3", 96 "PEBScounters": "0,1,2,3", 97 "SampleAfterValue": "200003", 98 "UMask": "0x8", 99 "Unit": "cpu_core" 100 }, 101 { 102 "BriefDescription": "Counts demand data reads that have any type of response.", 103 "Counter": "0,1,2,3", 104 "EventCode": "0x2A,0x2B", 105 "EventName": "OCR.DEMAND_DATA_RD.ANY_RESPONSE", 106 "MSRIndex": "0x1a6,0x1a7", 107 "MSRValue": "0x10001", 108 "SampleAfterValue": "100003", 109 "UMask": "0x1", 110 "Unit": "cpu_core" 111 }, 112 { 113 "BriefDescription": "Counts demand read for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that have any type of response.", 114 "Counter": "0,1,2,3", 115 "EventCode": "0x2A,0x2B", 116 "EventName": "OCR.DEMAND_RFO.ANY_RESPONSE", 117 "MSRIndex": "0x1a6,0x1a7", 118 "MSRValue": "0x10002", 119 "SampleAfterValue": "100003", 120 "UMask": "0x1", 121 "Unit": "cpu_core" 122 }, 123 { 124 "BriefDescription": "Counts streaming stores that have any type of response.", 125 "Counter": "0,1,2,3", 126 "EventCode": "0x2A,0x2B", 127 "EventName": "OCR.STREAMING_WR.ANY_RESPONSE", 128 "MSRIndex": "0x1a6,0x1a7", 129 "MSRValue": "0x10800", 130 "SampleAfterValue": "100003", 131 "UMask": "0x1", 132 "Unit": "cpu_core" 133 }, 134 { 135 "BriefDescription": "TBD", 136 "CollectPEBSRecord": "2", 137 "Counter": "0,1,2,3", 138 "CounterMask": "1", 139 "EventCode": "0x2d", 140 "EventName": "XQ.FULL_CYCLES", 141 "PEBScounters": "0,1,2,3", 142 "SampleAfterValue": "1000003", 143 "UMask": "0x1", 144 "Unit": "cpu_core" 145 } 146]