1[
2    {
3        "BriefDescription": "Counts the total number of BACLEARS due to all branch types including conditional and unconditional jumps, returns, and indirect branches.",
4        "CollectPEBSRecord": "2",
5        "Counter": "0,1,2,3,4,5",
6        "EventCode": "0xe6",
7        "EventName": "BACLEARS.ANY",
8        "PEBScounters": "0,1,2,3,4,5",
9        "SampleAfterValue": "100003",
10        "Speculative": "1",
11        "UMask": "0x1",
12        "Unit": "cpu_atom"
13    },
14    {
15        "BriefDescription": "Counts the number of requests to the instruction cache for one or more bytes of a cache line.",
16        "CollectPEBSRecord": "2",
17        "Counter": "0,1,2,3,4,5",
18        "EventCode": "0x80",
19        "EventName": "ICACHE.ACCESSES",
20        "PEBScounters": "0,1,2,3,4,5",
21        "SampleAfterValue": "200003",
22        "Speculative": "1",
23        "UMask": "0x3",
24        "Unit": "cpu_atom"
25    },
26    {
27        "BriefDescription": "Counts the number of instruction cache misses.",
28        "CollectPEBSRecord": "2",
29        "Counter": "0,1,2,3,4,5",
30        "EventCode": "0x80",
31        "EventName": "ICACHE.MISSES",
32        "PEBScounters": "0,1,2,3,4,5",
33        "SampleAfterValue": "200003",
34        "Speculative": "1",
35        "UMask": "0x2",
36        "Unit": "cpu_atom"
37    },
38    {
39        "BriefDescription": "Stalls caused by changing prefix length of the instruction.",
40        "CollectPEBSRecord": "2",
41        "Counter": "0,1,2,3",
42        "EventCode": "0x87",
43        "EventName": "DECODE.LCP",
44        "PEBScounters": "0,1,2,3",
45        "SampleAfterValue": "500009",
46        "Speculative": "1",
47        "UMask": "0x1",
48        "Unit": "cpu_core"
49    },
50    {
51        "BriefDescription": "DSB-to-MITE switch true penalty cycles.",
52        "CollectPEBSRecord": "2",
53        "Counter": "0,1,2,3",
54        "EventCode": "0x61",
55        "EventName": "DSB2MITE_SWITCHES.PENALTY_CYCLES",
56        "PEBScounters": "0,1,2,3",
57        "SampleAfterValue": "100003",
58        "Speculative": "1",
59        "UMask": "0x2",
60        "Unit": "cpu_core"
61    },
62    {
63        "BriefDescription": "Retired Instructions who experienced DSB miss.",
64        "CollectPEBSRecord": "2",
65        "Counter": "0,1,2,3,4,5,6,7",
66        "EventCode": "0xc6",
67        "EventName": "FRONTEND_RETIRED.ANY_DSB_MISS",
68        "MSRIndex": "0x3F7",
69        "MSRValue": "0x1",
70        "PEBS": "1",
71        "PEBScounters": "0,1,2,3,4,5,6,7",
72        "SampleAfterValue": "100007",
73        "TakenAlone": "1",
74        "UMask": "0x1",
75        "Unit": "cpu_core"
76    },
77    {
78        "BriefDescription": "Retired Instructions who experienced a critical DSB miss.",
79        "CollectPEBSRecord": "2",
80        "Counter": "0,1,2,3,4,5,6,7",
81        "EventCode": "0xc6",
82        "EventName": "FRONTEND_RETIRED.DSB_MISS",
83        "MSRIndex": "0x3F7",
84        "MSRValue": "0x11",
85        "PEBS": "1",
86        "PEBScounters": "0,1,2,3,4,5,6,7",
87        "SampleAfterValue": "100007",
88        "TakenAlone": "1",
89        "UMask": "0x1",
90        "Unit": "cpu_core"
91    },
92    {
93        "BriefDescription": "Retired Instructions who experienced iTLB true miss.",
94        "CollectPEBSRecord": "2",
95        "Counter": "0,1,2,3,4,5,6,7",
96        "EventCode": "0xc6",
97        "EventName": "FRONTEND_RETIRED.ITLB_MISS",
98        "MSRIndex": "0x3F7",
99        "MSRValue": "0x14",
100        "PEBS": "1",
101        "PEBScounters": "0,1,2,3,4,5,6,7",
102        "SampleAfterValue": "100007",
103        "TakenAlone": "1",
104        "UMask": "0x1",
105        "Unit": "cpu_core"
106    },
107    {
108        "BriefDescription": "Retired Instructions who experienced Instruction L1 Cache true miss.",
109        "CollectPEBSRecord": "2",
110        "Counter": "0,1,2,3,4,5,6,7",
111        "EventCode": "0xc6",
112        "EventName": "FRONTEND_RETIRED.L1I_MISS",
113        "MSRIndex": "0x3F7",
114        "MSRValue": "0x12",
115        "PEBS": "1",
116        "PEBScounters": "0,1,2,3,4,5,6,7",
117        "SampleAfterValue": "100007",
118        "TakenAlone": "1",
119        "UMask": "0x1",
120        "Unit": "cpu_core"
121    },
122    {
123        "BriefDescription": "Retired Instructions who experienced Instruction L2 Cache true miss.",
124        "CollectPEBSRecord": "2",
125        "Counter": "0,1,2,3,4,5,6,7",
126        "EventCode": "0xc6",
127        "EventName": "FRONTEND_RETIRED.L2_MISS",
128        "MSRIndex": "0x3F7",
129        "MSRValue": "0x13",
130        "PEBS": "1",
131        "PEBScounters": "0,1,2,3,4,5,6,7",
132        "SampleAfterValue": "100007",
133        "TakenAlone": "1",
134        "UMask": "0x1",
135        "Unit": "cpu_core"
136    },
137    {
138        "BriefDescription": "Retired instructions after front-end starvation of at least 1 cycle",
139        "CollectPEBSRecord": "2",
140        "Counter": "0,1,2,3,4,5,6,7",
141        "EventCode": "0xc6",
142        "EventName": "FRONTEND_RETIRED.LATENCY_GE_1",
143        "MSRIndex": "0x3F7",
144        "MSRValue": "0x600106",
145        "PEBS": "1",
146        "PEBScounters": "0,1,2,3,4,5,6,7",
147        "SampleAfterValue": "100007",
148        "TakenAlone": "1",
149        "UMask": "0x1",
150        "Unit": "cpu_core"
151    },
152    {
153        "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 128 cycles which was not interrupted by a back-end stall.",
154        "CollectPEBSRecord": "2",
155        "Counter": "0,1,2,3,4,5,6,7",
156        "EventCode": "0xc6",
157        "EventName": "FRONTEND_RETIRED.LATENCY_GE_128",
158        "MSRIndex": "0x3F7",
159        "MSRValue": "0x608006",
160        "PEBS": "1",
161        "PEBScounters": "0,1,2,3,4,5,6,7",
162        "SampleAfterValue": "100007",
163        "TakenAlone": "1",
164        "UMask": "0x1",
165        "Unit": "cpu_core"
166    },
167    {
168        "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 16 cycles which was not interrupted by a back-end stall.",
169        "CollectPEBSRecord": "2",
170        "Counter": "0,1,2,3,4,5,6,7",
171        "EventCode": "0xc6",
172        "EventName": "FRONTEND_RETIRED.LATENCY_GE_16",
173        "MSRIndex": "0x3F7",
174        "MSRValue": "0x601006",
175        "PEBS": "1",
176        "PEBScounters": "0,1,2,3,4,5,6,7",
177        "SampleAfterValue": "100007",
178        "TakenAlone": "1",
179        "UMask": "0x1",
180        "Unit": "cpu_core"
181    },
182    {
183        "BriefDescription": "Retired instructions after front-end starvation of at least 2 cycles",
184        "CollectPEBSRecord": "2",
185        "Counter": "0,1,2,3,4,5,6,7",
186        "EventCode": "0xc6",
187        "EventName": "FRONTEND_RETIRED.LATENCY_GE_2",
188        "MSRIndex": "0x3F7",
189        "MSRValue": "0x600206",
190        "PEBS": "1",
191        "PEBScounters": "0,1,2,3,4,5,6,7",
192        "SampleAfterValue": "100007",
193        "TakenAlone": "1",
194        "UMask": "0x1",
195        "Unit": "cpu_core"
196    },
197    {
198        "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 256 cycles which was not interrupted by a back-end stall.",
199        "CollectPEBSRecord": "2",
200        "Counter": "0,1,2,3,4,5,6,7",
201        "EventCode": "0xc6",
202        "EventName": "FRONTEND_RETIRED.LATENCY_GE_256",
203        "MSRIndex": "0x3F7",
204        "MSRValue": "0x610006",
205        "PEBS": "1",
206        "PEBScounters": "0,1,2,3,4,5,6,7",
207        "SampleAfterValue": "100007",
208        "TakenAlone": "1",
209        "UMask": "0x1",
210        "Unit": "cpu_core"
211    },
212    {
213        "BriefDescription": "Retired instructions that are fetched after an interval where the front-end had at least 1 bubble-slot for a period of 2 cycles which was not interrupted by a back-end stall.",
214        "CollectPEBSRecord": "2",
215        "Counter": "0,1,2,3,4,5,6,7",
216        "EventCode": "0xc6",
217        "EventName": "FRONTEND_RETIRED.LATENCY_GE_2_BUBBLES_GE_1",
218        "MSRIndex": "0x3F7",
219        "MSRValue": "0x100206",
220        "PEBS": "1",
221        "PEBScounters": "0,1,2,3,4,5,6,7",
222        "SampleAfterValue": "100007",
223        "TakenAlone": "1",
224        "UMask": "0x1",
225        "Unit": "cpu_core"
226    },
227    {
228        "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 32 cycles which was not interrupted by a back-end stall.",
229        "CollectPEBSRecord": "2",
230        "Counter": "0,1,2,3,4,5,6,7",
231        "EventCode": "0xc6",
232        "EventName": "FRONTEND_RETIRED.LATENCY_GE_32",
233        "MSRIndex": "0x3F7",
234        "MSRValue": "0x602006",
235        "PEBS": "1",
236        "PEBScounters": "0,1,2,3,4,5,6,7",
237        "SampleAfterValue": "100007",
238        "TakenAlone": "1",
239        "UMask": "0x1",
240        "Unit": "cpu_core"
241    },
242    {
243        "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 4 cycles which was not interrupted by a back-end stall.",
244        "CollectPEBSRecord": "2",
245        "Counter": "0,1,2,3,4,5,6,7",
246        "EventCode": "0xc6",
247        "EventName": "FRONTEND_RETIRED.LATENCY_GE_4",
248        "MSRIndex": "0x3F7",
249        "MSRValue": "0x600406",
250        "PEBS": "1",
251        "PEBScounters": "0,1,2,3,4,5,6,7",
252        "SampleAfterValue": "100007",
253        "TakenAlone": "1",
254        "UMask": "0x1",
255        "Unit": "cpu_core"
256    },
257    {
258        "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 512 cycles which was not interrupted by a back-end stall.",
259        "CollectPEBSRecord": "2",
260        "Counter": "0,1,2,3,4,5,6,7",
261        "EventCode": "0xc6",
262        "EventName": "FRONTEND_RETIRED.LATENCY_GE_512",
263        "MSRIndex": "0x3F7",
264        "MSRValue": "0x620006",
265        "PEBS": "1",
266        "PEBScounters": "0,1,2,3,4,5,6,7",
267        "SampleAfterValue": "100007",
268        "TakenAlone": "1",
269        "UMask": "0x1",
270        "Unit": "cpu_core"
271    },
272    {
273        "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 64 cycles which was not interrupted by a back-end stall.",
274        "CollectPEBSRecord": "2",
275        "Counter": "0,1,2,3,4,5,6,7",
276        "EventCode": "0xc6",
277        "EventName": "FRONTEND_RETIRED.LATENCY_GE_64",
278        "MSRIndex": "0x3F7",
279        "MSRValue": "0x604006",
280        "PEBS": "1",
281        "PEBScounters": "0,1,2,3,4,5,6,7",
282        "SampleAfterValue": "100007",
283        "TakenAlone": "1",
284        "UMask": "0x1",
285        "Unit": "cpu_core"
286    },
287    {
288        "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 8 cycles which was not interrupted by a back-end stall.",
289        "CollectPEBSRecord": "2",
290        "Counter": "0,1,2,3,4,5,6,7",
291        "EventCode": "0xc6",
292        "EventName": "FRONTEND_RETIRED.LATENCY_GE_8",
293        "MSRIndex": "0x3F7",
294        "MSRValue": "0x600806",
295        "PEBS": "1",
296        "PEBScounters": "0,1,2,3,4,5,6,7",
297        "SampleAfterValue": "100007",
298        "TakenAlone": "1",
299        "UMask": "0x1",
300        "Unit": "cpu_core"
301    },
302    {
303        "BriefDescription": "FRONTEND_RETIRED.MS_FLOWS",
304        "CollectPEBSRecord": "2",
305        "Counter": "0,1,2,3,4,5,6,7",
306        "EventCode": "0xc6",
307        "EventName": "FRONTEND_RETIRED.MS_FLOWS",
308        "MSRIndex": "0x3F7",
309        "MSRValue": "0x8",
310        "PEBS": "1",
311        "PEBScounters": "0,1,2,3,4,5,6,7",
312        "SampleAfterValue": "100007",
313        "TakenAlone": "1",
314        "UMask": "0x1",
315        "Unit": "cpu_core"
316    },
317    {
318        "BriefDescription": "Retired Instructions who experienced STLB (2nd level TLB) true miss.",
319        "CollectPEBSRecord": "2",
320        "Counter": "0,1,2,3,4,5,6,7",
321        "EventCode": "0xc6",
322        "EventName": "FRONTEND_RETIRED.STLB_MISS",
323        "MSRIndex": "0x3F7",
324        "MSRValue": "0x15",
325        "PEBS": "1",
326        "PEBScounters": "0,1,2,3,4,5,6,7",
327        "SampleAfterValue": "100007",
328        "TakenAlone": "1",
329        "UMask": "0x1",
330        "Unit": "cpu_core"
331    },
332    {
333        "BriefDescription": "FRONTEND_RETIRED.UNKNOWN_BRANCH",
334        "CollectPEBSRecord": "2",
335        "Counter": "0,1,2,3,4,5,6,7",
336        "EventCode": "0xc6",
337        "EventName": "FRONTEND_RETIRED.UNKNOWN_BRANCH",
338        "MSRIndex": "0x3F7",
339        "MSRValue": "0x17",
340        "PEBS": "1",
341        "PEBScounters": "0,1,2,3,4,5,6,7",
342        "SampleAfterValue": "100007",
343        "TakenAlone": "1",
344        "UMask": "0x1",
345        "Unit": "cpu_core"
346    },
347    {
348        "BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction cache miss.",
349        "CollectPEBSRecord": "2",
350        "Counter": "0,1,2,3",
351        "EventCode": "0x80",
352        "EventName": "ICACHE_DATA.STALLS",
353        "PEBScounters": "0,1,2,3",
354        "SampleAfterValue": "500009",
355        "Speculative": "1",
356        "UMask": "0x4",
357        "Unit": "cpu_core"
358    },
359    {
360        "BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction cache tag miss.",
361        "CollectPEBSRecord": "2",
362        "Counter": "0,1,2,3",
363        "EventCode": "0x83",
364        "EventName": "ICACHE_TAG.STALLS",
365        "PEBScounters": "0,1,2,3",
366        "SampleAfterValue": "200003",
367        "Speculative": "1",
368        "UMask": "0x4",
369        "Unit": "cpu_core"
370    },
371    {
372        "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering any Uop",
373        "CollectPEBSRecord": "2",
374        "Counter": "0,1,2,3",
375        "CounterMask": "1",
376        "EventCode": "0x79",
377        "EventName": "IDQ.DSB_CYCLES_ANY",
378        "PEBScounters": "0,1,2,3",
379        "SampleAfterValue": "2000003",
380        "Speculative": "1",
381        "UMask": "0x8",
382        "Unit": "cpu_core"
383    },
384    {
385        "BriefDescription": "Cycles DSB is delivering optimal number of Uops",
386        "CollectPEBSRecord": "2",
387        "Counter": "0,1,2,3",
388        "CounterMask": "6",
389        "EventCode": "0x79",
390        "EventName": "IDQ.DSB_CYCLES_OK",
391        "PEBScounters": "0,1,2,3",
392        "SampleAfterValue": "2000003",
393        "Speculative": "1",
394        "UMask": "0x8",
395        "Unit": "cpu_core"
396    },
397    {
398        "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path",
399        "CollectPEBSRecord": "2",
400        "Counter": "0,1,2,3",
401        "EventCode": "0x79",
402        "EventName": "IDQ.DSB_UOPS",
403        "PEBScounters": "0,1,2,3",
404        "SampleAfterValue": "2000003",
405        "Speculative": "1",
406        "UMask": "0x8",
407        "Unit": "cpu_core"
408    },
409    {
410        "BriefDescription": "Cycles MITE is delivering any Uop",
411        "CollectPEBSRecord": "2",
412        "Counter": "0,1,2,3",
413        "CounterMask": "1",
414        "EventCode": "0x79",
415        "EventName": "IDQ.MITE_CYCLES_ANY",
416        "PEBScounters": "0,1,2,3",
417        "SampleAfterValue": "2000003",
418        "Speculative": "1",
419        "UMask": "0x4",
420        "Unit": "cpu_core"
421    },
422    {
423        "BriefDescription": "Cycles MITE is delivering optimal number of Uops",
424        "CollectPEBSRecord": "2",
425        "Counter": "0,1,2,3",
426        "CounterMask": "6",
427        "EventCode": "0x79",
428        "EventName": "IDQ.MITE_CYCLES_OK",
429        "PEBScounters": "0,1,2,3",
430        "SampleAfterValue": "2000003",
431        "Speculative": "1",
432        "UMask": "0x4",
433        "Unit": "cpu_core"
434    },
435    {
436        "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from MITE path",
437        "CollectPEBSRecord": "2",
438        "Counter": "0,1,2,3",
439        "EventCode": "0x79",
440        "EventName": "IDQ.MITE_UOPS",
441        "PEBScounters": "0,1,2,3",
442        "SampleAfterValue": "2000003",
443        "Speculative": "1",
444        "UMask": "0x4",
445        "Unit": "cpu_core"
446    },
447    {
448        "BriefDescription": "Cycles when uops are being delivered to IDQ while MS is busy",
449        "CollectPEBSRecord": "2",
450        "Counter": "0,1,2,3",
451        "CounterMask": "1",
452        "EventCode": "0x79",
453        "EventName": "IDQ.MS_CYCLES_ANY",
454        "PEBScounters": "0,1,2,3",
455        "SampleAfterValue": "2000003",
456        "Speculative": "1",
457        "UMask": "0x20",
458        "Unit": "cpu_core"
459    },
460    {
461        "BriefDescription": "Number of switches from DSB or MITE to the MS",
462        "CollectPEBSRecord": "2",
463        "Counter": "0,1,2,3",
464        "CounterMask": "1",
465        "EdgeDetect": "1",
466        "EventCode": "0x79",
467        "EventName": "IDQ.MS_SWITCHES",
468        "PEBScounters": "0,1,2,3",
469        "SampleAfterValue": "100003",
470        "Speculative": "1",
471        "UMask": "0x20",
472        "Unit": "cpu_core"
473    },
474    {
475        "BriefDescription": "Uops delivered to IDQ while MS is busy",
476        "CollectPEBSRecord": "2",
477        "Counter": "0,1,2,3",
478        "EventCode": "0x79",
479        "EventName": "IDQ.MS_UOPS",
480        "PEBScounters": "0,1,2,3",
481        "SampleAfterValue": "1000003",
482        "Speculative": "1",
483        "UMask": "0x20",
484        "Unit": "cpu_core"
485    },
486    {
487        "BriefDescription": "Uops not delivered by IDQ when backend of the machine is not stalled",
488        "CollectPEBSRecord": "2",
489        "Counter": "0,1,2,3,4,5,6,7",
490        "EventCode": "0x9c",
491        "EventName": "IDQ_UOPS_NOT_DELIVERED.CORE",
492        "PEBScounters": "0,1,2,3,4,5,6,7",
493        "SampleAfterValue": "1000003",
494        "Speculative": "1",
495        "UMask": "0x1",
496        "Unit": "cpu_core"
497    },
498    {
499        "BriefDescription": "Cycles when no uops are not delivered by the IDQ when backend of the machine is not stalled",
500        "CollectPEBSRecord": "2",
501        "Counter": "0,1,2,3,4,5,6,7",
502        "CounterMask": "6",
503        "EventCode": "0x9c",
504        "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE",
505        "PEBScounters": "0,1,2,3,4,5,6,7",
506        "SampleAfterValue": "1000003",
507        "Speculative": "1",
508        "UMask": "0x1",
509        "Unit": "cpu_core"
510    },
511    {
512        "BriefDescription": "Cycles when optimal number of uops was delivered to the back-end when the back-end is not stalled",
513        "CollectPEBSRecord": "2",
514        "Counter": "0,1,2,3,4,5,6,7",
515        "CounterMask": "1",
516        "EventCode": "0x9c",
517        "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_FE_WAS_OK",
518        "Invert": "1",
519        "PEBScounters": "0,1,2,3,4,5,6,7",
520        "SampleAfterValue": "1000003",
521        "Speculative": "1",
522        "UMask": "0x1",
523        "Unit": "cpu_core"
524    }
525]
526