1[
2    {
3        "BriefDescription": "Counts the total number of BACLEARS due to all branch types including conditional and unconditional jumps, returns, and indirect branches.",
4        "CollectPEBSRecord": "2",
5        "Counter": "0,1,2,3,4,5",
6        "EventCode": "0xe6",
7        "EventName": "BACLEARS.ANY",
8        "PEBScounters": "0,1,2,3,4,5",
9        "SampleAfterValue": "100003",
10        "Speculative": "1",
11        "UMask": "0x1",
12        "Unit": "cpu_atom"
13    },
14    {
15        "BriefDescription": "Counts the number of requests to the instruction cache for one or more bytes of a cache line.",
16        "CollectPEBSRecord": "2",
17        "Counter": "0,1,2,3,4,5",
18        "EventCode": "0x80",
19        "EventName": "ICACHE.ACCESSES",
20        "PEBScounters": "0,1,2,3,4,5",
21        "SampleAfterValue": "200003",
22        "Speculative": "1",
23        "UMask": "0x3",
24        "Unit": "cpu_atom"
25    },
26    {
27        "BriefDescription": "Counts the number of instruction cache misses.",
28        "CollectPEBSRecord": "2",
29        "Counter": "0,1,2,3,4,5",
30        "EventCode": "0x80",
31        "EventName": "ICACHE.MISSES",
32        "PEBScounters": "0,1,2,3,4,5",
33        "SampleAfterValue": "200003",
34        "Speculative": "1",
35        "UMask": "0x2",
36        "Unit": "cpu_atom"
37    },
38    {
39        "BriefDescription": "Stalls caused by changing prefix length of the instruction.",
40        "CollectPEBSRecord": "2",
41        "Counter": "0,1,2,3",
42        "EventCode": "0x87",
43        "EventName": "DECODE.LCP",
44        "PEBScounters": "0,1,2,3",
45        "SampleAfterValue": "500009",
46        "Speculative": "1",
47        "UMask": "0x1",
48        "Unit": "cpu_core"
49    },
50    {
51        "BriefDescription": "Cycles the Microcode Sequencer is busy.",
52        "CollectPEBSRecord": "2",
53        "Counter": "0,1,2,3",
54        "EventCode": "0x87",
55        "EventName": "DECODE.MS_BUSY",
56        "PEBScounters": "0,1,2,3",
57        "SampleAfterValue": "500009",
58        "Speculative": "1",
59        "UMask": "0x2",
60        "Unit": "cpu_core"
61    },
62    {
63        "BriefDescription": "DSB-to-MITE switch true penalty cycles.",
64        "CollectPEBSRecord": "2",
65        "Counter": "0,1,2,3",
66        "EventCode": "0x61",
67        "EventName": "DSB2MITE_SWITCHES.PENALTY_CYCLES",
68        "PEBScounters": "0,1,2,3",
69        "SampleAfterValue": "100003",
70        "Speculative": "1",
71        "UMask": "0x2",
72        "Unit": "cpu_core"
73    },
74    {
75        "BriefDescription": "Retired Instructions who experienced DSB miss.",
76        "CollectPEBSRecord": "2",
77        "Counter": "0,1,2,3,4,5,6,7",
78        "EventCode": "0xc6",
79        "EventName": "FRONTEND_RETIRED.ANY_DSB_MISS",
80        "MSRIndex": "0x3F7",
81        "MSRValue": "0x1",
82        "PEBS": "1",
83        "PEBScounters": "0,1,2,3,4,5,6,7",
84        "SampleAfterValue": "100007",
85        "TakenAlone": "1",
86        "UMask": "0x1",
87        "Unit": "cpu_core"
88    },
89    {
90        "BriefDescription": "Retired Instructions who experienced a critical DSB miss.",
91        "CollectPEBSRecord": "2",
92        "Counter": "0,1,2,3,4,5,6,7",
93        "EventCode": "0xc6",
94        "EventName": "FRONTEND_RETIRED.DSB_MISS",
95        "MSRIndex": "0x3F7",
96        "MSRValue": "0x11",
97        "PEBS": "1",
98        "PEBScounters": "0,1,2,3,4,5,6,7",
99        "SampleAfterValue": "100007",
100        "TakenAlone": "1",
101        "UMask": "0x1",
102        "Unit": "cpu_core"
103    },
104    {
105        "BriefDescription": "Retired Instructions who experienced iTLB true miss.",
106        "CollectPEBSRecord": "2",
107        "Counter": "0,1,2,3,4,5,6,7",
108        "EventCode": "0xc6",
109        "EventName": "FRONTEND_RETIRED.ITLB_MISS",
110        "MSRIndex": "0x3F7",
111        "MSRValue": "0x14",
112        "PEBS": "1",
113        "PEBScounters": "0,1,2,3,4,5,6,7",
114        "SampleAfterValue": "100007",
115        "TakenAlone": "1",
116        "UMask": "0x1",
117        "Unit": "cpu_core"
118    },
119    {
120        "BriefDescription": "Retired Instructions who experienced Instruction L1 Cache true miss.",
121        "CollectPEBSRecord": "2",
122        "Counter": "0,1,2,3,4,5,6,7",
123        "EventCode": "0xc6",
124        "EventName": "FRONTEND_RETIRED.L1I_MISS",
125        "MSRIndex": "0x3F7",
126        "MSRValue": "0x12",
127        "PEBS": "1",
128        "PEBScounters": "0,1,2,3,4,5,6,7",
129        "SampleAfterValue": "100007",
130        "TakenAlone": "1",
131        "UMask": "0x1",
132        "Unit": "cpu_core"
133    },
134    {
135        "BriefDescription": "Retired Instructions who experienced Instruction L2 Cache true miss.",
136        "CollectPEBSRecord": "2",
137        "Counter": "0,1,2,3,4,5,6,7",
138        "EventCode": "0xc6",
139        "EventName": "FRONTEND_RETIRED.L2_MISS",
140        "MSRIndex": "0x3F7",
141        "MSRValue": "0x13",
142        "PEBS": "1",
143        "PEBScounters": "0,1,2,3,4,5,6,7",
144        "SampleAfterValue": "100007",
145        "TakenAlone": "1",
146        "UMask": "0x1",
147        "Unit": "cpu_core"
148    },
149    {
150        "BriefDescription": "Retired instructions after front-end starvation of at least 1 cycle",
151        "CollectPEBSRecord": "2",
152        "Counter": "0,1,2,3,4,5,6,7",
153        "EventCode": "0xc6",
154        "EventName": "FRONTEND_RETIRED.LATENCY_GE_1",
155        "MSRIndex": "0x3F7",
156        "MSRValue": "0x600106",
157        "PEBS": "1",
158        "PEBScounters": "0,1,2,3,4,5,6,7",
159        "SampleAfterValue": "100007",
160        "TakenAlone": "1",
161        "UMask": "0x1",
162        "Unit": "cpu_core"
163    },
164    {
165        "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 128 cycles which was not interrupted by a back-end stall.",
166        "CollectPEBSRecord": "2",
167        "Counter": "0,1,2,3,4,5,6,7",
168        "EventCode": "0xc6",
169        "EventName": "FRONTEND_RETIRED.LATENCY_GE_128",
170        "MSRIndex": "0x3F7",
171        "MSRValue": "0x608006",
172        "PEBS": "1",
173        "PEBScounters": "0,1,2,3,4,5,6,7",
174        "SampleAfterValue": "100007",
175        "TakenAlone": "1",
176        "UMask": "0x1",
177        "Unit": "cpu_core"
178    },
179    {
180        "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 16 cycles which was not interrupted by a back-end stall.",
181        "CollectPEBSRecord": "2",
182        "Counter": "0,1,2,3,4,5,6,7",
183        "EventCode": "0xc6",
184        "EventName": "FRONTEND_RETIRED.LATENCY_GE_16",
185        "MSRIndex": "0x3F7",
186        "MSRValue": "0x601006",
187        "PEBS": "1",
188        "PEBScounters": "0,1,2,3,4,5,6,7",
189        "SampleAfterValue": "100007",
190        "TakenAlone": "1",
191        "UMask": "0x1",
192        "Unit": "cpu_core"
193    },
194    {
195        "BriefDescription": "Retired instructions after front-end starvation of at least 2 cycles",
196        "CollectPEBSRecord": "2",
197        "Counter": "0,1,2,3,4,5,6,7",
198        "EventCode": "0xc6",
199        "EventName": "FRONTEND_RETIRED.LATENCY_GE_2",
200        "MSRIndex": "0x3F7",
201        "MSRValue": "0x600206",
202        "PEBS": "1",
203        "PEBScounters": "0,1,2,3,4,5,6,7",
204        "SampleAfterValue": "100007",
205        "TakenAlone": "1",
206        "UMask": "0x1",
207        "Unit": "cpu_core"
208    },
209    {
210        "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 256 cycles which was not interrupted by a back-end stall.",
211        "CollectPEBSRecord": "2",
212        "Counter": "0,1,2,3,4,5,6,7",
213        "EventCode": "0xc6",
214        "EventName": "FRONTEND_RETIRED.LATENCY_GE_256",
215        "MSRIndex": "0x3F7",
216        "MSRValue": "0x610006",
217        "PEBS": "1",
218        "PEBScounters": "0,1,2,3,4,5,6,7",
219        "SampleAfterValue": "100007",
220        "TakenAlone": "1",
221        "UMask": "0x1",
222        "Unit": "cpu_core"
223    },
224    {
225        "BriefDescription": "Retired instructions that are fetched after an interval where the front-end had at least 1 bubble-slot for a period of 2 cycles which was not interrupted by a back-end stall.",
226        "CollectPEBSRecord": "2",
227        "Counter": "0,1,2,3,4,5,6,7",
228        "EventCode": "0xc6",
229        "EventName": "FRONTEND_RETIRED.LATENCY_GE_2_BUBBLES_GE_1",
230        "MSRIndex": "0x3F7",
231        "MSRValue": "0x100206",
232        "PEBS": "1",
233        "PEBScounters": "0,1,2,3,4,5,6,7",
234        "SampleAfterValue": "100007",
235        "TakenAlone": "1",
236        "UMask": "0x1",
237        "Unit": "cpu_core"
238    },
239    {
240        "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 32 cycles which was not interrupted by a back-end stall.",
241        "CollectPEBSRecord": "2",
242        "Counter": "0,1,2,3,4,5,6,7",
243        "EventCode": "0xc6",
244        "EventName": "FRONTEND_RETIRED.LATENCY_GE_32",
245        "MSRIndex": "0x3F7",
246        "MSRValue": "0x602006",
247        "PEBS": "1",
248        "PEBScounters": "0,1,2,3,4,5,6,7",
249        "SampleAfterValue": "100007",
250        "TakenAlone": "1",
251        "UMask": "0x1",
252        "Unit": "cpu_core"
253    },
254    {
255        "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 4 cycles which was not interrupted by a back-end stall.",
256        "CollectPEBSRecord": "2",
257        "Counter": "0,1,2,3,4,5,6,7",
258        "EventCode": "0xc6",
259        "EventName": "FRONTEND_RETIRED.LATENCY_GE_4",
260        "MSRIndex": "0x3F7",
261        "MSRValue": "0x600406",
262        "PEBS": "1",
263        "PEBScounters": "0,1,2,3,4,5,6,7",
264        "SampleAfterValue": "100007",
265        "TakenAlone": "1",
266        "UMask": "0x1",
267        "Unit": "cpu_core"
268    },
269    {
270        "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 512 cycles which was not interrupted by a back-end stall.",
271        "CollectPEBSRecord": "2",
272        "Counter": "0,1,2,3,4,5,6,7",
273        "EventCode": "0xc6",
274        "EventName": "FRONTEND_RETIRED.LATENCY_GE_512",
275        "MSRIndex": "0x3F7",
276        "MSRValue": "0x620006",
277        "PEBS": "1",
278        "PEBScounters": "0,1,2,3,4,5,6,7",
279        "SampleAfterValue": "100007",
280        "TakenAlone": "1",
281        "UMask": "0x1",
282        "Unit": "cpu_core"
283    },
284    {
285        "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 64 cycles which was not interrupted by a back-end stall.",
286        "CollectPEBSRecord": "2",
287        "Counter": "0,1,2,3,4,5,6,7",
288        "EventCode": "0xc6",
289        "EventName": "FRONTEND_RETIRED.LATENCY_GE_64",
290        "MSRIndex": "0x3F7",
291        "MSRValue": "0x604006",
292        "PEBS": "1",
293        "PEBScounters": "0,1,2,3,4,5,6,7",
294        "SampleAfterValue": "100007",
295        "TakenAlone": "1",
296        "UMask": "0x1",
297        "Unit": "cpu_core"
298    },
299    {
300        "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 8 cycles which was not interrupted by a back-end stall.",
301        "CollectPEBSRecord": "2",
302        "Counter": "0,1,2,3,4,5,6,7",
303        "EventCode": "0xc6",
304        "EventName": "FRONTEND_RETIRED.LATENCY_GE_8",
305        "MSRIndex": "0x3F7",
306        "MSRValue": "0x600806",
307        "PEBS": "1",
308        "PEBScounters": "0,1,2,3,4,5,6,7",
309        "SampleAfterValue": "100007",
310        "TakenAlone": "1",
311        "UMask": "0x1",
312        "Unit": "cpu_core"
313    },
314    {
315        "BriefDescription": "FRONTEND_RETIRED.MS_FLOWS",
316        "CollectPEBSRecord": "2",
317        "Counter": "0,1,2,3,4,5,6,7",
318        "EventCode": "0xc6",
319        "EventName": "FRONTEND_RETIRED.MS_FLOWS",
320        "MSRIndex": "0x3F7",
321        "MSRValue": "0x8",
322        "PEBS": "1",
323        "PEBScounters": "0,1,2,3,4,5,6,7",
324        "SampleAfterValue": "100007",
325        "TakenAlone": "1",
326        "UMask": "0x1",
327        "Unit": "cpu_core"
328    },
329    {
330        "BriefDescription": "Retired Instructions who experienced STLB (2nd level TLB) true miss.",
331        "CollectPEBSRecord": "2",
332        "Counter": "0,1,2,3,4,5,6,7",
333        "EventCode": "0xc6",
334        "EventName": "FRONTEND_RETIRED.STLB_MISS",
335        "MSRIndex": "0x3F7",
336        "MSRValue": "0x15",
337        "PEBS": "1",
338        "PEBScounters": "0,1,2,3,4,5,6,7",
339        "SampleAfterValue": "100007",
340        "TakenAlone": "1",
341        "UMask": "0x1",
342        "Unit": "cpu_core"
343    },
344    {
345        "BriefDescription": "FRONTEND_RETIRED.UNKNOWN_BRANCH",
346        "CollectPEBSRecord": "2",
347        "Counter": "0,1,2,3,4,5,6,7",
348        "EventCode": "0xc6",
349        "EventName": "FRONTEND_RETIRED.UNKNOWN_BRANCH",
350        "MSRIndex": "0x3F7",
351        "MSRValue": "0x17",
352        "PEBS": "1",
353        "PEBScounters": "0,1,2,3,4,5,6,7",
354        "SampleAfterValue": "100007",
355        "TakenAlone": "1",
356        "UMask": "0x1",
357        "Unit": "cpu_core"
358    },
359    {
360        "BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction cache miss.",
361        "CollectPEBSRecord": "2",
362        "Counter": "0,1,2,3",
363        "EventCode": "0x80",
364        "EventName": "ICACHE_DATA.STALLS",
365        "PEBScounters": "0,1,2,3",
366        "SampleAfterValue": "500009",
367        "Speculative": "1",
368        "UMask": "0x4",
369        "Unit": "cpu_core"
370    },
371    {
372        "BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction cache tag miss.",
373        "CollectPEBSRecord": "2",
374        "Counter": "0,1,2,3",
375        "EventCode": "0x83",
376        "EventName": "ICACHE_TAG.STALLS",
377        "PEBScounters": "0,1,2,3",
378        "SampleAfterValue": "200003",
379        "Speculative": "1",
380        "UMask": "0x4",
381        "Unit": "cpu_core"
382    },
383    {
384        "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering any Uop",
385        "CollectPEBSRecord": "2",
386        "Counter": "0,1,2,3",
387        "CounterMask": "1",
388        "EventCode": "0x79",
389        "EventName": "IDQ.DSB_CYCLES_ANY",
390        "PEBScounters": "0,1,2,3",
391        "SampleAfterValue": "2000003",
392        "Speculative": "1",
393        "UMask": "0x8",
394        "Unit": "cpu_core"
395    },
396    {
397        "BriefDescription": "Cycles DSB is delivering optimal number of Uops",
398        "CollectPEBSRecord": "2",
399        "Counter": "0,1,2,3",
400        "CounterMask": "6",
401        "EventCode": "0x79",
402        "EventName": "IDQ.DSB_CYCLES_OK",
403        "PEBScounters": "0,1,2,3",
404        "SampleAfterValue": "2000003",
405        "Speculative": "1",
406        "UMask": "0x8",
407        "Unit": "cpu_core"
408    },
409    {
410        "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path",
411        "CollectPEBSRecord": "2",
412        "Counter": "0,1,2,3",
413        "EventCode": "0x79",
414        "EventName": "IDQ.DSB_UOPS",
415        "PEBScounters": "0,1,2,3",
416        "SampleAfterValue": "2000003",
417        "Speculative": "1",
418        "UMask": "0x8",
419        "Unit": "cpu_core"
420    },
421    {
422        "BriefDescription": "Cycles MITE is delivering any Uop",
423        "CollectPEBSRecord": "2",
424        "Counter": "0,1,2,3",
425        "CounterMask": "1",
426        "EventCode": "0x79",
427        "EventName": "IDQ.MITE_CYCLES_ANY",
428        "PEBScounters": "0,1,2,3",
429        "SampleAfterValue": "2000003",
430        "Speculative": "1",
431        "UMask": "0x4",
432        "Unit": "cpu_core"
433    },
434    {
435        "BriefDescription": "Cycles MITE is delivering optimal number of Uops",
436        "CollectPEBSRecord": "2",
437        "Counter": "0,1,2,3",
438        "CounterMask": "6",
439        "EventCode": "0x79",
440        "EventName": "IDQ.MITE_CYCLES_OK",
441        "PEBScounters": "0,1,2,3",
442        "SampleAfterValue": "2000003",
443        "Speculative": "1",
444        "UMask": "0x4",
445        "Unit": "cpu_core"
446    },
447    {
448        "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from MITE path",
449        "CollectPEBSRecord": "2",
450        "Counter": "0,1,2,3",
451        "EventCode": "0x79",
452        "EventName": "IDQ.MITE_UOPS",
453        "PEBScounters": "0,1,2,3",
454        "SampleAfterValue": "2000003",
455        "Speculative": "1",
456        "UMask": "0x4",
457        "Unit": "cpu_core"
458    },
459    {
460        "BriefDescription": "Cycles when uops are being delivered to IDQ while MS is busy",
461        "CollectPEBSRecord": "2",
462        "Counter": "0,1,2,3",
463        "CounterMask": "1",
464        "EventCode": "0x79",
465        "EventName": "IDQ.MS_CYCLES_ANY",
466        "PEBScounters": "0,1,2,3",
467        "SampleAfterValue": "2000003",
468        "Speculative": "1",
469        "UMask": "0x20",
470        "Unit": "cpu_core"
471    },
472    {
473        "BriefDescription": "Number of switches from DSB or MITE to the MS",
474        "CollectPEBSRecord": "2",
475        "Counter": "0,1,2,3",
476        "CounterMask": "1",
477        "EdgeDetect": "1",
478        "EventCode": "0x79",
479        "EventName": "IDQ.MS_SWITCHES",
480        "PEBScounters": "0,1,2,3",
481        "SampleAfterValue": "100003",
482        "Speculative": "1",
483        "UMask": "0x20",
484        "Unit": "cpu_core"
485    },
486    {
487        "BriefDescription": "Uops delivered to IDQ while MS is busy",
488        "CollectPEBSRecord": "2",
489        "Counter": "0,1,2,3",
490        "EventCode": "0x79",
491        "EventName": "IDQ.MS_UOPS",
492        "PEBScounters": "0,1,2,3",
493        "SampleAfterValue": "1000003",
494        "Speculative": "1",
495        "UMask": "0x20",
496        "Unit": "cpu_core"
497    },
498    {
499        "BriefDescription": "Uops not delivered by IDQ when backend of the machine is not stalled",
500        "CollectPEBSRecord": "2",
501        "Counter": "0,1,2,3,4,5,6,7",
502        "EventCode": "0x9c",
503        "EventName": "IDQ_UOPS_NOT_DELIVERED.CORE",
504        "PEBScounters": "0,1,2,3,4,5,6,7",
505        "SampleAfterValue": "1000003",
506        "Speculative": "1",
507        "UMask": "0x1",
508        "Unit": "cpu_core"
509    },
510    {
511        "BriefDescription": "Cycles when no uops are not delivered by the IDQ when backend of the machine is not stalled",
512        "CollectPEBSRecord": "2",
513        "Counter": "0,1,2,3,4,5,6,7",
514        "CounterMask": "6",
515        "EventCode": "0x9c",
516        "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE",
517        "PEBScounters": "0,1,2,3,4,5,6,7",
518        "SampleAfterValue": "1000003",
519        "Speculative": "1",
520        "UMask": "0x1",
521        "Unit": "cpu_core"
522    },
523    {
524        "BriefDescription": "Cycles when optimal number of uops was delivered to the back-end when the back-end is not stalled",
525        "CollectPEBSRecord": "2",
526        "Counter": "0,1,2,3,4,5,6,7",
527        "CounterMask": "1",
528        "EventCode": "0x9c",
529        "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_FE_WAS_OK",
530        "Invert": "1",
531        "PEBScounters": "0,1,2,3,4,5,6,7",
532        "SampleAfterValue": "1000003",
533        "Speculative": "1",
534        "UMask": "0x1",
535        "Unit": "cpu_core"
536    }
537]
538