1*f9900dd0SZhengjun Xing[ 2*f9900dd0SZhengjun Xing { 3*f9900dd0SZhengjun Xing "BriefDescription": "Counts the total number of BACLEARS due to all branch types including conditional and unconditional jumps, returns, and indirect branches.", 4*f9900dd0SZhengjun Xing "CollectPEBSRecord": "2", 5*f9900dd0SZhengjun Xing "Counter": "0,1,2,3,4,5", 6*f9900dd0SZhengjun Xing "EventCode": "0xe6", 7*f9900dd0SZhengjun Xing "EventName": "BACLEARS.ANY", 8*f9900dd0SZhengjun Xing "PEBScounters": "0,1,2,3,4,5", 9*f9900dd0SZhengjun Xing "SampleAfterValue": "100003", 10*f9900dd0SZhengjun Xing "UMask": "0x1", 11*f9900dd0SZhengjun Xing "Unit": "cpu_atom" 12*f9900dd0SZhengjun Xing }, 13*f9900dd0SZhengjun Xing { 14*f9900dd0SZhengjun Xing "BriefDescription": "Counts the number of requests to the instruction cache for one or more bytes of a cache line.", 15*f9900dd0SZhengjun Xing "CollectPEBSRecord": "2", 16*f9900dd0SZhengjun Xing "Counter": "0,1,2,3,4,5", 17*f9900dd0SZhengjun Xing "EventCode": "0x80", 18*f9900dd0SZhengjun Xing "EventName": "ICACHE.ACCESSES", 19*f9900dd0SZhengjun Xing "PEBScounters": "0,1,2,3,4,5", 20*f9900dd0SZhengjun Xing "SampleAfterValue": "200003", 21*f9900dd0SZhengjun Xing "UMask": "0x3", 22*f9900dd0SZhengjun Xing "Unit": "cpu_atom" 23*f9900dd0SZhengjun Xing }, 24*f9900dd0SZhengjun Xing { 25*f9900dd0SZhengjun Xing "BriefDescription": "Counts the number of instruction cache misses.", 26*f9900dd0SZhengjun Xing "CollectPEBSRecord": "2", 27*f9900dd0SZhengjun Xing "Counter": "0,1,2,3,4,5", 28*f9900dd0SZhengjun Xing "EventCode": "0x80", 29*f9900dd0SZhengjun Xing "EventName": "ICACHE.MISSES", 30*f9900dd0SZhengjun Xing "PEBScounters": "0,1,2,3,4,5", 31*f9900dd0SZhengjun Xing "SampleAfterValue": "200003", 32*f9900dd0SZhengjun Xing "UMask": "0x2", 33*f9900dd0SZhengjun Xing "Unit": "cpu_atom" 34*f9900dd0SZhengjun Xing }, 35*f9900dd0SZhengjun Xing { 36*f9900dd0SZhengjun Xing "BriefDescription": "Stalls caused by changing prefix length of the instruction.", 37*f9900dd0SZhengjun Xing "CollectPEBSRecord": "2", 38*f9900dd0SZhengjun Xing "Counter": "0,1,2,3", 39*f9900dd0SZhengjun Xing "EventCode": "0x87", 40*f9900dd0SZhengjun Xing "EventName": "DECODE.LCP", 41*f9900dd0SZhengjun Xing "PEBScounters": "0,1,2,3", 42*f9900dd0SZhengjun Xing "SampleAfterValue": "500009", 43*f9900dd0SZhengjun Xing "UMask": "0x1", 44*f9900dd0SZhengjun Xing "Unit": "cpu_core" 45*f9900dd0SZhengjun Xing }, 46*f9900dd0SZhengjun Xing { 47*f9900dd0SZhengjun Xing "BriefDescription": "DSB-to-MITE switch true penalty cycles.", 48*f9900dd0SZhengjun Xing "CollectPEBSRecord": "2", 49*f9900dd0SZhengjun Xing "Counter": "0,1,2,3", 50*f9900dd0SZhengjun Xing "EventCode": "0x61", 51*f9900dd0SZhengjun Xing "EventName": "DSB2MITE_SWITCHES.PENALTY_CYCLES", 52*f9900dd0SZhengjun Xing "PEBScounters": "0,1,2,3", 53*f9900dd0SZhengjun Xing "SampleAfterValue": "100003", 54*f9900dd0SZhengjun Xing "UMask": "0x2", 55*f9900dd0SZhengjun Xing "Unit": "cpu_core" 56*f9900dd0SZhengjun Xing }, 57*f9900dd0SZhengjun Xing { 58*f9900dd0SZhengjun Xing "BriefDescription": "Retired Instructions who experienced DSB miss.", 59*f9900dd0SZhengjun Xing "CollectPEBSRecord": "2", 60*f9900dd0SZhengjun Xing "Counter": "0,1,2,3,4,5,6,7", 61*f9900dd0SZhengjun Xing "EventCode": "0xc6", 62*f9900dd0SZhengjun Xing "EventName": "FRONTEND_RETIRED.ANY_DSB_MISS", 63*f9900dd0SZhengjun Xing "MSRIndex": "0x3F7", 64*f9900dd0SZhengjun Xing "MSRValue": "0x1", 65*f9900dd0SZhengjun Xing "PEBS": "1", 66*f9900dd0SZhengjun Xing "PEBScounters": "0,1,2,3,4,5,6,7", 67*f9900dd0SZhengjun Xing "SampleAfterValue": "100007", 68*f9900dd0SZhengjun Xing "TakenAlone": "1", 69*f9900dd0SZhengjun Xing "UMask": "0x1", 70*f9900dd0SZhengjun Xing "Unit": "cpu_core" 71*f9900dd0SZhengjun Xing }, 72*f9900dd0SZhengjun Xing { 73*f9900dd0SZhengjun Xing "BriefDescription": "Retired Instructions who experienced a critical DSB miss.", 74*f9900dd0SZhengjun Xing "CollectPEBSRecord": "2", 75*f9900dd0SZhengjun Xing "Counter": "0,1,2,3,4,5,6,7", 76*f9900dd0SZhengjun Xing "EventCode": "0xc6", 77*f9900dd0SZhengjun Xing "EventName": "FRONTEND_RETIRED.DSB_MISS", 78*f9900dd0SZhengjun Xing "MSRIndex": "0x3F7", 79*f9900dd0SZhengjun Xing "MSRValue": "0x11", 80*f9900dd0SZhengjun Xing "PEBS": "1", 81*f9900dd0SZhengjun Xing "PEBScounters": "0,1,2,3,4,5,6,7", 82*f9900dd0SZhengjun Xing "SampleAfterValue": "100007", 83*f9900dd0SZhengjun Xing "TakenAlone": "1", 84*f9900dd0SZhengjun Xing "UMask": "0x1", 85*f9900dd0SZhengjun Xing "Unit": "cpu_core" 86*f9900dd0SZhengjun Xing }, 87*f9900dd0SZhengjun Xing { 88*f9900dd0SZhengjun Xing "BriefDescription": "Retired Instructions who experienced iTLB true miss.", 89*f9900dd0SZhengjun Xing "CollectPEBSRecord": "2", 90*f9900dd0SZhengjun Xing "Counter": "0,1,2,3,4,5,6,7", 91*f9900dd0SZhengjun Xing "EventCode": "0xc6", 92*f9900dd0SZhengjun Xing "EventName": "FRONTEND_RETIRED.ITLB_MISS", 93*f9900dd0SZhengjun Xing "MSRIndex": "0x3F7", 94*f9900dd0SZhengjun Xing "MSRValue": "0x14", 95*f9900dd0SZhengjun Xing "PEBS": "1", 96*f9900dd0SZhengjun Xing "PEBScounters": "0,1,2,3,4,5,6,7", 97*f9900dd0SZhengjun Xing "SampleAfterValue": "100007", 98*f9900dd0SZhengjun Xing "TakenAlone": "1", 99*f9900dd0SZhengjun Xing "UMask": "0x1", 100*f9900dd0SZhengjun Xing "Unit": "cpu_core" 101*f9900dd0SZhengjun Xing }, 102*f9900dd0SZhengjun Xing { 103*f9900dd0SZhengjun Xing "BriefDescription": "Retired Instructions who experienced Instruction L1 Cache true miss.", 104*f9900dd0SZhengjun Xing "CollectPEBSRecord": "2", 105*f9900dd0SZhengjun Xing "Counter": "0,1,2,3,4,5,6,7", 106*f9900dd0SZhengjun Xing "EventCode": "0xc6", 107*f9900dd0SZhengjun Xing "EventName": "FRONTEND_RETIRED.L1I_MISS", 108*f9900dd0SZhengjun Xing "MSRIndex": "0x3F7", 109*f9900dd0SZhengjun Xing "MSRValue": "0x12", 110*f9900dd0SZhengjun Xing "PEBS": "1", 111*f9900dd0SZhengjun Xing "PEBScounters": "0,1,2,3,4,5,6,7", 112*f9900dd0SZhengjun Xing "SampleAfterValue": "100007", 113*f9900dd0SZhengjun Xing "TakenAlone": "1", 114*f9900dd0SZhengjun Xing "UMask": "0x1", 115*f9900dd0SZhengjun Xing "Unit": "cpu_core" 116*f9900dd0SZhengjun Xing }, 117*f9900dd0SZhengjun Xing { 118*f9900dd0SZhengjun Xing "BriefDescription": "Retired Instructions who experienced Instruction L2 Cache true miss.", 119*f9900dd0SZhengjun Xing "CollectPEBSRecord": "2", 120*f9900dd0SZhengjun Xing "Counter": "0,1,2,3,4,5,6,7", 121*f9900dd0SZhengjun Xing "EventCode": "0xc6", 122*f9900dd0SZhengjun Xing "EventName": "FRONTEND_RETIRED.L2_MISS", 123*f9900dd0SZhengjun Xing "MSRIndex": "0x3F7", 124*f9900dd0SZhengjun Xing "MSRValue": "0x13", 125*f9900dd0SZhengjun Xing "PEBS": "1", 126*f9900dd0SZhengjun Xing "PEBScounters": "0,1,2,3,4,5,6,7", 127*f9900dd0SZhengjun Xing "SampleAfterValue": "100007", 128*f9900dd0SZhengjun Xing "TakenAlone": "1", 129*f9900dd0SZhengjun Xing "UMask": "0x1", 130*f9900dd0SZhengjun Xing "Unit": "cpu_core" 131*f9900dd0SZhengjun Xing }, 132*f9900dd0SZhengjun Xing { 133*f9900dd0SZhengjun Xing "BriefDescription": "Retired instructions after front-end starvation of at least 1 cycle", 134*f9900dd0SZhengjun Xing "CollectPEBSRecord": "2", 135*f9900dd0SZhengjun Xing "Counter": "0,1,2,3,4,5,6,7", 136*f9900dd0SZhengjun Xing "EventCode": "0xc6", 137*f9900dd0SZhengjun Xing "EventName": "FRONTEND_RETIRED.LATENCY_GE_1", 138*f9900dd0SZhengjun Xing "MSRIndex": "0x3F7", 139*f9900dd0SZhengjun Xing "MSRValue": "0x600106", 140*f9900dd0SZhengjun Xing "PEBS": "1", 141*f9900dd0SZhengjun Xing "PEBScounters": "0,1,2,3,4,5,6,7", 142*f9900dd0SZhengjun Xing "SampleAfterValue": "100007", 143*f9900dd0SZhengjun Xing "TakenAlone": "1", 144*f9900dd0SZhengjun Xing "UMask": "0x1", 145*f9900dd0SZhengjun Xing "Unit": "cpu_core" 146*f9900dd0SZhengjun Xing }, 147*f9900dd0SZhengjun Xing { 148*f9900dd0SZhengjun Xing "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 128 cycles which was not interrupted by a back-end stall.", 149*f9900dd0SZhengjun Xing "CollectPEBSRecord": "2", 150*f9900dd0SZhengjun Xing "Counter": "0,1,2,3,4,5,6,7", 151*f9900dd0SZhengjun Xing "EventCode": "0xc6", 152*f9900dd0SZhengjun Xing "EventName": "FRONTEND_RETIRED.LATENCY_GE_128", 153*f9900dd0SZhengjun Xing "MSRIndex": "0x3F7", 154*f9900dd0SZhengjun Xing "MSRValue": "0x608006", 155*f9900dd0SZhengjun Xing "PEBS": "1", 156*f9900dd0SZhengjun Xing "PEBScounters": "0,1,2,3,4,5,6,7", 157*f9900dd0SZhengjun Xing "SampleAfterValue": "100007", 158*f9900dd0SZhengjun Xing "TakenAlone": "1", 159*f9900dd0SZhengjun Xing "UMask": "0x1", 160*f9900dd0SZhengjun Xing "Unit": "cpu_core" 161*f9900dd0SZhengjun Xing }, 162*f9900dd0SZhengjun Xing { 163*f9900dd0SZhengjun Xing "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 16 cycles which was not interrupted by a back-end stall.", 164*f9900dd0SZhengjun Xing "CollectPEBSRecord": "2", 165*f9900dd0SZhengjun Xing "Counter": "0,1,2,3,4,5,6,7", 166*f9900dd0SZhengjun Xing "EventCode": "0xc6", 167*f9900dd0SZhengjun Xing "EventName": "FRONTEND_RETIRED.LATENCY_GE_16", 168*f9900dd0SZhengjun Xing "MSRIndex": "0x3F7", 169*f9900dd0SZhengjun Xing "MSRValue": "0x601006", 170*f9900dd0SZhengjun Xing "PEBS": "1", 171*f9900dd0SZhengjun Xing "PEBScounters": "0,1,2,3,4,5,6,7", 172*f9900dd0SZhengjun Xing "SampleAfterValue": "100007", 173*f9900dd0SZhengjun Xing "TakenAlone": "1", 174*f9900dd0SZhengjun Xing "UMask": "0x1", 175*f9900dd0SZhengjun Xing "Unit": "cpu_core" 176*f9900dd0SZhengjun Xing }, 177*f9900dd0SZhengjun Xing { 178*f9900dd0SZhengjun Xing "BriefDescription": "Retired instructions after front-end starvation of at least 2 cycles", 179*f9900dd0SZhengjun Xing "CollectPEBSRecord": "2", 180*f9900dd0SZhengjun Xing "Counter": "0,1,2,3,4,5,6,7", 181*f9900dd0SZhengjun Xing "EventCode": "0xc6", 182*f9900dd0SZhengjun Xing "EventName": "FRONTEND_RETIRED.LATENCY_GE_2", 183*f9900dd0SZhengjun Xing "MSRIndex": "0x3F7", 184*f9900dd0SZhengjun Xing "MSRValue": "0x600206", 185*f9900dd0SZhengjun Xing "PEBS": "1", 186*f9900dd0SZhengjun Xing "PEBScounters": "0,1,2,3,4,5,6,7", 187*f9900dd0SZhengjun Xing "SampleAfterValue": "100007", 188*f9900dd0SZhengjun Xing "TakenAlone": "1", 189*f9900dd0SZhengjun Xing "UMask": "0x1", 190*f9900dd0SZhengjun Xing "Unit": "cpu_core" 191*f9900dd0SZhengjun Xing }, 192*f9900dd0SZhengjun Xing { 193*f9900dd0SZhengjun Xing "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 256 cycles which was not interrupted by a back-end stall.", 194*f9900dd0SZhengjun Xing "CollectPEBSRecord": "2", 195*f9900dd0SZhengjun Xing "Counter": "0,1,2,3,4,5,6,7", 196*f9900dd0SZhengjun Xing "EventCode": "0xc6", 197*f9900dd0SZhengjun Xing "EventName": "FRONTEND_RETIRED.LATENCY_GE_256", 198*f9900dd0SZhengjun Xing "MSRIndex": "0x3F7", 199*f9900dd0SZhengjun Xing "MSRValue": "0x610006", 200*f9900dd0SZhengjun Xing "PEBS": "1", 201*f9900dd0SZhengjun Xing "PEBScounters": "0,1,2,3,4,5,6,7", 202*f9900dd0SZhengjun Xing "SampleAfterValue": "100007", 203*f9900dd0SZhengjun Xing "TakenAlone": "1", 204*f9900dd0SZhengjun Xing "UMask": "0x1", 205*f9900dd0SZhengjun Xing "Unit": "cpu_core" 206*f9900dd0SZhengjun Xing }, 207*f9900dd0SZhengjun Xing { 208*f9900dd0SZhengjun Xing "BriefDescription": "Retired instructions that are fetched after an interval where the front-end had at least 1 bubble-slot for a period of 2 cycles which was not interrupted by a back-end stall.", 209*f9900dd0SZhengjun Xing "CollectPEBSRecord": "2", 210*f9900dd0SZhengjun Xing "Counter": "0,1,2,3,4,5,6,7", 211*f9900dd0SZhengjun Xing "EventCode": "0xc6", 212*f9900dd0SZhengjun Xing "EventName": "FRONTEND_RETIRED.LATENCY_GE_2_BUBBLES_GE_1", 213*f9900dd0SZhengjun Xing "MSRIndex": "0x3F7", 214*f9900dd0SZhengjun Xing "MSRValue": "0x100206", 215*f9900dd0SZhengjun Xing "PEBS": "1", 216*f9900dd0SZhengjun Xing "PEBScounters": "0,1,2,3,4,5,6,7", 217*f9900dd0SZhengjun Xing "SampleAfterValue": "100007", 218*f9900dd0SZhengjun Xing "TakenAlone": "1", 219*f9900dd0SZhengjun Xing "UMask": "0x1", 220*f9900dd0SZhengjun Xing "Unit": "cpu_core" 221*f9900dd0SZhengjun Xing }, 222*f9900dd0SZhengjun Xing { 223*f9900dd0SZhengjun Xing "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 32 cycles which was not interrupted by a back-end stall.", 224*f9900dd0SZhengjun Xing "CollectPEBSRecord": "2", 225*f9900dd0SZhengjun Xing "Counter": "0,1,2,3,4,5,6,7", 226*f9900dd0SZhengjun Xing "EventCode": "0xc6", 227*f9900dd0SZhengjun Xing "EventName": "FRONTEND_RETIRED.LATENCY_GE_32", 228*f9900dd0SZhengjun Xing "MSRIndex": "0x3F7", 229*f9900dd0SZhengjun Xing "MSRValue": "0x602006", 230*f9900dd0SZhengjun Xing "PEBS": "1", 231*f9900dd0SZhengjun Xing "PEBScounters": "0,1,2,3,4,5,6,7", 232*f9900dd0SZhengjun Xing "SampleAfterValue": "100007", 233*f9900dd0SZhengjun Xing "TakenAlone": "1", 234*f9900dd0SZhengjun Xing "UMask": "0x1", 235*f9900dd0SZhengjun Xing "Unit": "cpu_core" 236*f9900dd0SZhengjun Xing }, 237*f9900dd0SZhengjun Xing { 238*f9900dd0SZhengjun Xing "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 4 cycles which was not interrupted by a back-end stall.", 239*f9900dd0SZhengjun Xing "CollectPEBSRecord": "2", 240*f9900dd0SZhengjun Xing "Counter": "0,1,2,3,4,5,6,7", 241*f9900dd0SZhengjun Xing "EventCode": "0xc6", 242*f9900dd0SZhengjun Xing "EventName": "FRONTEND_RETIRED.LATENCY_GE_4", 243*f9900dd0SZhengjun Xing "MSRIndex": "0x3F7", 244*f9900dd0SZhengjun Xing "MSRValue": "0x600406", 245*f9900dd0SZhengjun Xing "PEBS": "1", 246*f9900dd0SZhengjun Xing "PEBScounters": "0,1,2,3,4,5,6,7", 247*f9900dd0SZhengjun Xing "SampleAfterValue": "100007", 248*f9900dd0SZhengjun Xing "TakenAlone": "1", 249*f9900dd0SZhengjun Xing "UMask": "0x1", 250*f9900dd0SZhengjun Xing "Unit": "cpu_core" 251*f9900dd0SZhengjun Xing }, 252*f9900dd0SZhengjun Xing { 253*f9900dd0SZhengjun Xing "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 512 cycles which was not interrupted by a back-end stall.", 254*f9900dd0SZhengjun Xing "CollectPEBSRecord": "2", 255*f9900dd0SZhengjun Xing "Counter": "0,1,2,3,4,5,6,7", 256*f9900dd0SZhengjun Xing "EventCode": "0xc6", 257*f9900dd0SZhengjun Xing "EventName": "FRONTEND_RETIRED.LATENCY_GE_512", 258*f9900dd0SZhengjun Xing "MSRIndex": "0x3F7", 259*f9900dd0SZhengjun Xing "MSRValue": "0x620006", 260*f9900dd0SZhengjun Xing "PEBS": "1", 261*f9900dd0SZhengjun Xing "PEBScounters": "0,1,2,3,4,5,6,7", 262*f9900dd0SZhengjun Xing "SampleAfterValue": "100007", 263*f9900dd0SZhengjun Xing "TakenAlone": "1", 264*f9900dd0SZhengjun Xing "UMask": "0x1", 265*f9900dd0SZhengjun Xing "Unit": "cpu_core" 266*f9900dd0SZhengjun Xing }, 267*f9900dd0SZhengjun Xing { 268*f9900dd0SZhengjun Xing "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 64 cycles which was not interrupted by a back-end stall.", 269*f9900dd0SZhengjun Xing "CollectPEBSRecord": "2", 270*f9900dd0SZhengjun Xing "Counter": "0,1,2,3,4,5,6,7", 271*f9900dd0SZhengjun Xing "EventCode": "0xc6", 272*f9900dd0SZhengjun Xing "EventName": "FRONTEND_RETIRED.LATENCY_GE_64", 273*f9900dd0SZhengjun Xing "MSRIndex": "0x3F7", 274*f9900dd0SZhengjun Xing "MSRValue": "0x604006", 275*f9900dd0SZhengjun Xing "PEBS": "1", 276*f9900dd0SZhengjun Xing "PEBScounters": "0,1,2,3,4,5,6,7", 277*f9900dd0SZhengjun Xing "SampleAfterValue": "100007", 278*f9900dd0SZhengjun Xing "TakenAlone": "1", 279*f9900dd0SZhengjun Xing "UMask": "0x1", 280*f9900dd0SZhengjun Xing "Unit": "cpu_core" 281*f9900dd0SZhengjun Xing }, 282*f9900dd0SZhengjun Xing { 283*f9900dd0SZhengjun Xing "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 8 cycles which was not interrupted by a back-end stall.", 284*f9900dd0SZhengjun Xing "CollectPEBSRecord": "2", 285*f9900dd0SZhengjun Xing "Counter": "0,1,2,3,4,5,6,7", 286*f9900dd0SZhengjun Xing "EventCode": "0xc6", 287*f9900dd0SZhengjun Xing "EventName": "FRONTEND_RETIRED.LATENCY_GE_8", 288*f9900dd0SZhengjun Xing "MSRIndex": "0x3F7", 289*f9900dd0SZhengjun Xing "MSRValue": "0x600806", 290*f9900dd0SZhengjun Xing "PEBS": "1", 291*f9900dd0SZhengjun Xing "PEBScounters": "0,1,2,3,4,5,6,7", 292*f9900dd0SZhengjun Xing "SampleAfterValue": "100007", 293*f9900dd0SZhengjun Xing "TakenAlone": "1", 294*f9900dd0SZhengjun Xing "UMask": "0x1", 295*f9900dd0SZhengjun Xing "Unit": "cpu_core" 296*f9900dd0SZhengjun Xing }, 297*f9900dd0SZhengjun Xing { 298*f9900dd0SZhengjun Xing "BriefDescription": "Retired Instructions who experienced STLB (2nd level TLB) true miss.", 299*f9900dd0SZhengjun Xing "CollectPEBSRecord": "2", 300*f9900dd0SZhengjun Xing "Counter": "0,1,2,3,4,5,6,7", 301*f9900dd0SZhengjun Xing "EventCode": "0xc6", 302*f9900dd0SZhengjun Xing "EventName": "FRONTEND_RETIRED.STLB_MISS", 303*f9900dd0SZhengjun Xing "MSRIndex": "0x3F7", 304*f9900dd0SZhengjun Xing "MSRValue": "0x15", 305*f9900dd0SZhengjun Xing "PEBS": "1", 306*f9900dd0SZhengjun Xing "PEBScounters": "0,1,2,3,4,5,6,7", 307*f9900dd0SZhengjun Xing "SampleAfterValue": "100007", 308*f9900dd0SZhengjun Xing "TakenAlone": "1", 309*f9900dd0SZhengjun Xing "UMask": "0x1", 310*f9900dd0SZhengjun Xing "Unit": "cpu_core" 311*f9900dd0SZhengjun Xing }, 312*f9900dd0SZhengjun Xing { 313*f9900dd0SZhengjun Xing "BriefDescription": "TBD", 314*f9900dd0SZhengjun Xing "CollectPEBSRecord": "2", 315*f9900dd0SZhengjun Xing "Counter": "0,1,2,3,4,5,6,7", 316*f9900dd0SZhengjun Xing "EventCode": "0xc6", 317*f9900dd0SZhengjun Xing "EventName": "FRONTEND_RETIRED.UNKNOWN_BRANCH", 318*f9900dd0SZhengjun Xing "MSRIndex": "0x3F7", 319*f9900dd0SZhengjun Xing "MSRValue": "0x17", 320*f9900dd0SZhengjun Xing "PEBS": "1", 321*f9900dd0SZhengjun Xing "PEBScounters": "0,1,2,3,4,5,6,7", 322*f9900dd0SZhengjun Xing "SampleAfterValue": "100007", 323*f9900dd0SZhengjun Xing "TakenAlone": "1", 324*f9900dd0SZhengjun Xing "UMask": "0x1", 325*f9900dd0SZhengjun Xing "Unit": "cpu_core" 326*f9900dd0SZhengjun Xing }, 327*f9900dd0SZhengjun Xing { 328*f9900dd0SZhengjun Xing "BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction cache miss.", 329*f9900dd0SZhengjun Xing "CollectPEBSRecord": "2", 330*f9900dd0SZhengjun Xing "Counter": "0,1,2,3", 331*f9900dd0SZhengjun Xing "EventCode": "0x80", 332*f9900dd0SZhengjun Xing "EventName": "ICACHE_DATA.STALLS", 333*f9900dd0SZhengjun Xing "PEBScounters": "0,1,2,3", 334*f9900dd0SZhengjun Xing "SampleAfterValue": "500009", 335*f9900dd0SZhengjun Xing "UMask": "0x4", 336*f9900dd0SZhengjun Xing "Unit": "cpu_core" 337*f9900dd0SZhengjun Xing }, 338*f9900dd0SZhengjun Xing { 339*f9900dd0SZhengjun Xing "BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction cache tag miss.", 340*f9900dd0SZhengjun Xing "CollectPEBSRecord": "2", 341*f9900dd0SZhengjun Xing "Counter": "0,1,2,3", 342*f9900dd0SZhengjun Xing "EventCode": "0x83", 343*f9900dd0SZhengjun Xing "EventName": "ICACHE_TAG.STALLS", 344*f9900dd0SZhengjun Xing "PEBScounters": "0,1,2,3", 345*f9900dd0SZhengjun Xing "SampleAfterValue": "200003", 346*f9900dd0SZhengjun Xing "UMask": "0x4", 347*f9900dd0SZhengjun Xing "Unit": "cpu_core" 348*f9900dd0SZhengjun Xing }, 349*f9900dd0SZhengjun Xing { 350*f9900dd0SZhengjun Xing "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering any Uop", 351*f9900dd0SZhengjun Xing "CollectPEBSRecord": "2", 352*f9900dd0SZhengjun Xing "Counter": "0,1,2,3", 353*f9900dd0SZhengjun Xing "CounterMask": "1", 354*f9900dd0SZhengjun Xing "EventCode": "0x79", 355*f9900dd0SZhengjun Xing "EventName": "IDQ.DSB_CYCLES_ANY", 356*f9900dd0SZhengjun Xing "PEBScounters": "0,1,2,3", 357*f9900dd0SZhengjun Xing "SampleAfterValue": "2000003", 358*f9900dd0SZhengjun Xing "UMask": "0x8", 359*f9900dd0SZhengjun Xing "Unit": "cpu_core" 360*f9900dd0SZhengjun Xing }, 361*f9900dd0SZhengjun Xing { 362*f9900dd0SZhengjun Xing "BriefDescription": "Cycles DSB is delivering optimal number of Uops", 363*f9900dd0SZhengjun Xing "CollectPEBSRecord": "2", 364*f9900dd0SZhengjun Xing "Counter": "0,1,2,3", 365*f9900dd0SZhengjun Xing "CounterMask": "6", 366*f9900dd0SZhengjun Xing "EventCode": "0x79", 367*f9900dd0SZhengjun Xing "EventName": "IDQ.DSB_CYCLES_OK", 368*f9900dd0SZhengjun Xing "PEBScounters": "0,1,2,3", 369*f9900dd0SZhengjun Xing "SampleAfterValue": "2000003", 370*f9900dd0SZhengjun Xing "UMask": "0x8", 371*f9900dd0SZhengjun Xing "Unit": "cpu_core" 372*f9900dd0SZhengjun Xing }, 373*f9900dd0SZhengjun Xing { 374*f9900dd0SZhengjun Xing "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path", 375*f9900dd0SZhengjun Xing "CollectPEBSRecord": "2", 376*f9900dd0SZhengjun Xing "Counter": "0,1,2,3", 377*f9900dd0SZhengjun Xing "EventCode": "0x79", 378*f9900dd0SZhengjun Xing "EventName": "IDQ.DSB_UOPS", 379*f9900dd0SZhengjun Xing "PEBScounters": "0,1,2,3", 380*f9900dd0SZhengjun Xing "SampleAfterValue": "2000003", 381*f9900dd0SZhengjun Xing "UMask": "0x8", 382*f9900dd0SZhengjun Xing "Unit": "cpu_core" 383*f9900dd0SZhengjun Xing }, 384*f9900dd0SZhengjun Xing { 385*f9900dd0SZhengjun Xing "BriefDescription": "Cycles MITE is delivering any Uop", 386*f9900dd0SZhengjun Xing "CollectPEBSRecord": "2", 387*f9900dd0SZhengjun Xing "Counter": "0,1,2,3", 388*f9900dd0SZhengjun Xing "CounterMask": "1", 389*f9900dd0SZhengjun Xing "EventCode": "0x79", 390*f9900dd0SZhengjun Xing "EventName": "IDQ.MITE_CYCLES_ANY", 391*f9900dd0SZhengjun Xing "PEBScounters": "0,1,2,3", 392*f9900dd0SZhengjun Xing "SampleAfterValue": "2000003", 393*f9900dd0SZhengjun Xing "UMask": "0x4", 394*f9900dd0SZhengjun Xing "Unit": "cpu_core" 395*f9900dd0SZhengjun Xing }, 396*f9900dd0SZhengjun Xing { 397*f9900dd0SZhengjun Xing "BriefDescription": "Cycles MITE is delivering optimal number of Uops", 398*f9900dd0SZhengjun Xing "CollectPEBSRecord": "2", 399*f9900dd0SZhengjun Xing "Counter": "0,1,2,3", 400*f9900dd0SZhengjun Xing "CounterMask": "6", 401*f9900dd0SZhengjun Xing "EventCode": "0x79", 402*f9900dd0SZhengjun Xing "EventName": "IDQ.MITE_CYCLES_OK", 403*f9900dd0SZhengjun Xing "PEBScounters": "0,1,2,3", 404*f9900dd0SZhengjun Xing "SampleAfterValue": "2000003", 405*f9900dd0SZhengjun Xing "UMask": "0x4", 406*f9900dd0SZhengjun Xing "Unit": "cpu_core" 407*f9900dd0SZhengjun Xing }, 408*f9900dd0SZhengjun Xing { 409*f9900dd0SZhengjun Xing "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from MITE path", 410*f9900dd0SZhengjun Xing "CollectPEBSRecord": "2", 411*f9900dd0SZhengjun Xing "Counter": "0,1,2,3", 412*f9900dd0SZhengjun Xing "EventCode": "0x79", 413*f9900dd0SZhengjun Xing "EventName": "IDQ.MITE_UOPS", 414*f9900dd0SZhengjun Xing "PEBScounters": "0,1,2,3", 415*f9900dd0SZhengjun Xing "SampleAfterValue": "2000003", 416*f9900dd0SZhengjun Xing "UMask": "0x4", 417*f9900dd0SZhengjun Xing "Unit": "cpu_core" 418*f9900dd0SZhengjun Xing }, 419*f9900dd0SZhengjun Xing { 420*f9900dd0SZhengjun Xing "BriefDescription": "Cycles when uops are being delivered to IDQ while MS is busy", 421*f9900dd0SZhengjun Xing "CollectPEBSRecord": "2", 422*f9900dd0SZhengjun Xing "Counter": "0,1,2,3", 423*f9900dd0SZhengjun Xing "CounterMask": "1", 424*f9900dd0SZhengjun Xing "EventCode": "0x79", 425*f9900dd0SZhengjun Xing "EventName": "IDQ.MS_CYCLES_ANY", 426*f9900dd0SZhengjun Xing "PEBScounters": "0,1,2,3", 427*f9900dd0SZhengjun Xing "SampleAfterValue": "2000003", 428*f9900dd0SZhengjun Xing "UMask": "0x20", 429*f9900dd0SZhengjun Xing "Unit": "cpu_core" 430*f9900dd0SZhengjun Xing }, 431*f9900dd0SZhengjun Xing { 432*f9900dd0SZhengjun Xing "BriefDescription": "Number of switches from DSB or MITE to the MS", 433*f9900dd0SZhengjun Xing "CollectPEBSRecord": "2", 434*f9900dd0SZhengjun Xing "Counter": "0,1,2,3", 435*f9900dd0SZhengjun Xing "CounterMask": "1", 436*f9900dd0SZhengjun Xing "EdgeDetect": "1", 437*f9900dd0SZhengjun Xing "EventCode": "0x79", 438*f9900dd0SZhengjun Xing "EventName": "IDQ.MS_SWITCHES", 439*f9900dd0SZhengjun Xing "PEBScounters": "0,1,2,3", 440*f9900dd0SZhengjun Xing "SampleAfterValue": "100003", 441*f9900dd0SZhengjun Xing "UMask": "0x20", 442*f9900dd0SZhengjun Xing "Unit": "cpu_core" 443*f9900dd0SZhengjun Xing }, 444*f9900dd0SZhengjun Xing { 445*f9900dd0SZhengjun Xing "BriefDescription": "Uops delivered to IDQ while MS is busy", 446*f9900dd0SZhengjun Xing "CollectPEBSRecord": "2", 447*f9900dd0SZhengjun Xing "Counter": "0,1,2,3", 448*f9900dd0SZhengjun Xing "EventCode": "0x79", 449*f9900dd0SZhengjun Xing "EventName": "IDQ.MS_UOPS", 450*f9900dd0SZhengjun Xing "PEBScounters": "0,1,2,3", 451*f9900dd0SZhengjun Xing "SampleAfterValue": "1000003", 452*f9900dd0SZhengjun Xing "UMask": "0x20", 453*f9900dd0SZhengjun Xing "Unit": "cpu_core" 454*f9900dd0SZhengjun Xing }, 455*f9900dd0SZhengjun Xing { 456*f9900dd0SZhengjun Xing "BriefDescription": "Uops not delivered by IDQ when backend of the machine is not stalled", 457*f9900dd0SZhengjun Xing "CollectPEBSRecord": "2", 458*f9900dd0SZhengjun Xing "Counter": "0,1,2,3,4,5,6,7", 459*f9900dd0SZhengjun Xing "EventCode": "0x9c", 460*f9900dd0SZhengjun Xing "EventName": "IDQ_UOPS_NOT_DELIVERED.CORE", 461*f9900dd0SZhengjun Xing "PEBScounters": "0,1,2,3,4,5,6,7", 462*f9900dd0SZhengjun Xing "SampleAfterValue": "1000003", 463*f9900dd0SZhengjun Xing "UMask": "0x1", 464*f9900dd0SZhengjun Xing "Unit": "cpu_core" 465*f9900dd0SZhengjun Xing }, 466*f9900dd0SZhengjun Xing { 467*f9900dd0SZhengjun Xing "BriefDescription": "Cycles when no uops are not delivered by the IDQ when backend of the machine is not stalled", 468*f9900dd0SZhengjun Xing "CollectPEBSRecord": "2", 469*f9900dd0SZhengjun Xing "Counter": "0,1,2,3,4,5,6,7", 470*f9900dd0SZhengjun Xing "CounterMask": "6", 471*f9900dd0SZhengjun Xing "EventCode": "0x9c", 472*f9900dd0SZhengjun Xing "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE", 473*f9900dd0SZhengjun Xing "PEBScounters": "0,1,2,3,4,5,6,7", 474*f9900dd0SZhengjun Xing "SampleAfterValue": "1000003", 475*f9900dd0SZhengjun Xing "UMask": "0x1", 476*f9900dd0SZhengjun Xing "Unit": "cpu_core" 477*f9900dd0SZhengjun Xing }, 478*f9900dd0SZhengjun Xing { 479*f9900dd0SZhengjun Xing "BriefDescription": "Cycles when optimal number of uops was delivered to the back-end when the back-end is not stalled", 480*f9900dd0SZhengjun Xing "CollectPEBSRecord": "2", 481*f9900dd0SZhengjun Xing "Counter": "0,1,2,3,4,5,6,7", 482*f9900dd0SZhengjun Xing "CounterMask": "1", 483*f9900dd0SZhengjun Xing "EventCode": "0x9c", 484*f9900dd0SZhengjun Xing "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_FE_WAS_OK", 485*f9900dd0SZhengjun Xing "Invert": "1", 486*f9900dd0SZhengjun Xing "PEBScounters": "0,1,2,3,4,5,6,7", 487*f9900dd0SZhengjun Xing "SampleAfterValue": "1000003", 488*f9900dd0SZhengjun Xing "UMask": "0x1", 489*f9900dd0SZhengjun Xing "Unit": "cpu_core" 490*f9900dd0SZhengjun Xing } 491*f9900dd0SZhengjun Xing]