1*f9900dd0SZhengjun Xing[ 2*f9900dd0SZhengjun Xing { 3*f9900dd0SZhengjun Xing "BriefDescription": "Counts the number of floating point operations retired that required microcode assist.", 4*f9900dd0SZhengjun Xing "CollectPEBSRecord": "2", 5*f9900dd0SZhengjun Xing "Counter": "0,1,2,3,4,5", 6*f9900dd0SZhengjun Xing "EventCode": "0xc3", 7*f9900dd0SZhengjun Xing "EventName": "MACHINE_CLEARS.FP_ASSIST", 8*f9900dd0SZhengjun Xing "PEBScounters": "0,1,2,3,4,5", 9*f9900dd0SZhengjun Xing "SampleAfterValue": "20003", 10*f9900dd0SZhengjun Xing "UMask": "0x4", 11*f9900dd0SZhengjun Xing "Unit": "cpu_atom" 12*f9900dd0SZhengjun Xing }, 13*f9900dd0SZhengjun Xing { 14*f9900dd0SZhengjun Xing "BriefDescription": "Counts the number of floating point divide uops retired (x87 and SSE, including x87 sqrt).", 15*f9900dd0SZhengjun Xing "CollectPEBSRecord": "2", 16*f9900dd0SZhengjun Xing "Counter": "0,1,2,3,4,5", 17*f9900dd0SZhengjun Xing "EventCode": "0xc2", 18*f9900dd0SZhengjun Xing "EventName": "UOPS_RETIRED.FPDIV", 19*f9900dd0SZhengjun Xing "PEBS": "1", 20*f9900dd0SZhengjun Xing "PEBScounters": "0,1,2,3,4,5", 21*f9900dd0SZhengjun Xing "SampleAfterValue": "2000003", 22*f9900dd0SZhengjun Xing "UMask": "0x8", 23*f9900dd0SZhengjun Xing "Unit": "cpu_atom" 24*f9900dd0SZhengjun Xing }, 25*f9900dd0SZhengjun Xing { 26*f9900dd0SZhengjun Xing "BriefDescription": "TBD", 27*f9900dd0SZhengjun Xing "CollectPEBSRecord": "2", 28*f9900dd0SZhengjun Xing "Counter": "0,1,2,3,4,5,6,7", 29*f9900dd0SZhengjun Xing "CounterMask": "1", 30*f9900dd0SZhengjun Xing "EventCode": "0xb0", 31*f9900dd0SZhengjun Xing "EventName": "ARITH.FPDIV_ACTIVE", 32*f9900dd0SZhengjun Xing "PEBScounters": "0,1,2,3,4,5,6,7", 33*f9900dd0SZhengjun Xing "SampleAfterValue": "1000003", 34*f9900dd0SZhengjun Xing "UMask": "0x1", 35*f9900dd0SZhengjun Xing "Unit": "cpu_core" 36*f9900dd0SZhengjun Xing }, 37*f9900dd0SZhengjun Xing { 38*f9900dd0SZhengjun Xing "BriefDescription": "Counts all microcode FP assists.", 39*f9900dd0SZhengjun Xing "CollectPEBSRecord": "2", 40*f9900dd0SZhengjun Xing "Counter": "0,1,2,3,4,5,6,7", 41*f9900dd0SZhengjun Xing "EventCode": "0xc1", 42*f9900dd0SZhengjun Xing "EventName": "ASSISTS.FP", 43*f9900dd0SZhengjun Xing "PEBScounters": "0,1,2,3,4,5,6,7", 44*f9900dd0SZhengjun Xing "SampleAfterValue": "100003", 45*f9900dd0SZhengjun Xing "UMask": "0x2", 46*f9900dd0SZhengjun Xing "Unit": "cpu_core" 47*f9900dd0SZhengjun Xing }, 48*f9900dd0SZhengjun Xing { 49*f9900dd0SZhengjun Xing "BriefDescription": "TBD", 50*f9900dd0SZhengjun Xing "CollectPEBSRecord": "2", 51*f9900dd0SZhengjun Xing "Counter": "0,1,2,3,4,5,6,7", 52*f9900dd0SZhengjun Xing "EventCode": "0xc1", 53*f9900dd0SZhengjun Xing "EventName": "ASSISTS.SSE_AVX_MIX", 54*f9900dd0SZhengjun Xing "PEBScounters": "0,1,2,3,4,5,6,7", 55*f9900dd0SZhengjun Xing "SampleAfterValue": "1000003", 56*f9900dd0SZhengjun Xing "UMask": "0x10", 57*f9900dd0SZhengjun Xing "Unit": "cpu_core" 58*f9900dd0SZhengjun Xing }, 59*f9900dd0SZhengjun Xing { 60*f9900dd0SZhengjun Xing "BriefDescription": "TBD", 61*f9900dd0SZhengjun Xing "CollectPEBSRecord": "2", 62*f9900dd0SZhengjun Xing "Counter": "0,1,2,3,4,5,6,7", 63*f9900dd0SZhengjun Xing "EventCode": "0xb3", 64*f9900dd0SZhengjun Xing "EventName": "FP_ARITH_DISPATCHED.PORT_0", 65*f9900dd0SZhengjun Xing "PEBScounters": "0,1,2,3,4,5,6,7", 66*f9900dd0SZhengjun Xing "SampleAfterValue": "2000003", 67*f9900dd0SZhengjun Xing "UMask": "0x1", 68*f9900dd0SZhengjun Xing "Unit": "cpu_core" 69*f9900dd0SZhengjun Xing }, 70*f9900dd0SZhengjun Xing { 71*f9900dd0SZhengjun Xing "BriefDescription": "TBD", 72*f9900dd0SZhengjun Xing "CollectPEBSRecord": "2", 73*f9900dd0SZhengjun Xing "Counter": "0,1,2,3,4,5,6,7", 74*f9900dd0SZhengjun Xing "EventCode": "0xb3", 75*f9900dd0SZhengjun Xing "EventName": "FP_ARITH_DISPATCHED.PORT_1", 76*f9900dd0SZhengjun Xing "PEBScounters": "0,1,2,3,4,5,6,7", 77*f9900dd0SZhengjun Xing "SampleAfterValue": "2000003", 78*f9900dd0SZhengjun Xing "UMask": "0x2", 79*f9900dd0SZhengjun Xing "Unit": "cpu_core" 80*f9900dd0SZhengjun Xing }, 81*f9900dd0SZhengjun Xing { 82*f9900dd0SZhengjun Xing "BriefDescription": "TBD", 83*f9900dd0SZhengjun Xing "CollectPEBSRecord": "2", 84*f9900dd0SZhengjun Xing "Counter": "0,1,2,3,4,5,6,7", 85*f9900dd0SZhengjun Xing "EventCode": "0xb3", 86*f9900dd0SZhengjun Xing "EventName": "FP_ARITH_DISPATCHED.PORT_5", 87*f9900dd0SZhengjun Xing "PEBScounters": "0,1,2,3,4,5,6,7", 88*f9900dd0SZhengjun Xing "SampleAfterValue": "2000003", 89*f9900dd0SZhengjun Xing "UMask": "0x4", 90*f9900dd0SZhengjun Xing "Unit": "cpu_core" 91*f9900dd0SZhengjun Xing }, 92*f9900dd0SZhengjun Xing { 93*f9900dd0SZhengjun Xing "BriefDescription": "Counts number of SSE/AVX computational 128-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 2 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", 94*f9900dd0SZhengjun Xing "CollectPEBSRecord": "2", 95*f9900dd0SZhengjun Xing "Counter": "0,1,2,3,4,5,6,7", 96*f9900dd0SZhengjun Xing "EventCode": "0xc7", 97*f9900dd0SZhengjun Xing "EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE", 98*f9900dd0SZhengjun Xing "PEBScounters": "0,1,2,3,4,5,6,7", 99*f9900dd0SZhengjun Xing "SampleAfterValue": "100003", 100*f9900dd0SZhengjun Xing "UMask": "0x4", 101*f9900dd0SZhengjun Xing "Unit": "cpu_core" 102*f9900dd0SZhengjun Xing }, 103*f9900dd0SZhengjun Xing { 104*f9900dd0SZhengjun Xing "BriefDescription": "Number of SSE/AVX computational 128-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", 105*f9900dd0SZhengjun Xing "CollectPEBSRecord": "2", 106*f9900dd0SZhengjun Xing "Counter": "0,1,2,3,4,5,6,7", 107*f9900dd0SZhengjun Xing "EventCode": "0xc7", 108*f9900dd0SZhengjun Xing "EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE", 109*f9900dd0SZhengjun Xing "PEBScounters": "0,1,2,3,4,5,6,7", 110*f9900dd0SZhengjun Xing "SampleAfterValue": "100003", 111*f9900dd0SZhengjun Xing "UMask": "0x8", 112*f9900dd0SZhengjun Xing "Unit": "cpu_core" 113*f9900dd0SZhengjun Xing }, 114*f9900dd0SZhengjun Xing { 115*f9900dd0SZhengjun Xing "BriefDescription": "Counts number of SSE/AVX computational 256-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", 116*f9900dd0SZhengjun Xing "CollectPEBSRecord": "2", 117*f9900dd0SZhengjun Xing "Counter": "0,1,2,3,4,5,6,7", 118*f9900dd0SZhengjun Xing "EventCode": "0xc7", 119*f9900dd0SZhengjun Xing "EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE", 120*f9900dd0SZhengjun Xing "PEBScounters": "0,1,2,3,4,5,6,7", 121*f9900dd0SZhengjun Xing "SampleAfterValue": "100003", 122*f9900dd0SZhengjun Xing "UMask": "0x10", 123*f9900dd0SZhengjun Xing "Unit": "cpu_core" 124*f9900dd0SZhengjun Xing }, 125*f9900dd0SZhengjun Xing { 126*f9900dd0SZhengjun Xing "BriefDescription": "Counts number of SSE/AVX computational 256-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", 127*f9900dd0SZhengjun Xing "CollectPEBSRecord": "2", 128*f9900dd0SZhengjun Xing "Counter": "0,1,2,3,4,5,6,7", 129*f9900dd0SZhengjun Xing "EventCode": "0xc7", 130*f9900dd0SZhengjun Xing "EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE", 131*f9900dd0SZhengjun Xing "PEBScounters": "0,1,2,3,4,5,6,7", 132*f9900dd0SZhengjun Xing "SampleAfterValue": "100003", 133*f9900dd0SZhengjun Xing "UMask": "0x20", 134*f9900dd0SZhengjun Xing "Unit": "cpu_core" 135*f9900dd0SZhengjun Xing }, 136*f9900dd0SZhengjun Xing { 137*f9900dd0SZhengjun Xing "BriefDescription": "Counts number of SSE/AVX computational scalar double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", 138*f9900dd0SZhengjun Xing "CollectPEBSRecord": "2", 139*f9900dd0SZhengjun Xing "Counter": "0,1,2,3,4,5,6,7", 140*f9900dd0SZhengjun Xing "EventCode": "0xc7", 141*f9900dd0SZhengjun Xing "EventName": "FP_ARITH_INST_RETIRED.SCALAR_DOUBLE", 142*f9900dd0SZhengjun Xing "PEBScounters": "0,1,2,3,4,5,6,7", 143*f9900dd0SZhengjun Xing "SampleAfterValue": "100003", 144*f9900dd0SZhengjun Xing "UMask": "0x1", 145*f9900dd0SZhengjun Xing "Unit": "cpu_core" 146*f9900dd0SZhengjun Xing }, 147*f9900dd0SZhengjun Xing { 148*f9900dd0SZhengjun Xing "BriefDescription": "Counts number of SSE/AVX computational scalar single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", 149*f9900dd0SZhengjun Xing "CollectPEBSRecord": "2", 150*f9900dd0SZhengjun Xing "Counter": "0,1,2,3,4,5,6,7", 151*f9900dd0SZhengjun Xing "EventCode": "0xc7", 152*f9900dd0SZhengjun Xing "EventName": "FP_ARITH_INST_RETIRED.SCALAR_SINGLE", 153*f9900dd0SZhengjun Xing "PEBScounters": "0,1,2,3,4,5,6,7", 154*f9900dd0SZhengjun Xing "SampleAfterValue": "100003", 155*f9900dd0SZhengjun Xing "UMask": "0x2", 156*f9900dd0SZhengjun Xing "Unit": "cpu_core" 157*f9900dd0SZhengjun Xing } 158*f9900dd0SZhengjun Xing]