1f9900dd0SZhengjun Xing[ 2f9900dd0SZhengjun Xing { 3f9900dd0SZhengjun Xing "BriefDescription": "Counts the number of floating point operations retired that required microcode assist.", 4f9900dd0SZhengjun Xing "CollectPEBSRecord": "2", 5f9900dd0SZhengjun Xing "Counter": "0,1,2,3,4,5", 6f9900dd0SZhengjun Xing "EventCode": "0xc3", 7f9900dd0SZhengjun Xing "EventName": "MACHINE_CLEARS.FP_ASSIST", 8f9900dd0SZhengjun Xing "PEBScounters": "0,1,2,3,4,5", 9f9900dd0SZhengjun Xing "SampleAfterValue": "20003", 10*5fa2481cSZhengjun Xing "Speculative": "1", 11f9900dd0SZhengjun Xing "UMask": "0x4", 12f9900dd0SZhengjun Xing "Unit": "cpu_atom" 13f9900dd0SZhengjun Xing }, 14f9900dd0SZhengjun Xing { 15f9900dd0SZhengjun Xing "BriefDescription": "Counts the number of floating point divide uops retired (x87 and SSE, including x87 sqrt).", 16f9900dd0SZhengjun Xing "CollectPEBSRecord": "2", 17f9900dd0SZhengjun Xing "Counter": "0,1,2,3,4,5", 18f9900dd0SZhengjun Xing "EventCode": "0xc2", 19f9900dd0SZhengjun Xing "EventName": "UOPS_RETIRED.FPDIV", 20f9900dd0SZhengjun Xing "PEBS": "1", 21f9900dd0SZhengjun Xing "PEBScounters": "0,1,2,3,4,5", 22f9900dd0SZhengjun Xing "SampleAfterValue": "2000003", 23f9900dd0SZhengjun Xing "UMask": "0x8", 24f9900dd0SZhengjun Xing "Unit": "cpu_atom" 25f9900dd0SZhengjun Xing }, 26f9900dd0SZhengjun Xing { 27*5fa2481cSZhengjun Xing "BriefDescription": "ARITH.FPDIV_ACTIVE", 28f9900dd0SZhengjun Xing "CollectPEBSRecord": "2", 29f9900dd0SZhengjun Xing "Counter": "0,1,2,3,4,5,6,7", 30f9900dd0SZhengjun Xing "CounterMask": "1", 31f9900dd0SZhengjun Xing "EventCode": "0xb0", 32f9900dd0SZhengjun Xing "EventName": "ARITH.FPDIV_ACTIVE", 33f9900dd0SZhengjun Xing "PEBScounters": "0,1,2,3,4,5,6,7", 34f9900dd0SZhengjun Xing "SampleAfterValue": "1000003", 35*5fa2481cSZhengjun Xing "Speculative": "1", 36f9900dd0SZhengjun Xing "UMask": "0x1", 37f9900dd0SZhengjun Xing "Unit": "cpu_core" 38f9900dd0SZhengjun Xing }, 39f9900dd0SZhengjun Xing { 40f9900dd0SZhengjun Xing "BriefDescription": "Counts all microcode FP assists.", 41f9900dd0SZhengjun Xing "CollectPEBSRecord": "2", 42f9900dd0SZhengjun Xing "Counter": "0,1,2,3,4,5,6,7", 43f9900dd0SZhengjun Xing "EventCode": "0xc1", 44f9900dd0SZhengjun Xing "EventName": "ASSISTS.FP", 45f9900dd0SZhengjun Xing "PEBScounters": "0,1,2,3,4,5,6,7", 46f9900dd0SZhengjun Xing "SampleAfterValue": "100003", 47*5fa2481cSZhengjun Xing "Speculative": "1", 48f9900dd0SZhengjun Xing "UMask": "0x2", 49f9900dd0SZhengjun Xing "Unit": "cpu_core" 50f9900dd0SZhengjun Xing }, 51f9900dd0SZhengjun Xing { 52*5fa2481cSZhengjun Xing "BriefDescription": "ASSISTS.SSE_AVX_MIX", 53f9900dd0SZhengjun Xing "CollectPEBSRecord": "2", 54f9900dd0SZhengjun Xing "Counter": "0,1,2,3,4,5,6,7", 55f9900dd0SZhengjun Xing "EventCode": "0xc1", 56f9900dd0SZhengjun Xing "EventName": "ASSISTS.SSE_AVX_MIX", 57f9900dd0SZhengjun Xing "PEBScounters": "0,1,2,3,4,5,6,7", 58f9900dd0SZhengjun Xing "SampleAfterValue": "1000003", 59*5fa2481cSZhengjun Xing "Speculative": "1", 60f9900dd0SZhengjun Xing "UMask": "0x10", 61f9900dd0SZhengjun Xing "Unit": "cpu_core" 62f9900dd0SZhengjun Xing }, 63f9900dd0SZhengjun Xing { 64*5fa2481cSZhengjun Xing "BriefDescription": "FP_ARITH_DISPATCHED.PORT_0", 65f9900dd0SZhengjun Xing "CollectPEBSRecord": "2", 66f9900dd0SZhengjun Xing "Counter": "0,1,2,3,4,5,6,7", 67f9900dd0SZhengjun Xing "EventCode": "0xb3", 68f9900dd0SZhengjun Xing "EventName": "FP_ARITH_DISPATCHED.PORT_0", 69f9900dd0SZhengjun Xing "PEBScounters": "0,1,2,3,4,5,6,7", 70f9900dd0SZhengjun Xing "SampleAfterValue": "2000003", 71*5fa2481cSZhengjun Xing "Speculative": "1", 72f9900dd0SZhengjun Xing "UMask": "0x1", 73f9900dd0SZhengjun Xing "Unit": "cpu_core" 74f9900dd0SZhengjun Xing }, 75f9900dd0SZhengjun Xing { 76*5fa2481cSZhengjun Xing "BriefDescription": "FP_ARITH_DISPATCHED.PORT_1", 77f9900dd0SZhengjun Xing "CollectPEBSRecord": "2", 78f9900dd0SZhengjun Xing "Counter": "0,1,2,3,4,5,6,7", 79f9900dd0SZhengjun Xing "EventCode": "0xb3", 80f9900dd0SZhengjun Xing "EventName": "FP_ARITH_DISPATCHED.PORT_1", 81f9900dd0SZhengjun Xing "PEBScounters": "0,1,2,3,4,5,6,7", 82f9900dd0SZhengjun Xing "SampleAfterValue": "2000003", 83*5fa2481cSZhengjun Xing "Speculative": "1", 84f9900dd0SZhengjun Xing "UMask": "0x2", 85f9900dd0SZhengjun Xing "Unit": "cpu_core" 86f9900dd0SZhengjun Xing }, 87f9900dd0SZhengjun Xing { 88*5fa2481cSZhengjun Xing "BriefDescription": "FP_ARITH_DISPATCHED.PORT_5", 89f9900dd0SZhengjun Xing "CollectPEBSRecord": "2", 90f9900dd0SZhengjun Xing "Counter": "0,1,2,3,4,5,6,7", 91f9900dd0SZhengjun Xing "EventCode": "0xb3", 92f9900dd0SZhengjun Xing "EventName": "FP_ARITH_DISPATCHED.PORT_5", 93f9900dd0SZhengjun Xing "PEBScounters": "0,1,2,3,4,5,6,7", 94f9900dd0SZhengjun Xing "SampleAfterValue": "2000003", 95*5fa2481cSZhengjun Xing "Speculative": "1", 96f9900dd0SZhengjun Xing "UMask": "0x4", 97f9900dd0SZhengjun Xing "Unit": "cpu_core" 98f9900dd0SZhengjun Xing }, 99f9900dd0SZhengjun Xing { 100f9900dd0SZhengjun Xing "BriefDescription": "Counts number of SSE/AVX computational 128-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 2 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", 101f9900dd0SZhengjun Xing "CollectPEBSRecord": "2", 102f9900dd0SZhengjun Xing "Counter": "0,1,2,3,4,5,6,7", 103f9900dd0SZhengjun Xing "EventCode": "0xc7", 104f9900dd0SZhengjun Xing "EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE", 105f9900dd0SZhengjun Xing "PEBScounters": "0,1,2,3,4,5,6,7", 106f9900dd0SZhengjun Xing "SampleAfterValue": "100003", 107f9900dd0SZhengjun Xing "UMask": "0x4", 108f9900dd0SZhengjun Xing "Unit": "cpu_core" 109f9900dd0SZhengjun Xing }, 110f9900dd0SZhengjun Xing { 111f9900dd0SZhengjun Xing "BriefDescription": "Number of SSE/AVX computational 128-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", 112f9900dd0SZhengjun Xing "CollectPEBSRecord": "2", 113f9900dd0SZhengjun Xing "Counter": "0,1,2,3,4,5,6,7", 114f9900dd0SZhengjun Xing "EventCode": "0xc7", 115f9900dd0SZhengjun Xing "EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE", 116f9900dd0SZhengjun Xing "PEBScounters": "0,1,2,3,4,5,6,7", 117f9900dd0SZhengjun Xing "SampleAfterValue": "100003", 118f9900dd0SZhengjun Xing "UMask": "0x8", 119f9900dd0SZhengjun Xing "Unit": "cpu_core" 120f9900dd0SZhengjun Xing }, 121f9900dd0SZhengjun Xing { 122f9900dd0SZhengjun Xing "BriefDescription": "Counts number of SSE/AVX computational 256-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", 123f9900dd0SZhengjun Xing "CollectPEBSRecord": "2", 124f9900dd0SZhengjun Xing "Counter": "0,1,2,3,4,5,6,7", 125f9900dd0SZhengjun Xing "EventCode": "0xc7", 126f9900dd0SZhengjun Xing "EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE", 127f9900dd0SZhengjun Xing "PEBScounters": "0,1,2,3,4,5,6,7", 128f9900dd0SZhengjun Xing "SampleAfterValue": "100003", 129f9900dd0SZhengjun Xing "UMask": "0x10", 130f9900dd0SZhengjun Xing "Unit": "cpu_core" 131f9900dd0SZhengjun Xing }, 132f9900dd0SZhengjun Xing { 133f9900dd0SZhengjun Xing "BriefDescription": "Counts number of SSE/AVX computational 256-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", 134f9900dd0SZhengjun Xing "CollectPEBSRecord": "2", 135f9900dd0SZhengjun Xing "Counter": "0,1,2,3,4,5,6,7", 136f9900dd0SZhengjun Xing "EventCode": "0xc7", 137f9900dd0SZhengjun Xing "EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE", 138f9900dd0SZhengjun Xing "PEBScounters": "0,1,2,3,4,5,6,7", 139f9900dd0SZhengjun Xing "SampleAfterValue": "100003", 140f9900dd0SZhengjun Xing "UMask": "0x20", 141f9900dd0SZhengjun Xing "Unit": "cpu_core" 142f9900dd0SZhengjun Xing }, 143f9900dd0SZhengjun Xing { 144f9900dd0SZhengjun Xing "BriefDescription": "Counts number of SSE/AVX computational scalar double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", 145f9900dd0SZhengjun Xing "CollectPEBSRecord": "2", 146f9900dd0SZhengjun Xing "Counter": "0,1,2,3,4,5,6,7", 147f9900dd0SZhengjun Xing "EventCode": "0xc7", 148f9900dd0SZhengjun Xing "EventName": "FP_ARITH_INST_RETIRED.SCALAR_DOUBLE", 149f9900dd0SZhengjun Xing "PEBScounters": "0,1,2,3,4,5,6,7", 150f9900dd0SZhengjun Xing "SampleAfterValue": "100003", 151f9900dd0SZhengjun Xing "UMask": "0x1", 152f9900dd0SZhengjun Xing "Unit": "cpu_core" 153f9900dd0SZhengjun Xing }, 154f9900dd0SZhengjun Xing { 155f9900dd0SZhengjun Xing "BriefDescription": "Counts number of SSE/AVX computational scalar single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", 156f9900dd0SZhengjun Xing "CollectPEBSRecord": "2", 157f9900dd0SZhengjun Xing "Counter": "0,1,2,3,4,5,6,7", 158f9900dd0SZhengjun Xing "EventCode": "0xc7", 159f9900dd0SZhengjun Xing "EventName": "FP_ARITH_INST_RETIRED.SCALAR_SINGLE", 160f9900dd0SZhengjun Xing "PEBScounters": "0,1,2,3,4,5,6,7", 161f9900dd0SZhengjun Xing "SampleAfterValue": "100003", 162f9900dd0SZhengjun Xing "UMask": "0x2", 163f9900dd0SZhengjun Xing "Unit": "cpu_core" 164f9900dd0SZhengjun Xing } 165f9900dd0SZhengjun Xing] 166